URL
https://opencores.org/ocsvn/zipcpu/zipcpu/trunk
Subversion Repositories zipcpu
Compare Revisions
- This comparison shows the changes necessary to convert path
/zipcpu/trunk/bench
- from Rev 36 to Rev 39
- ↔ Reverse comparison
Rev 36 → Rev 39
/cpp/zippy_tb.cpp
43,6 → 43,7
|
#include "verilated.h" |
#include "Vzipsystem.h" |
#include "cpudefs.h" |
|
#include "testb.h" |
// #include "twoc.h" |
184,18 → 185,18
int ln= 0; |
|
mvprintw(ln,0, "Peripherals-SS"); ln++; |
#ifdef OPT_ILLEGAL_INSTRUCTION |
printw(" %s", |
// (m_core->v__DOT__thecpu__DOT__pf_illegal)?"PI":" ", |
(m_core->v__DOT__thecpu__DOT__dcd_illegal)?"DI":" " |
); |
/* |
printw(" %s%s%s", |
(m_core->v__DOT__thecpu__DOT__ill_err)?"IL":" ", |
#endif |
|
#ifdef OPT_EARLY_BRANCHING |
printw(" %s%s", |
(m_core->v__DOT__thecpu__DOT__dcd_early_branch)?"EB":" ", |
(m_core->v__DOT__thecpu__DOT__dcd_early_branch_stb)?"S":" ", |
(m_core->v__DOT__thecpu__DOT__dcd_early_branch_stb)?"S":" ", |
); |
*/ |
(m_core->v__DOT__thecpu__DOT__dcd_early_branch_stb)?"S":" "); |
#endif |
|
/* |
showval(ln, 1, "TRAP", m_core->v__DOT__trap_data); |
305,6 → 306,9
attroff(A_BOLD); |
ln+=1; |
|
#ifdef OPT_SINGLE_FETCH |
ln+=2; |
#else |
mvprintw(ln, 0, "PFPIPE: rda=%08x/%d, bas=%08x, off=%08x, nv=%03x, ackw=%d,%d%d,%04x", |
m_core->v__DOT__thecpu__DOT__pf__DOT__r_addr, |
m_core->v__DOT__thecpu__DOT__pf__DOT__r_cv, |
325,6 → 329,7
(m_core->v__DOT__thecpu__DOT__pf_ack)?"ACK":" ", |
(m_core->v__DOT__thecpu__DOT__pf_stall)?"STL":" ", |
(m_core->v__DOT__wb_data)); ln++; |
#endif |
|
mvprintw(ln, 0, "MEMBUS: %3s %3s %s @0x%08x[0x%08x] -> %s %s %08x", |
(m_core->v__DOT__thecpu__DOT__mem_cyc_gbl)?"GCY" |
336,7 → 341,17
(m_core->v__DOT__thecpu__DOT__mem_data), |
(m_core->v__DOT__thecpu__DOT__mem_ack)?"ACK":" ", |
(m_core->v__DOT__thecpu__DOT__mem_stall)?"STL":" ", |
(m_core->v__DOT__thecpu__DOT__mem_result)); ln++; |
(m_core->v__DOT__thecpu__DOT__mem_result)); |
// #define OPT_PIPELINED_BUS_ACCESS |
#ifdef OPT_PIPELINED_BUS_ACCESS |
printw(" %x%x%c%c", |
(m_core->v__DOT__thecpu__DOT__domem__DOT__wraddr), |
(m_core->v__DOT__thecpu__DOT__domem__DOT__rdaddr), |
(m_core->v__DOT__thecpu__DOT__op_pipe)?'P':'-', |
(mem_pipe_stalled())?'S':'-'); ln++; |
#else |
ln++; |
#endif |
|
mvprintw(ln, 0, "SYSBS%c: %3s %3s %s @0x%08x[0x%08x] -> %s %s %08x", |
(m_core->v__DOT__thecpu__DOT__pformem__DOT__r_a_owner)?'M':'P', |
348,7 → 363,40
(m_core->i_wb_ack)?"ACK":" ", |
(m_core->i_wb_stall)?"STL":" ", |
(m_core->i_wb_data)); ln+=2; |
#ifdef OPT_PIPELINED_BUS_ACCESS |
mvprintw(ln-1, 0, "Mem CE: %d = %d%d%d%d%d, stall: %d = %d%d(%d|%d%d|..)", |
(m_core->v__DOT__thecpu__DOT__mem_ce), |
(m_core->v__DOT__thecpu__DOT__master_ce), |
(m_core->v__DOT__thecpu__DOT__opvalid_mem), |
(!m_core->v__DOT__thecpu__DOT__clear_pipeline), |
(m_core->v__DOT__thecpu__DOT__set_cond), |
(!m_core->v__DOT__thecpu__DOT__mem_stalled), |
|
(m_core->v__DOT__thecpu__DOT__mem_stalled), |
(m_core->v__DOT__thecpu__DOT__opvalid_mem), |
(m_core->v__DOT__thecpu__DOT__master_ce), |
(mem_pipe_stalled()), |
(!m_core->v__DOT__thecpu__DOT__op_pipe), |
(m_core->v__DOT__thecpu__DOT__mem_busy)); |
printw(" op_pipe = %d%d%d%d%d(%d|%d)", |
(m_core->v__DOT__thecpu__DOT__dcdvalid), |
(m_core->v__DOT__thecpu__DOT__opvalid_mem), |
(m_core->v__DOT__thecpu__DOT__dcdM), |
(!((m_core->v__DOT__thecpu__DOT__dcdOp |
^m_core->v__DOT__thecpu__DOT__opn)&1)), |
(m_core->v__DOT__thecpu__DOT__dcdB |
== m_core->v__DOT__thecpu__DOT__op_B), |
(m_core->v__DOT__thecpu__DOT__r_dcdI |
== m_core->v__DOT__thecpu__DOT__r_opI), |
(m_core->v__DOT__thecpu__DOT__r_dcdI+1 |
== m_core->v__DOT__thecpu__DOT__r_opI)); |
mvprintw(4,4,"r_dcdI = 0x%06x, r_opI = 0x%06x", |
(m_core->v__DOT__thecpu__DOT__r_dcdI), |
(m_core->v__DOT__thecpu__DOT__r_opI)); |
#endif |
mvprintw(4,42,"0x%08x", m_core->v__DOT__thecpu__DOT__instruction); |
|
|
showins(ln, "I ", |
!m_core->v__DOT__thecpu__DOT__dcd_stalled, |
m_core->v__DOT__thecpu__DOT__pf_valid, |
364,6 → 412,13
m_core->v__DOT__thecpu__DOT__dcd_gie, |
m_core->v__DOT__thecpu__DOT__dcd_stalled, |
m_core->v__DOT__thecpu__DOT__dcd_pc-1); ln++; |
#ifdef OPT_ILLEGAL_INSTRUCTION |
if (m_core->v__DOT__thecpu__DOT__dcd_illegal) |
mvprintw(ln-1,10,"I"); |
else |
#endif |
if (m_core->v__DOT__thecpu__DOT__dcdM) |
mvprintw(ln-1,10,"M"); |
|
showins(ln, "Op", |
m_core->v__DOT__thecpu__DOT__op_ce, |
370,7 → 425,16
m_core->v__DOT__thecpu__DOT__opvalid, |
m_core->v__DOT__thecpu__DOT__op_gie, |
m_core->v__DOT__thecpu__DOT__op_stall, |
m_core->v__DOT__thecpu__DOT__op_pc-1); ln++; |
op_pc()); ln++; |
#ifdef OPT_ILLEGAL_INSTRUCTION |
if (m_core->v__DOT__thecpu__DOT__op_illegal) |
mvprintw(ln-1,10,"I"); |
else |
#endif |
if (m_core->v__DOT__thecpu__DOT__opvalid_mem) |
mvprintw(ln-1,10,"M"); |
else if (m_core->v__DOT__thecpu__DOT__opvalid_alu) |
mvprintw(ln-1,10,"A"); |
|
showins(ln, "Al", |
m_core->v__DOT__thecpu__DOT__alu_ce, |
377,9 → 441,11
m_core->v__DOT__thecpu__DOT__alu_pc_valid, |
m_core->v__DOT__thecpu__DOT__alu_gie, |
m_core->v__DOT__thecpu__DOT__alu_stall, |
m_core->v__DOT__thecpu__DOT__alu_pc-1); ln++; |
alu_pc()); ln++; |
if (m_core->v__DOT__thecpu__DOT__wr_reg_ce) |
mvprintw(ln-1,10,"W"); |
|
mvprintw(ln-5, 48,"%s %s", |
mvprintw(ln-5, 65,"%s %s", |
(m_core->v__DOT__thecpu__DOT__op_break)?"OB":" ", |
(m_core->v__DOT__thecpu__DOT__clear_pipeline)?"CLRP":" "); |
mvprintw(ln-4, 48, |
415,7 → 481,7
(m_core->v__DOT__thecpu__DOT__mem_ce)?"CE":" ", |
(m_core->v__DOT__thecpu__DOT__mem_we)?"Wr ":"Rd ", |
(m_core->v__DOT__thecpu__DOT__mem_stalled)?"PIPE":" ", |
(m_core->v__DOT__thecpu__DOT__mem_valid)?"MEMV":" ", |
(m_core->v__DOT__thecpu__DOT__mem_valid)?"V":" ", |
zop_regstr[(m_core->v__DOT__thecpu__DOT__mem_wreg&0x1f)^0x10]); |
} |
|
599,7 → 665,7
m_core->v__DOT__thecpu__DOT__opvalid, |
m_core->v__DOT__thecpu__DOT__op_gie, |
m_core->v__DOT__thecpu__DOT__op_stall, |
m_core->v__DOT__thecpu__DOT__op_pc-1); ln++; |
op_pc()); ln++; |
|
showins(ln, "Al", |
m_core->v__DOT__thecpu__DOT__alu_ce, |
606,7 → 672,7
m_core->v__DOT__thecpu__DOT__alu_pc_valid, |
m_core->v__DOT__thecpu__DOT__alu_gie, |
m_core->v__DOT__thecpu__DOT__alu_stall, |
m_core->v__DOT__thecpu__DOT__alu_pc-1); ln++; |
alu_pc()); ln++; |
} |
void tick(void) { |
int gie = m_core->v__DOT__thecpu__DOT__gie; |
660,7 → 726,7
m_core->v__DOT__thecpu__DOT__dcd_ce, |
m_core->v__DOT__thecpu__DOT__dcd_pc, |
m_core->v__DOT__thecpu__DOT__op_ce, |
m_core->v__DOT__thecpu__DOT__op_pc, |
op_pc(), |
m_core->v__DOT__thecpu__DOT__dcdA, |
m_core->v__DOT__thecpu__DOT__opR, |
m_core->v__DOT__cmd_halt, |
751,13 → 817,13
m_core->v__DOT__thecpu__DOT__opvalid, |
m_core->v__DOT__thecpu__DOT__op_gie, |
m_core->v__DOT__thecpu__DOT__op_stall, |
m_core->v__DOT__thecpu__DOT__op_pc-1); |
op_pc()); |
dbgins("Al - ", |
m_core->v__DOT__thecpu__DOT__alu_ce, |
m_core->v__DOT__thecpu__DOT__alu_pc_valid, |
m_core->v__DOT__thecpu__DOT__alu_gie, |
m_core->v__DOT__thecpu__DOT__alu_stall, |
m_core->v__DOT__thecpu__DOT__alu_pc-1); |
alu_pc()); |
|
} |
} |
767,10 → 833,43
&&(m_core->v__DOT__thecpu__DOT__sleep)); |
} |
|
unsigned op_pc(void) { |
/* |
unsigned r = m_core->v__DOT__thecpu__DOT__dcd_pc-1; |
if (m_core->v__DOT__thecpu__DOT__dcdvalid) |
r--; |
return r; |
*/ |
return m_core->v__DOT__thecpu__DOT__op_pc-1; |
} |
|
unsigned alu_pc(void) { |
/* |
unsigned r = op_pc(); |
if (m_core->v__DOT__thecpu__DOT__opvalid) |
r--; |
return r; |
*/ |
return m_core->v__DOT__thecpu__DOT__alu_pc-1; |
} |
|
#ifdef OPT_PIPELINED_BUS_ACCESS |
int mem_pipe_stalled(void) { |
int r = 0; |
r = ((m_core->v__DOT__thecpu__DOT__mem_cyc_gbl) |
||(m_core->v__DOT__thecpu__DOT__mem_cyc_lcl)); |
r = r && ((m_core->v__DOT__thecpu__DOT__mem_stall) |
||( |
((!m_core->v__DOT__thecpu__DOT__mem_stb_gbl) |
&&(!m_core->v__DOT__thecpu__DOT__mem_stb_lcl)))); |
return r; |
// return m_core->v__DOT__thecpu__DOT__mem_pipe_stalled; |
} |
#endif |
|
bool test_failure(void) { |
return ((m_core->v__DOT__thecpu__DOT__alu_pc_valid) |
&&(m_mem[m_core->v__DOT__thecpu__DOT__alu_pc-1] |
== 0x2f0f7fff) |
&&(m_mem[alu_pc()] == 0x2f0f7fff) |
&&(!m_core->v__DOT__thecpu__DOT__clear_pipeline)); |
} |
|
1117,7 → 1216,7
halted = true; |
erase(); |
break; |
case 's': case 'S': |
case 's': |
if (!halted) |
erase(); |
tb->wb_write(CMD_REG, CMD_STEP); |
1124,10 → 1223,30
manual = false; |
halted = true; |
break; |
case 't': case 'T': |
case 'S': |
if ((!manual)||(halted)) |
erase(); |
manual = true; |
halted = true; |
tb->m_core->v__DOT__cmd_halt = 0; |
tb->m_core->v__DOT__cmd_step = 1; |
tb->eval(); |
tb->tick(); |
break; |
case 'T': // |
if ((!manual)||(halted)) |
erase(); |
manual = true; |
halted = true; |
tb->m_core->v__DOT__cmd_halt = 1; |
tb->m_core->v__DOT__cmd_step = 0; |
tb->eval(); |
tb->tick(); |
break; |
case 't': |
if ((!manual)||(halted)) |
erase(); |
manual = true; |
halted = false; |
// tb->m_core->v__DOT__thecpu__DOT__step = 0; |
// tb->m_core->v__DOT__cmd_halt = 0; |
/cpp/Makefile
39,7 → 39,8
CXX := g++ |
FLAGS := -Wall -Og -g |
ZASM := ../../sw/zasm |
INCS := -I../../rtl/obj_dir/ -I/usr/share/verilator/include -I../../sw/zasm |
RTLD := ../../rtl |
INCS := -I$(RTLD)/obj_dir/ -I$(RTLD) -I/usr/share/verilator/include -I../../sw/zasm |
SOURCES := zippy_tb.cpp memsim.cpp twoc.cpp $(ZASM)/zopcodes.cpp $(ZASM)/zparser.cpp |
RAWLIB := /usr/share/verilator/include/verilated.cpp ../../rtl/obj_dir/Vzipsystem__ALL.a |
LIBS := $(RAWLIB) -lncurses |
46,6 → 47,7
TESTF := ../../sw/zasm/z.out |
|
zippy_tb: $(SOURCES) $(RAWLIB) $(ZASM)/zopcodes.h $(ZASM)/zparser.h testb.h |
zippy_tb: $(RTLD)/cpudefs.h |
$(CXX) $(FLAGS) $(INCS) $(SOURCES) $(LIBS) -o $@ |
|
.PHONY: stest |