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/src/spec.tex
87,14 → 87,16
\title{Specification} |
\author{Dan Gisselquist, Ph.D.} |
\email{dgisselq (at) opencores.org} |
\revision{Rev.~0.9} |
\revision{Rev.~0.91} |
\definecolor{webred}{rgb}{0.5,0,0} |
\definecolor{webgreen}{rgb}{0,0.4,0} |
\usepackage[dvips,ps2pdf,colorlinks=true, |
anchorcolor=black,pdfpagelabels,hypertexnames, |
\hypersetup{ |
ps2pdf, |
pdfpagelabels, |
hypertexnames, |
pdfauthor={Dan Gisselquist}, |
pdfsubject={Zip CPU}]{hyperref} |
\hypersetup{ |
pdfsubject={Zip CPU}, |
anchorcolor= black, |
colorlinks = true, |
linkcolor = webred, |
citecolor = webgreen |
122,6 → 124,7
\begin{revisionhistory} |
0.9 & 4/20/2016 & Gisselquist & Modified ISA: LDIHI replaced with MPY, MPYU and MPYS replaced with MPYUHI, and MPYSHI respectively. LOCK instruction now |
permits an intermediate ALU operation. \\\hline |
0.91& 7/16/2016 & Gisselquist & :escribed three more CC bits\\\hline |
0.8 & 1/28/2016 & Gisselquist & Reduced complexity early branching \\\hline |
0.7 & 12/22/2015 & Gisselquist & New Instruction Set Architecture \\\hline |
0.6 & 11/17/2015 & Gisselquist & Added graphics to illustrate pipeline discussion.\\\hline |
521,13 → 524,16
Fig.~\ref{tbl:cc-register}, |
\begin{table}\begin{center} |
\begin{bitlist} |
31\ldots 13 & R/W & Reserved for future uses\\\hline |
31\ldots 23 & R & Reserved for future uses\\\hline |
22\ldots 15 & R/W & Reserved for future uses\\\hline |
14 & W & Clear I-Cache command\\\hline |
13 & R & VLIW instruction phase (1 for first half)\\\hline |
12 & R & (Reserved for) Floating Point Exception\\\hline |
11 & R & Division by Zero Exception\\\hline |
10 & R & Bus-Error Flag\\\hline |
9 & R & Trap, or user interrupt, Flag. Cleared on return to userspace.\\\hline |
9 & R & Trap Flag (or user interrupt). Cleared on return to userspace.\\\hline |
8 & R & Illegal Instruction Flag\\\hline |
7 & R/W & Break--Enable\\\hline |
7 & R/W & Break--Enable (sCC), or user break (uCC)\\\hline |
6 & R/W & Step\\\hline |
5 & R/W & Global Interrupt Enable (GIE)\\\hline |
4 & R/W & Sleep. When GIE is also set, the CPU waits for an interrupt.\\\hline |
538,7 → 544,7
\end{bitlist} |
\caption{Condition Code Register Bit Assignment}\label{tbl:cc-register} |
\end{center}\end{table} |
the lower 11~bits of the status register form |
the lower 15~bits of the status register form |
a set of CPU state and condition codes. Writes to other bits of this register |
are preserved. |
|
586,12 → 592,17
of course. |
|
|
The eighth bit is a break enable bit. This controls whether a break |
instruction in user mode will halt the processor for an external debugger |
(break enabled), or whether the break instruction will simply send send the |
CPU into interrupt mode. Encountering a break in supervisor mode will |
halt the CPU independent of the break enable bit. This bit can only be set |
within supervisor mode. |
The eighth bit is a break enable bit. When applied to the supervisor CC |
register, this controls whether a break instruction in user mode will halt |
the processor for an external debugger (break enabled), or whether the break |
instruction will simply send send the CPU into interrupt mode. Encountering |
a break in supervisor mode will halt the CPU independent of the break enable |
bit. This bit can only be set within supervisor mode. However, when applied |
to the user CC register, from supervisor mode, this bit will indicate whether |
or not the reason the CPU entered supervisor mode was from a break instruction |
or not. This break reason bit is automatically cleared upon any transition to |
user mode, although it can also be cleared by the supervisor writing to the |
user CC register. |
|
% Should break enable be a supervisor mode bit, while the break enable bit |
% in user mode is a break has taken place bit? |
611,6 → 622,37
supervisor, in supervisor mode, to determine whether it got to supervisor |
mode from a trap or from an external interrupt or both. |
|
The eleventh bit is a bus error flag. If the user program encountered a bus |
error, this bit will be set in the user CC register and the CPU will switch to |
supervisor mode. The bit may be cleared by the supervisor, otherwise it is |
automatically cleared upon any return to user mode. If the supervisor |
encounters a bus error, this bit will be set in the supervisor CC register |
and the CPU will halt. In that case, either a CPU reset or a write to the |
supervisor CC register will clear this register. |
|
The twelth bit is a division by zero exception flag. This operates in a fashion |
similar to the bus error flag. If the user attempts to use the divide |
instruction with a zero denominator, the system will switch to supervisor mode |
and set this bit in the user CC register. The bit is automatically cleared |
upon any return to user mode, although it can also be manually cleared by |
the supervisor. In a similar fashion, if the supervisor attempts to execute |
a divide by zero, the CPU will halt and set the zero exception flag in the |
supervisor's CC register. This will automatically be cleared upon any CPU |
reset, or it may be manually cleared by the external debugger writing to this |
register. |
|
The thirteenth bit will operate in a similar fashion to both the bus error |
and division by zero flags, only it will be set upon a (yet to be determined) |
floating point error. |
|
Finally, the fourteenth bit references a clear cache bit. The supervisor may |
write a one to this bit in order to clear the CPU instruction cache. The |
bit always reads as a zero. |
|
Some of the upper bits have been temporarily assigned to indicate CPU |
capabilities. This is not a permanent feature, as these upper bits officially |
remain reserved. |
|
\section{Instruction Format} |
All Zip CPU instructions fit in one of the formats shown in |
Fig.~\ref{fig:iset-format}. |
2464,7 → 2506,7
14\ldots 10 & R/W & Select among one of 32~possible interrupt lines.\\\hline |
9\ldots 0 & R/W & Intermediate transfer length minus one. Thus, to transfer |
one item at a time set this value to 0. To transfer 1024 at a time, |
set it to 1024.\\\hline |
set it to 1023.\\\hline |
\end{bitlist} |
\caption{DMA Control Register Bits}\label{tbl:dmacbits} |
\end{center}\end{table} |
2478,7 → 2520,7
DMA controller does not use the interrupt controller, and cannot clear |
interrupts.) As a third example, if you wished to write to an external |
FIFO anytime it was less than half full (had fewer than 512 items), and |
interrupt line 2 indicated this condition, you might wish to issue a |
interrupt line 3 indicated this condition, you might wish to issue a |
\hbox{32'h1fed8dff} to this port. |
|
\section{Debug Port Registers} |