URL
https://opencores.org/ocsvn/zipcpu/zipcpu/trunk
Subversion Repositories zipcpu
Compare Revisions
- This comparison shows the changes necessary to convert path
/zipcpu/trunk/rtl/peripherals
- from Rev 2 to Rev 9
- ↔ Reverse comparison
Rev 2 → Rev 9
/zipjiffies.v
101,9 → 101,19
wire signed [(BW-1):0] till_when, till_wb; |
assign till_when = int_when-r_counter; |
assign till_wb = new_when-r_counter; |
|
initial new_set = 1'b0; |
always @(posedge i_clk) |
// Delay things by a clock to simplify our logic |
if ((i_wb_cyc)&&(i_wb_stb)&&(i_wb_we)) |
begin |
new_set <= 1'b1; |
new_when<= i_wb_data; |
end else |
new_set <= 1'b0; |
|
initial o_int = 1'b0; |
initial int_set = 1'b0; |
initial new_set = 1'b0; |
always @(posedge i_clk) |
begin |
o_int <= 1'b0; |
113,19 → 123,11
int_set <= 1'b0;// Clear the interrupt |
end |
|
new_set <= 1'b0; |
if ((new_set)&&(till_wb > 0)&&((till_wb<till_when)||(~int_set))) |
begin |
int_when <= new_when; |
int_set <= ((int_set)||(till_wb>0)); |
end |
|
// Delay things by a clock to simplify our logic |
if ((i_wb_cyc)&&(i_wb_stb)&&(i_wb_we)) |
begin |
new_set <= 1'b1; |
new_when<= i_wb_data; |
end |
end |
|
// |
134,7 → 136,7
// |
always @(posedge i_clk) |
o_wb_ack <= (i_wb_cyc)&&(i_wb_stb); |
|
assign o_wb_data = r_counter; |
assign o_wb_stall = 1'b0; |
|
endmodule |
/ziptimer.v
4,7 → 4,7
// |
// Project: Zip CPU -- a small, lightweight, RISC CPU soft core |
// |
// Purpose: |
// Purpose: A lighter weight implementation of the Zip Timer. |
// |
// Interface: |
// Two options: |
22,18 → 22,13
// |
// |
// Control bits: |
// Start_n/Stop. Writing a '0' starts the timer, '1' stops it. |
// Thus, ignoring this bit sets it to start. |
// (Start_n/Stop. This bit has been dropped. Writing to this |
// timer any value but zero starts it. Writing a zero |
// clears and stops it.) |
// AutoReload. If set, then on reset the timer automatically |
// loads the last set value and starts over. This is |
// useful for distinguishing between a one-time interrupt |
// timer, and a repetitive interval timer. |
// (COUNT: If set, the timer only ticks whenever an external |
// line goes high. What this external line is ... is |
// not specified here. This, however, breaks my |
// interface ideal of having our peripheral set not depend |
// upon anything. Hence, this is an advanced option |
// enabled at compile time only.) |
// (INTEN. Interrupt enable--reaching zero always creates an |
// interrupt, so this control bit isn't needed. The |
// interrupt controller can be used to mask the interrupt.) |
72,7 → 67,7
i_wb_cyc, i_wb_stb, i_wb_we, i_wb_data, |
o_wb_ack, o_wb_stall, o_wb_data, |
o_int); |
parameter BW = 32, VW = (BW-2); |
parameter BW = 32, VW = (BW-1); |
input i_clk, i_rst, i_ce; |
// Wishbone inputs |
input i_wb_cyc, i_wb_stb, i_wb_we; |
86,34 → 81,41
|
reg r_auto_reload, r_running; |
reg [(VW-1):0] r_reload_value; |
|
wire wb_write; |
assign wb_write = ((i_wb_cyc)&&(i_wb_stb)&&(i_wb_we)); |
|
initial r_running = 1'b0; |
initial r_auto_reload = 1'b0; |
always @(posedge i_clk) |
if (i_rst) |
begin |
r_running <= 1'b0; |
r_auto_reload <= 1'b0; |
end else if ((i_wb_cyc)&&(i_wb_stb)&&(i_wb_we)) |
begin |
r_running <= (~i_wb_data[(BW-1)])&&(|i_wb_data[(BW-2):0]); |
r_auto_reload <= (i_wb_data[(BW-2)]); |
else if (wb_write) |
r_running <= (|i_wb_data[(VW-1):0]); |
else if ((o_int)&&(~r_auto_reload)) |
r_running <= 1'b0; |
|
// If setting auto-reload mode, and the value to other |
// than zero, set the auto-reload value |
if ((i_wb_data[(BW-2)])&&(|i_wb_data[(BW-3):0])) |
r_reload_value <= i_wb_data[(BW-3):0]; |
end |
|
always @(posedge i_clk) |
if (wb_write) |
r_auto_reload <= (i_wb_data[(BW-1)]); |
|
// If setting auto-reload mode, and the value to other |
// than zero, set the auto-reload value |
always @(posedge i_clk) |
if ((wb_write)&&(i_wb_data[(BW-1)])&&(|i_wb_data[(VW-1):0])) |
r_reload_value <= i_wb_data[(VW-1):0]; |
|
|
reg [(VW-1):0] r_value; |
initial r_value = 0; |
always @(posedge i_clk) |
if ((r_running)&&(|r_value)&&(i_ce)) |
begin |
if (wb_write) |
r_value <= i_wb_data[(VW-1):0]; |
else if ((r_running)&&(i_ce)&&(~o_int)) |
r_value <= r_value - 1; |
end else if ((r_running)&&(r_auto_reload)) |
else if ((r_running)&&(r_auto_reload)&&(o_int)) |
r_value <= r_reload_value; |
else if ((~r_running)&&(i_wb_cyc)&&(i_wb_stb)&&(i_wb_we)) |
r_value <= i_wb_data[(VW-1):0]; |
|
// Set the interrupt on our last tick. |
initial o_int = 1'b0; |
128,6 → 130,6
o_wb_ack <= (i_wb_cyc)&&(i_wb_stb); |
assign o_wb_stall = 1'b0; |
|
assign o_wb_data = { ~r_running, r_auto_reload, r_value }; |
assign o_wb_data = { r_auto_reload, r_value }; |
|
endmodule |