URL
https://opencores.org/ocsvn/zipcpu/zipcpu/trunk
Subversion Repositories zipcpu
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- This comparison shows the changes necessary to convert path
/zipcpu/trunk
- from Rev 14 to Rev 15
- ↔ Reverse comparison
Rev 14 → Rev 15
/rtl/core/cpuops.v
42,6 → 42,13
assign w_rol_tmp = { i_a, i_a } << i_b[4:0]; |
wire [31:0] w_rol_result; |
assign w_rol_result = w_rol_tmp[63:32]; // Won't set flags |
wire [33:0] w_lsr_result, w_asr_result; |
wire signed [33:0] w_ia_input; |
assign w_ia_input = { i_a[31], i_a, 1'b0 }; |
assign w_asr_result = (|i_b[31:5])? {(34){i_a[31]}} |
: ( w_ia_input >>> (i_b[4:0]) );// ASR |
assign w_lsr_result = (|i_b[31:5])? 34'h00 |
: { 1'b0, i_a, 1'b0 } >> (i_b[4:0]);// LSR |
|
wire z, n, v; |
reg c, pre_sign, set_ovfl; |
68,8 → 75,8
4'hb: o_c <= i_a | i_b; // Or |
4'hc: o_c <= i_a ^ i_b; // Xor |
4'hd: { c, o_c } <= (|i_b[31:5])? 33'h00 : {1'b0, i_a } << i_b[4:0]; // LSL |
4'he: { c, o_c } <= (|i_b[31:5])? {(33){i_a[31]}}:{ i_a[31],i_a}>> (i_b[4:0]);// ASR |
4'hf: { c, o_c } <= (|i_b[31:5])? 33'h00 : { 1'b0, i_a } >> (i_b[4:0]);// LSR |
4'he: { o_c, c } <= w_asr_result[32:0];// ASR |
4'hf: { o_c, c } <= w_lsr_result[32:0];// LSR |
default: o_c <= i_b; // MOV, LDI |
endcase |
end |
/rtl/aux/busdelay.v
87,7 → 87,9
always @(posedge i_clk) |
o_wb_data <= i_dly_data; |
|
// Our only non-delayed line, yet still really delayed. |
assign o_wb_stall = ((i_wb_cyc)&&(o_dly_cyc)&&(i_dly_stall)); |
// Our only non-delayed line, yet still really delayed. Perhaps |
// there's a way to register this? |
// o_wb_stall <= (i_wb_cyc)&&(i_wb_stb) ... or some such? |
assign o_wb_stall = ((i_wb_cyc)&&(o_dly_cyc)&&(i_dly_stall)&&(~o_dly_stb)); |
|
endmodule |