URL
https://opencores.org/ocsvn/zipcpu/zipcpu/trunk
Subversion Repositories zipcpu
Compare Revisions
- This comparison shows the changes necessary to convert path
/zipcpu
- from Rev 126 to Rev 127
- ↔ Reverse comparison
Rev 126 → Rev 127
/trunk/sw/gcc-zippatch.patch
138,7 → 138,7
+ |
+struct gcc_targetm_common targetm_common = TARGETM_COMMON_INITIALIZER; |
diff -Naur '--exclude=*.swp' gcc-5.3.0-original/gcc/config/aarch64/aarch64-linux.h gcc-5.3.0-zip/gcc/config/aarch64/aarch64-linux.h |
--- gcc-5.3.0-original/gcc/config/aarch64/aarch64-linux.h 2016-04-13 12:14:18.252711082 -0400 |
--- gcc-5.3.0-original/gcc/config/aarch64/aarch64-linux.h 2016-04-21 20:04:11.745606740 -0400 |
+++ gcc-5.3.0-zip/gcc/config/aarch64/aarch64-linux.h 2015-07-24 12:00:26.000000000 -0400 |
@@ -21,7 +21,7 @@ |
#ifndef GCC_AARCH64_LINUX_H |
150,7 → 150,7
#undef ASAN_CC1_SPEC |
#define ASAN_CC1_SPEC "%{%:sanitize(address):-funwind-tables}" |
diff -Naur '--exclude=*.swp' gcc-5.3.0-original/gcc/config/alpha/linux-elf.h gcc-5.3.0-zip/gcc/config/alpha/linux-elf.h |
--- gcc-5.3.0-original/gcc/config/alpha/linux-elf.h 2016-04-13 12:14:18.252711082 -0400 |
--- gcc-5.3.0-original/gcc/config/alpha/linux-elf.h 2016-04-21 20:04:11.761606648 -0400 |
+++ gcc-5.3.0-zip/gcc/config/alpha/linux-elf.h 2015-01-05 07:33:28.000000000 -0500 |
@@ -23,8 +23,8 @@ |
#define EXTRA_SPECS \ |
164,7 → 164,7
#define CHOOSE_DYNAMIC_LINKER(G, U) "%{mglibc:" G ";:" U "}" |
#elif DEFAULT_LIBC == LIBC_GLIBC |
diff -Naur '--exclude=*.swp' gcc-5.3.0-original/gcc/config/arm/linux-eabi.h gcc-5.3.0-zip/gcc/config/arm/linux-eabi.h |
--- gcc-5.3.0-original/gcc/config/arm/linux-eabi.h 2016-04-13 12:14:18.252711082 -0400 |
--- gcc-5.3.0-original/gcc/config/arm/linux-eabi.h 2016-04-21 20:04:11.761606648 -0400 |
+++ gcc-5.3.0-zip/gcc/config/arm/linux-eabi.h 2015-01-05 07:33:28.000000000 -0500 |
@@ -68,8 +68,8 @@ |
GLIBC_DYNAMIC_LINKER_DEFAULT and TARGET_DEFAULT_FLOAT_ABI. */ |
178,7 → 178,7
|
#define GLIBC_DYNAMIC_LINKER \ |
diff -Naur '--exclude=*.swp' gcc-5.3.0-original/gcc/config/arm/linux-elf.h gcc-5.3.0-zip/gcc/config/arm/linux-elf.h |
--- gcc-5.3.0-original/gcc/config/arm/linux-elf.h 2016-04-13 12:14:18.252711082 -0400 |
--- gcc-5.3.0-original/gcc/config/arm/linux-elf.h 2016-04-21 20:04:11.761606648 -0400 |
+++ gcc-5.3.0-zip/gcc/config/arm/linux-elf.h 2015-06-23 05:26:54.000000000 -0400 |
@@ -62,7 +62,7 @@ |
|
190,7 → 190,7
#define LINUX_TARGET_LINK_SPEC "%{h*} \ |
%{static:-Bstatic} \ |
diff -Naur '--exclude=*.swp' gcc-5.3.0-original/gcc/config/bfin/linux.h gcc-5.3.0-zip/gcc/config/bfin/linux.h |
--- gcc-5.3.0-original/gcc/config/bfin/linux.h 2016-04-13 12:14:18.252711082 -0400 |
--- gcc-5.3.0-original/gcc/config/bfin/linux.h 2016-04-21 20:04:11.761606648 -0400 |
+++ gcc-5.3.0-zip/gcc/config/bfin/linux.h 2015-01-05 07:33:28.000000000 -0500 |
@@ -45,7 +45,7 @@ |
%{shared:-G -Bdynamic} \ |
202,7 → 202,7
|
#undef TARGET_SUPPORTS_SYNC_CALLS |
diff -Naur '--exclude=*.swp' gcc-5.3.0-original/gcc/config/cris/linux.h gcc-5.3.0-zip/gcc/config/cris/linux.h |
--- gcc-5.3.0-original/gcc/config/cris/linux.h 2016-04-13 12:14:18.252711082 -0400 |
--- gcc-5.3.0-original/gcc/config/cris/linux.h 2016-04-21 20:04:11.761606648 -0400 |
+++ gcc-5.3.0-zip/gcc/config/cris/linux.h 2015-01-05 07:33:28.000000000 -0500 |
@@ -102,7 +102,7 @@ |
#undef CRIS_DEFAULT_CPU_VERSION |
214,7 → 214,7
#undef CRIS_LINK_SUBTARGET_SPEC |
#define CRIS_LINK_SUBTARGET_SPEC \ |
diff -Naur '--exclude=*.swp' gcc-5.3.0-original/gcc/config/freebsd-spec.h gcc-5.3.0-zip/gcc/config/freebsd-spec.h |
--- gcc-5.3.0-original/gcc/config/freebsd-spec.h 2016-04-13 12:14:18.252711082 -0400 |
--- gcc-5.3.0-original/gcc/config/freebsd-spec.h 2016-04-21 20:04:11.761606648 -0400 |
+++ gcc-5.3.0-zip/gcc/config/freebsd-spec.h 2015-06-25 13:53:14.000000000 -0400 |
@@ -129,9 +129,9 @@ |
#endif |
229,7 → 229,7
|
/* NOTE: The freebsd-spec.h header is included also for various |
diff -Naur '--exclude=*.swp' gcc-5.3.0-original/gcc/config/frv/linux.h gcc-5.3.0-zip/gcc/config/frv/linux.h |
--- gcc-5.3.0-original/gcc/config/frv/linux.h 2016-04-13 12:14:18.256711056 -0400 |
--- gcc-5.3.0-original/gcc/config/frv/linux.h 2016-04-21 20:04:11.761606648 -0400 |
+++ gcc-5.3.0-zip/gcc/config/frv/linux.h 2015-01-05 07:33:28.000000000 -0500 |
@@ -34,7 +34,7 @@ |
#define ENDFILE_SPEC \ |
241,7 → 241,7
#undef LINK_SPEC |
#define LINK_SPEC "\ |
diff -Naur '--exclude=*.swp' gcc-5.3.0-original/gcc/config/i386/gnu.h gcc-5.3.0-zip/gcc/config/i386/gnu.h |
--- gcc-5.3.0-original/gcc/config/i386/gnu.h 2016-04-13 12:14:18.256711056 -0400 |
--- gcc-5.3.0-original/gcc/config/i386/gnu.h 2016-04-21 20:04:11.761606648 -0400 |
+++ gcc-5.3.0-zip/gcc/config/i386/gnu.h 2015-01-05 07:33:28.000000000 -0500 |
@@ -22,7 +22,7 @@ |
#define GNU_USER_LINK_EMULATION "elf_i386" |
253,7 → 253,7
#undef STARTFILE_SPEC |
#if defined HAVE_LD_PIE |
diff -Naur '--exclude=*.swp' gcc-5.3.0-original/gcc/config/i386/kfreebsd-gnu64.h gcc-5.3.0-zip/gcc/config/i386/kfreebsd-gnu64.h |
--- gcc-5.3.0-original/gcc/config/i386/kfreebsd-gnu64.h 2016-04-13 12:14:18.256711056 -0400 |
--- gcc-5.3.0-original/gcc/config/i386/kfreebsd-gnu64.h 2016-04-21 20:04:11.761606648 -0400 |
+++ gcc-5.3.0-zip/gcc/config/i386/kfreebsd-gnu64.h 2015-01-05 07:33:28.000000000 -0500 |
@@ -22,6 +22,6 @@ |
#define GNU_USER_LINK_EMULATION64 "elf_x86_64_fbsd" |
266,7 → 266,7
+#define GLIBC_DYNAMIC_LINKER64 "/lib/ld-kfreebsd-x86-64.so.1" |
+#define GLIBC_DYNAMIC_LINKERX32 "/lib/ld-kfreebsd-x32.so.1" |
diff -Naur '--exclude=*.swp' gcc-5.3.0-original/gcc/config/i386/kfreebsd-gnu.h gcc-5.3.0-zip/gcc/config/i386/kfreebsd-gnu.h |
--- gcc-5.3.0-original/gcc/config/i386/kfreebsd-gnu.h 2016-04-13 12:14:18.256711056 -0400 |
--- gcc-5.3.0-original/gcc/config/i386/kfreebsd-gnu.h 2016-04-21 20:04:11.761606648 -0400 |
+++ gcc-5.3.0-zip/gcc/config/i386/kfreebsd-gnu.h 2015-01-05 07:33:28.000000000 -0500 |
@@ -19,4 +19,4 @@ |
<http://www.gnu.org/licenses/>. */ |
275,7 → 275,7
-#define GLIBC_DYNAMIC_LINKER "/tools/lib/ld.so.1" |
+#define GLIBC_DYNAMIC_LINKER "/lib/ld.so.1" |
diff -Naur '--exclude=*.swp' gcc-5.3.0-original/gcc/config/i386/linux64.h gcc-5.3.0-zip/gcc/config/i386/linux64.h |
--- gcc-5.3.0-original/gcc/config/i386/linux64.h 2016-04-13 12:14:18.256711056 -0400 |
--- gcc-5.3.0-original/gcc/config/i386/linux64.h 2016-04-21 20:04:11.761606648 -0400 |
+++ gcc-5.3.0-zip/gcc/config/i386/linux64.h 2015-01-05 07:33:28.000000000 -0500 |
@@ -27,6 +27,6 @@ |
#define GNU_USER_LINK_EMULATION64 "elf_x86_64" |
288,7 → 288,7
+#define GLIBC_DYNAMIC_LINKER64 "/lib64/ld-linux-x86-64.so.2" |
+#define GLIBC_DYNAMIC_LINKERX32 "/libx32/ld-linux-x32.so.2" |
diff -Naur '--exclude=*.swp' gcc-5.3.0-original/gcc/config/i386/linux.h gcc-5.3.0-zip/gcc/config/i386/linux.h |
--- gcc-5.3.0-original/gcc/config/i386/linux.h 2016-04-13 12:14:18.256711056 -0400 |
--- gcc-5.3.0-original/gcc/config/i386/linux.h 2016-04-21 20:04:11.761606648 -0400 |
+++ gcc-5.3.0-zip/gcc/config/i386/linux.h 2015-01-05 07:33:28.000000000 -0500 |
@@ -20,4 +20,4 @@ |
<http://www.gnu.org/licenses/>. */ |
297,7 → 297,7
-#define GLIBC_DYNAMIC_LINKER "/tools/lib/ld-linux.so.2" |
+#define GLIBC_DYNAMIC_LINKER "/lib/ld-linux.so.2" |
diff -Naur '--exclude=*.swp' gcc-5.3.0-original/gcc/config/ia64/linux.h gcc-5.3.0-zip/gcc/config/ia64/linux.h |
--- gcc-5.3.0-original/gcc/config/ia64/linux.h 2016-04-13 12:14:18.256711056 -0400 |
--- gcc-5.3.0-original/gcc/config/ia64/linux.h 2016-04-21 20:04:11.761606648 -0400 |
+++ gcc-5.3.0-zip/gcc/config/ia64/linux.h 2015-01-05 07:33:28.000000000 -0500 |
@@ -55,7 +55,7 @@ |
/* Define this for shared library support because it isn't in the main |
309,7 → 309,7
#undef LINK_SPEC |
#define LINK_SPEC "\ |
diff -Naur '--exclude=*.swp' gcc-5.3.0-original/gcc/config/knetbsd-gnu.h gcc-5.3.0-zip/gcc/config/knetbsd-gnu.h |
--- gcc-5.3.0-original/gcc/config/knetbsd-gnu.h 2016-04-13 12:14:18.256711056 -0400 |
--- gcc-5.3.0-original/gcc/config/knetbsd-gnu.h 2016-04-21 20:04:11.761606648 -0400 |
+++ gcc-5.3.0-zip/gcc/config/knetbsd-gnu.h 2015-01-05 07:33:28.000000000 -0500 |
@@ -32,4 +32,4 @@ |
|
318,7 → 318,7
-#define GNU_USER_DYNAMIC_LINKER "/tools/lib/ld.so.1" |
+#define GNU_USER_DYNAMIC_LINKER "/lib/ld.so.1" |
diff -Naur '--exclude=*.swp' gcc-5.3.0-original/gcc/config/kopensolaris-gnu.h gcc-5.3.0-zip/gcc/config/kopensolaris-gnu.h |
--- gcc-5.3.0-original/gcc/config/kopensolaris-gnu.h 2016-04-13 12:14:18.256711056 -0400 |
--- gcc-5.3.0-original/gcc/config/kopensolaris-gnu.h 2016-04-21 20:04:11.761606648 -0400 |
+++ gcc-5.3.0-zip/gcc/config/kopensolaris-gnu.h 2015-01-05 07:33:28.000000000 -0500 |
@@ -31,5 +31,4 @@ |
while (0) |
328,7 → 328,7
- |
+#define GNU_USER_DYNAMIC_LINKER "/lib/ld.so.1" |
diff -Naur '--exclude=*.swp' gcc-5.3.0-original/gcc/config/linux.h gcc-5.3.0-zip/gcc/config/linux.h |
--- gcc-5.3.0-original/gcc/config/linux.h 2016-04-13 12:14:18.256711056 -0400 |
--- gcc-5.3.0-original/gcc/config/linux.h 2016-04-21 20:04:11.761606648 -0400 |
+++ gcc-5.3.0-zip/gcc/config/linux.h 2015-01-05 07:33:28.000000000 -0500 |
@@ -73,10 +73,10 @@ |
GLIBC_DYNAMIC_LINKER must be defined for each target using them, or |
346,7 → 346,7
#define BIONIC_DYNAMIC_LINKER32 "/system/bin/linker" |
#define BIONIC_DYNAMIC_LINKER64 "/system/bin/linker64" |
diff -Naur '--exclude=*.swp' gcc-5.3.0-original/gcc/config/lm32/uclinux-elf.h gcc-5.3.0-zip/gcc/config/lm32/uclinux-elf.h |
--- gcc-5.3.0-original/gcc/config/lm32/uclinux-elf.h 2016-04-13 12:14:18.256711056 -0400 |
--- gcc-5.3.0-original/gcc/config/lm32/uclinux-elf.h 2016-04-21 20:04:11.761606648 -0400 |
+++ gcc-5.3.0-zip/gcc/config/lm32/uclinux-elf.h 2015-01-05 07:33:28.000000000 -0500 |
@@ -67,7 +67,7 @@ |
%{shared:-shared} \ |
358,7 → 358,7
#define TARGET_OS_CPP_BUILTINS() GNU_USER_TARGET_OS_CPP_BUILTINS() |
|
diff -Naur '--exclude=*.swp' gcc-5.3.0-original/gcc/config/m68k/linux.h gcc-5.3.0-zip/gcc/config/m68k/linux.h |
--- gcc-5.3.0-original/gcc/config/m68k/linux.h 2016-04-13 12:14:18.256711056 -0400 |
--- gcc-5.3.0-original/gcc/config/m68k/linux.h 2016-04-21 20:04:11.761606648 -0400 |
+++ gcc-5.3.0-zip/gcc/config/m68k/linux.h 2015-01-05 07:33:28.000000000 -0500 |
@@ -71,7 +71,7 @@ |
When the -shared link option is used a final link is not being |
370,7 → 370,7
#undef LINK_SPEC |
#define LINK_SPEC "-m m68kelf %{shared} \ |
diff -Naur '--exclude=*.swp' gcc-5.3.0-original/gcc/config/microblaze/linux.h gcc-5.3.0-zip/gcc/config/microblaze/linux.h |
--- gcc-5.3.0-original/gcc/config/microblaze/linux.h 2016-04-13 12:14:18.256711056 -0400 |
--- gcc-5.3.0-original/gcc/config/microblaze/linux.h 2016-04-21 20:04:11.761606648 -0400 |
+++ gcc-5.3.0-zip/gcc/config/microblaze/linux.h 2015-05-28 10:08:19.000000000 -0400 |
@@ -28,7 +28,7 @@ |
#undef TLS_NEEDS_GOT |
382,7 → 382,7
#define SUBTARGET_EXTRA_SPECS \ |
{ "dynamic_linker", DYNAMIC_LINKER } |
diff -Naur '--exclude=*.swp' gcc-5.3.0-original/gcc/config/mips/linux.h gcc-5.3.0-zip/gcc/config/mips/linux.h |
--- gcc-5.3.0-original/gcc/config/mips/linux.h 2016-04-13 12:14:18.256711056 -0400 |
--- gcc-5.3.0-original/gcc/config/mips/linux.h 2016-04-21 20:04:11.761606648 -0400 |
+++ gcc-5.3.0-zip/gcc/config/mips/linux.h 2015-01-05 07:33:28.000000000 -0500 |
@@ -22,20 +22,20 @@ |
#define GNU_USER_LINK_EMULATIONN32 "elf32%{EB:b}%{EL:l}tsmipn32" |
412,7 → 412,7
#define BIONIC_DYNAMIC_LINKERN32 "/system/bin/linker32" |
#define GNU_USER_DYNAMIC_LINKERN32 \ |
diff -Naur '--exclude=*.swp' gcc-5.3.0-original/gcc/config/mn10300/linux.h gcc-5.3.0-zip/gcc/config/mn10300/linux.h |
--- gcc-5.3.0-original/gcc/config/mn10300/linux.h 2016-04-13 12:14:18.256711056 -0400 |
--- gcc-5.3.0-original/gcc/config/mn10300/linux.h 2016-04-21 20:04:11.761606648 -0400 |
+++ gcc-5.3.0-zip/gcc/config/mn10300/linux.h 2015-01-05 07:33:28.000000000 -0500 |
@@ -32,7 +32,7 @@ |
#undef ASM_SPEC |
424,7 → 424,7
#undef LINK_SPEC |
#define LINK_SPEC "%{mrelax:--relax} %{shared:-shared} \ |
diff -Naur '--exclude=*.swp' gcc-5.3.0-original/gcc/config/pa/pa-linux.h gcc-5.3.0-zip/gcc/config/pa/pa-linux.h |
--- gcc-5.3.0-original/gcc/config/pa/pa-linux.h 2016-04-13 12:14:18.256711056 -0400 |
--- gcc-5.3.0-original/gcc/config/pa/pa-linux.h 2016-04-21 20:04:11.761606648 -0400 |
+++ gcc-5.3.0-zip/gcc/config/pa/pa-linux.h 2015-09-24 20:04:26.000000000 -0400 |
@@ -37,7 +37,7 @@ |
/* Define this for shared library support because it isn't in the main |
436,7 → 436,7
#undef LINK_SPEC |
#define LINK_SPEC "\ |
diff -Naur '--exclude=*.swp' gcc-5.3.0-original/gcc/config/rs6000/linux64.h gcc-5.3.0-zip/gcc/config/rs6000/linux64.h |
--- gcc-5.3.0-original/gcc/config/rs6000/linux64.h 2016-04-13 12:14:18.256711056 -0400 |
--- gcc-5.3.0-original/gcc/config/rs6000/linux64.h 2016-04-21 20:04:11.761606648 -0400 |
+++ gcc-5.3.0-zip/gcc/config/rs6000/linux64.h 2015-03-09 19:18:57.000000000 -0400 |
@@ -357,14 +357,14 @@ |
#undef LINK_OS_DEFAULT_SPEC |
459,7 → 459,7
#define CHOOSE_DYNAMIC_LINKER(G, U) "%{mglibc:" G ";:" U "}" |
#elif DEFAULT_LIBC == LIBC_GLIBC |
diff -Naur '--exclude=*.swp' gcc-5.3.0-original/gcc/config/rs6000/sysv4.h gcc-5.3.0-zip/gcc/config/rs6000/sysv4.h |
--- gcc-5.3.0-original/gcc/config/rs6000/sysv4.h 2016-04-13 12:14:18.256711056 -0400 |
--- gcc-5.3.0-original/gcc/config/rs6000/sysv4.h 2016-04-21 20:04:11.761606648 -0400 |
+++ gcc-5.3.0-zip/gcc/config/rs6000/sysv4.h 2015-09-24 09:46:45.000000000 -0400 |
@@ -757,8 +757,8 @@ |
|
473,7 → 473,7
#define CHOOSE_DYNAMIC_LINKER(G, U) "%{mglibc:" G ";:" U "}" |
#elif !defined (DEFAULT_LIBC) || DEFAULT_LIBC == LIBC_GLIBC |
diff -Naur '--exclude=*.swp' gcc-5.3.0-original/gcc/config/s390/linux.h gcc-5.3.0-zip/gcc/config/s390/linux.h |
--- gcc-5.3.0-original/gcc/config/s390/linux.h 2016-04-13 12:14:18.256711056 -0400 |
--- gcc-5.3.0-original/gcc/config/s390/linux.h 2016-04-21 20:04:11.761606648 -0400 |
+++ gcc-5.3.0-zip/gcc/config/s390/linux.h 2015-05-11 03:14:10.000000000 -0400 |
@@ -60,8 +60,8 @@ |
#define MULTILIB_DEFAULTS { "m31" } |
487,7 → 487,7
#undef LINK_SPEC |
#define LINK_SPEC \ |
diff -Naur '--exclude=*.swp' gcc-5.3.0-original/gcc/config/sh/linux.h gcc-5.3.0-zip/gcc/config/sh/linux.h |
--- gcc-5.3.0-original/gcc/config/sh/linux.h 2016-04-13 12:14:18.256711056 -0400 |
--- gcc-5.3.0-original/gcc/config/sh/linux.h 2016-04-21 20:04:11.761606648 -0400 |
+++ gcc-5.3.0-zip/gcc/config/sh/linux.h 2015-01-05 07:33:28.000000000 -0500 |
@@ -43,7 +43,7 @@ |
|
499,7 → 499,7
#undef SUBTARGET_LINK_EMUL_SUFFIX |
#define SUBTARGET_LINK_EMUL_SUFFIX "_linux" |
diff -Naur '--exclude=*.swp' gcc-5.3.0-original/gcc/config/sparc/linux64.h gcc-5.3.0-zip/gcc/config/sparc/linux64.h |
--- gcc-5.3.0-original/gcc/config/sparc/linux64.h 2016-04-13 12:14:18.256711056 -0400 |
--- gcc-5.3.0-original/gcc/config/sparc/linux64.h 2016-04-21 20:04:11.761606648 -0400 |
+++ gcc-5.3.0-zip/gcc/config/sparc/linux64.h 2015-01-05 07:33:28.000000000 -0500 |
@@ -84,8 +84,8 @@ |
When the -shared link option is used a final link is not being |
522,7 → 522,7
%{!static: \ |
%{rdynamic:-export-dynamic} \ |
diff -Naur '--exclude=*.swp' gcc-5.3.0-original/gcc/config/sparc/linux.h gcc-5.3.0-zip/gcc/config/sparc/linux.h |
--- gcc-5.3.0-original/gcc/config/sparc/linux.h 2016-04-13 12:14:18.256711056 -0400 |
--- gcc-5.3.0-original/gcc/config/sparc/linux.h 2016-04-21 20:04:11.761606648 -0400 |
+++ gcc-5.3.0-zip/gcc/config/sparc/linux.h 2015-01-05 07:33:28.000000000 -0500 |
@@ -83,7 +83,7 @@ |
When the -shared link option is used a final link is not being |
534,7 → 534,7
#undef LINK_SPEC |
#define LINK_SPEC "-m elf32_sparc %{shared:-shared} \ |
diff -Naur '--exclude=*.swp' gcc-5.3.0-original/gcc/config/vax/linux.h gcc-5.3.0-zip/gcc/config/vax/linux.h |
--- gcc-5.3.0-original/gcc/config/vax/linux.h 2016-04-13 12:14:18.256711056 -0400 |
--- gcc-5.3.0-original/gcc/config/vax/linux.h 2016-04-21 20:04:11.761606648 -0400 |
+++ gcc-5.3.0-zip/gcc/config/vax/linux.h 2015-01-05 07:33:28.000000000 -0500 |
@@ -41,7 +41,7 @@ |
%{!shared: \ |
546,7 → 546,7
|
#undef WCHAR_TYPE |
diff -Naur '--exclude=*.swp' gcc-5.3.0-original/gcc/config/xtensa/linux.h gcc-5.3.0-zip/gcc/config/xtensa/linux.h |
--- gcc-5.3.0-original/gcc/config/xtensa/linux.h 2016-04-13 12:14:18.256711056 -0400 |
--- gcc-5.3.0-original/gcc/config/xtensa/linux.h 2016-04-21 20:04:11.761606648 -0400 |
+++ gcc-5.3.0-zip/gcc/config/xtensa/linux.h 2015-01-05 07:33:28.000000000 -0500 |
@@ -44,7 +44,7 @@ |
%{mlongcalls:--longcalls} \ |
696,8 → 696,8
+ |
diff -Naur '--exclude=*.swp' gcc-5.3.0-original/gcc/config/zip/zip.c gcc-5.3.0-zip/gcc/config/zip/zip.c |
--- gcc-5.3.0-original/gcc/config/zip/zip.c 1969-12-31 19:00:00.000000000 -0500 |
+++ gcc-5.3.0-zip/gcc/config/zip/zip.c 2016-04-07 16:23:35.651592937 -0400 |
@@ -0,0 +1,2126 @@ |
+++ gcc-5.3.0-zip/gcc/config/zip/zip.c 2016-04-21 16:52:37.544818916 -0400 |
@@ -0,0 +1,2174 @@ |
+//////////////////////////////////////////////////////////////////////////////// |
+// |
+// Filename: zip.c |
933,6 → 933,7
+ if (dbg) zip_debug_rtx(x); |
+ switch(GET_CODE(x)) { |
+ case REG: |
+ gcc_assert(is_ZIP_REG(REGNO(x))); |
+ fprintf(file, "(%s)", reg_names[REGNO(x)]); |
+ break; |
+ case SYMBOL_REF: |
955,7 → 956,8
+ fprintf(stderr, "Unsupported address construct\n"); |
+ zip_debug_rtx(x); |
+ abort(); |
+ } if (CONST_INT_P(XEXP(x, 1))) { |
+ } gcc_assert(is_ZIP_REG(REGNO(XEXP(x,0)))); |
+ if (CONST_INT_P(XEXP(x, 1))) { |
+ if (INTVAL(XEXP(x,1))!=0) { |
+ fprintf(file, "%ld(%s)", |
+ INTVAL(XEXP(x, 1)), |
1198,6 → 1200,8
+ zip_compute_frame(); |
+ |
+ if (dbg) fprintf(stderr, "PROLOGUE: Computing Prologue instructions\n"); |
+ if (dbg) fprintf(stderr, "PROLOGUE: SP-FP offset is %d\n", |
+ cfun->machine->sp_fp_offset); |
+ if (cfun->machine->size_for_adjusting_sp != 0) { |
+ insn = emit_insn(gen_subsi3(stack_pointer_rtx, |
+ stack_pointer_rtx, |
1212,6 → 1216,10
+ int offset = 0, regno; |
+ for(regno=0; regno < FIRST_PSEUDO_REGISTER; regno++) { |
+ if (zip_save_reg(regno)) { |
+ if (dbg) fprintf(stderr, |
+ "PROLOGUE: Saving R%d in %d+%d(SP)\n", |
+ regno, cfun->machine->sp_fp_offset, |
+ offset); |
+ insn=emit_insn(gen_movsi_sto_off( |
+ stack_pointer_rtx, |
+ GEN_INT(cfun->machine->sp_fp_offset |
2020,24 → 2028,34
+ debug_rtx(x); |
+ break; |
+ case REG: { |
+ char buf[25]; |
+ char buf[25], mstr[4]; |
+ mstr[0] = '\0'; |
+ if (GET_MODE(x) == SImode) |
+ strcpy(mstr, ":SI"); |
+ else if (GET_MODE(x) == DImode) |
+ strcpy(mstr, ":DI"); |
+ else if (GET_MODE(x) == VOIDmode) |
+ strcpy(mstr, ":V"); |
+ if (REGNO(x) == zip_PC) |
+ sprintf(buf, "(PC)"); |
+ sprintf(buf, "(PC%s)", mstr); |
+ else if (REGNO(x) == zip_CC) |
+ sprintf(buf, "(CC)"); |
+ sprintf(buf, "(CC%s)", mstr); |
+ else if (REGNO(x) == zip_SP) |
+ sprintf(buf, "(SP)"); |
+ sprintf(buf, "(SP%s)", mstr); |
+ else if (REGNO(x) == zip_FP) |
+ sprintf(buf, "(REG FP)"); |
+ sprintf(buf, "(REG%s FP)", mstr); |
+ else if (REGNO(x) == zip_GOT) |
+ sprintf(buf, "(REG GBL)"); |
+ sprintf(buf, "(REG%s GBL)", mstr); |
+ else if (FUNCTION_VALUE_REGNO_P(REGNO(x))) |
+ sprintf(buf, "(REG RTN-VL)"); |
+ sprintf(buf, "(REG%s RTN-VL)", mstr); |
+ else if (REGNO(x) == RETURN_ADDRESS_REGNUM) |
+ sprintf(buf, "(REG RTN-AD)"); |
+ sprintf(buf, "(REG%s RTN-AD)", mstr); |
+ else |
+ sprintf(buf, "(REG %d)", REGNO(x)); |
+ zip_debug_print_m(pfx, lvl, buf, GET_MODE(x)); |
+ sprintf(buf, "(REG%s %d)", mstr, REGNO(x)); |
+ if (mstr[0]) |
+ zip_debug_print(pfx, lvl, buf); |
+ else |
+ zip_debug_print_m(pfx, lvl, buf, GET_MODE(x)); |
+ } break; |
+ case IF_THEN_ELSE: // 51 |
+ zip_debug_print(pfx, lvl, "(IF-THEN-ELSE"); |
2053,7 → 2071,7
+ zip_debug_print(pfx, lvl, "(CC0)"); |
+ break; |
+ case COMPARE: |
+ zip_debug_print(pfx, lvl, "(COMPARE"); |
+ zip_debug_print_m(pfx, lvl, "(COMPARE", GET_MODE(x)); |
+ zip_debug_rtx_1(pfx, XEXP(x,0),lvl+1); |
+ zip_debug_rtx_1(pfx, XEXP(x,1),lvl+1); |
+ zip_debug_print(pfx, lvl, ")"); |
2218,6 → 2236,24
+ zip_debug_print(pfx, lvl, ")"); |
+ }} |
+ break; |
+ case ASHIFT: |
+ zip_debug_print_m(pfx, lvl, "(ASHIFT", GET_MODE(x)); |
+ zip_debug_rtx_1(pfx, XEXP(x,0),lvl+1); |
+ zip_debug_rtx_1(pfx, XEXP(x,1),lvl+1); |
+ zip_debug_print(pfx, lvl, ")"); |
+ break; |
+ case ASHIFTRT: |
+ zip_debug_print_m(pfx, lvl, "(ASHIFTRT", GET_MODE(x)); |
+ zip_debug_rtx_1(pfx, XEXP(x,0),lvl+1); |
+ zip_debug_rtx_1(pfx, XEXP(x,1),lvl+1); |
+ zip_debug_print(pfx, lvl, ")"); |
+ break; |
+ case LSHIFTRT: |
+ zip_debug_print_m(pfx, lvl, "(LSHIFTRT", GET_MODE(x)); |
+ zip_debug_rtx_1(pfx, XEXP(x,0),lvl+1); |
+ zip_debug_rtx_1(pfx, XEXP(x,1),lvl+1); |
+ zip_debug_print(pfx, lvl, ")"); |
+ break; |
+ default: |
+ { char buf[128]; |
+ sprintf(buf, "(? = %d) -- calling DEBUG-RTX", GET_CODE(x)); |
2414,15 → 2450,17
+ |
+ if (dbg) fprintf(stderr, "is ZIP-CONST-ADDRESS?\n"); |
+ if (dbg) zip_debug_rtx(x); |
+ if ((GET_MODE(x) != SImode)&&(GET_MODE(x) != VOIDmode)) |
+ if ((GET_MODE(x) != SImode)&&(GET_MODE(x) != VOIDmode)) { |
+ fprintf(stderr, "is ZIP-CONST-ADDRESS? -> NO, BAD MODE\n"); |
+ return false; |
+ } |
+ if ((GET_CODE(x) == LABEL_REF) |
+ ||(GET_CODE(x) == CODE_LABEL) |
+ ||(GET_CODE(x) == SYMBOL_REF)) { |
+ if (dbg) fprintf(stderr, "is ZIP-CONST-ADDRESS? -> YES!\n"); |
+ if (dbg) fprintf(stderr, "is ZIP-CONST-ADDRESS? -> YES! (LBL)\n"); |
+ return true; |
+ } else if (CONST_INT_P(x)) { |
+ if (dbg) fprintf(stderr, "is ZIP-CONST-ADDRESS? -> YES!\n"); |
+ if (dbg) fprintf(stderr, "is ZIP-CONST-ADDRESS? -> YES! (INT)\n"); |
+ return true; |
+ } else if (GET_CODE(x) == PLUS) { |
+ if (dbg) fprintf(stderr, "is ZIP-CONST-ADDRESS(PLUS)\n"); |
2535,6 → 2573,7
+ } |
+} |
+ |
+/* |
+const char *zip_binary_movsicc(rtx_code condition, const char *op, const int opno) { |
+ static char result[64] = ""; |
+ switch(condition) { |
2581,31 → 2620,31
+ return NULL; |
+ } return result; |
+} |
+*/ |
+ |
+const char *zip_tertiary_movsicc(rtx condition, const char *optrue, const char *opfalse) { |
+ static char result[64] = ""; |
+ switch(GET_CODE(condition)) { |
+ case EQ: sprintf(result,"%s\t%%3,%%0\n\t%s.Z\t%%2,%%0", opfalse, optrue); break; |
+ case NE: sprintf(result,"%s\t%%3,%%0\n\t%s.NZ\t%%2,%%0", opfalse, optrue); break; |
+ case LT: sprintf(result,"%s\t%%3,%%0\n\t%s.LT\t%%2,%%0", opfalse, optrue); break; |
+ case GT: sprintf(result,"%s\t%%3,%%0\n\t%s.GT\t%%2,%%0", opfalse, optrue); break; |
+ // LE doesn't exist on a Zip CPU. Accomplish this by |
+ // reversing the condition: i.e., load the false value into |
+ // the register, and the on condition load the true value. |
+ case LE: sprintf(result,"%s\t%%2,%%0\n\t%s.GT\t%%3,%%0", optrue, opfalse); break; |
+ case GE: sprintf(result,"%s\t%%3,%%0\n\t%s.GE\t%%2,%%0", opfalse, optrue); break; |
+ case LTU: sprintf(result,"%s\t%%3,%%0\n\t%s.C\t%%2,%%0", opfalse, optrue); break; |
+ // |
+ case GTU: sprintf(result,"%s\t%%2,%%0\n\t%s.C\t%%3,%%0\n\t%s.Z\t%%3,%%0", optrue, opfalse, opfalse); break; |
+ case LEU: sprintf(result,"%s\t%%3,%%0\n\t%s.C\t%%2,%%0\n\t%s.Z\t%%2,%%0", opfalse, optrue, optrue); break; |
+ case GEU: sprintf(result,"%s\t%%2,%%0\n\t%s.C\t%%3,%%0\n", optrue, opfalse); break; |
+ default: |
+ internal_error("MOVSICC Unsupported condition"); |
+ return NULL; |
+ } return result; |
+bool |
+zip_supported_condition(int c) { |
+ switch(c) { |
+ case NE: case LT: case EQ: case GT: case GE: case LTU: |
+ return true; |
+ break; |
+ default: |
+ break; |
+ } return false; |
+} |
+ |
+const char *zip_movsicc(rtx dst, rtx condition, rtx iftrue, rtx iffalse) { |
+bool |
+zip_signed_comparison(int c) { |
+ switch(c) { |
+ case NE: case LT: case EQ: case GT: case GE: |
+ return true; |
+ default: |
+ break; |
+ } return false; |
+} |
+ |
+void |
+zip_expand_movsicc(rtx dst, rtx condition, rtx iftrue, rtx iffalse) { |
+ const bool dbg = ((ALL_DEBUG_ON)||(false))&&(!ALL_DEBUG_OFF); |
+ if (dbg) fprintf(stderr, "ZIP::MOVSICC\n"); |
+ if (dbg) zip_debug_rtx_pfx("DST", dst); |
2612,74 → 2651,76
+ if (dbg) zip_debug_rtx_pfx("CND", condition); |
+ if (dbg) zip_debug_rtx_pfx("TRU", iftrue); |
+ if (dbg) zip_debug_rtx_pfx("FAL", iffalse); |
+ if ((REG_P(iftrue))&&(REGNO(dst)==REGNO(iftrue))) { |
+ if (dbg) fprintf(stderr, "ZIP::MOVSICC -- CASE if(X) -> R\n"); |
+ if (zip_legitimate_move_operand_p(SImode, iffalse, true)) |
+ return zip_binary_movsicc(reverse_condition(GET_CODE(condition)), "MOV", 3); |
+ else if (zip_const_address_operand(iffalse)) |
+ return zip_binary_movsicc(reverse_condition(GET_CODE(condition)), "LDI", 3); |
+ else if (zip_const_address_operand(iffalse)) |
+ return zip_binary_movsicc(reverse_condition(GET_CODE(condition)), "LDI", 3); |
+ else if ((MEM_P(iffalse))&&(zip_legitimate_opb(XEXP(iffalse,0), true))) |
+ return zip_binary_movsicc(reverse_condition(GET_CODE(condition)), "LOD", 3); |
+ else { |
+ internal_error("MOVSICC Unsupported mode"); |
+ return NULL; |
+ |
+ // Start with the condition |
+ rtx cmpa = XEXP(condition,0), cmpb=XEXP(condition,1); |
+ enum rtx_code cmpcode = GET_CODE(condition); |
+ |
+ //; Do we need to swap or adjust the condition? |
+ if (zip_supported_condition((int)cmpcode)) { |
+ // Keep everything as is |
+ } else if ((zip_supported_condition(reverse_condition(cmpcode))) |
+ &&(!MEM_P(iffalse))) { |
+ rtx tem = iffalse; |
+ iffalse = iftrue; |
+ iftrue = tem; |
+ |
+ cmpcode = reverse_condition(cmpcode); |
+ } else if ((zip_supported_condition((int)swap_condition(cmpcode))) |
+ &&((REG_P(cmpb))||(can_create_pseudo_p()))) { |
+ rtx tem = cmpa; |
+ cmpa = cmpb; |
+ cmpa = tem; |
+ cmpcode = swap_condition(cmpcode); |
+ |
+ if ((GET_CODE(cmpa)==PLUS)&&(zip_signed_comparison((int)cmpcode)) |
+ &&(REG_P(XEXP(cmpa,0))) |
+ &&(CONST_INT_P(XEXP(cmpa,1))) |
+ &&(abs(INTVAL(XEXP(cmpa,1)))<(1<<17))) { |
+ |
+ // If we were doing CMP x(Rb),Ra |
+ // and we just changed it to CMP Ra,x(Rb) |
+ // adjust it to CMP -x(Ra),Rb |
+ cmpb = plus_constant(SImode, cmpb, -INTVAL(XEXP(cmpa,1))); |
+ cmpa = XEXP(cmpa,0); |
+ } else if (!REG_P(cmpa)) { |
+ // Otherwise, if we had anything else in Rb other than |
+ // a register ... such as a constant, then load it into |
+ // a register before comparing it. So |
+ // CMP x,Ra |
+ // became |
+ // CMP Ra,x |
+ // now becomes |
+ // LDI x,Rt |
+ // CMP Ra,Rt |
+ // (We already tested for can_create_pseudo_p() above..) |
+ tem = gen_reg_rtx(SImode); |
+ emit_move_insn(tem, cmpa); |
+ cmpa = tem; |
+ } |
+ } if ((REG_P(iftrue))&&(REGNO(dst)==REGNO(iftrue))) { |
+ if (dbg) fprintf(stderr, "ZIP::MOVSICC -- CASE if(!X) -> R\n"); |
+ if (zip_legitimate_move_operand_p(SImode, iftrue, true)) |
+ return zip_binary_movsicc(GET_CODE(condition), "MOV",2); |
+ else if (zip_const_address_operand(iffalse)) |
+ return zip_binary_movsicc(GET_CODE(condition), "LDI",2); |
+ else if (zip_const_address_operand(iffalse)) |
+ return zip_binary_movsicc(GET_CODE(condition), "LDI",2); |
+ else if ((MEM_P(iffalse))&&(zip_legitimate_opb(XEXP(iffalse,0), true))) |
+ return zip_binary_movsicc(GET_CODE(condition), "LOD",2); |
+ else { |
+ internal_error("MOVSICC Unsupported mode"); |
+ return NULL; |
+ } |
+ } if ((zip_const_address_operand(iftrue))&&(zip_const_address_operand(iffalse))) { |
+ if (dbg) fprintf(stderr, "ZIP::MOVSICC -- IF(X) #1 ELSE #2\n"); |
+ return zip_tertiary_movsicc(condition, "LDI", "LDI"); |
+ } if ((zip_const_address_operand(iftrue))&&(zip_legitimate_move_operand_p(SImode, iffalse, true))) { |
+ if (dbg) fprintf(stderr, "ZIP::MOVSICC -- IF(X) #1 ELSE A+B\n"); |
+ return zip_tertiary_movsicc(condition, "LDI", "MOV"); |
+ } if ((zip_legitimate_move_operand_p(SImode, iftrue, true))&&(zip_const_address_operand(iffalse))) { |
+ if (dbg) fprintf(stderr, "ZIP::MOVSICC -- IF(X) A+B ELSE #x\n"); |
+ return zip_tertiary_movsicc(condition, "MOV", "LDI"); |
+ } if ((zip_legitimate_move_operand_p(SImode, iftrue, true)) |
+ &&(zip_legitimate_move_operand_p(SImode, iffalse, true))) { |
+ if (dbg) fprintf(stderr, "ZIP::MOVSICC -- IF(X) A+B ELSE C+D\n"); |
+ return zip_tertiary_movsicc(condition, "MOV", "MOV"); |
+ } |
+ if ((MEM_P(iftrue)) |
+ &&(zip_legitimate_opb(XEXP(iftrue,0), true)) |
+ &&(zip_legitimate_move_operand_p(SImode, iffalse, true))) { |
+ if (dbg) fprintf(stderr, "ZIP::MOVSICC -- IF(X) A[B] ELSE C+D\n"); |
+ return zip_tertiary_movsicc(condition, "LOD", "MOV"); |
+ } if ((zip_legitimate_move_operand_p(SImode, iftrue, true)) |
+ &&(MEM_P(iffalse))&&(zip_legitimate_opb(XEXP(iffalse,0), true))) { |
+ if (dbg) fprintf(stderr, "ZIP::MOVSICC -- IF(X) A+B ELSE C[D]\n"); |
+ return zip_tertiary_movsicc(condition, "MOV", "LOD"); |
+ } if ((MEM_P(iftrue))&&(zip_legitimate_opb(XEXP(iftrue,0), true)) |
+ &&(MEM_P(iffalse))&&(zip_legitimate_opb(XEXP(iffalse,0), true))) { |
+ if (dbg) fprintf(stderr, "ZIP::MOVSICC -- IF(X) A[B] ELSE C[D]\n"); |
+ return zip_tertiary_movsicc(condition, "LOD", "LOD"); |
+ } if ((MEM_P(iftrue)) |
+ &&(zip_legitimate_opb(XEXP(iftrue,0),true)) |
+ &&(zip_const_address_operand(iffalse))) { |
+ if (dbg) fprintf(stderr, "ZIP::MOVSICC -- IF(X) A[B] ELSE #x\n"); |
+ return zip_tertiary_movsicc(condition, "LOD", "LDI"); |
+ } if ((MEM_P(iffalse)) |
+ &&(zip_legitimate_opb(XEXP(iffalse,0),true)) |
+ &&(zip_const_address_operand(iftrue))) { |
+ if (dbg) fprintf(stderr, "ZIP::MOVSICC -- IF(X) #x ELSE A[B]\n"); |
+ return zip_tertiary_movsicc(condition, "LDI", "LOD"); |
+ } else { |
+ // Here's our last chance. |
+ // This will adjust for less than equal types of stuff |
+ int cod = (int)cmpcode; |
+ zip_canonicalize_comparison(&cod, &cmpa, &cmpb, false); |
+ cmpcode = (enum rtx_code)cod; |
+ } |
+ |
+ internal_error("MOVSICC Operands not supported"); |
+ gcc_assert(zip_supported_condition((int)cmpcode)); |
+ |
+ //; Always do the default move |
+ emit_move_insn(dst, iffalse); |
+ |
+ rtx cc_rtx = gen_rtx_REG(CCmode, zip_CC); |
+ |
+ //; Now let's get our comparison right |
+ emit_insn(gen_rtx_SET(VOIDmode, cc_rtx, |
+ gen_rtx_COMPARE(CCmode, cmpa, cmpb))); |
+ |
+ //; Finally, let's load the value on true |
+ emit_insn(gen_movsicc_bare(dst, |
+ gen_rtx_fmt_ee(cmpcode, SImode, NULL_RTX, NULL_RTX), |
+ iftrue, dst)); |
+} |
+ |
+const char *zip_addsicc(rtx dst, rtx condition, rtx ifsrc, rtx addv ATTRIBUTE_UNUSED) { |
2824,10 → 2865,17
+*/ |
+} |
+ |
+int zip_insn_sets_cc(rtx_insn *insn) { |
+ return (get_attr_ccresult(insn)==CCRESULT_SET); |
+} |
+ |
+int zip_is_conditional(rtx_insn *insn) { |
+ return (get_attr_conditional(insn)==CONDITIONAL_YES); |
+} |
diff -Naur '--exclude=*.swp' gcc-5.3.0-original/gcc/config/zip/zip.h gcc-5.3.0-zip/gcc/config/zip/zip.h |
--- gcc-5.3.0-original/gcc/config/zip/zip.h 1969-12-31 19:00:00.000000000 -0500 |
+++ gcc-5.3.0-zip/gcc/config/zip/zip.h 2016-04-12 22:10:09.239940653 -0400 |
@@ -0,0 +1,3987 @@ |
+++ gcc-5.3.0-zip/gcc/config/zip/zip.h 2016-04-21 16:49:43.785679680 -0400 |
@@ -0,0 +1,4058 @@ |
+//////////////////////////////////////////////////////////////////////////////// |
+// |
+// Filename: gcc/config/zip/zip.h |
2869,7 → 2917,7
+ |
+// |
+// |
+// Zip CPU configuration registers |
+// Zip CPU configuration defines |
+// |
+// |
+#define ZIP_USER 0 // Assume we are in supervisor mode |
2881,6 → 2929,8
+#define ZIP_ATOMIC ((ZIP_PIPELINED)&&(ZIP_VLIW)) |
+#define ZIP_PIC 0 // Attempting to produce PIC code, with GOT |
+#define ZIP_HAS_DI 1 |
+// Should we use the peephole optimizations? |
+#define ZIP_PEEPHOLE 1 // 0 means no peephole optimizations. |
+ |
+// Zip has 16 registers in each user mode. |
+// Register 15 is the program counter (PC) |
2923,7 → 2973,7
+ |
+/* Assembler Commands for Alignment */ |
+#define ASM_OUTPUT_ALIGN(STREAM,POWER) \ |
+ { int pwr = POWER; fprintf(STREAM, "\t.p2align %d\n", (pwr<2)?2:pwr); } |
+ { int pwr = POWER; fprintf(STREAM, "\t.p2align %d\n", (pwr<2)?2:pwr); } |
+ |
+ |
+/* A C compound statement to output to stdio stream STREAM the assembler syntax |
2955,50 → 3005,9
+#define EPILOGUE_USES(R) (R == RETURN_ADDRESS_REGNUM) |
+ |
+ |
+/* Normal alignment required for function parameters on the stack, in bits. All |
+ * stack parameters receive at leaswt this much alignment regardless of data |
+ * type. */ |
+#define PARM_BOUNDARY 32 |
+ |
+/* Alignment of field after 'int : 0' in a structure. */ |
+#define EMPTY_FIELD_BOUNDARY 32 |
+ |
+/* No data type wants to be aligned rounder than this. */ |
+#define BIGGEST_ALIGNMENT 32 |
+ |
+/* The best alignment to use in cases where we have a choice. */ |
+#define FASTEST_ALIGNMENT 32 |
+#define FASTEST_ALIGNMENT BITS_PER_WORD |
+ |
+/* Every structures size must be a multiple of 32-bits. */ |
+#define STRUCTURE_SIZE_BOUNDARY 32 |
+ |
+/* PCC_BITFIELD_TYPE_MATTERS -- define this if you wish to imitate the the way |
+ * other C compilers handle alignment of bit-fields and the structures that |
+ * contain them. |
+ * |
+ * The behavior is that the type written for a named bit-field (int, short, or |
+ * other integer type) imposes an alignment for the entire structure, as if the |
+ * structure really did contain an ordinary field of that type. In addition, |
+ * the bit-field is placed within the structure so that it would fit within |
+ * such a field, not crossing a boundary for it. |
+ * |
+ * Thus, no most machines, a named bit-field whose type is written as int would |
+ * not cross a four-byte boundary, and would force four-byte alignment for the |
+ * whole structure. (The alignment used may not be four bytes; it is controlled |
+ * by other alignment parameters.) |
+ * |
+ * An unnamed bit-field will not affect the alignment of the containing |
+ * structure. |
+ * |
+ * If thhe macro is defined, its definition should be a C expression, a non |
+ * zero value for the expression enables this behavior. |
+ * Look at the fundamental type that is used for a bit-field and use that to |
+ * impose alignment on the enclosing structure. struct s{int a:8}; should |
+ * have the same alignment as 'int', not 'char'. |
+ */ |
+#undef PCC_BITFIELD_TYPE_MATTERS |
+#define PCC_BITFIELD_TYPE_MATTERS 0 |
+ |
+/* MAX_FIXED_MODE_SIZE -- An integer expression for the size in bits of the |
+ * largest integer machine mode that should actually be used. All integer |
+ * machine modes of this size and smaller can be used for structures and unions |
3008,15 → 3017,6
+ * ZipCPU -- The default looks good enough for us. |
+ */ |
+ |
+/* Make strings word-aligned so strcpy from constants will be faster. */ |
+#define CONSTANT_ALIGNMENT(EXP, ALIGN) (((TREE_CODE(EXP)==STRING_CST) \ |
+ && ((ALIGN) < FASTEST_ALIGNMENT)) ? FASTEST_ALIGNMENT : (ALIGN)) |
+ |
+/* Make arrays of chars word-aligned for the same reasons. */ |
+#define DATA_ALIGNMENT(TYPE, ALIGN) ((TREE_CODE(TYPE) == ARRAY_TYPE) \ |
+ && (TYPE_MODE(TREE_TYPE(TYPE)) == QImode) \ |
+ && ((ALIGN < FASTEST_ALIGNMENT) ? FASTEST_ALIGNMENT : (ALIGN))) |
+ |
+/* Generate Code for Profiling |
+ */ |
+#define FUNCTION_PROFILER(FILE,LABELNO) (abort(), 0) |
3243,7 → 3243,7
+ * number of bits as SImode. Therefore, one might wish to convert between the |
+ * two. Hence, we specify how we would do that here. |
+ */ |
+#define POINTERS_EXTEND_UNSIGNED 0 |
+#define POINTERS_EXTEND_UNSIGNED 1 |
+ |
+/* PROMOTE_MODE(m,unsignedp,type) ... A macro to update m and unsignedp when an |
+ * object whose type is type and which has he specified mode and signedness is |
3287,9 → 3287,13
+#define STACK_BOUNDARY PARM_BOUNDARY |
+ |
+/* PREFERRED_STACK_BOUNDARY ... Define this ... */ |
+#define PREFERRED_STACK_BOUNDARY STACK_BOUNDARY |
+ |
+/* INCOMING_STACK_BOUNDARY |
+/* INCOMING_STACK_BOUNDARY ... Define this macro if the incoming stack boundary |
+ * may be different from PREFERRED_STACK_BOUNDARY. This macro must evaluate |
+ * to a value equal to or larger than STACK_BOUNDARY. |
+ */ |
+#define INCOMING_STACK_BOUNDARY STACK_BOUNDARY |
+ |
+/* FUNCTION_BOUNDARY ... Alignment required for a function entry point, in bits. |
+ */ |
3301,6 → 3305,12
+ */ |
+#define BIGGEST_ALIGNMENT 32 |
+ |
+/* MALLOC_ABI_ALIGNMENT |
+ */ |
+ |
+/* ATTRIBUTE_ALIGNED_VALUE |
+ */ |
+ |
+/* MINIMUM_ATOMIC_ALIGNMENT ... If defined, the smallest alignment, that can be |
+ * given to an object that can be referenced in one operation, without |
+ * disturbing any nearby object. Normally, this is BITS_PER_UNIT, but may be |
3308,6 → 3318,83
+ */ |
+#define MINIMUM_ATOMIC_ALIGNMENT BITS_PER_UNIT |
+ |
+/* BIGGEST_FIELD_ALIGNMENT ... Biggest alignment that any structure or union |
+ * field can require on this machine, in bits. If defined, this overrides |
+ * BIGGEST_ALIGNMENT for structure and union fields only, unless the field |
+ * alignment has been set by the __attribute__((aligned(n))) construct. |
+ */ |
+#define BIGGEST_FIELD_ALIGNMENT BITS_PER_UNIT |
+ |
+/* ADJUST_FIELD_ALIGN |
+ */ |
+#define ADJUST_FIELD_ALIGN(A,B) BITS_PER_WORD |
+ |
+/* MAX_STACK_ALIGNMENT |
+ */ |
+#define MAX_STACK_ALIGNMENT BITS_PER_WORD |
+ |
+/* MAX_OFILE_ALIGNMENT |
+ */ |
+ |
+/* DATA_ALIGNMENT(TYPE, BASIC-ALIGN) ... If defined, a C expression to compute |
+ * the alignment for a variable in the static store. TYPE is the data type, and |
+ * BASIC-ALIGN is the alignment that the object would ordinarily have. The |
+ * value of this macro is used instead of that alignment to align the object. |
+ * |
+ * If this macro is not defined, then BASIC-ALIGN is used. |
+ * |
+ * ZipCPU -- in hindsight, if this macro is not defined then the compiler is |
+ * broken. So we define it to be our fastest alignment, or 32-bits. |
+ */ |
+#define DATA_ALIGNMENT(TYPE, ALIGN) BITS_PER_WORD |
+ |
+ |
+/* DATA_ABI_ALIGNMENT(TYPE,BASIC-ALIGN) |
+ */ |
+ |
+/* CONSTANT_ALIGNMENT(CONST, BASIC-ALIGN) ... If defined, a C expression to |
+ * compute the alignment given to a constant that is being placed in memory. |
+ * CONST is the constant and BASIC-ALIGN is the alignment that the object |
+ * would ordinarily have. The value of this macro is used instead of that |
+ * alignment to align the object. |
+ * |
+ * If this macro is not defined, then BASIC-ALIGN is used. |
+ * |
+ * ZipCPU -- in hindsiht, if this macro is not defined then the compiler is |
+ * broken. We'll define it as above. |
+ * |
+ */ |
+#define CONSTANT_ALIGNMENT(EXP, ALIGN) BITS_PER_WORD |
+ |
+/* LOCAL_ALIGNMENT(TYPE,BASIC-ALIGN) ... If defined ... |
+ */ |
+#define LOCAL_ALIGNMENT(TYP,ALIGN) BITS_PER_WORD |
+ |
+/* TARGET_VECTOR_ALIGNMENT |
+ */ |
+ |
+/* STACK_SLOT_ALIGNMENT |
+ */ |
+#define STACK_SLOT_ALIGNMENT(T,M,B) BITS_PER_WORD |
+ |
+/* LOCAL_DECL_ALIGNMEN(DECL) |
+ */ |
+#define LOCAL_DECL_ALIGNMENT(DECL) BITS_PER_WORD |
+ |
+/* MINIMUM_ALIGNMENT |
+ */ |
+#define MINIMUM_ALIGNMENT(EXP,MOD,ALIGN) BITS_PER_WORD |
+ |
+/* EMPTY_FIELD_BOUNDARY |
+ * Alignment of field after 'int : 0' in a structure. |
+ */ |
+#define EMPTY_FIELD_BOUNDARY BITS_PER_WORD |
+ |
+/* STRUCTURE_SIE_BOUNDARY |
+ * ZipCPU -- Every structures size must be a multiple of 32-bits. |
+ */ |
+#define STRUCTURE_SIZE_BOUNDARY BITS_PER_WORD |
+ |
+/* STRICT_ALIGNMENT ... Set this nonzero if move instructions will actually |
+ * fail to work when given unaligned data. If instructions will merely go |
+ * slower in that case, define this macro as 0. |
3318,6 → 3405,33
+ */ |
+#define STRICT_ALIGNMENT 0 |
+ |
+/* PCC_BITFIELD_TYPE_MATTERS -- define this if you wish to imitate the the way |
+ * other C compilers handle alignment of bit-fields and the structures that |
+ * contain them. |
+ * |
+ * The behavior is that the type written for a named bit-field (int, short, or |
+ * other integer type) imposes an alignment for the entire structure, as if the |
+ * structure really did contain an ordinary field of that type. In addition, |
+ * the bit-field is placed within the structure so that it would fit within |
+ * such a field, not crossing a boundary for it. |
+ * |
+ * Thus, no most machines, a named bit-field whose type is written as int would |
+ * not cross a four-byte boundary, and would force four-byte alignment for the |
+ * whole structure. (The alignment used may not be four bytes; it is controlled |
+ * by other alignment parameters.) |
+ * |
+ * An unnamed bit-field will not affect the alignment of the containing |
+ * structure. |
+ * |
+ * If the macro is defined, its definition should be a C expression, a non |
+ * zero value for the expression enables this behavior. |
+ * Look at the fundamental type that is used for a bit-field and use that to |
+ * impose alignment on the enclosing structure. struct s{int a:8}; should |
+ * have the same alignment as 'int', not 'char'. |
+ */ |
+#undef PCC_BITFIELD_TYPE_MATTERS |
+#define PCC_BITFIELD_TYPE_MATTERS 0 |
+ |
+/* MAX_FIXED_MODE_SIZE ... An integer expression for the size in bits of the |
+ * largest integer machine mode that should actually be used. All integer |
+ * machine modes of this size or smaller can be used for structures and unions |
3438,7 → 3552,7
+ */ |
+ |
+/* PTRDIFF_TYPE ... A C expression for a string describing the name of the data |
+ * type to use fo rthe result of subtracting two pointers. The typedef name |
+ * type to use for the result of subtracting two pointers. The typedef name |
+ * ptrdiff_t is defined using the contents of the string. See SIZE_TYPE for |
+ * more information. |
+ * |
3596,10 → 3710,14
+ * Other registers, such as FP (the frame pointer) or GBL (the global offset |
+ * table pointer) are registers that we hope will not be so fixed. |
+ */ |
+#ifdef zip_FP_PSEUDO |
+# define FIXED_REGISTERS { 0,0,0,0,0,0,0,0,0,0,0,0,0,1,1,1,1 } |
+#ifdef DEFINE_USER_REGS |
+# define FIXED_REGISTERS { 0,0,0,0,0,0,0,0,0,0,0,0,0,1,1,1,1, 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1 } |
+#else |
+# define FIXED_REGISTERS { 0,0,0,0,0,0,0,0,0,0,0,0,0,1,1,1 } |
+# ifdef zip_FP_PSEUDO |
+# define FIXED_REGISTERS { 0,0,0,0,0,0,0,0,0,0,0,0,0,1,1,1,1 } |
+# else |
+# define FIXED_REGISTERS { 0,0,0,0,0,0,0,0,0,0,0,0,0,1,1,1 } |
+# endif |
+#endif |
+ |
+/* CALL_USED_REGISTERS ... like FIXED_REGISTERS but has 1 for each register |
3615,10 → 3733,14
+ * On the Zip CPU, we must save R0 (the return address), and (let's pick) any |
+ * register above R5. |
+ */ |
+#ifdef zip_FP_PSEUDO |
+# define CALL_USED_REGISTERS { 0,1,1,1,1,0,0,0,0,0,0,0,0,1,1,1,1 } |
+#ifdef DEFINE_USER_REGS |
+# define CALL_USED_REGISTERS { 0,1,1,1,1,0,0,0,0,0,0,0,0,1,1,1,1, 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1 } |
+#else |
+# define CALL_USED_REGISTERS { 0,1,1,1,1,0,0,0,0,0,0,0,0,1,1,1 } |
+# ifdef zip_FP_PSEUDO |
+# define CALL_USED_REGISTERS { 0,1,1,1,1,0,0,0,0,0,0,0,0,1,1,1,1 } |
+# else |
+# define CALL_USED_REGISTERS { 0,1,1,1,1,0,0,0,0,0,0,0,0,1,1,1 } |
+# endif |
+#endif |
+ |
+/* CALL_REALLY_USED_REGISTERS ... optional macro that, if not defined, defaults |
3631,10 → 3753,10
+ * this macro need not be defined. It is only required for machines that do |
+ * not preserve the entire contents of a register across a call. |
+ * |
+ * In the Zip CPU, we clobber R0 with our return address during a call, so let's |
+ * make sure this gets included here. |
+ * ZipCPU--Always preserves the entire contents of those registers that are |
+ * preserved across calls, so this shouldnt need to be defined. |
+ */ |
+#define HARD_REGNO_CALL_PART_CLOBBERED(REGNO,MODE) (REGNO==0) |
+// #define HARD_REGNO_CALL_PART_CLOBBERED(REGNO,MODE) (REGNO==0) |
+ |
+/* TARGET_CONDITIONAL_REGISTER_USAGE(VOID) ... This hook may conditionally |
+ * modify five variables fixed_regs, call_used_regs, global_regs, reg_names, and |
3797,7 → 3919,7
+ * the ZipCPU stack pointer register. |
+ */ |
+ |
+#define ZIP_REG_BYTE_SIZE 1 |
+// #define ZIP_REG_BYTE_SIZE 1 |
+ |
+/* 17.08 Register Classes */ |
+ |
3826,10 → 3948,14
+ * classes as C string constants. These names are used in writing some of the |
+ * debugging dumps. |
+ */ |
+#define REG_CLASS_NAMES { "NO_REGS", "GENERAL_REGS", "ALL_REGS" } |
+#ifdef DEFINE_USER_REGS |
+# define REG_CLASS_NAMES { "NO_REGS", "GENERAL_REGS", "USER_REGS", "ALL_REGS" } |
+#else |
+# define REG_CLASS_NAMES { "NO_REGS", "GENERAL_REGS", "ALL_REGS" } |
+#endif |
+ |
+/* REG_CLASS_CONTENTS ... An initializer containing the contents of the register |
+ * classes, as integerss which are bit masks. The nth integer specifies the |
+ * classes, as integers which are bit masks. The nth integer specifies the |
+ * contents of class n. That way the integer mask is interpreted as that |
+ * register r is in the class if (mask&(1<<r)) is 1. |
+ * |
3837,19 → 3963,16
+ * |
+ * ZipCPU --- This is straight forward, three register classes, etc. |
+ */ |
+#ifdef zip_FP_PSEUDO |
+#define REG_CLASS_CONTENTS { { 0x00000}, {0x13fff}, {0x1ffff} } |
+#ifdef DEFINE_USER_REGS |
+# define REG_CLASS_CONTENTS { { 0x000000000}, {0x00003fff}, {0x0ffff0000l}, {0x0ffffffffl} } |
+#else |
+#define REG_CLASS_CONTENTS { { 0x00000}, {0x03fff}, {0x0ffff} } |
+# ifdef zip_FP_PSEUDO |
+# define REG_CLASS_CONTENTS { { 0x00000}, {0x13fff}, {0x1ffff} } |
+# else |
+# define REG_CLASS_CONTENTS { { 0x00000}, {0x03fff}, {0x0ffff} } |
+# endif |
+#endif |
+ |
+#ifdef DEFINE_USER_REGS |
+#define REG_CLASS_NAMES { "NO_REGS", "GENERAL_REGS", "USER_REGS", "ALL_REGS" } |
+#define REG_CLASS_CONTENTS { { 0x00000},{0x03fff},{0x0ffff0000},{0x0ffffffff} } |
+#define FIXED_REGISTERS { 0,0,0,0,0,0,0,0,0,0,0,0,0,1,1,1, 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1 } |
+#define CALL_USED_REGISTERS { 0,1,1,1,1,0,0,0,0,0,0,0,0,1,1,1, 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1 } |
+#endif |
+ |
+/* REGNO_REG_CLASS ... A C expression whose value is a register class |
+ * containing hard register REGNO. In general there is more than one such |
+ * class; Choose a class which is minimal, meaning that no smaller class also |
3900,11 → 4023,7
+ * number num is suitable for use as a base register in operand addresses. |
+ */ |
+#undef REGNO_OK_FOR_BASE_P |
+#ifdef DEFINE_USER_REGS |
+# define REGNO_OK_FOR_BASE_P(NUM) ((NUM != zip_CC)&&(NUM < 16)) |
+#else |
+# define REGNO_OK_FOR_BASE_P(NUM) (NUM != zip_CC) |
+#endif |
+# define REGNO_OK_FOR_BASE_P(NUM) ((NUM>=FIRST_PSEUDO_REGISTER)||(NUM != zip_CC)) |
+ |
+/* REGNO_MODE_OK_FOR_BASE_P ... A C expressison that is just like |
+ * REGNO_OK_FOR_BASE_P, except that that expression may examine the mode of the |
5908,7 → 6027,7
+/* TARGET_ASM_LABEL_ALIGN */ |
+/* Assembler Commands for Alignment */ |
+#define ASM_OUTPUT_ALIGN(STREAM,POWER) \ |
+ { int pwr = POWER; fprintf(STREAM, "\t.p2align %d\n", (pwr<2)?2:pwr); } |
+ { int pwr = POWER; fprintf(STREAM, "\t.p2align %d\n", (pwr<2)?2:pwr); } |
+ |
+ |
+ |
6817,8 → 6936,8
+ |
diff -Naur '--exclude=*.swp' gcc-5.3.0-original/gcc/config/zip/zip.md gcc-5.3.0-zip/gcc/config/zip/zip.md |
--- gcc-5.3.0-original/gcc/config/zip/zip.md 1969-12-31 19:00:00.000000000 -0500 |
+++ gcc-5.3.0-zip/gcc/config/zip/zip.md 2016-04-12 21:02:20.294810924 -0400 |
@@ -0,0 +1,2422 @@ |
+++ gcc-5.3.0-zip/gcc/config/zip/zip.md 2016-04-21 20:01:08.790659796 -0400 |
@@ -0,0 +1,2961 @@ |
+;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; |
+;; |
+;; Filename: zip.md |
6897,6 → 7016,7
+ (UNSPEC_GETUCC 8) |
+ (UNSPEC_GETCC 9) |
+ (UNSPEC_LDILO 10) |
+ ; (UNSPEC_RAW_CALL 11) |
+ ]) |
+; |
+; |
7245,6 → 7365,25
+; |
+;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; |
+;; |
+;; Substitution Pattern |
+;; |
+;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; |
+; |
+; |
+(define_subst "cc_substitution" |
+ ; The pattern may not have any match_dup expressions. |
+ [(set (match_operand:SI 0 "" "") (match_operand:SI 1 "" "")) |
+ (clobber (reg:CC CC_REG))] |
+ "" |
+ [(set (match_dup 0) (match_dup 1)) |
+ (set (reg:CC CC_REG) (compare:CC (match_dup 0) (const_int 0))) |
+ ]) |
+; |
+(define_subst_attr "cc_subst" "cc_substitution" "_raw" "_clobber") |
+; |
+; |
+;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; |
+;; |
+;; General arithmetic instructions |
+;; |
+;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; |
7253,20 → 7392,51
+; |
+; |
+(define_expand "add<mode>3" ; Fastest/best instruction always goes first |
+ [(parallel [(set (match_operand:ZI 0 "register_operand" "=r") |
+ [(set (match_operand:ZI 0 "register_operand" "=r") |
+ (plus:ZI (match_operand:ZI 1 "register_operand" "0") |
+ (match_operand:ZI 2 "zip_opb_operand_p" ""))) |
+ (set (reg:CC CC_REG) (compare:CC (match_dup 0) (const_int 0))) |
+ ]) ]) |
+(define_insn "*addsi3_reg" ; Fastest/best instruction always goes first |
+ ]) |
+(define_insn_and_split "add<mode>3_split_reg" |
+ [(set (match_operand:ZI 0 "register_operand" "=r") |
+ (plus:ZI (match_operand:ZI 1 "register_operand" "0") |
+ (match_operand:ZI 2 "zip_opb_single_operand_p" "rO")))] |
+ "" |
+ "#" ; This code means the instruction *must* be split |
+ "(reload_completed)&&(REG_P(operands[0]))&&(REG_P(operands[1]))&&(REGNO(operands[0])==REGNO(operands[1]))" |
+ [(parallel [(set (match_dup 0) (plus:ZI (match_dup 1) (match_dup 2))) |
+ (clobber (reg:CC CC_REG))])] |
+ "" |
+ [(set_attr "predicable" "yes")]) |
+(define_insn_and_split "add<mode>3_split_off" |
+ [(set (match_operand:ZI 0 "register_operand" "=r") |
+ (plus:ZI (match_operand:ZI 1 "register_operand" "0") |
+ (plus:ZI (match_operand:ZI 2 "register_operand" "r") |
+ (match_operand:ZI 3 "zip_opb_immv_p" "N"))))] |
+ "" |
+ "#" ; This code means the instruction *must* be split |
+ "(reload_completed)&&(REG_P(operands[0]))&&(REG_P(operands[1]))&&(REGNO(operands[0])==REGNO(operands[1]))" |
+ [(parallel [(set (match_dup 0) (plus:ZI (match_dup 1) |
+ (plus:ZI (match_dup 2) (match_dup 3)))) |
+ (clobber (reg:CC CC_REG))])] |
+ "" |
+ [(set_attr "predicable" "yes")]) |
+(define_insn "addsi3_reg_clobber" |
+ [(set (match_operand:SI 0 "register_operand" "=r") |
+ (plus:SI (match_operand:SI 1 "register_operand" "0") |
+ (match_operand:SI 2 "zip_opb_single_operand_p" "rO"))) |
+ (clobber (reg:CC CC_REG))] |
+ "" |
+ "ADD %2,%0" |
+ [(set_attr "ccresult" "set")]) |
+(define_insn "addsi3_reg_raw" |
+ [(set (match_operand:SI 0 "register_operand" "=r") |
+ (plus:SI (match_operand:SI 1 "register_operand" "0") |
+ (match_operand:SI 2 "zip_opb_single_operand_p" "rO"))) |
+ (set (reg:CC CC_REG) (compare:CC (match_dup 0) (const_int 0)))] |
+ "" |
+ "ADD %2,%0" |
+ [(set_attr "ccresult" "set")]) |
+(define_insn "add<mode>3_off" ; Fastest/best instruction always goes first |
+(define_insn "add<mode>3_off_raw" |
+ [(set (match_operand:ZI 0 "register_operand" "=r") |
+ (plus:ZI (match_operand:ZI 1 "register_operand" "0") |
+ (plus:ZI (match_operand:ZI 2 "register_operand" "r") |
7275,6 → 7445,15
+ "" |
+ "ADD %3+%2,%0" |
+ [(set_attr "ccresult" "set")]) |
+(define_insn "add<mode>3_off_clobber" |
+ [(set (match_operand:ZI 0 "register_operand" "=r") |
+ (plus:ZI (match_operand:ZI 1 "register_operand" "0") |
+ (plus:ZI (match_operand:ZI 2 "register_operand" "r") |
+ (match_operand:ZI 3 "zip_opb_immv_p" "N")))) |
+ (clobber (reg:CC CC_REG))] |
+ "" |
+ "ADD %3+%2,%0" |
+ [(set_attr "ccresult" "set")]) |
+; |
+; |
+; |
7283,23 → 7462,64
+ (minus:ZI (match_operand:ZI 1 "register_operand" "0") |
+ (match_operand:ZI 2 "zip_opb_operand_p" ""))) |
+ (set (reg:CC CC_REG) (compare:CC (match_dup 0) (const_int 0)))])]) |
+(define_insn "sub<mode>3_reg" |
+(define_insn_and_split "sub<mode>3_split_reg" |
+ [(set (match_operand:ZI 0 "register_operand" "=r") |
+ (minus:ZI (match_operand:ZI 1 "register_operand" "0") |
+ (match_operand:ZI 2 "zip_opb_single_operand_p" "rO")))] |
+ "" |
+ "#" |
+ "(reload_completed)" |
+ [(parallel [(set (match_dup 0) (minus:ZI (match_dup 1) (match_dup 2))) |
+ (clobber (reg:CC CC_REG))])] |
+ "" |
+ [(set_attr "ccresult" "set")]) |
+(define_insn "sub<mode>3_reg_raw" |
+ [(set (match_operand:ZI 0 "register_operand" "=r") |
+ (minus:ZI (match_operand:ZI 1 "register_operand" "0") |
+ (match_operand:ZI 2 "zip_opb_single_operand_p" "rO"))) |
+ (set (reg:CC CC_REG) (compare:CC (match_dup 0) (const_int 0)))] |
+ "" |
+ "SUB %2,%0" |
+ [(set_attr "ccresult" "set")]) |
+(define_insn "sub<mode>3_off" |
+(define_insn "sub<mode>3_reg_clobber" |
+ [(set (match_operand:ZI 0 "register_operand" "=r") |
+ (minus:ZI (match_operand:ZI 1 "register_operand" "0") |
+ (match_operand:ZI 2 "zip_opb_single_operand_p" "rO"))) |
+ (clobber (reg:CC CC_REG))] |
+ "" |
+ "SUB %2,%0" |
+ [(set_attr "ccresult" "set")]) |
+(define_insn_and_split "sub<mode>3_off_split" |
+ [(set (match_operand:ZI 0 "register_operand" "=r") |
+ (minus:ZI (match_operand:ZI 1 "register_operand" "0") |
+ (plus:ZI (match_operand:ZI 2 "register_operand" "%r") |
+ (match_operand:ZI 3 "zip_opb_immv_p" "N"))))] |
+ "" |
+ "#" |
+ "(reload_completed)" |
+ [(parallel [(set (match_dup 0) (minus:ZI (match_dup 1) |
+ (plus:ZI (match_dup 2) (match_dup 3)))) |
+ (clobber (reg:CC CC_REG))])] |
+ "" |
+ [(set_attr "ccresult" "set")]) |
+(define_insn "sub<mode>3_off_raw" |
+ [(set (match_operand:ZI 0 "register_operand" "=r") |
+ (minus:ZI (match_operand:ZI 1 "register_operand" "0") |
+ (plus:ZI (match_operand:ZI 2 "register_operand" "%r") |
+ (match_operand:ZI 3 "zip_opb_immv_p" "N")))) |
+ (set (reg:CC CC_REG) (compare:CC (match_dup 0) (const_int 0)))] |
+ "" |
+ "SUB %3+%2,%0" |
+ [(set_attr "ccresult" "set")]) |
+(define_insn "sub<mode>3_off_clobber" |
+ [(set (match_operand:ZI 0 "register_operand" "=r") |
+ (minus:ZI (match_operand:ZI 1 "register_operand" "0") |
+ (plus:ZI (match_operand:ZI 2 "register_operand" "%r") |
+ (match_operand:ZI 3 "zip_opb_immv_p" "N")))) |
+ (clobber (reg:CC CC_REG))] |
+ "" |
+ "SUB %3+%2,%0" |
+ [(set_attr "ccresult" "set")]) |
+(define_insn "mul<mode>3" |
+ [(set (match_operand:ZI 0 "register_operand" "=r") |
+ (mult:ZI (match_operand:ZI 1 "register_operand" "%r") |
7414,50 → 7634,137
+ "CMP %0,%2 |
+ MOV.LT %2,%0" |
+ [(set_attr "predicable" "no") (set_attr "ccresult" "unknown")]) |
+; |
+; |
+(define_expand "and<mode>3" |
+ [(parallel [(set (match_operand:ZI 0 "register_operand" "=r") |
+ [(set (match_operand:ZI 0 "register_operand" "=r") |
+ (and:ZI (match_operand:ZI 1 "register_operand" "%0") |
+ (match_operand:ZI 2 "zip_opb_operand_p" ""))) |
+ (set (reg:CC CC_REG) (compare:CC (match_dup 0) (const_int 0)))])]) |
+(define_insn "and<mode>3_reg" |
+ (match_operand:ZI 2 "zip_opb_operand_p" "")))]) |
+(define_insn_and_split "and<mode>3_reg_split" |
+ [(set (match_operand:ZI 0 "register_operand" "=r") |
+ (and:ZI (match_operand:ZI 1 "register_operand" "%0") |
+ (match_operand:ZI 2 "zip_opb_single_operand_p" "rO")))] |
+ "" |
+ "#" |
+ "(reload_completed)" |
+ [(parallel [(set (match_dup 0) (and:ZI (match_dup 1) (match_dup 2))) |
+ (clobber (reg:CC CC_REG))])] |
+ "" |
+ [(set_attr "ccresult" "set")]) |
+(define_insn "and<mode>3_reg_raw" |
+ [(set (match_operand:ZI 0 "register_operand" "=r") |
+ (and:ZI (match_operand:ZI 1 "register_operand" "%0") |
+ (match_operand:ZI 2 "zip_opb_single_operand_p" "rO"))) |
+ (set (reg:CC CC_REG) (compare:CC (match_dup 0) (const_int 0)))] |
+ "" |
+ "AND %2,%0" |
+ [(set_attr "ccresult" "set")]) |
+(define_insn "and<mode>3_off" |
+(define_insn "and<mode>3_reg_clobber" |
+ [(set (match_operand:ZI 0 "register_operand" "=r") |
+ (and:ZI (match_operand:ZI 1 "register_operand" "%0") |
+ (match_operand:ZI 2 "zip_opb_single_operand_p" "rO"))) |
+ (clobber (reg:CC CC_REG))] |
+ "" |
+ "AND %2,%0" |
+ [(set_attr "ccresult" "set")]) |
+(define_insn_and_split "and<mode>3_off_split" |
+ [(set (match_operand:ZI 0 "register_operand" "=r") |
+ (and:ZI (match_operand:ZI 1 "register_operand" "0") |
+ (plus:ZI (match_operand:ZI 2 "register_operand" "r") |
+ (match_operand:ZI 3 "zip_opb_immv_p" "N"))))] |
+ "" |
+ "#" |
+ "(reload_completed)" |
+ [(parallel [(set (match_dup 0) (and:ZI (match_dup 1) |
+ (plus:ZI (match_dup 2) (match_dup 3)))) |
+ (clobber (reg:CC CC_REG))])] |
+ "" |
+ [(set_attr "ccresult" "set")]) |
+(define_insn "and<mode>3_off_raw" |
+ [(set (match_operand:ZI 0 "register_operand" "=r") |
+ (and:ZI (match_operand:ZI 1 "register_operand" "0") |
+ (plus:ZI (match_operand:ZI 2 "register_operand" "r") |
+ (match_operand:ZI 3 "zip_opb_immv_p" "N")))) |
+ (set (reg:CC CC_REG) (compare:CC (match_dup 0) (const_int 0)))] |
+ "" |
+ "AND %3+%2,%0" |
+ [(set_attr "ccresult" "set")]) |
+(define_insn "and<mode>3_off_clobber" |
+ [(set (match_operand:ZI 0 "register_operand" "=r") |
+ (and:ZI (match_operand:ZI 1 "register_operand" "0") |
+ (plus:ZI (match_operand:ZI 2 "register_operand" "r") |
+ (match_operand:ZI 3 "zip_opb_immv_p" "N")))) |
+ (clobber (reg:CC CC_REG))] |
+ "" |
+ "AND %3+%2,%0" |
+ [(set_attr "ccresult" "set")]) |
+; |
+; |
+(define_expand "ior<mode>3" |
+ [(parallel [(set (match_operand:ZI 0 "register_operand" "=r") |
+ [(set (match_operand:ZI 0 "register_operand" "=r") |
+ (ior:ZI (match_operand:ZI 1 "register_operand" "%0") |
+ (match_operand:ZI 2 "zip_opb_operand_p" ""))) |
+ (set (reg:CC CC_REG) (compare:CC (match_dup 0) (const_int 0)))])]) |
+(define_insn "ior<mode>3_reg" |
+ (match_operand:ZI 2 "zip_opb_operand_p" "")))]) |
+(define_insn_and_split "ior<mode>3_reg_split" |
+ [(set (match_operand:ZI 0 "register_operand" "=r") |
+ (ior:ZI (match_operand:ZI 1 "register_operand" "%0") |
+ (match_operand:ZI 2 "zip_opb_single_operand_p" "rO")))] |
+ "" |
+ "#" |
+ "(reload_completed)" |
+ [(parallel [(set (match_dup 0) (ior:ZI (match_dup 1) (match_dup 2))) |
+ (clobber (reg:CC CC_REG))])] |
+ "" |
+ [(set_attr "ccresult" "set")]) |
+(define_insn "ior<mode>3_reg_raw" |
+ [(set (match_operand:ZI 0 "register_operand" "=r") |
+ (ior:ZI (match_operand:ZI 1 "register_operand" "%0") |
+ (match_operand:ZI 2 "zip_opb_single_operand_p" "rO"))) |
+ (set (reg:CC CC_REG) (compare:CC (match_dup 0) (const_int 0)))] |
+ "" |
+ "OR %2,%0" |
+ [(set_attr "ccresult" "set")]) |
+(define_insn "ior<mode>3_off" |
+(define_insn "ior<mode>3_reg_clobber" |
+ [(set (match_operand:ZI 0 "register_operand" "=r") |
+ (ior:ZI (match_operand:ZI 1 "register_operand" "%0") |
+ (match_operand:ZI 2 "zip_opb_single_operand_p" "rO"))) |
+ (clobber (reg:CC CC_REG))] |
+ "" |
+ "OR %2,%0" |
+ [(set_attr "ccresult" "set")]) |
+(define_insn_and_split "ior<mode>3_off_split" |
+ [(set (match_operand:ZI 0 "register_operand" "=r") |
+ (ior:ZI (match_operand:ZI 1 "register_operand" "0") |
+ (plus:ZI (match_operand:ZI 2 "register_operand" "r") |
+ (match_operand:ZI 3 "zip_opb_immv_p" "N"))))] |
+ "" |
+ "#" |
+ "(reload_completed)" |
+ [(parallel [(set (match_dup 0) (ior:ZI (match_dup 1) |
+ (plus:ZI (match_dup 2) (match_dup 3)))) |
+ (clobber (reg:CC CC_REG))])] |
+ "" |
+ [(set_attr "ccresult" "set")]) |
+(define_insn "ior<mode>3_off_raw" |
+ [(set (match_operand:ZI 0 "register_operand" "=r") |
+ (ior:ZI (match_operand:ZI 1 "register_operand" "0") |
+ (plus:ZI (match_operand:ZI 2 "register_operand" "r") |
+ (match_operand:ZI 3 "zip_opb_immv_p" "N")))) |
+ (set (reg:CC CC_REG) (compare:CC (match_dup 0) (const_int 0)))] |
+ "" |
+ "OR %3+%2,%0" |
+ [(set_attr "ccresult" "set")]) |
+(define_insn "ior<mode>3_off_clobber" |
+ [(set (match_operand:ZI 0 "register_operand" "=r") |
+ (ior:ZI (match_operand:ZI 1 "register_operand" "0") |
+ (plus:ZI (match_operand:ZI 2 "register_operand" "r") |
+ (match_operand:ZI 3 "zip_opb_immv_p" "N")))) |
+ (clobber (reg:CC CC_REG))] |
+ "" |
+ "OR %3+%2,%0" |
+ [(set_attr "ccresult" "set")]) |
+; |
+; |
+; |
+(define_expand "xor<mode>3" |
+ [(parallel [(set (match_operand:ZI 0 "register_operand" "=r") |
+ (xor:ZI (match_operand:ZI 1 "register_operand" "%0") |
7464,23 → 7771,64
+ (match_operand:ZI 2 "zip_opb_operand_p" ""))) |
+ (set (reg:CC CC_REG) (compare:CC (match_dup 0) (const_int 0)))])] |
+ "") |
+(define_insn "xor<mode>3_reg" |
+(define_insn_and_split "xor<mode>3_reg_split" |
+ [(set (match_operand:ZI 0 "register_operand" "=r") |
+ (xor:ZI (match_operand:ZI 1 "register_operand" "%0") |
+ (match_operand:ZI 2 "zip_opb_single_operand_p" "rO")))] |
+ "" |
+ "#" |
+ "(reload_completed)" |
+ [(parallel [(set (match_dup 0) (xor:ZI (match_dup 1) (match_dup 2))) |
+ (clobber (reg:CC CC_REG))])] |
+ "" |
+ [(set_attr "ccresult" "set")]) |
+(define_insn "xor<mode>3_reg_raw" |
+ [(set (match_operand:ZI 0 "register_operand" "=r") |
+ (xor:ZI (match_operand:ZI 1 "register_operand" "%0") |
+ (match_operand:ZI 2 "zip_opb_single_operand_p" "rO"))) |
+ (set (reg:CC CC_REG) (compare:CC (match_dup 0) (const_int 0)))] |
+ "" |
+ "XOR %2,%0" |
+ [(set_attr "ccresult" "set")]) |
+(define_insn "xor<mode>3_off" |
+(define_insn "xor<mode>3_reg_clobber" |
+ [(set (match_operand:ZI 0 "register_operand" "=r") |
+ (xor:ZI (match_operand:ZI 1 "register_operand" "%0") |
+ (match_operand:ZI 2 "zip_opb_single_operand_p" "rO"))) |
+ (clobber (reg:CC CC_REG))] |
+ "" |
+ "XOR %2,%0" |
+ [(set_attr "ccresult" "set")]) |
+(define_insn_and_split "xor<mode>3_off_split" |
+ [(set (match_operand:ZI 0 "register_operand" "=r") |
+ (xor:ZI (match_operand:ZI 1 "register_operand" "0") |
+ (plus:ZI (match_operand:ZI 2 "register_operand" "r") |
+ (match_operand:ZI 3 "zip_opb_immv_p" "N"))))] |
+ "" |
+ "#" |
+ "(reload_completed)" |
+ [(parallel [(set (match_dup 0) (xor:ZI (match_dup 1) |
+ (plus:ZI (match_dup 2) (match_dup 3)))) |
+ (clobber (reg:CC CC_REG))])] |
+ "" |
+ [(set_attr "ccresult" "set")]) |
+(define_insn "xor<mode>3_off_raw" |
+ [(set (match_operand:ZI 0 "register_operand" "=r") |
+ (xor:ZI (match_operand:ZI 1 "register_operand" "0") |
+ (plus:ZI (match_operand:ZI 2 "register_operand" "r") |
+ (match_operand:ZI 3 "zip_opb_immv_p" "N")))) |
+ (set (reg:CC CC_REG) (compare:CC (match_dup 0) (const_int 0)))] |
+ "" |
+ "XOR %3+%2,%0" |
+ [(set_attr "ccresult" "set")]) |
+(define_insn "xor<mode>3_off_clobber" |
+ [(set (match_operand:ZI 0 "register_operand" "=r") |
+ (xor:ZI (match_operand:ZI 1 "register_operand" "0") |
+ (plus:ZI (match_operand:ZI 2 "register_operand" "r") |
+ (match_operand:ZI 3 "zip_opb_immv_p" "N")))) |
+ (clobber (reg:CC CC_REG))] |
+ "" |
+ "XOR %3+%2,%0" |
+ [(set_attr "ccresult" "set")]) |
+;(define_insn "addv<mode>4" |
+ ;[(set (match_operand:ZI 0 "register_operand" "=r") |
+ ;(plus:ZI (match_operand:ZI 1 "register_operand" "%r") |
7509,39 → 7857,139
+;; (define_insn "umulvsi4" |
+;; ... ???) |
+;; |
+(define_insn "ashr<mode>3" |
+(define_expand "ashr<mode>3" |
+ [(set (match_operand:ZI 0 "register_operand" "=r") |
+ (ashiftrt:ZI (match_operand:ZI 1 "register_operand" "0") |
+ (match_operand:ZI 2 "zip_opb_single_operand_p" "rR")))]) |
+(define_insn_and_split "ashr<mode>3_split" |
+ [(set (match_operand:ZI 0 "register_operand" "=r") |
+ (ashiftrt:ZI (match_operand:ZI 1 "register_operand" "0") |
+ (match_operand:ZI 2 "zip_opb_single_operand_p" "rR")))] |
+ "" |
+ "#" |
+ "(reload_completed)" |
+ [(parallel [(set (match_dup 0) (ashiftrt:ZI (match_dup 1) (match_dup 2))) |
+ (clobber (reg:CC CC_REG))])] |
+ "" |
+ [(set_attr "ccresult" "set")]) |
+(define_insn "ashr<mode>3_raw" |
+ [(set (match_operand:ZI 0 "register_operand" "=r") |
+ (ashiftrt:ZI (match_operand:ZI 1 "register_operand" "0") |
+ (match_operand:ZI 2 "zip_opb_single_operand_p" "rR"))) |
+ (set (reg:CC CC_REG) (compare:CC (match_dup 0) (const_int 0)))] |
+ "" |
+ "ASR %2,%0" |
+ [(set_attr "ccresult" "set")]) |
+(define_insn "ashl<mode>3" |
+(define_insn "ashr<mode>3_clobber" |
+ [(set (match_operand:ZI 0 "register_operand" "=r") |
+ (ashiftrt:ZI (match_operand:ZI 1 "register_operand" "0") |
+ (match_operand:ZI 2 "zip_opb_single_operand_p" "rR"))) |
+ (clobber (reg:CC CC_REG))] |
+ "" |
+ "ASR %2,%0" |
+ [(set_attr "ccresult" "set")]) |
+; |
+; |
+(define_expand "ashl<mode>3" |
+ [(set (match_operand:ZI 0 "register_operand" "=r") |
+ (ashift:ZI (match_operand:ZI 1 "register_operand" "0") |
+ (match_operand:ZI 2 "zip_opb_single_operand_p" "rR")))]) |
+(define_insn_and_split "ashl<mode>3_split" |
+ [(set (match_operand:ZI 0 "register_operand" "=r") |
+ (ashift:ZI (match_operand:ZI 1 "register_operand" "0") |
+ (match_operand:ZI 2 "zip_opb_single_operand_p" "rR")))] |
+ "" |
+ "#" |
+ "(reload_completed)" |
+ [(parallel [(set (match_dup 0) (ashift:ZI (match_dup 1) (match_dup 2))) |
+ (clobber (reg:CC CC_REG))])] |
+ "" |
+ [(set_attr "ccresult" "set")]) |
+(define_insn "ashl<mode>3_raw" |
+ [(set (match_operand:ZI 0 "register_operand" "=r") |
+ (ashift:ZI (match_operand:ZI 1 "register_operand" "0") |
+ (match_operand:ZI 2 "zip_opb_single_operand_p" "rR"))) |
+ (set (reg:CC CC_REG) (compare:CC (match_dup 0) (const_int 0)))] |
+ "" |
+ "LSL %2,%0" |
+ [(set_attr "ccresult" "set")]) |
+(define_insn "lshr<mode>3" |
+(define_insn "ashl<mode>3_clobber" |
+ [(set (match_operand:ZI 0 "register_operand" "=r") |
+ (ashift:ZI (match_operand:ZI 1 "register_operand" "0") |
+ (match_operand:ZI 2 "zip_opb_single_operand_p" "rR"))) |
+ (clobber (reg:CC CC_REG))] |
+ "" |
+ "LSL %2,%0" |
+ [(set_attr "ccresult" "set")]) |
+; |
+; |
+(define_expand "lshr<mode>3" |
+ [(set (match_operand:ZI 0 "register_operand" "=r") |
+ (lshiftrt:ZI (match_operand:ZI 1 "register_operand" "0") |
+ (match_operand:ZI 2 "register_operand" "rR"))) |
+ (match_operand:ZI 2 "zip_opb_single_operand_p" "rR")))]) |
+(define_insn_and_split "lshr<mode>3_split" |
+ [(set (match_operand:ZI 0 "register_operand" "=r") |
+ (lshiftrt:ZI (match_operand:ZI 1 "register_operand" "0") |
+ (match_operand:ZI 2 "zip_opb_single_operand_p" "rR")))] |
+ "" |
+ "#" |
+ "(reload_completed)" |
+ [(parallel [(set (match_dup 0) (lshiftrt:ZI (match_dup 1) (match_dup 2))) |
+ (clobber (reg:CC CC_REG))])] |
+ "" |
+ [(set_attr "ccresult" "set")]) |
+(define_insn "lshr<mode>3_raw" |
+ [(set (match_operand:ZI 0 "register_operand" "=r") |
+ (lshiftrt:ZI (match_operand:ZI 1 "register_operand" "0") |
+ (match_operand:ZI 2 "zip_opb_single_operand_p" "rR"))) |
+ (set (reg:CC CC_REG) (compare:CC (match_dup 0) (const_int 0)))] |
+ "" |
+ "LSR %2,%0" |
+ [(set_attr "ccresult" "set")]) |
+(define_insn "rotl<mode>3" |
+(define_insn "lshr<mode>3_clobber" |
+ [(set (match_operand:ZI 0 "register_operand" "=r") |
+ (lshiftrt:ZI (match_operand:ZI 1 "register_operand" "0") |
+ (match_operand:ZI 2 "zip_opb_single_operand_p" "rR"))) |
+ (clobber (reg:CC CC_REG))] |
+ "" |
+ "LSR %2,%0" |
+ [(set_attr "ccresult" "set")]) |
+; |
+; |
+(define_expand "rotl<mode>3" |
+ [(set (match_operand:ZI 0 "register_operand" "=r") |
+ (rotate:ZI (match_operand:ZI 1 "register_operand" "0") |
+ (match_operand:ZI 2 "zip_opb_single_operand_p" "rR")))]) |
+(define_insn_and_split "rotl<mode>3_split" |
+ [(set (match_operand:ZI 0 "register_operand" "=r") |
+ (rotate:ZI (match_operand:ZI 1 "register_operand" "0") |
+ (match_operand:ZI 2 "zip_opb_single_operand_p" "rR")))] |
+ "" |
+ "#" |
+ "(reload_completed)" |
+ [(parallel [(set (match_dup 0) (rotate:ZI (match_dup 1) (match_dup 2))) |
+ (clobber (reg:CC CC_REG))])] |
+ "" |
+ [(set_attr "ccresult" "set")]) |
+(define_insn "rotl<mode>3_raw" |
+ [(set (match_operand:ZI 0 "register_operand" "=r") |
+ (rotate:ZI (match_operand:ZI 1 "register_operand" "0") |
+ (match_operand:ZI 2 "zip_opb_single_operand_p" "rR"))) |
+ (set (reg:CC CC_REG) (compare:CC (match_dup 0) (const_int 0)))] |
+ "" |
+ "ROL %2,%0" |
+ [(set_attr "ccresult" "set")]) |
+(define_insn "rotl<mode>3_clobber" |
+ [(set (match_operand:ZI 0 "register_operand" "=r") |
+ (rotate:ZI (match_operand:ZI 1 "register_operand" "0") |
+ (match_operand:ZI 2 "zip_opb_single_operand_p" "rR"))) |
+ (clobber (reg:CC CC_REG))] |
+ "" |
+ "ROL %2,%0" |
+ [(set_attr "ccresult" "set")]) |
+; |
+; |
+; |
+(define_insn "neg<mode>2" |
+ [(set (match_operand:ZI 0 "register_operand" "=r") |
+ (neg:ZI (match_operand:ZI 1 "register_operand" "r"))) |
7567,7 → 8015,7
+(define_expand "parity<mode>2" |
+ [(parallel [(set (match_operand:ZI 0 "register_operand" "=r") |
+ (popcount:ZI (match_operand:ZI 1 "register_operand" "r"))) |
+ (set (reg:CC CC_REG) (compare:CC (match_dup 0) (const_int 0)))]) |
+ (clobber (reg:CC CC_REG))]) |
+ (parallel [ |
+ (set (match_dup 0) (and:ZI (match_dup 0) (const_int -2))) |
+ (set (reg:CC CC_REG) (compare:CC (match_dup 0) (const_int 0)))]) |
7632,7 → 8080,7
+ INTVAL(XEXP(operands[0],1)+1)); |
+ return buf; |
+ } |
+ } else return "BREAK"; |
+ } return "BREAK"; |
+ } |
+ [(set_attr "predicable" "no") (set_attr "ccresult" "unchanged")]) |
+(define_insn "movdi_ldi" |
7970,17 → 8418,29
+ { return (zip_set_zero_or_one(operands[1], operands[0])); |
+ } |
+ [(set_attr "predicable" "no") (set_attr "ccresult" "unchanged")]) |
+(define_insn "mov<mode>cc" |
+(define_expand "mov<mode>cc" |
+ [(set (match_operand:ZI 0 "register_operand" "=r") |
+ (if_then_else:ZI (match_operator 1 "ordered_comparison_operator" |
+ [(reg:CC CC_REG) (const_int 0)]) |
+ (if_then_else:ZI (match_operand 1 "comparison_operator") |
+ (match_operand:ZI 2 "general_operand" "rio") |
+ (match_operand:ZI 3 "nonmemory_operand" "rio")))] |
+ "" |
+ { |
+ return zip_movsicc(operands[0], operands[1], operands[2], operands[3]); |
+ } |
+ [(set_attr "predicable" "no") (set_attr "ccresult" "unchanged")]) |
+ zip_expand_movsicc(operands[0], operands[1], operands[2], operands[3]); |
+ DONE; |
+ }) |
+(define_insn_and_split "movsicc_bare" |
+ [(set (match_operand:SI 0 "register_operand" "=r") |
+ (if_then_else (match_operator 1 "ordered_comparison_operator" |
+ [(reg:CC CC_REG) (const_int 0)]) |
+ (match_operand:SI 2 "general_operand" "rio") |
+ (match_operand:SI 3 "register_operand" "0")))] |
+ "(zip_supported_condition(GET_CODE(operands[1])))" |
+ "#" |
+ "(reload_completed)" |
+ [(cond_exec (match_operator 1 "ordered_comparison_operator" |
+ [(reg:CC CC_REG) (const_int 0)]) |
+ (set (match_dup 0) (match_dup 2)))] |
+ "" [(set_attr "predicable" "no")]) |
+(define_insn "add<mode>cc" |
+ [(set (match_operand:ZI 0 "register_operand" "=r,r") |
+ (if_then_else:ZI (match_operator 1 "ordered_comparison_operator" |
7995,22 → 8455,14
+ [(set_attr "predicable" "no") (set_attr "ccresult" "unchanged")]) |
+; |
+; |
+;(define_expand "mov<mode>cc" |
+; [(set (match_operand:ZI 0 "general_operand" "=rm,rm,r,r,r" |
+; (if_then_else:ZI (match_operator 1 "ordered_comparison_operator" |
+; [(reg:CC CC_REG) (const_int 0)]) |
+; (match_operand:ZI 2 "general_operand" "0,r,0,m,rm") |
+; (match_operand:ZI 3 "general_operand" "r,0,m,0,rm"))))] |
+; ) |
+; |
+; |
+; |
+; While an interesting approach, the following suffers from problems when the |
+; move amount is constant. At anything less than four, moves should not require |
+; the movmemSI instruction. At anything greater, if constant, the initial tests |
+; are not required and should result in a hardcoded result. Practically, |
+; though, this should really be a define_expand instruction, calling on the |
+; RTX's of all the respective subinstructions found below. |
+; RTX's of all the respective subinstructions found below. Or, perhaps, it is |
+; better as a subroutine? |
+; |
+;(define_insn "movmemSI" |
+; [(parallel [(set (mem:BLK (match_operand 0 "register_operand" "+r"));Dst |
8087,8 → 8539,8
+(define_expand "jump" |
+ [(set (pc) |
+ (label_ref (match_operand 0 "" "")))]); // Was general-op, "mro" |
+(define_insn "jump_const" ; Must be modeless, VOIDmode, not SI or any othr |
+ [(set (pc) ; Otherwise it won't accept jumps to labels |
+(define_insn "jump_const" |
+ [(set (pc) |
+ (match_operand:SI 0 "zip_const_address_operand_p" ""))] |
+ "" |
+ "BRA %0" |
8311,8 → 8763,7
+ ;(clobber (reg:CC CC_REG)) |
+ ] |
+ "" ; Flip the condition, and then we can jump |
+ "XOR\t2,CC |
+ BC\t%0" |
+ "BC\t.Lgtu%=\n\tBZ\t.Lgtu%=\n\tBRA\t%0\n.Lgtu%=:" |
+ [(set_attr "predicable" "no") |
+ (set_attr "conditional" "yes") |
+ (set_attr "ccresult" "unknown")]) |
8332,12 → 8783,8
+ (pc))) |
+ ;(clobber (reg:CC CC_REG)) |
+ ] |
+ "" ; Flip the comparison, then check for GEU (once flipped)a |
+ ; Z is naturally checked for, as C would've never been set on Z |
+ ; so by flipping it, it is tantamount to saying Z or GTU. |
+ "BZ\t%0 |
+ XOR\t2,CC |
+ BC\t%0" |
+ "" |
+ "BC\t.Lgeu%=\n\tBRA\t%0\n.Lgeu%=:" |
+ [(set_attr "predicable" "no") |
+ (set_attr "conditional" "yes") |
+ (set_attr "ccresult" "unknown")]) |
8910,12 → 9357,41
+ (set (pc) (if_then_else (gtu (reg:CC CC_REG) (const_int 0)) |
+ (label_ref (match_operand 2 "")) |
+ (pc)))] |
+ "" |
+ "(ZIP_PEEPHOLE)" |
+ [(set (reg:CC CC_REG) (compare:CC (match_dup 1) (match_dup 0))) |
+ (set (pc) (if_then_else (ltu (reg:CC CC_REG) (const_int 0)) |
+ (label_ref (match_dup 2)) |
+ (pc)))] |
+ "") |
+(define_peephole2 |
+ [(match_scratch:SI 3 "=r") |
+ (set (reg:CC CC_REG) (compare:CC |
+ (match_operand:SI 0 "register_operand") |
+ (match_operand 1 "const_int_operand"))) |
+ (match_dup 3) |
+ (set (pc) (if_then_else (gtu (reg:CC CC_REG) (const_int 0)) |
+ (label_ref (match_operand 2 "")) |
+ (pc)))] |
+ "(ZIP_PEEPHOLE)" |
+ [(set (match_dup 3) (match_dup 1)) |
+ (set (reg:CC CC_REG) (compare:CC (match_dup 3) (match_dup 0))) |
+ (set (pc) (if_then_else (ltu (reg:CC CC_REG) (const_int 0)) |
+ (label_ref (match_dup 2)) |
+ (pc)))] |
+ "") |
+;(define_peephole2 |
+; [(set (reg:CC CC_REG) (compare:CC |
+; (match_operand:SI 0 "register_operand") |
+; (match_operand 1 "const_int_operand"))) |
+; (set (pc) (if_then_else (gtu (reg:CC CC_REG) (const_int 0)) |
+; (label_ref (match_operand 2 "")) |
+; (pc)))] |
+; "" |
+; [(set (reg:CC CC_REG) (compare:CC (match_dup 0) (match_dup 1))) |
+; (set (pc) (if_then_else (geu (reg:CC CC_REG) (const_int 0)) |
+; (label_ref (match_dup 2)) |
+; (pc)))] |
+; "operands[1] = GEN_INT(INTVAL(operands[1])-1);") |
+; |
+; |
+; Match: |
8932,7 → 9408,7
+ (set (pc) (if_then_else (geu (reg:CC CC_REG) (const_int 0)) |
+ (label_ref (match_operand 2 "")) |
+ (pc)))] |
+ "" |
+ "(ZIP_PEEPHOLE)" |
+ [(set (reg:CC CC_REG) (compare:CC |
+ (match_dup 1) (plus (match_dup 0) (const_int 1)))) |
+ (set (pc) (if_then_else (ltu (reg:CC CC_REG) (const_int 0)) |
8955,7 → 9431,7
+ (set (pc) (if_then_else (ge (reg:CC CC_REG) (const_int 0)) |
+ (label_ref (match_operand 2 "")) |
+ (pc)))] |
+ "" |
+ "(ZIP_PEEPHOLE)" |
+ [(set (reg:CC CC_REG) (compare:CC (match_dup 1) |
+ (plus:SI (match_dup 0) (const_int 1)))) |
+ (set (pc) (if_then_else (lt (reg:CC CC_REG) (const_int 0)) |
8978,7 → 9454,7
+ (set (pc) (if_then_else (leu (reg:CC CC_REG) (const_int 0)) |
+ (label_ref (match_operand 2 "" "")) |
+ (pc)))] |
+ "" |
+ "(ZIP_PEEPHOLE)" |
+ [(set (reg:CC CC_REG) (compare:CC (match_dup 0) |
+ (plus (match_dup 1) (const_int 1)))) |
+ (set (pc) (if_then_else (ltu (reg:CC CC_REG) (const_int 0)) |
8986,39 → 9462,81
+ (pc)))] |
+ "") |
+; |
+; I need to revisit these peephole optimizations when I can come up with another |
+; way of adding one to the constant integer. The approach listed below just |
+; ... doesn't work. |
+(define_peephole2 |
+ [(set (reg:CC CC_REG) |
+ (compare:CC (match_operand:SI 0 "register_operand" "") |
+ (match_operand:SI 1 "const_int_operand" ""))) |
+ (set (pc) (if_then_else (le (reg:CC CC_REG) (const_int 0)) |
+ (label_ref (match_operand 2 "" "")) |
+ (pc)))] |
+ "(ZIP_PEEPHOLE)&&(INTVAL(operands[1])<((1<<17)-2))" |
+ [(set (reg:CC CC_REG) (compare:CC (match_dup 0) (match_dup 1))) |
+ (set (pc) (if_then_else (lt (reg:CC CC_REG) (const_int 0)) |
+ (label_ref (match_dup 2)) |
+ (pc)))] |
+ "operands[1] = GEN_INT(INTVAL(operands[1])+1);") |
+(define_peephole2 |
+ [(set (reg:CC CC_REG) |
+ (compare:CC (match_operand:SI 0 "register_operand" "") |
+ (match_operand:SI 1 "const_int_operand" ""))) |
+ (set (pc) (if_then_else (leu (reg:CC CC_REG) (const_int 0)) |
+ (label_ref (match_operand 2 "" "")) |
+ (pc)))] |
+ "(ZIP_PEEPHOLE)&&(INTVAL(operands[1])<((1<<17)-2))" |
+ [(set (reg:CC CC_REG) (compare:CC (match_dup 0) (match_dup 1))) |
+ (set (pc) (if_then_else (lt (reg:CC CC_REG) (const_int 0)) |
+ (label_ref (match_dup 2)) |
+ (pc)))] |
+ "operands[1] = GEN_INT(INTVAL(operands[1])+1);") |
+; |
+;(define_peephole2 |
+; [(set (reg:CC CC_REG) (compare (match_operand:SI 0 "register_operand" "") |
+; (match_operand:SI 1 "const_int_operand" ""))) |
+; (set (pc) (if_then_else (le (reg:CC CC_REG) (const_int 0)) |
+; (label_ref (match_operand 2 "" "")) |
+; (pc)))] |
+; "(INTVAL(operands[1])<((1<<17)-2))" |
+; [(set (reg:CC CC_REG) (compare (match_dup 0) (plus (match_dup 1) (const_int 1)))) |
+; (set (pc) (if_then_else (lt (reg:CC CC_REG) (const_int 0)) |
+; (label_ref (match_dup 2)) |
+; (pc)))] |
+; "") |
+;(define_peephole2 |
+; [(set (reg:CC CC_REG) (compare (match_operand:SI 0 "register_operand" "") |
+; (match_operand:SI 1 "const_int_operand" ""))) |
+; (set (pc) (if_then_else (leu (reg:CC CC_REG) (const_int 0)) |
+; (label_ref (match_operand 2 "" "")) |
+; (pc)))] |
+; "(INTVAL(operands[1])<((1<<17)-2))" |
+; [(set (reg:CC CC_REG) (compare (match_dup 0) (plus (match_dup 1) (const_int 1)))) |
+; (set (pc) (if_then_else (lt (reg:CC CC_REG) (const_int 0)) |
+; (label_ref (match_dup 2)) |
+; (pc)))] |
+; "") |
+; |
+; |
+; |
+; Match: |
+; (parallel [(set () ()) (clobber (CC))]) |
+; (compare () ()) |
+; Transform to: |
+; (parallel [(set () ()) (set (CC) (0))] |
+; (compare () ()) |
+; |
+(define_peephole2 |
+ [(parallel [(set (match_operand:SI 0 "") (match_operand:SI 1 "")) |
+ (clobber (reg:CC CC_REG))]) |
+ (set (reg:CC CC_REG) (compare:CC (match_operand:SI 2 "") |
+ (match_operand:SI 3 "")))] |
+ "(ZIP_PEEPHOLE)&&zip_insn_sets_cc(insn)" |
+ [(parallel [(set (match_dup 0) (match_dup 1)) |
+ (set (reg:CC CC_REG) (compare:CC (match_dup 0) (const_int 0)))]) |
+ (set (reg:CC CC_REG) (compare:CC (match_dup 2) (match_dup 3)))] |
+ "") |
+; |
+; |
+; |
+; Match: |
+; (parallel [(set () ()) (clobber (CC))]) |
+; (set () ()) |
+; (compare () ()) |
+; Transform to: |
+; (parallel [(set () ()) (set (CC) (0))] |
+; (set () ()) |
+; (compare () ()) |
+; |
+(define_peephole2 |
+ [(parallel [(set (match_operand:SI 0 "") (match_operand:SI 1 "")) |
+ (clobber (reg:CC CC_REG))]) |
+ (set (match_operand 2 "") (match_operand 3 "")) |
+ (set (reg:CC CC_REG) (compare:CC (match_operand:SI 4 "") |
+ (match_operand:SI 5 "")))] |
+ "(ZIP_PEEPHOLE)&&(zip_insn_sets_cc(insn))&&((!REG_P(operands[2]))||(REGNO(operands[2])!=CC_REG))" |
+ [(parallel [(set (match_dup 0) (match_dup 1)) |
+ (set (reg:CC CC_REG) (compare:CC (match_dup 0) (const_int 0)))]) |
+ (set (match_dup 2) (match_dup 3)) |
+ (set (reg:CC CC_REG) (compare:CC (match_dup 4) (match_dup 5)))] |
+ "") |
+; |
+; |
+; |
+; Match: |
+; MOV A(R1),R3 |
+; CMP R3,R0 |
+; (R3 is dead) |
9032,7 → 9550,7
+ (set (reg:CC CC_REG) |
+ (compare:CC (match_operand:SI 0 "register_operand") |
+ (match_dup 3)))] |
+ "peep2_regno_dead_p(2, REGNO(operands[3]))" |
+ "(ZIP_PEEPHOLE)&&peep2_regno_dead_p(2, REGNO(operands[3]))" |
+ [(set (reg:CC CC_REG) (compare:CC (match_dup 0) |
+ (plus:SI (match_dup 1) (match_dup 2))))] |
+ "") |
9049,7 → 9567,7
+ (match_operand:SI 1 "")) |
+ (set (reg:CC CC_REG) (compare:CC (match_dup 0) (const_int 0)))]) |
+ (set (reg:CC CC_REG) (compare:CC (match_dup 0) (const_int 0)))] |
+ "" |
+ "(ZIP_PEEPHOLE)" |
+ [(parallel [(set (match_dup 0) (match_dup 1)) |
+ (set (reg:CC CC_REG) (compare:CC (match_dup 0) (const_int 0)))]) |
+ ]) |
9058,7 → 9576,7
+; Match: |
+; ALU OpB,R0 |
+; MOV R1,R2 // Can be LDI, LOD, STO, etc. |
+; CMP 0,R1 |
+; CMP 0,R0 |
+; Transform to: |
+; ALU OpB,R0 |
+; MOV R0,R1 |
9069,7 → 9587,7
+ (set (reg:CC CC_REG) (compare:CC (match_dup 0) (const_int 0)))]) |
+ (set (match_operand:SI 2 "nonimmediate_operand") (match_operand:SI 3 "")) |
+ (set (reg:CC CC_REG) (compare:CC (match_dup 0) (const_int 0)))] |
+ "(!REG_P(operands[2]))||((REGNO(operands[2])!=REGNO(operands[0]))&&((REGNO(operands[2])>FIRST_PSEUDO_REGISTER)||(REGNO(operands[2])<CC_REG)))" |
+ "(ZIP_PEEPHOLE)&&((!REG_P(operands[2]))||((REGNO(operands[2])!=REGNO(operands[0]))&&((REGNO(operands[2])>=FIRST_PSEUDO_REGISTER)||(REGNO(operands[2])<CC_REG))))" |
+ [(parallel [(set (match_dup 0) (match_dup 1)) |
+ (set (reg:CC CC_REG) (compare:CC (match_dup 0) (const_int 0)))]) |
+ (set (match_dup 2) (match_dup 3)) |
9090,7 → 9608,7
+ (set (reg:CC CC_REG) (compare:CC (match_dup 0) (const_int 0)))]) |
+ (set (match_operand:SI 2 "register_operand") (match_dup 0)) |
+ (set (reg:CC CC_REG) (compare:CC (match_dup 2) (const_int 0)))] |
+ "" |
+ "(ZIP_PEEPHOLE)" |
+ [(parallel [(set (match_dup 0) (match_dup 1)) |
+ (set (reg:CC CC_REG) (compare:CC (match_dup 0) (const_int 0)))]) |
+ (set (match_dup 2) (match_dup 3)) |
9098,18 → 9616,11
+; |
+; |
+; Match: |
+; MOV A(R0),R0 |
+; ADD $x,R1 |
+; (CCREG is dead, and (A+x) is within range ...) |
+; Transform to: |
+; MOV (A+$x)(R1),R0 |
+; ... how do I do the plus? Let's build it with a plus of zero, and work from |
+; there |
+; MOV R1,R0 |
+; ADD $x,R0 |
+; (CCREG is dead, and x is within range ...) |
+; Transform to: |
+; MOV (A+$x)(R1),R0 |
+; MOV $x(R1),R0 |
+(define_peephole2 |
+ [(set (match_operand:SI 0 "register_operand") |
+ (match_operand:SI 1 "register_operand")) |
9117,11 → 9628,32
+ (match_operand 2 "zip_mvimm_operand_p"))) |
+ (set (reg:CC CC_REG) (compare:CC (match_dup 0) (const_int 0)))]) |
+ ] |
+ "(peep2_regno_dead_p(2,CC_REG))" |
+ "(ZIP_PEEPHOLE)&&(peep2_regno_dead_p(2,CC_REG))" |
+ [(set (match_dup 0) (plus:SI (match_dup 1) (match_dup 2)))]) |
+; |
+; Match: |
+; MOV A(R0),R0 |
+; ADD $x,R1 |
+; (CCREG is dead, and (A+x) is within range ...) |
+; Transform to: |
+; MOV $x(R1),R0 |
+; |
+(define_peephole2 |
+ [(set (match_operand:SI 0 "register_operand") |
+ (plus:SI (match_operand:SI 1 "register_operand") |
+ (match_operand 2 "zip_mvimm_operand_p"))) |
+ (parallel [(set (match_dup 0) (plus:SI (match_dup 0) |
+ (match_operand 3 "zip_mvimm_operand_p"))) |
+ (set (reg:CC CC_REG) (compare:CC (match_dup 0) (const_int 0)))]) |
+ ] |
+ "(ZIP_PEEPHOLE)&&(peep2_regno_dead_p(2,CC_REG)) |
+ &&(INTVAL(operands[2])+INTVAL(operands[3])<((1<<17))) |
+ &&(INTVAL(operands[2])+INTVAL(operands[3])>=-(1<<17))" |
+ [(set (match_dup 0) (plus:SI (match_dup 1) (match_dup 2)))] |
+ "operands[2]=GEN_INT(INTVAL(operands[2])+INTVAL(operands[3]));") |
+; |
+; |
+; |
+; Match: |
+; ADD $x,R0 |
+; MOV R0,R1 |
9136,11 → 9668,38
+ (match_operand 1 "zip_mvimm_operand_p"))) |
+ (set (reg:CC CC_REG) (compare:CC (match_dup 0) (const_int 0)))]) |
+ (set (match_operand:SI 2 "register_operand") (match_dup 0))] |
+ "(peep2_regno_dead_p(2, REGNO(operands[0])))&&(peep2_regno_dead_p(2,CC_REG))" |
+ "(ZIP_PEEPHOLE)&&(peep2_regno_dead_p(2, REGNO(operands[0])))&&(peep2_regno_dead_p(2,CC_REG))" |
+ [(set (match_dup 2) (plus:SI (match_dup 0) (match_dup 1)))]) |
+; |
+; |
+; |
+; Match: |
+; ADD $x,R0 |
+; MOV A(R0),R1 |
+; (CCREG is dead, and R0 is dead) |
+; Transform to: |
+; MOV (A+$x)(R0),R1 |
+; |
+(define_peephole2 |
+ [(parallel [ |
+ (set (match_operand:SI 0 "register_operand") |
+ (plus:SI (match_dup 0) |
+ (match_operand 1 "zip_mvimm_operand_p"))) |
+ (set (reg:CC CC_REG) (compare:CC (match_dup 0) (const_int 0)))]) |
+ (set (match_operand:SI 2 "register_operand") |
+ (plus:SI (match_dup 0) |
+ (match_operand 3 "zip_mvimm_operand_p"))) |
+ ] |
+ "(ZIP_PEEPHOLE)&&(peep2_regno_dead_p(2,CC_REG)) |
+ &&(peep2_regno_dead_p(1,REGNO(operands[0]))) |
+ &&(INTVAL(operands[1])+INTVAL(operands[3])<((1<<17))) |
+ &&(INTVAL(operands[1])+INTVAL(operands[3])>=-(1<<17))" |
+ [(set (match_dup 0) (plus:SI (match_dup 2) (match_dup 3)))] |
+ "operands[3]=GEN_INT(INTVAL(operands[1])+INTVAL(operands[3]));") |
+; |
+; |
+; |
+; Match: |
+; ADD $x,R0 |
+; ADD R0,Rn |
+; (R0 is dead, if R0 is not Rn) |
9156,7 → 9715,7
+ (plus:SI (match_dup 2) (match_dup 0))) |
+ (set (reg:CC CC_REG) (compare:CC (match_dup 2) (const_int 0)))]) |
+ ] |
+ "(REGNO(operands[0])!=REGNO(operands[2]))&&(peep2_regno_dead_p(2, REGNO(operands[0])))" |
+ "(ZIP_PEEPHOLE)&&(REGNO(operands[0])!=REGNO(operands[2]))&&(peep2_regno_dead_p(2, REGNO(operands[0])))" |
+ [(parallel [(set (match_dup 2) |
+ (plus:SI (match_dup 2) |
+ (plus:SI (match_dup 0) |
9180,11 → 9739,25
+ (mem:SI (plus:SI (match_dup 0) |
+ (match_operand 2 "zip_opb_immv_p")))) |
+ ] |
+ "(REGNO(operands[0])!=REGNO(operands[1]))&&(INTVAL(operands[1])==-INTVAL(operands[2]))" |
+ "(ZIP_PEEPHOLE)&&(REGNO(operands[0])!=REGNO(operands[1]))&&(INTVAL(operands[1])==-INTVAL(operands[2]))" |
+ [(set (match_dup 3) (mem:SI (match_dup 0))) |
+ (parallel [(set (match_dup 0) (plus:SI (match_dup 0) (match_dup 1))) |
+ (set (reg:CC CC_REG) (compare:CC (match_dup 0) (const_int 0)))]) |
+ ]) |
+(define_peephole2 |
+ [(parallel [(set (match_operand:SI 0 "register_operand") |
+ (plus:SI (match_dup 0) |
+ (match_operand 1 "zip_opb_immv_p"))) |
+ (clobber (reg:CC CC_REG))]) |
+ (set (match_operand:SI 3 "register_operand") |
+ (mem:SI (plus:SI (match_dup 0) |
+ (match_operand 2 "zip_opb_immv_p")))) |
+ ] |
+ "(ZIP_PEEPHOLE)&&(REGNO(operands[0])!=REGNO(operands[1]))&&(INTVAL(operands[1])==-INTVAL(operands[2]))" |
+ [(set (match_dup 3) (mem:SI (match_dup 0))) |
+ (parallel [(set (match_dup 0) (plus:SI (match_dup 0) (match_dup 1))) |
+ (set (reg:CC CC_REG) (compare:CC (match_dup 0) (const_int 0)))]) |
+ ]) |
+; |
+; |
+; |
9203,11 → 9776,24
+ (set (mem:SI (plus:SI (match_dup 0) (match_operand 2 "zip_opb_immv_p"))) |
+ (match_operand:SI 3 "register_operand")) |
+ ] |
+ "(REGNO(operands[0])!=REGNO(operands[1]))&&(INTVAL(operands[1])==-INTVAL(operands[2]))" |
+ "(ZIP_PEEPHOLE)&&(REGNO(operands[0])!=REGNO(operands[1]))&&(INTVAL(operands[1])==-INTVAL(operands[2]))" |
+ [(set (mem:SI (match_dup 0)) (match_dup 3)) |
+ (parallel [(set (match_dup 0) (plus:SI (match_dup 0) (match_dup 1))) |
+ (set (reg:CC CC_REG) (compare:CC (match_dup 0) (const_int 0)))]) |
+ ]) |
+(define_peephole2 |
+ [(parallel [(set (match_operand:SI 0 "register_operand") |
+ (plus:SI (match_dup 0) |
+ (match_operand 1 "zip_opb_immv_p"))) |
+ (clobber (reg:CC CC_REG))]) |
+ (set (mem:SI (plus:SI (match_dup 0) (match_operand 2 "zip_opb_immv_p"))) |
+ (match_operand:SI 3 "register_operand")) |
+ ] |
+ "(ZIP_PEEPHOLE)&&(REGNO(operands[0])!=REGNO(operands[1]))&&(INTVAL(operands[1])==-INTVAL(operands[2]))" |
+ [(set (mem:SI (match_dup 0)) (match_dup 3)) |
+ (parallel [(set (match_dup 0) (plus:SI (match_dup 0) (match_dup 1))) |
+ (set (reg:CC CC_REG) (compare:CC (match_dup 0) (const_int 0)))]) |
+ ]) |
+; |
+; |
+; Match: |
9221,13 → 9807,85
+; |
+; |
+; |
+; Need a peephole optimizer (not peephole2) for |
+; [(call ... |
+; (set (pc) (label))] |
+; To result with |
+; "MOV\tlabel,R0 |
+; JMP\tsubroutine" |
+; Match: |
+; MOV R1,R0 |
+; AND #/R2,R0 |
+; (Ry dead ...) |
+; Transform to: |
+; TEST #/Rz,Rx |
+; |
+(define_peephole2 |
+ [(set (match_operand:SI 0 "register_operand") |
+ (match_operand:SI 1 "register_operand")) |
+ (parallel [(set (match_dup 0) |
+ (and:SI (match_dup 0) |
+ (match_operand:SI 2 "zip_opb_single_operand_p"))) |
+ (set (reg:CC CC_REG) (compare:CC (match_dup 0) (const_int 0)))]) |
+ ] |
+ "((1)||(ZIP_PEEPHOLE))&&(peep2_regno_dead_p(2, REGNO(operands[0])))" |
+ [(set (reg:CC CC_REG) (compare:CC (and:ZI (match_dup 1) (match_dup 2)) |
+ (const_int 0)))]) |
+; |
+; Match: |
+; (call ... |
+; (set (pc) (label)) |
+; or (in asm) |
+; MOV .Lcallx(PC),R0 |
+; BRA (somewhere) |
+; .Lcallx |
+; BRA (somewhere-else) |
+; Transform to: |
+; |
+; (sequence [(call ... |
+; (set (pc) (label))]) |
+; or (in asm) |
+; "LDI (somewhere-else),R0 |
+; BRA subroutine" |
+; |
+; While the following looks good, it doesnt work. My guess is that the reason |
+; why it doesnt work is that the jump at the end crosses basic block boundaries. |
+; |
+;(define_insn "void_call_mem_unspec" |
+; [(call (unspec:SI [(mem:SI (match_operand:VOID 0 "zip_const_address_operand_p" ""))] UNSPEC_RAW_CALL) |
+; (match_operand 1 "const_int_operand" "n")) |
+; (clobber (reg:SI RTN_REG)) |
+; (clobber (reg:CC CC_REG))] |
+; "" |
+; "BRA\t%0,PC" |
+; [(set_attr "predicable" "no") (set_attr "ccresult" "unknown")]) |
+;(define_peephole2 |
+; [(parallel [(call (mem:SI (match_operand:VOID 0 "zip_const_address_operand_p")) |
+; (match_operand 1 "const_int_operand")) |
+; (clobber (reg:SI RTN_REG)) |
+; (clobber (reg:CC CC_REG))]) |
+; ; The match operand for the (set (pc) ...) cannot have anything but |
+; ; VOIDmode, or it wont match. |
+; (set (pc) (match_operand:VOID 2 "zip_const_address_operand_p"))] |
+; "" |
+; [(set (reg:SI RTN_REG) (match_dup 2)) |
+; (call (unspec:SI [(mem:SI (match_operand:VOID 0 "zip_const_address_operand_p"))] UNSPEC_RAW_CALL) |
+; (match_operand 1 "const_int_operand")) |
+; (use (reg:SI RTN_REG)) |
+; (clobber (reg:SI RTN_REG)) |
+; (clobber (reg:CC CC_REG))] |
+; "fprintf(stderr, \"CALL-JUMP Matched\");") |
+; |
+; |
+; |
+; So, the following *should* have worked as well. However, this falls apart |
+; because the 'final' routine can't tell if we are calling a subroutine in this |
+; function or not. |
+; |
+;(define_peephole |
+ ;[(parallel [(call (mem:SI (match_operand:SI 0 "zip_const_address_operand_p")) |
+ ;(match_operand 1 "const_int_operand")) |
+ ;(clobber (reg:SI RTN_REG)) |
+ ;(clobber (reg:CC CC_REG))]) |
+ ;(set (pc) (label_ref (match_operand 2 "")))] |
+ ;"" |
+ ;"LDI\t%2,R0\;BRA\t%0" |
+ ;[(set_attr "predicable" "no") (set_attr "ccresult" "unknown")]) |
+; |
+; and for |
+; BRA target |
+; BRA target ; two branches to the same identical target in a row ... |
9270,8 → 9928,8
+// config directory. |
diff -Naur '--exclude=*.swp' gcc-5.3.0-original/gcc/config/zip/zip-protos.h gcc-5.3.0-zip/gcc/config/zip/zip-protos.h |
--- gcc-5.3.0-original/gcc/config/zip/zip-protos.h 1969-12-31 19:00:00.000000000 -0500 |
+++ gcc-5.3.0-zip/gcc/config/zip/zip-protos.h 2016-04-06 14:25:35.431154171 -0400 |
@@ -0,0 +1,78 @@ |
+++ gcc-5.3.0-zip/gcc/config/zip/zip-protos.h 2016-04-21 16:19:02.122215475 -0400 |
@@ -0,0 +1,82 @@ |
+//////////////////////////////////////////////////////////////////////////////// |
+// |
+// Filename: zip-protos.h |
9310,8 → 9968,10
+#ifndef ZIP_PROTOS_H |
+#define ZIP_PROTOS_H |
+ |
+extern bool zip_supported_condition(int c); |
+extern void zip_expand_prologue(void); |
+extern void zip_expand_epilogue(void); |
+extern void zip_expand_movsicc(rtx,rtx,rtx,rtx); |
+extern int zip_initial_elimination_offset(int, int); |
+extern void zip_print_operand(FILE *, rtx, int); |
+extern void zip_print_operand_address(FILE *, rtx); |
9333,6 → 9993,8
+extern const char *zip_set_zero_or_one(rtx, rtx); |
+extern const char *zip_movsicc(rtx, rtx, rtx, rtx); |
+ |
+extern int zip_insn_sets_cc(rtx_insn *insn); |
+extern int zip_is_conditional(rtx_insn *insn); |
+extern int zip_ct_address_operand(rtx op); |
+extern int zip_pd_opb_operand(rtx op); |
+extern int zip_pd_mov_operand(rtx op); |
9503,6 → 10165,24
#else |
#error Unknown BITS_PER_UNIT |
#endif |
diff -Naur '--exclude=*.swp' gcc-5.3.0-original/gcc/df-scan.c gcc-5.3.0-zip/gcc/df-scan.c |
--- gcc-5.3.0-original/gcc/df-scan.c 2015-01-09 15:18:42.000000000 -0500 |
+++ gcc-5.3.0-zip/gcc/df-scan.c 2016-04-14 16:12:03.614777002 -0400 |
@@ -61,6 +61,14 @@ |
|
typedef struct df_mw_hardreg *df_mw_hardreg_ptr; |
|
+// #define DO_ZIP_DEBUGS |
+#ifdef DO_ZIP_DEBUGS |
+extern void zip_debug_rtx(const_rtx); |
+#define ZIP_DEBUG_LINE(STR,RTX) do { fprintf(stderr, "%s:%d/%s\n", __FILE__,__LINE__,STR); zip_debug_rtx(RTX); } while(0) |
+#else |
+#define ZIP_DEBUG_LINE(STR,RTX) |
+#endif |
+ |
|
#ifndef HAVE_epilogue |
#define HAVE_epilogue 0 |
diff -Naur '--exclude=*.swp' gcc-5.3.0-original/gcc/doc/gcc.log gcc-5.3.0-zip/gcc/doc/gcc.log |
--- gcc-5.3.0-original/gcc/doc/gcc.log 1969-12-31 19:00:00.000000000 -0500 |
+++ gcc-5.3.0-zip/gcc/doc/gcc.log 2016-01-30 15:18:43.262724969 -0500 |
9723,7 → 10403,7
+duced! |
diff -Naur '--exclude=*.swp' gcc-5.3.0-original/gcc/emit-rtl.c gcc-5.3.0-zip/gcc/emit-rtl.c |
--- gcc-5.3.0-original/gcc/emit-rtl.c 2015-08-05 07:20:59.000000000 -0400 |
+++ gcc-5.3.0-zip/gcc/emit-rtl.c 2016-04-01 06:40:42.812171791 -0400 |
+++ gcc-5.3.0-zip/gcc/emit-rtl.c 2016-04-20 20:54:45.148982373 -0400 |
@@ -81,6 +81,15 @@ |
#include "builtins.h" |
#include "rtl-iter.h" |
9740,16 → 10420,7
struct target_rtl default_target_rtl; |
#if SWITCHABLE_TARGET |
struct target_rtl *this_target_rtl = &default_target_rtl; |
@@ -2925,6 +2934,8 @@ |
int copied = 0; |
int length; |
|
+ZIP_DEBUG_LINE("Copy RTX if shared",*orig1); |
+ |
/* Repeat is used to turn tail-recursion into iteration. */ |
repeat: |
x = *orig1; |
@@ -2979,6 +2990,8 @@ |
@@ -2979,6 +2988,8 @@ |
break; |
} |
|
9758,7 → 10429,7
/* This rtx may not be shared. If it has already been seen, |
replace it with a copy of itself. */ |
|
@@ -2989,6 +3002,8 @@ |
@@ -2989,6 +3000,8 @@ |
} |
RTX_FLAG (x, used) = 1; |
|
9767,6 → 10438,24
/* Now scan the subexpressions recursively. |
We can store any replaced subexpressions directly into X |
since we know X is not shared! Any vectors in X |
@@ -3665,7 +3678,9 @@ |
split_branch_probability = XINT (note, 0); |
probability = split_branch_probability; |
|
+ZIP_DEBUG_LINE("Before split", trial); |
seq = safe_as_a <rtx_insn *> (split_insns (pat, trial)); |
+ZIP_DEBUG_LINE("After split", seq); |
|
split_branch_probability = -1; |
|
@@ -3834,6 +3849,7 @@ |
if (! tem->deleted () && INSN_P (tem)) |
tem = try_split (PATTERN (tem), tem, 1); |
|
+ |
/* Return either the first or the last insn, depending on which was |
requested. */ |
return last |
diff -Naur '--exclude=*.swp' gcc-5.3.0-original/gcc/expr.c gcc-5.3.0-zip/gcc/expr.c |
--- gcc-5.3.0-original/gcc/expr.c 2015-04-07 10:34:06.000000000 -0400 |
+++ gcc-5.3.0-zip/gcc/expr.c 2016-03-08 04:07:01.426335724 -0500 |
9781,7 → 10470,7
enum expand_modifier modifier, rtx *alt_rtl, |
diff -Naur '--exclude=*.swp' gcc-5.3.0-original/gcc/final.c gcc-5.3.0-zip/gcc/final.c |
--- gcc-5.3.0-original/gcc/final.c 2015-01-15 08:28:42.000000000 -0500 |
+++ gcc-5.3.0-zip/gcc/final.c 2016-04-12 22:11:51.147370235 -0400 |
+++ gcc-5.3.0-zip/gcc/final.c 2016-04-20 20:52:07.186056061 -0400 |
@@ -109,6 +109,14 @@ |
#include "wide-int-print.h" |
#include "rtl-iter.h" |
10167,7 → 10856,7
|
diff -Naur '--exclude=*.swp' gcc-5.3.0-original/gcc/recog.c gcc-5.3.0-zip/gcc/recog.c |
--- gcc-5.3.0-original/gcc/recog.c 2015-03-20 02:07:30.000000000 -0400 |
+++ gcc-5.3.0-zip/gcc/recog.c 2016-04-06 17:45:29.552304498 -0400 |
+++ gcc-5.3.0-zip/gcc/recog.c 2016-04-14 23:19:07.630839483 -0400 |
@@ -68,6 +68,15 @@ |
#include "df.h" |
#include "insn-codes.h" |
10210,7 → 10899,7
|
diff -Naur '--exclude=*.swp' gcc-5.3.0-original/gcc/reload1.c gcc-5.3.0-zip/gcc/reload1.c |
--- gcc-5.3.0-original/gcc/reload1.c 2015-01-15 08:28:42.000000000 -0500 |
+++ gcc-5.3.0-zip/gcc/reload1.c 2016-04-13 11:32:23.013097569 -0400 |
+++ gcc-5.3.0-zip/gcc/reload1.c 2016-04-20 20:51:38.590252867 -0400 |
@@ -72,6 +72,14 @@ |
#include "dumpfile.h" |
#include "rtl-iter.h" |
10226,12 → 10915,13
/* This file contains the reload pass of the compiler, which is |
run after register allocation has been done. It checks that |
each insn is valid (operands required to be in registers really |
@@ -794,6 +802,18 @@ |
@@ -794,6 +802,20 @@ |
basic_block bb; |
bool inserted; |
|
+#ifdef DO_ZIP_DEBUGS |
+ { |
+ fprintf(stderr, "BEFORE-RELOAD\n"); |
+ int total_count = 0, current_count = 0; |
+ for (insn = first; insn; insn = NEXT_INSN (insn)) |
+ total_count++; |
10239,6 → 10929,7
+ fprintf(stderr, "B %3d/%3d", current_count++, total_count); |
+ zip_debug_rtx(insn); |
+ } |
+ fprintf(stderr, "BEFORE-RELOAD -- END OF INSTRUCTION LIST\n"); |
+ } |
+#endif |
+ |
10245,12 → 10936,13
/* Make sure even insns with volatile mem refs are recognizable. */ |
init_recog (); |
|
@@ -1366,6 +1386,18 @@ |
@@ -1366,6 +1388,20 @@ |
|
reload_completed = !failure; |
|
+#ifdef DO_ZIP_DEBUGS |
+ { |
+ fprintf(stderr, "AFTER-RELOAD\n"); |
+ int total_count = 0, current_count = 0; |
+ for (insn = first; insn; insn = NEXT_INSN (insn)) |
+ total_count++; |
10258,6 → 10950,7
+ fprintf(stderr, "A %3d/%3d", current_count++, total_count); |
+ zip_debug_rtx(insn); |
+ } |
+ fprintf(stderr, "AFTER-RELOAD -- END OF INSTRUCTION LIST\n"); |
+ } |
+#endif |
+ |
/trunk/sw/binutils-2.25.patch
28,7 → 28,7
}; |
diff -Naur '--exclude=*.swp' binutils-2.25-original/bfd/bfd-in2.h binutils-2.25/bfd/bfd-in2.h |
--- binutils-2.25-original/bfd/bfd-in2.h 2014-11-04 04:54:41.000000000 -0500 |
+++ binutils-2.25/bfd/bfd-in2.h 2016-02-25 09:45:29.607954979 -0500 |
+++ binutils-2.25/bfd/bfd-in2.h 2016-04-19 07:41:48.387151802 -0400 |
@@ -2283,6 +2283,8 @@ |
#define bfd_mach_aarch64_ilp32 32 |
bfd_arch_nios2, |
38,7 → 38,7
bfd_arch_last |
}; |
|
@@ -6066,6 +6068,24 @@ |
@@ -6066,6 +6068,25 @@ |
|
/* Adapteva EPIPHANY - 8 bit immediate for 16 bit mov instruction. */ |
BFD_RELOC_EPIPHANY_IMM8, |
55,6 → 55,7
+ BFD_RELOC_ZIP_LDI, |
+ BFD_RELOC_ZIP_LLO, |
+ BFD_RELOC_ZIP_LHI, |
+ BFD_RELOC_ZIP_BREV, |
+ |
+/* This is the same as the ZIP_VALUE relocation, save only that the value is |
+right shifted by two, since it is an address and Zip addresses increment |
231,8 → 232,8
|
diff -Naur '--exclude=*.swp' binutils-2.25-original/bfd/elf32-zip.c binutils-2.25/bfd/elf32-zip.c |
--- binutils-2.25-original/bfd/elf32-zip.c 1969-12-31 19:00:00.000000000 -0500 |
+++ binutils-2.25/bfd/elf32-zip.c 2016-03-27 21:14:45.877301706 -0400 |
@@ -0,0 +1,1149 @@ |
+++ binutils-2.25/bfd/elf32-zip.c 2016-04-21 10:09:50.311094483 -0400 |
@@ -0,0 +1,1280 @@ |
+//////////////////////////////////////////////////////////////////////////////// |
+// |
+// Filename: tc-zip.c |
272,10 → 273,12
+//////////////////////////////////////////////////////////////////////////////// |
+#include "sysdep.h" |
+#include "bfd.h" |
+#include "bfdlink.h" |
+#include "libbfd.h" |
+#include "elf-bfd.h" |
+#include "elf/zip.h" |
+#include <limits.h> |
+#include <stdint.h> |
+ |
+/* |
+bfd_reloc_status_type |
283,6 → 286,10
+ asection *, bfd *, char **); |
+*/ |
+#define zip_relocation bfd_elf_generic_reloc |
+static bfd_reloc_status_type |
+zip_brev_relocation(bfd *, arelent *, asymbol *, void *, asection *, |
+ bfd *, char **error_messsage); |
+static uint32_t zip_bitreverse(uint32_t v); |
+ |
+/* Forward declarations. */ |
+static reloc_howto_type zip_elf_howto_table [] = |
464,6 → 471,20
+ 0x0000ffff, /* dst_mask */ |
+ FALSE), /* pcrel_offset */ |
+ |
+ HOWTO (R_ZIP_BREV, /* type -- LDIHI, but with bitreverse */ |
+ 0, /* rightshift */ |
+ 2, /* size (0 = byte, 1 = short, 2 = long) */ |
+ 16, /* bitsize */ |
+ FALSE, /* pc_relative */ |
+ 0, /* bitpos */ |
+ complain_overflow_bitfield, /* complain_on_overflow */ |
+ zip_brev_relocation, /* special_function--needed for the bitreverse */ |
+ "R_ZIP_BREV", /* name */ |
+ FALSE, /* partial_inplace */ |
+ 0, /* src_mask */ |
+ 0x0003ffff, /* dst_mask */ |
+ FALSE), /* pcrel_offset */ |
+ |
+ HOWTO (R_ZIP_BROKEN_BYTE, /* type */ |
+ 0, /* rightshift */ |
+ 2, /* size (0 = byte, 1 = short, 2 = long) */ |
501,6 → 522,7
+ { BFD_RELOC_ZIP_LDI, R_ZIP_LDI }, |
+ { BFD_RELOC_ZIP_LLO, R_ZIP_LLO }, |
+ { BFD_RELOC_ZIP_LHI, R_ZIP_LHI }, |
+ { BFD_RELOC_ZIP_BREV, R_ZIP_BREV }, |
+ { BFD_RELOC_14, R_ZIP_OPB_OFFSET }, |
+ { BFD_RELOC_16, R_ZIP_LLO }, |
+ { BFD_RELOC_32, R_ZIP_VALUE } |
617,10 → 639,31
+ if (info->relocatable) |
+ continue; |
+ |
+ r = _bfd_final_link_relocate(howto, input_bfd, input_section, |
+ if (howto->type == R_ZIP_BREV) { |
+ if (rel->r_offset > bfd_get_section_limit(input_bfd, input_section)) { |
+ r = bfd_reloc_outofrange; |
+ } else { |
+ uint32_t brev_reloc; |
+ bfd_byte *location; |
+ bfd_vma x; |
+ |
+ location = contents + rel->r_offset * bfd_octets_per_byte(input_bfd); |
+ |
+ relocation += rel->r_addend; |
+ brev_reloc= zip_bitreverse(relocation); |
+ x = bfd_get_32(input_bfd, location); |
+ x = ((x & ~howto->dst_mask) |
+ |(((x & howto->src_mask)+brev_reloc)&howto->dst_mask)); |
+ bfd_put_32(input_bfd, x, location); |
+ r = bfd_reloc_ok; |
+ } |
+ } else { |
+ r = _bfd_final_link_relocate(howto, input_bfd, |
+ input_section, |
+ contents, rel->r_offset, |
+ relocation, |
+ rel->r_addend); |
+ } |
+ |
+ |
+ if (r != bfd_reloc_ok) |
668,8 → 711,7
+ return TRUE; |
+} |
+ |
+#define bfd_elf32_bfd_define_common_symbol zip_define_common_symbol |
+bfd_boolean |
+static bfd_boolean |
+zip_define_common_symbol(bfd *output_bfd, |
+ struct bfd_link_info *info ATTRIBUTE_UNUSED, |
+ struct bfd_link_hash_entry *h) { |
697,8 → 739,98
+ section->flags &= ~SEC_IS_COMMON; |
+ return TRUE; |
+} |
+#define bfd_elf32_bfd_define_common_symbol zip_define_common_symbol |
+ |
+static uint32_t |
+zip_bitreverse(uint32_t v) { |
+ unsigned r = 0, b; |
+ |
+ for(b=0; b<32; b++, v>>=1) |
+ r = (r<<1)|(v&1); |
+ |
+ return r; |
+} |
+ |
+static bfd_reloc_status_type |
+zip_brev_relocation(bfd *abfd ATTRIBUTE_UNUSED, |
+ arelent *reloc_entry, |
+ asymbol *symbol, |
+ void *data ATTRIBUTE_UNUSED, |
+ asection *input_section, |
+ bfd *output_bfd, |
+ char **error_messsage ATTRIBUTE_UNUSED) |
+{ |
+ bfd_vma relocation; |
+ bfd_size_type octets = reloc_entry->address * bfd_octets_per_byte(abfd); |
+ bfd_vma output_base = 0; |
+ reloc_howto_type *howto = reloc_entry->howto; |
+ |
+ if ((output_bfd != NULL) |
+ &&((symbol->flags & BSF_SECTION_SYM)==0) |
+ &&((! reloc_entry->howto->partial_inplace) |
+ || (reloc_entry->addend == 0))) { |
+ reloc_entry->address += input_section->output_offset; |
+ return bfd_reloc_ok; |
+ } |
+ |
+ // Otherwise, we need to adjust our file itself with this value ... |
+ if (reloc_entry->address > bfd_get_section_limit(abfd, input_section)) |
+ return bfd_reloc_outofrange; |
+ |
+ // Get symbol value */ |
+ if (bfd_is_com_section(symbol->section)) |
+ relocation = 0; |
+ else |
+ relocation = symbol->value; |
+ |
+ /* Convert input-section relative symbol value to absolute */ |
+ if (((output_bfd)&&(!howto->partial_inplace)) |
+ ||(symbol->section->output_section == NULL)) |
+ output_base = 0; |
+ else |
+ output_base = symbol->section->output_section->vma; |
+ |
+ relocation += output_base + symbol->section->output_offset; |
+ |
+ /* Add in supplied addend. */ |
+ relocation += reloc_entry->addend; |
+ |
+ // BREV does not handle PC relative offsets |
+ // if howto->pcrel_offset ... |
+ |
+ // |
+ if (output_bfd != NULL) { |
+ reloc_entry->addend = relocation; |
+ reloc_entry->address += input_section->output_offset; |
+ if (!howto->partial_inplace) { |
+ return bfd_reloc_ok; |
+ } |
+ } |
+ |
+ // Ignore overflow checking ... we don't know (yet) whether or not we |
+ // even have an overflow at this point. That is, if we could. We're |
+ // encoding the top 16 (18) bits of a number, overflow is ... not a |
+ // problem. |
+ // |
+ // if howto->complain_on_overflow ... |
+ |
+ // relocation >>= howto->rightshift; // = 0 |
+ // relocation <<= howto->bitpos; // = 0 |
+ |
+ // Logic (nearly) copied from reloc.c:bfd_perform_relocation |
+ unsigned x = bfd_get_32(abfd, (bfd_byte *)data + octets); |
+ |
+ // Here's why we are going through this pain! |
+ x = zip_bitreverse((unsigned)x); |
+ |
+ // Now we can continue as before.... |
+ x = ((x&(~howto->dst_mask)) |
+ |(((x&howto->src_mask)+relocation)&howto->dst_mask)); |
+ bfd_put_32(abfd, (bfd_vma)x, (bfd_byte *)data + octets); |
+ |
+ return bfd_reloc_ok; |
+} |
+ |
+// Zip Defines |
+#define TARGET_BIG_SYM zip_elf32_vec |
+#define TARGET_BIG_NAME "elf32-zip" |
2008,8 → 2140,8
+#endif /* _ZIPBSD_H */ |
diff -Naur '--exclude=*.swp' binutils-2.25-original/bfd/libbfd.h binutils-2.25/bfd/libbfd.h |
--- binutils-2.25-original/bfd/libbfd.h 2014-11-04 04:54:41.000000000 -0500 |
+++ binutils-2.25/bfd/libbfd.h 2016-02-04 21:12:06.487473383 -0500 |
@@ -2953,6 +2953,18 @@ |
+++ binutils-2.25/bfd/libbfd.h 2016-04-19 07:41:48.395151746 -0400 |
@@ -2953,6 +2953,19 @@ |
"BFD_RELOC_EPIPHANY_SIMM11", |
"BFD_RELOC_EPIPHANY_IMM11", |
"BFD_RELOC_EPIPHANY_IMM8", |
2024,6 → 2156,7
+ "BFD_RELOC_ZIP_LDI", |
+ "BFD_RELOC_ZIP_LLO", |
+ "BFD_RELOC_ZIP_LHI", |
+ "BFD_RELOC_ZIP_BREV", |
+ "BFD_RELOC_ZIP_ADDRESS", |
"@@overflow: BFD_RELOC_UNUSED@@", |
}; |
2121,7 → 2254,7
|
diff -Naur '--exclude=*.swp' binutils-2.25-original/bfd/reloc.c binutils-2.25/bfd/reloc.c |
--- binutils-2.25-original/bfd/reloc.c 2014-10-14 03:32:02.000000000 -0400 |
+++ binutils-2.25/bfd/reloc.c 2016-02-21 19:51:11.949429002 -0500 |
+++ binutils-2.25/bfd/reloc.c 2016-04-21 10:10:44.122704152 -0400 |
@@ -1362,7 +1362,7 @@ |
} |
|
2131,15 → 2264,7
} |
|
/* Relocate a given location using a given value and howto. */ |
@@ -1524,6 +1524,7 @@ |
bfd_put_16 (input_bfd, x, location); |
break; |
case 4: |
+ // Location is WRONG here |
bfd_put_32 (input_bfd, x, location); |
break; |
case 8: |
@@ -7325,7 +7326,36 @@ |
@@ -7325,7 +7325,38 @@ |
BFD_RELOC_EPIPHANY_IMM8 |
ENUMDOC |
Adapteva EPIPHANY - 8 bit immediate for 16 bit mov instruction. |
2166,6 → 2291,8
+ BFD_RELOC_ZIP_LLO |
+ENUMX |
+ BFD_RELOC_ZIP_LHI |
+ENUMX |
+ BFD_RELOC_ZIP_BREV |
+ENUMDOC |
+ ZIP CPU value (not address) relocations. |
+ENUM |
2375,8 → 2502,8
optimize the copying in the simple case without using the |
diff -Naur '--exclude=*.swp' binutils-2.25-original/gas/config/tc-zip.c binutils-2.25/gas/config/tc-zip.c |
--- binutils-2.25-original/gas/config/tc-zip.c 1969-12-31 19:00:00.000000000 -0500 |
+++ binutils-2.25/gas/config/tc-zip.c 2016-04-08 19:37:24.940027857 -0400 |
@@ -0,0 +1,2285 @@ |
+++ binutils-2.25/gas/config/tc-zip.c 2016-04-20 18:52:24.189215496 -0400 |
@@ -0,0 +1,2317 @@ |
+//////////////////////////////////////////////////////////////////////////////// |
+// |
+// Filename: tc-zip.c |
2679,7 → 2806,9
+ case ZIPO_LSL: printf("%7s", "LSL"); break; |
+ case ZIPO_ASR: printf("%7s", "ASR"); break; |
+ case ZIPO_LDI: printf("%7s", "LDI"); break; |
+#ifndef LONG_MPY |
+ case ZIPO_LDIHI: printf("%7s", "LDIHI"); break; |
+#endif |
+ case ZIPO_LDILO: printf("%7s", "LDILO"); break; |
+ case ZIPO_MPYU: printf("%7s", "MPYU"); break; |
+ case ZIPO_MPYS: printf("%7s", "MPYS"); break; |
3143,10 → 3272,16
+ } else if (strcasecmp(opstr, "ASR")==0) { |
+ insn->i_op = ZIPO_ASR; |
+ insn_form = TWO_OP; |
+#ifdef LONG_MPY |
+ } else if (strcasecmp(opstr, "MPY")==0) { |
+ insn_form = TWO_OP; |
+ insn->i_op = ZIPO_MPY; |
+#else |
+ } else if((strcasecmp(opstr, "LDIHI")==0) |
+ ||(strcasecmp(opstr, "LHI")==0)) { |
+ insn_form = TWO_OP; |
+ insn->i_op = ZIPO_LDIHI; |
+#endif |
+ } else if((strcasecmp(opstr, "LDILO")==0) |
+ ||(strcasecmp(opstr, "LLO")==0)) { |
+ insn->i_op = ZIPO_LDILO; |
3154,6 → 3289,14
+ // } else if (strcasecmp(opstr, "MPY")==0) { |
+ // insn->i_op = ZIPO_MPY; |
+ // insn_form = TWO_OP |
+#ifdef LONG_MPY |
+ } else if (strcasecmp(opstr, "MPYUHI")==0) { // MPUHI |
+ insn->i_op = ZIPO_MPYUHI; |
+ insn_form = TWO_OP; |
+ } else if (strcasecmp(opstr, "MPYSHI")==0) { // MPSHI |
+ insn->i_op = ZIPO_MPYSHI; |
+ insn_form = TWO_OP; |
+#else |
+ } else if (strcasecmp(opstr, "MPYU")==0) { // MPUHI |
+ insn->i_op = ZIPO_MPYU; |
+ insn_form = TWO_OP; |
3160,6 → 3303,7
+ } else if (strcasecmp(opstr, "MPYS")==0) { // MPSHI |
+ insn->i_op = ZIPO_MPYS; |
+ insn_form = TWO_OP; |
+#endif |
+ } else if (strcasecmp(opstr, "BREV")==0) { |
+ insn->i_op = ZIPO_BREV; |
+ insn_form = TWO_OP; |
3459,11 → 3603,17
+ switch(insn->i_op) { |
+ case ZIPO_SUB: case ZIPO_AND: case ZIPO_ADD: case ZIPO_OR: |
+ case ZIPO_XOR: case ZIPO_LSR: case ZIPO_LSL: case ZIPO_ASR: |
+ case ZIPO_LDIHI: case ZIPO_LDILO: |
+ case ZIPO_MPYU: case ZIPO_MPYS: |
+ case ZIPO_LDILO: |
+ case ZIPO_DIVU: case ZIPO_DIVS: |
+ case ZIPO_LDI: case ZIPO_LDIn: |
+ case ZIPO_BREV: case ZIPO_POPC: case ZIPO_ROL: |
+#ifdef LONG_MPY |
+ case ZIPO_MPYUHI: case ZIPO_MPYSHI: |
+ case ZIPO_MPY: |
+#else |
+ case ZIPO_MPYU: case ZIPO_MPYS: |
+ case ZIPO_LDIHI: |
+#endif |
+ break; |
+ case ZIPO_MOV: |
+ if (insn->i_breg == ZIP_RNONE) |
3602,7 → 3752,10
+ imm = (a & 0x03fffff); break; |
+ case ZIPO_LDIn: |
+ imm = (a & 0x03fffff); imm |= -0x0200000; break; |
+ case ZIPO_LDILO: case ZIPO_LDIHI: // BREVx would rm LDIHI |
+ case ZIPO_LDILO: |
+#ifndef LONG_MPY |
+ case ZIPO_LDIHI: // BREVx would rm LDIHI |
+#endif |
+ imm = (a & 0x0ffff); break; |
+ default: |
+ if (a & 0x040000) { |
3659,7 → 3812,10
+ if (a & 0x03fff) return 0; |
+ break; |
+ case ZIPO_LDI: case ZIPO_LDIn: |
+ case ZIPO_LDILO: case ZIPO_LDIHI: // BREVx would rm LDIHI |
+ case ZIPO_LDILO: |
+#ifndef LONG_MPY |
+ case ZIPO_LDIHI: // BREVx would rm LDIHI |
+#endif |
+ // LDIxx instructions have only immediates. If the |
+ // immediate doesn't fit in 5 bits, this won't work. |
+ imma = zip_non_vliw_immediate(a); |
3687,7 → 3843,10
+ if (b & 0x03fff) return 0; |
+ break; |
+ case ZIPO_LDI: case ZIPO_LDIn: |
+ case ZIPO_LDILO: case ZIPO_LDIHI: |
+ case ZIPO_LDILO: |
+#ifndef LONG_MPY |
+ case ZIPO_LDIHI: |
+#endif |
+ // LDIxx instructions have only immediates. If the |
+ // immediate doesn't fit in 5 bits, this won't work. |
+ immb = zip_non_vliw_immediate(b); |
3941,11 → 4100,11
+ |
+ // BREV Extension would modify this statement |
+ insn->i_naux = 1; |
+ // insn->i_code = IMMOP(ZIPO_BREV, insn->i_cnd, |
+ // zip_brev(immv)&0x01ffff, insn->i_areg); |
+ insn->i_code = IMMOP(ZIPO_LDIHI, insn->i_cnd, |
+ (immv>>16)&0x0ffff, |
+ insn->i_areg); |
+ insn->i_code = IMMOP(ZIPO_BREV, insn->i_cnd, |
+ zip_brev(immv)&0x01ffff, insn->i_areg); |
+ // insn->i_code = IMMOP(ZIPO_LDIHI, insn->i_cnd, |
+ // immv&0x0ffff, |
+ // insn->i_areg); |
+ insn->i_aux[0]=IMMOP(ZIPO_LDILO, insn->i_cnd, |
+ (immv&0x0ffff), insn->i_areg); |
+ if (insn->i_rp) |
4431,12 → 4590,13
+ md_number_to_chars((char *)buf, iword, 4); |
+ fixP->fx_done = final_fix; |
+ break; |
+ // BREV extension would replace LHI here ... |
+ // case BFD_RELOC_ZIP_BREV: |
+ // iword |= zip_brev(*val)&0x01ffff; |
+ // md_number_to_chars((char *)buf, iword, 4); |
+ // fixP->fx_done = final_fix; |
+ // break; |
+ case BFD_RELOC_ZIP_BREV: |
+ // (*val) &= 0x0fffe0000; |
+ iword &= (~0x1ffff); |
+ iword |= zip_brev(*val)&0x01ffff; |
+ md_number_to_chars((char *)buf, iword, 4); |
+ fixP->fx_done = final_fix; |
+ break; |
+ case BFD_RELOC_ZIP_LHI: |
+ // printf("\tMD-APPLY-FIX: BFD_RELOC_ZIP_LHI\n"); |
+ iword |= ((*val)>>16)&0x0ffff; |
4617,9 → 4777,8
+ insn->i_rp->r_sym, // Add symbol, |
+ insn->i_imm,// Fixed/known offset to the symbol |
+ insn->i_rp->r_pcrel, // T if PC-Relative reloc |
+ // BREV would change the Reloc type |
+ // to BFD_RELOC_ZIP_BREV |
+ BFD_RELOC_ZIP_LHI); // Reloc type |
+ BFD_RELOC_ZIP_BREV); // Reloc type |
+ // BFD_RELOC_ZIP_LHI); // Reloc type |
+ fix_new(fragP, |
+ OCTETS_PER_BYTE * (insn->i_rp->r_fr_offset+1), // where w/in frag? |
+ 4, // 1,2, or 4 usually ... ?? |
4664,8 → 4823,8
+} |
diff -Naur '--exclude=*.swp' binutils-2.25-original/gas/config/tc-zip.h binutils-2.25/gas/config/tc-zip.h |
--- binutils-2.25-original/gas/config/tc-zip.h 1969-12-31 19:00:00.000000000 -0500 |
+++ binutils-2.25/gas/config/tc-zip.h 2016-02-21 12:53:04.848523892 -0500 |
@@ -0,0 +1,206 @@ |
+++ binutils-2.25/gas/config/tc-zip.h 2016-04-19 10:26:34.818991485 -0400 |
@@ -0,0 +1,211 @@ |
+//////////////////////////////////////////////////////////////////////////////// |
+// |
+// Filename: tc-zip.h |
4870,6 → 5029,11
+ ZIPO_JMP, ZIPO_NOT, ZIPO_NEG |
+} ZIP_OPCODE; |
+ |
+// If LONG_MPY is defined (or not) we then use these opcodes |
+#define ZIPO_MPYUHI ZIPO_MPYU |
+#define ZIPO_MPYSHI ZIPO_MPYS |
+#define ZIPO_MPY ZIPO_LDIHI |
+ |
+#endif |
+ |
diff -Naur '--exclude=*.swp' binutils-2.25-original/gas/configure.tgt binutils-2.25/gas/configure.tgt |
5659,8 → 5823,8
/* Values for e_version. */ |
diff -Naur '--exclude=*.swp' binutils-2.25-original/include/elf/zip.h binutils-2.25/include/elf/zip.h |
--- binutils-2.25-original/include/elf/zip.h 1969-12-31 19:00:00.000000000 -0500 |
+++ binutils-2.25/include/elf/zip.h 2016-02-04 21:28:38.315592078 -0500 |
@@ -0,0 +1,73 @@ |
+++ binutils-2.25/include/elf/zip.h 2016-04-19 07:25:33.241829488 -0400 |
@@ -0,0 +1,74 @@ |
+//////////////////////////////////////////////////////////////////////////////// |
+// |
+// Filename: zip.h |
5715,7 → 5879,8
+ RELOC_NUMBER (R_ZIP_LDI, 9) |
+ RELOC_NUMBER (R_ZIP_LLO, 10) |
+ RELOC_NUMBER (R_ZIP_LHI, 11) |
+ RELOC_NUMBER (R_ZIP_BROKEN_BYTE,12) |
+ RELOC_NUMBER (R_ZIP_BREV ,12) |
+ RELOC_NUMBER (R_ZIP_BROKEN_BYTE,13) |
+END_RELOC_NUMBERS(R_ZIP_max) |
+ |
+/* ZIP-CPU Relocation Types */ |
6273,8 → 6438,8
@am__fastdepCC_TRUE@ mv -f $(DEPDIR)/$*.Tpo $(DEPDIR)/$*.Plo |
diff -Naur '--exclude=*.swp' binutils-2.25-original/opcodes/zip-dis.c binutils-2.25/opcodes/zip-dis.c |
--- binutils-2.25-original/opcodes/zip-dis.c 1969-12-31 19:00:00.000000000 -0500 |
+++ binutils-2.25/opcodes/zip-dis.c 2016-04-06 13:09:18.900143908 -0400 |
@@ -0,0 +1,230 @@ |
+++ binutils-2.25/opcodes/zip-dis.c 2016-04-20 19:51:51.082018704 -0400 |
@@ -0,0 +1,291 @@ |
+//////////////////////////////////////////////////////////////////////////////// |
+// |
+// Filename: zip-dis.c |
6313,6 → 6478,7
+#include "config.h" |
+ |
+#include <stdio.h> |
+#include <stdint.h> |
+#include <ctype.h> |
+#include <strings.h> |
+#include <string.h> |
6321,6 → 6487,39
+#include "zip-opc.h" |
+#include "zip-dis.h" |
+ |
+static inline int |
+TWOWORD_LOAD(uint32_t one, uint32_t two) { |
+ if (((one&0x87c40000)==0x03000000)&&((two&0x87c40000)==0x02400000) |
+ &&(((one^two)&0xf8380000)==0)) |
+ return 1; |
+#ifdef LONG_MPY |
+ return 0; |
+#else |
+ return (((one&0x87c40000)==0x02000000)&&((two&0x87c40000)==0x02400000) |
+ &&(((one^two)&0xf8380000)==0))?1:0; |
+#endif |
+} |
+ |
+static uint32_t |
+zip_bitreverse(uint32_t v) { |
+ uint32_t r=0, b; |
+ for(b=0; b<32; b++, v>>=1) |
+ r = (r<<1)|(v&1); |
+ return r; |
+} |
+ |
+static inline uint32_t |
+TWOWORD_VALUE(uint32_t one, uint32_t two) { |
+#ifdef LONG_MPY |
+ return ((two&0x0ffff)|(zip_bitreverse(one&0x0ffff))); |
+#else |
+ if ((one&0x87c40000)==0x03000000) |
+ return ((two&0x0ffff)|(zip_bitreverse(one&0x0ffff))); |
+ else |
+ return (two&0x0ffff)|((one&0x0ffff)<<16); |
+#endif |
+} |
+ |
+static long |
+zip_sbits(const long val, const int bits) { |
+ long r; |
6349,8 → 6548,23
+} |
+ |
+static void |
+zipi_to_halfstring(const unsigned addr, const ZIPI ins, const unsigned nxtword, char *line, const ZOPCODE *listp) |
+zipi_to_halfstring(const uint32_t addr, const ZIPI ins, const ZIPI nxtword, char *line, const ZOPCODE *listp, uint32_t *refaddr) |
+{ |
+ *refaddr = 0; |
+ |
+ if ((TWOWORD_LOAD(ins,nxtword))&&(listp==zip_oplist)) { |
+ int cv = zip_getbits(ins, ZIP_BITFIELD(3,19)); |
+ int dv = zip_getbits(ins, ZIP_REGFIELD(27)); |
+ |
+ sprintf(line, "%s%s", "LDI", zip_ccstr[cv]); |
+ sprintf(line, "%-11s", line); |
+ sprintf(line, "%s0x%08x", line, TWOWORD_VALUE(ins,nxtword)); |
+ sprintf(&line[strlen(line)], ",%s", zip_regstr[dv]); |
+ |
+ *refaddr = TWOWORD_VALUE(ins,nxtword); |
+ return; |
+ } |
+ |
+ int i; |
+ for(i=0; i<nzip_oplist; i++) { |
+ if (((~zip_oplist[i].s_mask)&zip_oplist[i].s_val)!=0) { |
6399,6 → 6613,7
+ // Treat long jumps special |
+ } else if (strncasecmp("LJMP",listp[i].s_opstr, 3)==0) { |
+ sprintf(&line[strlen(line)], "@0x%08x", nxtword); |
+ *refaddr = nxtword; |
+ // Treat relative jumps (branches) specially as well |
+ } else if ((toupper(listp[i].s_opstr[0]=='B')) |
+ &&(strcasecmp(listp[i].s_opstr,"BUSY")!=0) |
6408,10 → 6623,11
+ // Branch instruction: starts with B and isn't |
+ // BREV (bit reverse), BRK (break), or |
+ // BUSY |
+ unsigned target = addr; |
+ uint32_t target = addr; |
+ |
+ target += zip_getbits(ins, listp[i].s_i)+1; |
+ sprintf(&line[strlen(line)], "@0x%08x", target); |
+ *refaddr = target; |
+ } else { |
+ int memop = (strncasecmp("LOD", |
+ listp[i].s_opstr, 3)==0) ? 1:0; |
6457,11 → 6673,12
+} |
+ |
+static void |
+zipi_to_double_string(const unsigned addr, const ZIPI ins, const unsigned nxtword, char *la, char *lb) { |
+ zipi_to_halfstring(addr, ins, nxtword, la, zip_oplist); |
+zipi_to_double_string(const uint32_t addr, const ZIPI ins, const ZIPI nxtword, char *la, char *lb, uint32_t *refaddr) { |
+ zipi_to_halfstring(addr, ins, nxtword, la, zip_oplist, refaddr); |
+ if (lb) { |
+ if (ins & 0x80000000) { |
+ zipi_to_halfstring(addr, ins, nxtword, lb, zip_opbottomlist); |
+ zipi_to_halfstring(addr, ins, nxtword, lb, zip_opbottomlist, refaddr); |
+ *refaddr = 0; |
+ } else lb[0] = '\0'; |
+ } |
+} |
6469,15 → 6686,15
+static int |
+print_zip_insn(bfd_vma vma, disassemble_info *info) |
+{ |
+ ZIPI iword; |
+ ZIPI iword, nxtword; |
+ char astr[80], bstr[80]; |
+ unsigned char ibytes[8]; |
+ unsigned nxtword; |
+ uint32_t refaddr; |
+ |
+ (*info->read_memory_func)(vma, ibytes, 8, info); |
+ iword = (ibytes[0]<<24)|(ibytes[1]<<16)|(ibytes[2]<<8)|(ibytes[3]); |
+ nxtword= (ibytes[4]<<24)|(ibytes[5]<<16)|(ibytes[6]<<8)|(ibytes[7]); |
+ zipi_to_double_string(vma, iword, nxtword, astr, bstr); |
+ zipi_to_double_string(vma, iword, nxtword, astr, bstr, &refaddr); |
+ |
+ if (bstr[0]) |
+ (*info->fprintf_func)(info->stream, "%-25s | %-25s", astr, bstr); |
6484,6 → 6701,11
+ else |
+ (*info->fprintf_func)(info->stream, "%s", astr); |
+ |
+ if ((info->print_address_func)&&(refaddr != 0)) { |
+ (*info->fprintf_func)(info->stream, "\t// "); |
+ (*info->print_address_func)(refaddr, info); |
+ } |
+ |
+ // Normal LOD (PC),PC = 0x7c87c000 |
+ // 1'b0, 4'hf, 5'h12, 3'h0, 1'b1, 4'hf, 14'h00 |
+ // 0111 1100 1000 0111 1100 0000 0000 0000 |
6493,8 → 6715,12
+ // 0x80203fff mask, val = 0x80003e5f |
+ if ((iword == 0x7c87c000)||((iword&0x80203fff)==0x80003e5f)) |
+ return 8; |
+ // Two word load: Destination registers and conditional execution bits |
+ // must match as well. |
+ if (TWOWORD_LOAD(iword,nxtword)) |
+ return 8; |
+ if ((iword&0xffc7ffff)==0x7c87c001) // Conditional long jump |
+ return 12; |
+ return 12; // LOD.C 1(PC),PC, BRA 1+PC, @ADDRESS |
+ return 4; |
+} |
+ |
6556,8 → 6782,8
+#endif |
diff -Naur '--exclude=*.swp' binutils-2.25-original/opcodes/zip-opc.c binutils-2.25/opcodes/zip-opc.c |
--- binutils-2.25-original/opcodes/zip-opc.c 1969-12-31 19:00:00.000000000 -0500 |
+++ binutils-2.25/opcodes/zip-opc.c 2016-04-05 15:39:32.321631782 -0400 |
@@ -0,0 +1,501 @@ |
+++ binutils-2.25/opcodes/zip-opc.c 2016-04-19 09:12:35.702319550 -0400 |
@@ -0,0 +1,550 @@ |
+//////////////////////////////////////////////////////////////////////////////// |
+// |
+// Filename: zip-opc.c |
6706,17 → 6932,32
+ { "ASR", 0x87c40000, 0x01c00000, ZIP_REGFIELD(27), ZIP_REGFIELD(27), ZIP_OPUNUSED, ZIP_IMMFIELD(18,0), ZIP_BITFIELD(3,19) }, |
+ { "ASR", 0x87c40000, 0x01c40000, ZIP_REGFIELD(27), ZIP_REGFIELD(27), ZIP_REGFIELD(14), ZIP_IMMFIELD(14,0), ZIP_BITFIELD(3,19) }, |
+ // |
+#ifdef LONG_MPY |
+ { "MPY",0x87c40000, 0x02000000, ZIP_REGFIELD(27), ZIP_REGFIELD(27), ZIP_OPUNUSED, ZIP_IMMFIELD(18,0), ZIP_BITFIELD(3,19) }, |
+ { "MPY",0x87c40000, 0x02040000, ZIP_REGFIELD(27), ZIP_REGFIELD(27), ZIP_REGFIELD(14), ZIP_IMMFIELD(14,0), ZIP_BITFIELD(3,19) }, |
+#else |
+ { "LDIHI",0x87c40000, 0x02000000, ZIP_REGFIELD(27), ZIP_REGFIELD(27), ZIP_OPUNUSED, ZIP_IMMFIELD(18,0), ZIP_BITFIELD(3,19) }, |
+ { "LDIHI",0x87c40000, 0x02040000, ZIP_REGFIELD(27), ZIP_REGFIELD(27), ZIP_REGFIELD(14), ZIP_IMMFIELD(14,0), ZIP_BITFIELD(3,19) }, |
+#endif |
+ // |
+ { "LDILO",0x87c40000, 0x02400000, ZIP_REGFIELD(27), ZIP_REGFIELD(27), ZIP_OPUNUSED, ZIP_IMMFIELD(18,0), ZIP_BITFIELD(3,19) }, |
+ { "LDILO",0x87c40000, 0x02440000, ZIP_REGFIELD(27), ZIP_REGFIELD(27), ZIP_REGFIELD(14), ZIP_IMMFIELD(14,0), ZIP_BITFIELD(3,19) }, |
+ // |
+#ifdef LONG_MPY |
+ // |
+ { "MPYUHI", 0x87c40000, 0x02800000, ZIP_REGFIELD(27), ZIP_REGFIELD(27), ZIP_OPUNUSED, ZIP_IMMFIELD(18,0), ZIP_BITFIELD(3,19) }, |
+ { "MPYUHI", 0x87c40000, 0x02840000, ZIP_REGFIELD(27), ZIP_REGFIELD(27), ZIP_REGFIELD(14), ZIP_IMMFIELD(14,0), ZIP_BITFIELD(3,19) }, |
+ // |
+ { "MPYSHI", 0x87c40000, 0x02c00000, ZIP_REGFIELD(27), ZIP_REGFIELD(27), ZIP_OPUNUSED, ZIP_IMMFIELD(18,0), ZIP_BITFIELD(3,19) }, |
+ { "MPYSHI", 0x87c40000, 0x02c40000, ZIP_REGFIELD(27), ZIP_REGFIELD(27), ZIP_REGFIELD(14), ZIP_IMMFIELD(14,0), ZIP_BITFIELD(3,19) }, |
+#else |
+ // |
+ { "MPYU", 0x87c40000, 0x02800000, ZIP_REGFIELD(27), ZIP_REGFIELD(27), ZIP_OPUNUSED, ZIP_IMMFIELD(18,0), ZIP_BITFIELD(3,19) }, |
+ { "MPYU", 0x87c40000, 0x02840000, ZIP_REGFIELD(27), ZIP_REGFIELD(27), ZIP_REGFIELD(14), ZIP_IMMFIELD(14,0), ZIP_BITFIELD(3,19) }, |
+ // |
+ { "MPYS", 0x87c40000, 0x02c00000, ZIP_REGFIELD(27), ZIP_REGFIELD(27), ZIP_OPUNUSED, ZIP_IMMFIELD(18,0), ZIP_BITFIELD(3,19) }, |
+ { "MPYS", 0x87c40000, 0x02c40000, ZIP_REGFIELD(27), ZIP_REGFIELD(27), ZIP_REGFIELD(14), ZIP_IMMFIELD(14,0), ZIP_BITFIELD(3,19) }, |
+#endif |
+ // |
+ { "BREV", 0x87c40000, 0x03000000, ZIP_REGFIELD(27), ZIP_REGFIELD(27), ZIP_OPUNUSED, ZIP_IMMFIELD(18,0), ZIP_BITFIELD(3,19) }, |
+ { "BREV", 0x87c40000, 0x03040000, ZIP_REGFIELD(27), ZIP_REGFIELD(27), ZIP_REGFIELD(14), ZIP_IMMFIELD(14,0), ZIP_BITFIELD(3,19) }, |
6815,14 → 7056,27
+ { "ASR", 0x87c40000, 0x81c00000, ZIP_REGFIELD(27), ZIP_REGFIELD(27), ZIP_OPUNUSED, ZIP_IMMFIELD(4,14), ZIP_BITFIELD(2,19) }, |
+ { "ASR", 0x87c40000, 0x81c40000, ZIP_REGFIELD(27), ZIP_REGFIELD(27), ZIP_REGFIELD(14), ZIP_OPUNUSED, ZIP_BITFIELD(2,19) }, |
+ // |
+#ifdef LONG_MPY |
+ { "MPY",0x87c40000, 0x82000000, ZIP_REGFIELD(27), ZIP_REGFIELD(27), ZIP_OPUNUSED, ZIP_IMMFIELD(5,14), ZIP_BITFIELD(2,19) }, |
+#else |
+ { "LDIHI",0x87c40000, 0x82000000, ZIP_REGFIELD(27), ZIP_REGFIELD(27), ZIP_OPUNUSED, ZIP_IMMFIELD(5,14), ZIP_BITFIELD(2,19) }, |
+#endif |
+ { "LDILO",0x87c40000, 0x82400000, ZIP_REGFIELD(27), ZIP_REGFIELD(27), ZIP_OPUNUSED, ZIP_IMMFIELD(5,14), ZIP_BITFIELD(2,19) }, |
+#ifdef LONG_MPY |
+ // |
+ { "MPYUHI", 0x87c40000, 0x82800000, ZIP_REGFIELD(27), ZIP_REGFIELD(27), ZIP_OPUNUSED, ZIP_IMMFIELD(4,14), ZIP_BITFIELD(2,19) }, |
+ { "MPYUHI", 0x87c40000, 0x82840000, ZIP_REGFIELD(27), ZIP_REGFIELD(27), ZIP_REGFIELD(14), ZIP_OPUNUSED, ZIP_BITFIELD(2,19) }, |
+ // |
+ { "MPYSHI", 0x87c40000, 0x82c00000, ZIP_REGFIELD(27), ZIP_REGFIELD(27), ZIP_OPUNUSED, ZIP_IMMFIELD(4,14), ZIP_BITFIELD(2,19) }, |
+ { "MPYSHI", 0x87c40000, 0x82c40000, ZIP_REGFIELD(27), ZIP_REGFIELD(27), ZIP_REGFIELD(14), ZIP_OPUNUSED, ZIP_BITFIELD(2,19) }, |
+#else |
+ // |
+ { "MPYU", 0x87c40000, 0x82800000, ZIP_REGFIELD(27), ZIP_REGFIELD(27), ZIP_OPUNUSED, ZIP_IMMFIELD(4,14), ZIP_BITFIELD(2,19) }, |
+ { "MPYU", 0x87c40000, 0x82840000, ZIP_REGFIELD(27), ZIP_REGFIELD(27), ZIP_REGFIELD(14), ZIP_OPUNUSED, ZIP_BITFIELD(2,19) }, |
+ // |
+ { "MPYS", 0x87c40000, 0x82c00000, ZIP_REGFIELD(27), ZIP_REGFIELD(27), ZIP_OPUNUSED, ZIP_IMMFIELD(4,14), ZIP_BITFIELD(2,19) }, |
+ { "MPYS", 0x87c40000, 0x82c40000, ZIP_REGFIELD(27), ZIP_REGFIELD(27), ZIP_REGFIELD(14), ZIP_OPUNUSED, ZIP_BITFIELD(2,19) }, |
+#endif |
+ // |
+ { "BREV", 0x87c40000, 0x83000000, ZIP_REGFIELD(27), ZIP_REGFIELD(27), ZIP_OPUNUSED, ZIP_IMMFIELD(4,14), ZIP_BITFIELD(2,19) }, |
+ { "BREV", 0x87c40000, 0x83040000, ZIP_REGFIELD(27), ZIP_REGFIELD(27), ZIP_REGFIELD(14), ZIP_OPUNUSED, ZIP_BITFIELD(2,19) }, |
6953,14 → 7207,33
+ { "ASR", 0x802003f0, 0x802000e0, ZIP_REGFIELD(10), ZIP_REGFIELD(10), ZIP_OPUNUSED, ZIP_IMMFIELD(4,0), ZIP_OPUNUSED }, |
+ { "ASR", 0x800003f0, 0x800000f0, ZIP_REGFIELD(10), ZIP_REGFIELD(10), ZIP_REGFIELD(0), ZIP_OPUNUSED, ZIP_BITFIELD(2,19) }, |
+ { "ASR", 0x802003f0, 0x802000f0, ZIP_REGFIELD(10), ZIP_REGFIELD(10), ZIP_REGFIELD(0), ZIP_OPUNUSED, ZIP_OPUNUSED }, |
+#ifdef LONG_MPY |
+ // |
+ { "MPY",0x800003e0, 0x80000100, ZIP_REGFIELD(10), ZIP_REGFIELD(10), ZIP_OPUNUSED, ZIP_IMMFIELD(5,0), ZIP_BITFIELD(2,19) }, |
+ { "MPY",0x802003e0, 0x80200100, ZIP_REGFIELD(10), ZIP_REGFIELD(10), ZIP_OPUNUSED, ZIP_IMMFIELD(5,0), ZIP_OPUNUSED }, |
+#else |
+ // |
+ { "LDIHI",0x800003e0, 0x80000100, ZIP_REGFIELD(10), ZIP_REGFIELD(10), ZIP_OPUNUSED, ZIP_IMMFIELD(5,0), ZIP_BITFIELD(2,19) }, |
+ { "LDIHI",0x802003e0, 0x80200100, ZIP_REGFIELD(10), ZIP_REGFIELD(10), ZIP_OPUNUSED, ZIP_IMMFIELD(5,0), ZIP_OPUNUSED }, |
+#endif |
+ // |
+ { "LDILO",0x800003e0, 0x80000120, ZIP_REGFIELD(10), ZIP_REGFIELD(10), ZIP_OPUNUSED, ZIP_IMMFIELD(5,0), ZIP_BITFIELD(2,19) }, |
+ { "LDILO",0x802003e0, 0x80200120, ZIP_REGFIELD(10), ZIP_REGFIELD(10), ZIP_OPUNUSED, ZIP_IMMFIELD(5,0), ZIP_OPUNUSED }, |
+ // |
+#ifdef LONG_MPY |
+ // |
+ { "MPYUHI", 0x800003f0, 0x80000140, ZIP_REGFIELD(10), ZIP_REGFIELD(10), ZIP_OPUNUSED, ZIP_IMMFIELD(4,0), ZIP_BITFIELD(2,19) }, |
+ { "MPYUHI", 0x802003f0, 0x80200140, ZIP_REGFIELD(10), ZIP_REGFIELD(10), ZIP_OPUNUSED, ZIP_IMMFIELD(4,0), ZIP_OPUNUSED }, |
+ { "MPYUHI", 0x800003f0, 0x80000150, ZIP_REGFIELD(10), ZIP_REGFIELD(10), ZIP_REGFIELD(0), ZIP_OPUNUSED, ZIP_BITFIELD(2,19) }, |
+ { "MPYUHI", 0x802003f0, 0x80200150, ZIP_REGFIELD(10), ZIP_REGFIELD(10), ZIP_REGFIELD(0), ZIP_OPUNUSED, ZIP_OPUNUSED }, |
+ // |
+ { "MPYSHI", 0x800003f0, 0x80000160, ZIP_REGFIELD(10), ZIP_REGFIELD(10), ZIP_OPUNUSED, ZIP_IMMFIELD(4,0), ZIP_BITFIELD(2,19) }, |
+ { "MPYSHI", 0x802003f0, 0x80200160, ZIP_REGFIELD(10), ZIP_REGFIELD(10), ZIP_OPUNUSED, ZIP_IMMFIELD(4,0), ZIP_OPUNUSED }, |
+ { "MPYSHI", 0x800003f0, 0x80000170, ZIP_REGFIELD(10), ZIP_REGFIELD(10), ZIP_REGFIELD(0), ZIP_OPUNUSED, ZIP_BITFIELD(2,19) }, |
+ { "MPYSHI", 0x802003f0, 0x80200170, ZIP_REGFIELD(10), ZIP_REGFIELD(10), ZIP_REGFIELD(0), ZIP_OPUNUSED, ZIP_OPUNUSED }, |
+ // |
+#else |
+ // |
+ { "MPYU", 0x800003f0, 0x80000140, ZIP_REGFIELD(10), ZIP_REGFIELD(10), ZIP_OPUNUSED, ZIP_IMMFIELD(4,0), ZIP_BITFIELD(2,19) }, |
+ { "MPYU", 0x802003f0, 0x80200140, ZIP_REGFIELD(10), ZIP_REGFIELD(10), ZIP_OPUNUSED, ZIP_IMMFIELD(4,0), ZIP_OPUNUSED }, |
+ { "MPYU", 0x800003f0, 0x80000150, ZIP_REGFIELD(10), ZIP_REGFIELD(10), ZIP_REGFIELD(0), ZIP_OPUNUSED, ZIP_BITFIELD(2,19) }, |
6971,6 → 7244,8
+ { "MPYS", 0x800003f0, 0x80000170, ZIP_REGFIELD(10), ZIP_REGFIELD(10), ZIP_REGFIELD(0), ZIP_OPUNUSED, ZIP_BITFIELD(2,19) }, |
+ { "MPYS", 0x802003f0, 0x80200170, ZIP_REGFIELD(10), ZIP_REGFIELD(10), ZIP_REGFIELD(0), ZIP_OPUNUSED, ZIP_OPUNUSED }, |
+ // |
+#endif |
+ // |
+ { "BREV", 0x800003f0, 0x80000180, ZIP_REGFIELD(10), ZIP_OPUNUSED, ZIP_OPUNUSED, ZIP_IMMFIELD(4,0), ZIP_BITFIELD(2,19) }, |
+ { "BREV", 0x802003f0, 0x80200180, ZIP_REGFIELD(10), ZIP_OPUNUSED, ZIP_OPUNUSED, ZIP_IMMFIELD(4,0), ZIP_OPUNUSED }, |
+ { "BREV", 0x800003f0, 0x80000190, ZIP_REGFIELD(10), ZIP_OPUNUSED, ZIP_REGFIELD(0), ZIP_OPUNUSED, ZIP_BITFIELD(2,19) }, |
7061,8 → 7336,8
+ |
diff -Naur '--exclude=*.swp' binutils-2.25-original/opcodes/zip-opc.h binutils-2.25/opcodes/zip-opc.h |
--- binutils-2.25-original/opcodes/zip-opc.h 1969-12-31 19:00:00.000000000 -0500 |
+++ binutils-2.25/opcodes/zip-opc.h 2016-04-06 13:03:17.106368687 -0400 |
@@ -0,0 +1,80 @@ |
+++ binutils-2.25/opcodes/zip-opc.h 2016-04-19 09:58:59.566634476 -0400 |
@@ -0,0 +1,82 @@ |
+//////////////////////////////////////////////////////////////////////////////// |
+// |
+// Filename: zip-opc.h |
7101,6 → 7376,8
+#ifndef ZIP_OPC_H |
+#define ZIP_OPC_H |
+ |
+#include <stdint.h> |
+ |
+// MACROS used in the instruction definition list. |
+#define ZIP_OPUNUSED -1 |
+#define ZIP_BITFIELD(LN,MN) (((LN&0x0ff)<<8)+(MN&0x0ff)) // A generic bitfield |
7114,7 → 7391,7
+// #define ISLCLROP(A) ((a&(~0x0f))==0x020) // Current register set |
+// #define SRGFIELD(MN) (0x0200400 +(MN&0x0ff)) // Supervisor reg fld |
+ |
+typedef unsigned int ZIPI; // A Zip CPU instruction |
+typedef uint32_t ZIPI; // A Zip CPU instruction |
+ |
+typedef struct { |
+ char s_opstr[8]; // OPCode name |