OpenCores
URL https://opencores.org/ocsvn/zx_ula/zx_ula/trunk

Subversion Repositories zx_ula

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  • This comparison shows the changes necessary to convert path 
    /zx_ula/branches/xilinx/ulaplus_replacement-upgrade_for_sp16-48k/rtl_ulaplus
    from Rev 26 to Rev 29
    ↔ Reverse comparison
  •

Rev 26 → Rev 29

/ipcore_dir/master_ula_clock.xaw
1,3 → 1,3
XILINX-XDB 0.1 STUB 0.1 ASCII
XILINX-XDM V1.6e
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/ula.v
23,12 → 23,15
`define cycleend(a,b) ((a)==(b+1))
 
module ula(
input clk14, // 14MHz master clock
input clk28, // 28MHz master clock
input reset_n, // to reset the ULA to normal color mode.
// CPU interfacing
input [15:0] a, // Address bus from CPU (not all lines are used)
input [7:0] din, // Input data bus from CPU
output [7:0] dout, // Output data bus to CPU
input a15, // Address bus from CPU (not all lines are used)
input a14,
input a7,
input a6,
input a2,
inout [7:0] d, // Data bus from/to CPU
input mreq_n, // MREQ from CPU
input ioreq_n, // IORQ+A0 from main board
input iorq_n, // IORQ from CPU
37,12 → 40,10
output clkcpu, // CLK to CPU
output msk_int_n, // Vertical retrace interrupt, to CPU
// VRAM interfacing
output [13:0] va, // Address bus to VRAM (16K)
input [7:0] vramdout,// Data from VRAM to ULA/CPU
output [7:0] vramdin,// Data from CPU to VRAM
output vramoe, //
output vramcs, // Control signals for VRAM
output vramwe, //
output [6:0] va, // Address bus to VRAM (16K)
output ras_n, //
output cas_n, // Control signals for VRAM
output dramwe_n, //
// ULA I/O
input ear, //
output mic, // I/O ports
64,13 → 65,22
reg ULAPlusConfig = 0; // bit 0 of reg.64
reg [7:0] ULAPlusAddrReg = 0; // ULA+ register address, BF3Bh port.
assign ulaplus_enabled = ULAPlusConfig;
wire addrportsel = !iorq_n && a[0] && !a[2] && (a[7:6]==2'b00) && (a[15:14]==2'b10); // port BF3Bh
wire dataportsel = !iorq_n && a[0] && !a[2] && (a[7:6]==2'b00) && (a[15:14]==2'b11); // port FF3Bh
wire a0 = (!ioreq_n && !iorq_n)? 0 : 1; // Regenerate a valid (for IORQ access) a0 signal
wire addrportsel = !iorq_n && a0 && !a2 && !a7 && !a6 && a15 && !a14; // port BF3Bh
wire dataportsel = !iorq_n && a0 && !a2 && !a7 && !a6 && a15 && a14; // port FF3Bh
wire cpu_writes_palette = dataportsel && !wr_n && (ULAPlusAddrReg[7:6]==2'b00); //=1 if CPU wants to write a palette entry to RAM
reg [5:0] paletteaddr; // address bus of palette RAM
wire [7:0] palettedout; // data out port of palette RAM
reg palettewe; // WE signal of palette RAM (palette RAM is always selected and output enabled)
 
// Clocks
reg [1:0] clk28div = 0;
always @(posedge clk28) // 28MHz for RAS/CAS generation
clk28div <= clk28div + 1;
wire clk7 = clk28div[1]; // For pixel operations
wire clk14 = clk28div[0]; // For palette operations
// Palette RAM instantiation
ram64bytes palette (
.clk(clk14), // only for write operations. Read operations are asynchronous
.a(paletteaddr),
79,11 → 89,6
.we(palettewe) // RAM is written if WE is enabled at the rising edge of clk
);
 
// Pixel clock
reg clk7 = 0;
always @(posedge clk14)
clk7 <= !clk7;
// Horizontal counter
reg [8:0] hc = 0;
always @(posedge clk7) begin
253,23 → 258,19
end
//CSync generation
assign csync = HSync_n & VSync_n;
assign csync = HSync_n & VSync_n;
// VRAM address and control line generation
// VRAM address and control line generation (TO-DO)
reg [13:0] rVA = 0;
reg rVCS = 0;
reg rVOE = 0;
reg rVWE = 0;
assign va = rVA;
assign vramcs = rVCS;
assign vramoe = rVOE;
assign vramwe = rVWE;
// Latches to hold delayed versions of V and H counters
reg [8:0] v = 0;
reg [8:0] c = 0;
// Address and control line multiplexor ULA/CPU
always @(negedge clk7) begin
if (Border_n && (hc[3:0]==4'b0111 || hc[3:0]==4'b1011)) begin // cycles 7 and 11: load V and C from VC and HC
if (Border_n && (hc[3:0]==7 || hc[3:0]==11)) begin // cycles 7 and 11: load V and C from VC and HC
c <= hc;
v <= vc;
end
276,7 → 277,7
end
// Address and control line multiplexor ULA/CPU
always @(*) begin
if (Border_n && (hc[3:0]==4'b1000 || hc[3:0]==4'b1001 || hc[3:0]==4'b1100 || hc[3:0]==4'b1101)) begin // cycles 8 and 12: present attribute address to VRAM
if (Border_n && (hc[3:0]==8 || hc[3:0]==9 || hc[3:0]==12 || hc[3:0]==13)) begin // cycles 8 and 12: present attribute address to VRAM
rVA = (TimexHiColorMode)? {1'b1,v[7:6],v[2:0],v[5:3],c[7:3]} : // (cycles 9 and 13 load attr byte).
{4'b0110,v[7:3],c[7:3]}; // Attribute address depends upon the mode selected
rVCS = 1;
283,13 → 284,13
rVOE = !hc[0];
rVWE = 0;
end
else if (Border_n && (hc[3:0]==4'b1010 || hc[3:0]==4'b1011 || hc[3:0]==4'b1110 || hc[3:0]==4'b1111)) begin // cycles 10 and 14: present display address to VRAM
else if (Border_n && (hc[3:0]==10 || hc[3:0]==11 || hc[3:0]==14 || hc[3:0]==15)) begin // cycles 10 and 14: present display address to VRAM
rVA = {1'b0,v[7:6],v[2:0],v[5:3],c[7:3]}; // (cycles 11 and 15 load display byte)
rVCS = 1;
rVOE = !hc[0];
rVWE = 0;
end
else if (Border_n && hc[3:0]==4'b0000) begin
else if (Border_n && hc[3:0]==0) begin
rVA = a[13:0];
rVCS = 0;
rVOE = 0;
296,13 → 297,20
rVWE = 0;
end
else begin // when VRAM is not in use by ULA, give it to CPU
rVA = a[13:0];
rVCS = !a[15] & a[14] & !mreq_n;
rVOE = !rd_n;
rVWE = !wr_n;
 
end
end
 
// RAS/CAS/DRAMWE generation
reg rRAS_n = 1;
reg rCAS_n = 1;
reg rDRAMWE_n = 1;
wire [5:0] RCycle = {hc[3:0],clk28div};
always @(posedge clk28) begin
 
// ULA+ : palette RAM address and control bus multiplexing
always @(*) begin
if (Border_n && (hc[3:0]==10 || hc[3:0]==14)) begin // present address of paper to palette RAM
/iseconfig/ulaplus_replacement.projectmgr
1,4 → 1,4
<?xml version="1.0" encoding="utf-8"?>
<?xml version='1.0' encoding='utf-8'?>
<!--This is an ISE project configuration file.-->
<!--It holds project specific layout data for the projectmgr plugin.-->
<!--Copyright (c) 1995-2009 Xilinx, Inc. All rights reserved.-->
14,13 → 14,13
<ClosedNode>/ulaplus_tld C:|Documents and Settings|rodriguj|Mis documentos|opencores|zx_ula|branches|xilinx|ulaplus_replacement-upgrade_for_sp16-48k|rtl_ulaplus|ulaplus_tld.v/video_final_stage - rgbdtoa</ClosedNode>
</ClosedNodes>
<SelectedItems>
<SelectedItem>the_ula - ula (C:/Documents and Settings/rodriguj/Mis documentos/opencores/zx_ula/branches/xilinx/ulaplus_replacement-upgrade_for_sp16-48k/rtl_ulaplus/ula.v)</SelectedItem>
<SelectedItem>clock28mhz - master_ula_clock (C:/Documents and Settings/rodriguj/Mis documentos/opencores/zx_ula/branches/xilinx/ulaplus_replacement-upgrade_for_sp16-48k/rtl_ulaplus/ipcore_dir/master_ula_clock.xaw)</SelectedItem>
</SelectedItems>
<ScrollbarPosition orientation="vertical" >0</ScrollbarPosition>
<ScrollbarPosition orientation="horizontal" >0</ScrollbarPosition>
<ViewHeaderState orientation="horizontal" >000000ff0000000000000001000000010000000000000000000000000000000002020000000100000001000000640000015f000000020000000000000000000000000000000064ffffffff0000008100000000000000020000015f0000000100000000000000000000000100000000</ViewHeaderState>
<UserChangedColumnWidths orientation="horizontal" >false</UserChangedColumnWidths>
<CurrentItem>the_ula - ula (C:/Documents and Settings/rodriguj/Mis documentos/opencores/zx_ula/branches/xilinx/ulaplus_replacement-upgrade_for_sp16-48k/rtl_ulaplus/ula.v)</CurrentItem>
<CurrentItem>clock28mhz - master_ula_clock (C:/Documents and Settings/rodriguj/Mis documentos/opencores/zx_ula/branches/xilinx/ulaplus_replacement-upgrade_for_sp16-48k/rtl_ulaplus/ipcore_dir/master_ula_clock.xaw)</CurrentItem>
</ItemView>
<ItemView engineview="SynthesisOnly" sourcetype="" guiview="Process" >
<ClosedNodes>
28,13 → 28,13
<ClosedNode>Design Utilities</ClosedNode>
</ClosedNodes>
<SelectedItems>
<SelectedItem></SelectedItem>
<SelectedItem/>
</SelectedItems>
<ScrollbarPosition orientation="vertical" >0</ScrollbarPosition>
<ScrollbarPosition orientation="horizontal" >0</ScrollbarPosition>
<ViewHeaderState orientation="horizontal" >000000ff000000000000000100000001000000000000000000000000000000000000000000000000f6000000010000000100000000000000000000000064ffffffff000000810000000000000001000000f60000000100000000</ViewHeaderState>
<UserChangedColumnWidths orientation="horizontal" >false</UserChangedColumnWidths>
<CurrentItem></CurrentItem>
<CurrentItem/>
</ItemView>
<ItemView guiview="File" >
<ClosedNodes>
65,13 → 65,13
<ClosedNode>User Constraints</ClosedNode>
</ClosedNodes>
<SelectedItems>
<SelectedItem></SelectedItem>
<SelectedItem/>
</SelectedItems>
<ScrollbarPosition orientation="vertical" >0</ScrollbarPosition>
<ScrollbarPosition orientation="horizontal" >0</ScrollbarPosition>
<ViewHeaderState orientation="horizontal" >000000ff000000000000000100000001000000000000000000000000000000000000000000000000f6000000010000000100000000000000000000000064ffffffff000000810000000000000001000000f60000000100000000</ViewHeaderState>
<UserChangedColumnWidths orientation="horizontal" >false</UserChangedColumnWidths>
<CurrentItem></CurrentItem>
<CurrentItem/>
</ItemView>
<ItemView engineview="SynthesisOnly" sourcetype="DESUT_VERILOG" guiview="Process" >
<ClosedNodes>
95,10 → 95,12
<ClosedNodes>
<ClosedNodesVersion>1</ClosedNodesVersion>
</ClosedNodes>
<SelectedItems/>
<SelectedItems>
<SelectedItem></SelectedItem>
</SelectedItems>
<ScrollbarPosition orientation="vertical" >0</ScrollbarPosition>
<ScrollbarPosition orientation="horizontal" >0</ScrollbarPosition>
<ViewHeaderState orientation="horizontal" ></ViewHeaderState>
<ViewHeaderState orientation="horizontal" >000000ff000000000000000100000001000000000000000000000000000000000000000000000000f6000000010000000100000000000000000000000064ffffffff000000810000000000000001000000f60000000100000000</ViewHeaderState>
<UserChangedColumnWidths orientation="horizontal" >false</UserChangedColumnWidths>
<CurrentItem></CurrentItem>
</ItemView>
/ulaplus_tld.v
59,10 → 59,10
output csync
);
 
wire clk14;
master_ula_clock clock14mhz (
wire clk28;
master_ula_clock clock28mhz (
.CLKIN_IN(clk50),
.CLKFX_OUT(clk14),
.CLKFX_OUT(clk28),
.CLKIN_IBUFG_OUT(),
.CLK0_OUT()
);
75,7 → 75,7
wire [7:0] rgbulaplus;
ula the_ula (
.clk14(clk14),
.clk28(clk28),
.reset_n(reset_n),
.a15(a15),
.a14(a14),
82,8 → 82,7
.a7(a7),
.a6(a6),
.a2(a2),
.din(uladin),
.dout(uladout),
.d(d),
.mreq_n(mreq_n),
.ioreq_n(ioreq_n),
.iorq_n(iorq_n),
91,7 → 90,10
.wr_n(wr_n),
.clkcpu(cpuclk_n),
.int_n(int_n),
.va(va),
.va(va),
.ras_n(ras_n),
.cas_n(cas_n),
.dramwe_n(dramwe_n),
.ear(ear),
.mic(mic),
.spk(spk),
124,7 → 126,7
// Audio mixer
/////////////////////////////////////
mixer audio_mix (
.clkdac(clk14),
.clkdac(clk28),
.reset_n(reset_n),
.ear(ear),
.mic(mic),

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