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Rev 8 → Rev 9

/trunk/rtl/verilog/RxModule.v
1,6 → 1,6
//author :gurenliang
//author :Renliang Gu
//Email: gurenliang@gmail.com
//note: if there are some errors, you are welcome to contact me. It would be the best appreciation to me.
//note: if there are some errors, please feel free to contact me. Thank you very much!
 
//Next step, reduce the resource consumed
 
13,18 → 13,20
 
`include "common.v"
 
`define ff_source_cnt_len 8 //(2^ff_source_cnt_len) must be larger than uframelen
`define nibble_cnt_len 10 //(2^nibble_cnt_len) must be larger than eth_buf_len/4
`define delay_cnt_len 4 //(2^delay_cnt_len) must be larger than the number of clocks you want TxModule to wait at the beginning
`define delay_cnt_config 4'h9 //the initiation value for the delay_cnt
`define ff_data_buf_index_len 5 //(2^ff_data_buf_index_len) must be larger than or equal to num_uframe*2
`define toggle_lsbs 4'h0 //the length of zeros is ff_data_buf_index_len-1
`define IDXlen 3 //2^IDXlen should be the number of cyclic queue
`define queue_len (1<<3) //define the length of the cyclic queue
 
//8 bytes preamble, 12 bytes source address and destination address, 2 bytes length/type, 3bytes frameID
`define eth_buf_len (8*(8+6+6+2)+`frameidlen+`uframelen*`num_uframe+8*4) //the last 4 bytes CRC
`define da_offset (8<<1) //8 byte before
`define sa_offset (`da_offset+(6<<1)) //8+6 bytes before
`define typelen_offset (`sa_offset+(6<<1))
`define frameid_offset (`typelen_offset+(2<<1))//index of first bit of frameid
`define data_offset (`frameid_offset+(`frameidlen>>2))
//index of first bit of data
`define rx_crc_offset (`data_offset+(`uframelen*`num_uframe/4)) //index of first bit of crc
`define rx_total_len (`rx_crc_offset + (4<<1))
`define rxdata_len (`uframelen*`num_uframe/4)
 
`define frameid_offset 176 //index of frameid in eth_buf
`define data_offset (`frameid_offset+`frameidlen) //index of beginning of data in eth_buf
`define delay_cnt_config 0 //the initiation value for the delay_cnt
 
module RxModule(phy_rxd, phy_rxen, phy_rxclk, phy_rxer,
ff_clk, ff_data, ff_en,
33,7 → 35,9
frameid,
`endif
start);
start,
test1, test2, test3, test4
);
input phy_rxen, phy_rxclk, phy_rxer; //MII interface
input [3:0] phy_rxd;
42,124 → 46,244
`ifdef frameIDfromRx
output[`frameidlen-1:0] frameid;
reg[`frameidlen-1:0] frameid;
`endif
output start; //to tell TxModule that buf in RxModule needs data
output test1, test2, test3, test4;
reg test1, test2;
parameter delay_cnt_len = (`delay_cnt_config <= 2) ? 1 : (`delay_cnt_config <= 4) ? 2 :
(`delay_cnt_config <= 8) ? 3 : (`delay_cnt_config <= 16) ? 4 :
(`delay_cnt_config <= 32) ? 5 : (`delay_cnt_config <= 64) ? 6 :
(`delay_cnt_config <= 128) ? 7 : 8;
parameter nibble_idx_len = (`rx_total_len<= 2)? 1 : (`rx_total_len<= 4)? 2 :
(`rx_total_len<= 8)? 3 : (`rx_total_len<= 16)? 4 :
(`rx_total_len<= 32)? 5 : (`rx_total_len<= 64)? 6 :
(`rx_total_len<= 128)? 7 : (`rx_total_len<= 256)? 8 :
(`rx_total_len<= 512)? 9 : (`rx_total_len<=1024)? 10 :
(`rx_total_len<=2048)? 11 : 12;
parameter ff_idx_len = (`rxdata_len<= 2)? 1 : (`rxdata_len<= 4)? 2 :
(`rxdata_len<= 8)? 3 : (`rxdata_len<= 16)? 4 :
(`rxdata_len<= 32)? 5 : (`rxdata_len<= 64)? 6 :
(`rxdata_len<= 128)? 7 : (`rxdata_len<= 256)? 8 :
(`rxdata_len<= 512)? 9 : (`rxdata_len<=1024)?10 :
(`rxdata_len<=2048)?10 : 11;
parameter frameid_idx_len = ((`frameidlen>>2)<= 2)? 1 : ((`frameidlen>>2)<= 4)? 2 :
((`frameidlen>>2)<= 8)? 3 : ((`frameidlen>>2)<= 16)? 4 :
((`frameidlen>>2)<= 32)? 5 : ((`frameidlen>>2)<= 64)? 6 :
((`frameidlen>>2)<= 64)? 7 : 8;
parameter ff_cnt_len = (`uframelen < 2) ? 1 : (`uframelen < 4) ? 2 :
(`uframelen < 8) ? 3 : (`uframelen < 16) ? 4 :
(`uframelen < 32) ? 5 : (`uframelen < 64) ? 6 :
(`uframelen < 128) ? 7 : (`uframelen < 256) ? 8 :
(`uframelen < 512) ? 9 : (`uframelen < 1024) ? 10:
(`uframelen < 2048) ? 11: (`uframelen < 4096) ? 12:
(`uframelen < 8192) ? 13: 14;
reg ff_data;
reg ff_en;
 
reg[ff_cnt_len-1:0] ff_cnt;
reg[2:0] ff_d;
reg[`uframelen-1:0] ff_data_buf[0:`num_uframe*2-1]; //declare
reg[`uframelen-1:0] ff_d;
reg[`ff_source_cnt_len-1:0] ff_cnt;
reg[`eth_buf_len-1:0] eth_buf;
reg start=1'b0;
reg start_intra=1'b0;
reg[delay_cnt_len-1:0] delay_cnt;
reg[`nibble_cnt_len-1:0] nibble_cnt=0;
reg[3:0] gap_cnt;
reg[1:0] gap_len_ctl;
reg[1:0] cycle;
`ifdef frameIDfromRx
reg[`frameidlen-1:0] frameidt[0:1];
`endif
reg[3:0] rxdata_buf [0:(`rxdata_len*`queue_len+1)]; //more ram for special usage
wire[ff_idx_len+`IDXlen-1:0] rxdata_buf_writer_address;
reg[ff_idx_len+`IDXlen-1:0] rxdata_buf_reader_address;
reg start=1'b0;
reg start_intra=1'b0;
reg[`delay_cnt_len-1:0] delay_cnt;
reg[`frameidlen-1:0] frameid_buf[0:(`queue_len-1)];
reg[`ff_data_buf_index_len-1:0] ff_data_buf_index;
wire[`ff_data_buf_index_len-1:0] toggle;
reg ff_state;
reg[3:0] gap_cnt = 4'h0;
reg[nibble_idx_len-1:0] nibble_idx;
reg[ff_idx_len-1:0] ff_idx;
parameter transfer = 1'b0, gap = 1'b1;
reg[`IDXlen-1:0] rxIDX, ffIDX;
reg bad_da;
reg queue_empty;
reg[2:0] rxState = 0;
parameter s_preamble = 0, s_address = 1, s_typelen = 2,
s_frameid = 3, s_data = 4, s_crc = 5;
reg[1:0] ff_state = 0;
parameter ffs_idle = 0, ffs_transfer = 1, ffs_gap = 2;
wire[47:0] mac_add;
wire[3:0] da[0:11];
assign mac_add = `MAC_ADD;
assign da[ 0] = mac_add[ 3: 0];
assign da[ 1] = mac_add[ 7: 4];
assign da[ 2] = mac_add[11: 8];
assign da[ 3] = mac_add[15:12];
assign da[ 4] = mac_add[19:16];
assign da[ 5] = mac_add[23:20];
assign da[ 6] = mac_add[27:24];
assign da[ 7] = mac_add[31:28];
assign da[ 8] = mac_add[35:32];
assign da[ 9] = mac_add[39:36];
assign da[10] = mac_add[43:40];
assign da[11] = mac_add[47:44];
assign test4 = start_intra;
assign test3 = start;
 
always@(posedge phy_rxclk)begin //control the increasing of nibble_idx;
if(phy_rxen & ~phy_rxer) //data is valid and no error
nibble_idx <= nibble_idx + 1;
else
nibble_idx <= 0;
end
always@(posedge phy_rxclk)begin
if(phy_rxen & ~phy_rxer)
case (rxState)
s_preamble:
if(nibble_idx == `da_offset-1) rxState <= s_address;
else rxState <= s_preamble;
s_address:
if(nibble_idx == `typelen_offset-1) rxState <= s_typelen;
else rxState <= s_address;
s_typelen:
if(nibble_idx == `frameid_offset-1) rxState <= s_frameid;
else rxState <= s_typelen;
s_frameid:
if(nibble_idx == `data_offset-1) rxState <= s_data;
else rxState <= s_frameid;
s_data:
if(nibble_idx == `rx_crc_offset-1) rxState <= s_crc;
else rxState <= s_data;
s_crc:
if(nibble_idx == `rx_total_len-1) rxState <= s_preamble;
else rxState <= s_crc;
default: rxState <= rxState;
endcase
else
rxState <= s_preamble;
end
assign rxdata_buf_writer_address = rxIDX*`rxdata_len + nibble_idx - `data_offset;
always@(posedge phy_rxclk)begin //receive data from Ethernet including the preamble, SFD and CRC
if(phy_rxen & ~phy_rxer) begin //data is valid and no error
eth_buf <= {phy_rxd, eth_buf[`eth_buf_len-1:4]};
nibble_cnt <= nibble_cnt + 1;
end
else if ((nibble_cnt == (`eth_buf_len>>2) ) & (eth_buf[111:64] == `MAC_ADD)) begin
case (rxState)
s_preamble: test1 <= ~test1;
s_address:
if((phy_rxd!=da[nibble_idx-`da_offset])&(nibble_idx < `sa_offset))
bad_da <= 1;
s_frameid: begin
if(nibble_idx==`frameid_offset) begin
rxIDX <= phy_rxd[2:0];
frameid_buf[phy_rxd[2:0]][(`frameidlen-1):(`frameidlen-4)] <= phy_rxd;
end else
frameid_buf[rxIDX] <= {phy_rxd, frameid_buf[rxIDX][(`frameidlen-1):4]};
end
s_data: begin
//test2 <= ~test2;
rxdata_buf[rxdata_buf_writer_address] <= phy_rxd;
end
endcase
end else if ((nibble_idx == `rx_total_len ) & (!bad_da)) begin
//one frame has been transfered over, the destinate address is right and then been put into the buffer
`ifdef frameIDfromRx
frameidt[~ff_data_buf_index[`ff_data_buf_index_len-1]] <= eth_buf[`data_offset-1:`frameid_offset];
`endif
`ifdef num_cover_4
ff_data_buf[toggle ] <= eth_buf[`data_offset+ 1*`uframelen-1: `data_offset+ 0*`uframelen];
ff_data_buf[toggle + 1] <= eth_buf[`data_offset+ 2*`uframelen-1: `data_offset+ 1*`uframelen];
ff_data_buf[toggle + 2] <= eth_buf[`data_offset+ 3*`uframelen-1: `data_offset+ 2*`uframelen];
ff_data_buf[toggle + 3] <= eth_buf[`data_offset+ 4*`uframelen-1: `data_offset+ 3*`uframelen];
`ifdef num_cover_8
ff_data_buf[toggle + 4] <= eth_buf[`data_offset+ 5*`uframelen-1: `data_offset+ 4*`uframelen];
ff_data_buf[toggle + 5] <= eth_buf[`data_offset+ 6*`uframelen-1: `data_offset+ 5*`uframelen];
ff_data_buf[toggle + 6] <= eth_buf[`data_offset+ 7*`uframelen-1: `data_offset+ 6*`uframelen];
ff_data_buf[toggle + 7] <= eth_buf[`data_offset+ 8*`uframelen-1: `data_offset+ 7*`uframelen];
`ifdef num_cover_16
ff_data_buf[toggle + 8] <= eth_buf[`data_offset+ 9*`uframelen-1: `data_offset+ 8*`uframelen];
ff_data_buf[toggle + 9] <= eth_buf[`data_offset+10*`uframelen-1: `data_offset+ 9*`uframelen];
ff_data_buf[toggle + 10] <= eth_buf[`data_offset+11*`uframelen-1: `data_offset+10*`uframelen];
ff_data_buf[toggle + 11] <= eth_buf[`data_offset+12*`uframelen-1: `data_offset+11*`uframelen];
ff_data_buf[toggle + 12] <= eth_buf[`data_offset+13*`uframelen-1: `data_offset+12*`uframelen];
ff_data_buf[toggle + 13] <= eth_buf[`data_offset+14*`uframelen-1: `data_offset+13*`uframelen];
ff_data_buf[toggle + 14] <= eth_buf[`data_offset+15*`uframelen-1: `data_offset+14*`uframelen];
ff_data_buf[toggle + 15] <= eth_buf[`data_offset+16*`uframelen-1: `data_offset+15*`uframelen];
`endif
`endif
`endif
start_intra <= 1'b1;
nibble_cnt <= 0;
end
else
nibble_cnt <= 0;
start_intra <= 1;
end else
bad_da <= 0;
end
//assign empty = ((ff_data_buf_index[2:0]==3'b011)|(ff_data_buf_index[2:0]==3'b100));
//every four 148bit, generate an empty signal to the TxModule
assign toggle = {~ff_data_buf_index[`ff_data_buf_index_len-1],`toggle_lsbs}; //indicate which half buffer is available
always@(negedge ff_clk) begin
case(ff_state)
ffs_idle: begin //wait the first frame to come
gap_len_ctl <= 0;
if(start_intra) ff_state <= ffs_transfer;
else ff_state <= ffs_idle;
end
ffs_transfer: begin
if(ff_cnt == `uframelen-1)begin //every `uframelen bit need a gap
ff_state <= ffs_gap;
gap_len_ctl <= gap_len_ctl + 1;
end
else ff_state <= ffs_transfer;
end
ffs_gap: begin
if(((gap_len_ctl == 0)&(gap_cnt == 8)) | ((gap_len_ctl != 0)&(gap_cnt == 7)))
ff_state <=ffs_transfer;
else ff_state <= ffs_gap;
end
endcase
end
`ifdef frameIDfromRx
assign frameid = frameidt[ff_data_buf_index[`ff_data_buf_index_len-1]];//
`endif
always@(negedge ff_clk) //flow the data out of the buffer
if(start_intra==1'b0) begin //wait the first frame to come
ff_state <= transfer;
ff_cnt <= 0;
ff_data_buf_index <= -1; // to fill every bit in ff_data_buf_index with 1s
ff_en <= 1'b0;
delay_cnt <= `delay_cnt_config;
end
else
case(ff_state)
transfer: begin
delay_cnt <= delay_cnt - 1;
if(delay_cnt == 0) start <=1'b1;
if(ff_cnt==0) begin //load new 148 bits
{ff_d[`uframelen-2:0],ff_data} <= ff_data_buf[ff_data_buf_index + 1];
ff_data_buf_index <= ff_data_buf_index + 1;
ff_cnt <= ff_cnt + 1;
ff_en <= 1'b1;
always@(negedge ff_clk) begin //flow the data out of the buffer
case(ff_state)
ffs_idle: begin
ff_cnt <= 0;
delay_cnt <= 0;
cycle <= 0;
ff_en <= 0;
ff_idx <= 0;
ffIDX <= rxIDX + 2;
start <= 0;
rxdata_buf_reader_address <= ffIDX*`rxdata_len+ff_idx;
end
ffs_transfer: begin
`ifdef frameIDfromRx
frameid <= frameid_buf[ffIDX];
`endif
if(delay_cnt == `delay_cnt_config) start <= 1;
delay_cnt <= delay_cnt + 1;
gap_cnt <= 0;
ff_cnt <= ff_cnt + 1;
cycle <= cycle + 1;
ff_en <= 1;
if(cycle==0) begin
{ff_d[2:0],ff_data} <= rxdata_buf[rxdata_buf_reader_address];
if(ff_idx == `rxdata_len-1)begin
if(ffIDX!=rxIDX) begin
queue_empty <= 0;
if(queue_empty) begin
ffIDX <= rxIDX + 2;
rxdata_buf_reader_address <= (rxIDX + 2)*`rxdata_len;
end
else begin
ffIDX <= ffIDX + 1;
rxdata_buf_reader_address <= (ffIDX+1)*`rxdata_len;
end
end else begin
rxdata_buf_reader_address <= ffIDX*`rxdata_len;
queue_empty <= 1;
end
ff_idx <= 0;
end
else if(ff_cnt == `uframelen) begin //every 148 bit need a gap
ff_en <= 1'b0;
ff_cnt <= 0;
ff_state <= gap;
ff_data <= 1'b0;
end
else begin
{ff_d[`uframelen-2:0],ff_data} <= ff_d;
ff_cnt <= ff_cnt + 1;
ff_idx <= ff_idx + 1;
rxdata_buf_reader_address <= ffIDX*`rxdata_len+ff_idx+1;
end
end
gap: begin //the 8.25 bit gap is implement by (3*8+9)/4
gap_cnt <= gap_cnt + 4'h1;
if(((ff_data_buf_index[1:0]==2'b11)&(gap_cnt == 4'h7))
| ((ff_data_buf_index[1:0]!=2'b11)&(gap_cnt == 4'h6)))begin
gap_cnt <= 4'h0;
ff_state <= transfer;
end
end
endcase
endmodule
end else
{ff_d[1:0],ff_data} <= ff_d;
end
ffs_gap: begin //the 8.25 bit gap is implement by (3*8+9)/4
ff_en <= 0;
ff_data <= 0;
ff_cnt <= 0;
gap_cnt <= gap_cnt + 1;
end
endcase
end
endmodule
/trunk/rtl/verilog/TxModule.v
2,9 → 2,10
//Email: gurenliang@gmail.com
//note: if there are some errors, you are welcome to contact me. It would be the best appreciation to me.
 
//Next step, reduce the resource consumed
 
//version 0.5, defined many parameter to configure the IP core, making it easier to use.
 
//Next step, add ff_data control to show the IP is busy
 
//version 0.3, declared a new variable data_av, and use it to start sending frame.
//version 0.3, delete the usage of pre_buf, and rename the pre to preaddlt
//version 0.3, add the option of frameID mode, by include common.v and judge the macro-varible frameIDfromRx
11,17 → 12,16
//This module is used to receive data from the demodulate module and send the data to the Ethernet PHY chip
`include "common.v"
 
`define tx_data_buf_len (`frameidlen+`uframelen*`num_uframe+132)
`define tx_data_buf_len (`frameidlen+`uframelen*`num_uframe+66)
//132=8.25*`num_uframe is the space between the uframes
`define tx_data_madeup 4 //add to tx_data_buf_len to make 132 is dividible by 8
`define append_zero 4'h0
//66=8.25*`num_uframe is the space between the uframes
`define tx_data_madeup 6 //add to tx_data_buf_len to make 132 is dividible by 8
//add to tx_data_buf_len to make 66 is dividible by 8
 
`define tx_data_len (`tx_data_buf_len+`tx_data_madeup)
//make the length of tx_data_buf be conformed to IEEE802.3
`define ff_sink_cnt_len 12 //make sure 2^ff_sink_cnt_len is larger than or equal to tx_data_buf_len
`define ff_cnt_init (1+`frameidlen)
 
`define tx_cnt_len 10 //make sure 2^tx_cnt_len is larger than [(`tx_data_len >> 2) + 51]
 
module TxModule(reset, phy_txd, phy_txen, phy_txclk, phy_txer,
ff_clk, ff_en, ff_data,
 
31,6 → 31,36
start,
test1, test2, test3, test4);
//make sure 2^ff_sink_cnt_len is larger than or equal to tx_data_buf_len
parameter ff_sink_cnt_len = (`tx_data_buf_len <= 2) ? 1 :
(`tx_data_buf_len <= 4) ? 2 :
(`tx_data_buf_len <= 8) ? 3 :
(`tx_data_buf_len <= 16) ? 4 :
(`tx_data_buf_len <= 32) ? 5 :
(`tx_data_buf_len <= 64) ? 6 :
(`tx_data_buf_len <= 128) ? 7 :
(`tx_data_buf_len <= 256) ? 8 :
(`tx_data_buf_len <= 512) ? 9 :
(`tx_data_buf_len <= 1024) ? 10:
(`tx_data_buf_len <= 2048) ? 11:
(`tx_data_buf_len <= 4096) ? 12:
(`tx_data_buf_len <= 8192) ? 13: 14;
//make sure 2^tx_cnt_len is larger than [(`tx_data_len >> 2) + 51]
parameter tx_cnt_len = (((`tx_data_len >> 2) + 51) <= 2) ? 1 :
(((`tx_data_len >> 2) + 51) <= 4) ? 2 :
(((`tx_data_len >> 2) + 51) <= 8) ? 3 :
(((`tx_data_len >> 2) + 51) <= 16) ? 4 :
(((`tx_data_len >> 2) + 51) <= 32) ? 5 :
(((`tx_data_len >> 2) + 51) <= 64) ? 6 :
(((`tx_data_len >> 2) + 51) <= 128) ? 7 :
(((`tx_data_len >> 2) + 51) <= 256) ? 8 :
(((`tx_data_len >> 2) + 51) <= 512) ? 9 :
(((`tx_data_len >> 2) + 51) <= 1024) ? 10:
(((`tx_data_len >> 2) + 51) <= 2048) ? 11:
(((`tx_data_len >> 2) + 51) <= 4096) ? 12:
(((`tx_data_len >> 2) + 51) <= 8192) ? 13: 14;
input phy_txclk, reset;
input ff_clk, ff_en, ff_data; //ff_clk should be 207.83333KHz
56,13 → 86,13
//reg[175:0] pre_buf=176'h0008_5952_264C_5247_FFFF_FFFF_FFFF_D555_5555_5555_5555;
reg[`tx_data_buf_len-1:0] tx_data_buf[0:1]; //two buffer helps to step over different frame seamlessly
reg pre_toggle, toggle=1'b0; //helps to decide when to give PC a MAC frame
reg pre_toggle1,pre_toggle2, toggle=1'b0; //helps to decide when to give PC a MAC frame
reg[`tx_data_len-1:0] tx_data; //used as FIFO
reg[`ff_sink_cnt_len-1:0] ff_cnt=0;
reg[ff_sink_cnt_len-1:0] ff_cnt=0;
reg[`tx_cnt_len-1:0] tx_cnt;
reg data_av;
reg[tx_cnt_len-1:0] tx_cnt;
wire data_av;
reg Enable_Crc, Initialize_Crc; //declare the variables for the CRC module
wire [3:0] Data_Crc;
104,6 → 134,12
end
assign phy_txer = 1'b0;
assign data_av = pre_toggle1^pre_toggle2;
always @ (negedge phy_txclk) begin //state machine run to send out the MAC frame
pre_toggle1 <= toggle;
pre_toggle2 <= pre_toggle1;
end
 
// Determine the next state
always @ (negedge phy_txclk) begin //state machine run to send out the MAC frame
110,13 → 146,11
if (reset)
state <= s_idle;
else begin
if(pre_toggle ^ toggle) data_av<=1'b1;
case (state)
s_idle: begin //wait to be trigged
test1 <= ~test1;
if(data_av) begin //once be trigged, prepare the data to send
state <= s_pre;
data_av <= 1'b0;
end
else state <= s_idle;
end
151,10 → 185,6
end
always @ (negedge phy_txclk) begin //state machine run to send out the MAC frame
pre_toggle <= toggle;
end
always @ (negedge phy_txclk) begin //state machine run to send out the MAC frame
if (reset)
tx_cnt <= 0;
else if(state==s_idle)
169,7 → 199,7
else
case (state)
s_idle: begin
tx_data <= {`append_zero, tx_data_buf[~toggle]};
tx_data <= {{`tx_data_madeup{1'b0}}, tx_data_buf[~toggle]};
//already stored MAC preamble, dest address and source address from right to left.
//decide whether should ask PC for new frame
/*if(empty) preaddlt <= {16'h0008, `MAC_ADD, `PC_MAC_ADD, `Preamble};
/trunk/rtl/verilog/test_feedback.v
1,3 → 1,7
//author :Renliang Gu
//Email: gurenliang@gmail.com
//note: if there are some errors, please feel free to contact me. Thank you very much!
 
//version 0.4, the test_feedback is created, main task is to test the top module, EthernetModule.v
// the ff_data_source is feed back to ff_data_sink
 
32,10 → 36,10
.test1(test1), .test2(test2), .test3(test3), .test4(test4)
);
pll pll_inst (
.inclk0 ( clk_in ),
.c0 ( clk_10K ),
.c1 ( ff_clk )
);
pll pll_inst (
.inclk0 ( clk_in ),
.c0 ( clk_10K ),
.c1 ( ff_clk )
);
 
endmodule
/trunk/rtl/verilog/EthernetModule.v
31,7 → 31,6
//after reset, phy_txclk and phy_rxen must be input ports
inout phy_txclk, phy_col, phy_rxen, phy_linksts, phy_crs;
//wire ff_en, ff_data,
wire out_en;
wire rxen_in, txclk_in;
56,7 → 55,8
.frameid(frameid),
`endif
.start(start),
.test1(test1), .test2(test2), .test3(test3), .test4(test4));
.test1(), .test2(), .test3(), .test4());
//.test1(test1), .test2(test2), .test3(test3), .test4(test4));
 
RxModule RxModule_inst(.phy_rxd(phy_rxd), .phy_rxen(rxen_in), .phy_rxclk(phy_rxclk), .phy_rxer(phy_rxer),
.ff_clk(ff_clk), .ff_data(ff_data_source), .ff_en(ff_en_source),
63,9 → 63,8
`ifdef frameIDfromRx
.frameid(frameid),
`endif
.start(start));
//assign test1 = ff_en;
//assign test2 = ff_data;
.start(start),
//.test1(), .test2(), .test3(), .test4());
.test1(test1), .test2(test2), .test3(test3), .test4(test4));
endmodule
/trunk/rtl/verilog/common.v
1,6 → 1,6
//author :gurenliang
//author :Renliang Gu
//Email: gurenliang@gmail.com
//note: if there are some errors, you are welcome to contact me. It would be the best appreciation to me.
//note: if there are some errors, please feel free to contact me. Thank you very much!
 
//Next step, reduce the resource consumed
 
18,12 → 18,8
`define MAC_ADD 48'h0100_0000_0000 //mac address: 0x00-00-00-00-00-01
`define PC_MAC_ADD 48'hffff_ffff_ffff //mac address of the other terminal
 
`define uframelen 148 //148-bit
`define num_uframe 16 //the number of uframes received once
//`define num_cover_32
`define num_cover_16
`define num_cover_8
`define num_cover_4
 
 
`define frameidlen 24 //the id of the MAC frame
`define frameidlen 24 //the id of the MAC frame
`define uframelen 148 //148-bit
`define num_uframe 8 //the number of uframes received once
`define interval 8.25 //the interval between frames without send any data on fifo

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