OpenCores

trunk/vga_lcd/doc/vga_core.pdf Property changes : Deleted: svn:mime-type ## -1 +0,0 ## -application/octet-stream \ No newline at end of property Index: trunk/vga_lcd/doc/src/vga_core_enh.doc =================================================================== Cannot display: file marked as a binary type. svn:mime-type = application/octet-stream Index: trunk/vga_lcd/doc/src/vga_core_enh.doc =================================================================== --- trunk/vga_lcd/doc/src/vga_core_enh.doc (revision 5) +++ trunk/vga_lcd/doc/src/vga_core_enh.doc (nonexistent)

trunk/vga_lcd/doc/src/vga_core_enh.doc Property changes : Deleted: svn:mime-type ## -1 +0,0 ## -application/octet-stream \ No newline at end of property Index: trunk/vga_lcd/sim/rtl_sim/bin/Makefile =================================================================== --- trunk/vga_lcd/sim/rtl_sim/bin/Makefile (revision 5) +++ trunk/vga_lcd/sim/rtl_sim/bin/Makefile (nonexistent) @@ -1,161 +0,0 @@ - -all: sim -SHELL = /bin/sh -#MS="-s" - -########################################################################## -# -# DUT Sources -# -########################################################################## -DUT_SRC_DIR=../../../rtl/verilog -_TARGETS_= $(DUT_SRC_DIR)/generic_dpram.v \ - $(DUT_SRC_DIR)/generic_spram.v \ - $(DUT_SRC_DIR)/csm_spram_bw.v \ - $(DUT_SRC_DIR)/vga_colproc.v \ - $(DUT_SRC_DIR)/vga_csm_pb.v \ - $(DUT_SRC_DIR)/vga_cur_cregs.v \ - $(DUT_SRC_DIR)/vga_curproc.v \ - $(DUT_SRC_DIR)/vga_enh_top.v \ - $(DUT_SRC_DIR)/vga_dvi_top.v \ - $(DUT_SRC_DIR)/vga_fifo.v \ - $(DUT_SRC_DIR)/vga_fifo_dc.v \ - $(DUT_SRC_DIR)/vga_pgen.v \ - $(DUT_SRC_DIR)/vga_tgen.v \ - $(DUT_SRC_DIR)/vga_vtim.v \ - $(DUT_SRC_DIR)/vga_wb_master.v \ - $(DUT_SRC_DIR)/vga_wb_slave.v - - -########################################################################## -# -# Test Bench Sources -# -########################################################################## -TB_SRC_DIR=../../../bench/verilog -_TB_= $(TB_SRC_DIR)/test_bench_top.v \ - $(TB_SRC_DIR)/wb_slv_model.v \ - $(TB_SRC_DIR)/wb_mast_model.v \ - $(TB_SRC_DIR)/sync_check.v \ - $(TB_SRC_DIR)/artsmcl18u_ram/art_hssp_512x24_bw_bist.v \ - $(TB_SRC_DIR)/artsmcl18u_ram/art_hsdp_128x24_bist.v \ - $(TB_SRC_DIR)/bist/rtl/verilog/bist_dp_top.v \ - $(TB_SRC_DIR)/bist/rtl/verilog/bist_sp_top.v \ - $(TB_SRC_DIR)/bist/rtl/verilog/bist_tp_top.v \ - $(TB_SRC_DIR)/bist/rtl/verilog/bist.v \ - $(TB_SRC_DIR)/artsmcl18u_ram/art_hssp_512x24_bw/art_hssp_512x24_bw.v \ - $(TB_SRC_DIR)/artsmcl18u_ram/art_hsdp_128x24/art_hsdp_128x24.v \ - $(TB_SRC_DIR)/wb_b3_check.v - -########################################################################## -# -# Misc Variables -# -########################################################################## - -_TOP_=test -INCDIR="-INCDIR ./$(DUT_SRC_DIR)/ -INCDIR ./$(TB_SRC_DIR)/" -LOGF=-LOGFILE .nclog -NCCOMMON=-CDSLIB ncwork/cds.lib -HDLVAR ncwork/hdl.var -NOCOPYRIGHT -UMC_LIB=/tools/dc_libraries/virtual_silicon/umc_lib.v -GATE_NETLIST=../../../syn/out/vga_vga_and_clut_ps.v - -########################################################################## -# -# Make Targets -# -########################################################################## -simw: - @$(MAKE) -s sim ACCESS="-ACCESS +r" WAVES="-DEFINE WAVES" - -ss: - signalscan -do waves/waves.do -waves waves/waves.trn & - -sim: - @echo "" - @echo "----- Running NCVLOG ... ----------" - @$(MAKE) $(MS) vlog \ - TARGETS="$(_TARGETS_)" \ - TB="$(_TB_)" \ - INCDIR=$(INCDIR) \ - WAVES="$(WAVES)" \ - TOP=$(_TOP_) - @echo "" - @echo "----- Running NCELAB ... ----------" - @$(MAKE) $(MS) elab \ - ACCESS="$(ACCESS)" TOP=$(_TOP_) - @echo "" - @echo "----- Running NCSIM ... ----------" - @$(MAKE) $(MS) ncsim \ - TOP=$(_TOP_) - @echo "" - - -gatew: - @$(MAKE) -s gate ACCESS="-ACCESS +r " WAVES="-DEFINE WAVES" - -gate: - @echo "" - @echo "----- Running NCVLOG ... ----------" - $(MAKE)$(MS) vlog \ - TARGETS="$(UMC_LIB) $(GATE_NETLIST)" \ - TB="$(_TB_)" \ - INCDIR=$(INCDIR) \ - WAVES="$(WAVES)" - @echo "" - @echo "----- Running NCELAB ... ----------" - @$(MAKE) $(MS) elab \ - ACCESS="$(ACCESS)" TOP=$(_TOP_) - @echo "" - @echo "----- Running NCSIM ... ----------" - @$(MAKE) $(MS) ncsim TOP=$(_TOP_) - @echo "" - - -hal: - @echo "" - @echo "----- Running HAL ... ----------" - hal +incdir+$(DUT_SRC_DIR) \ - -NOP -NOS -nocheck STYVAL:USEPRT:NOBLKN:DLNBLK \ - "$(_TARGETS_)" - @echo "----- DONE ... ----------" - -clean: - rm -rf ./waves/*.dsn ./waves/*.trn \ - ncwork/worklib/* ncwork/count/* \ - ncwork/worklib/.i* ncwork/count/.i* - -########################################################################## -# -# NCVLOG -# -########################################################################## - -vlog: - ncvlog $(NCCOMMON) $(LOGF) \ - -WORK worklib $(WAVES) $(TARGETS) $(TB) $(INCDIR) - -########################################################################## -# -# NCELAB -# -########################################################################## - -elab: - ncelab $(NCCOMMON) $(LOGF) -APPEND_LOG \ - -WORK worklib $(ACCESS) \ - -NOTIMINGCHECKS \ - worklib.$(TOP) - -########################################################################## -# -# NCSIM -# -########################################################################## - -ncsim: - ncsim $(NCCOMMON) $(LOGF) -APPEND_LOG \ - -EXIT -ERRORMAX 10 worklib.$(TOP) - - - Index: trunk/vga_lcd/syn/bin/comp.dc =================================================================== --- trunk/vga_lcd/syn/bin/comp.dc (revision 5) +++ trunk/vga_lcd/syn/bin/comp.dc (nonexistent) @@ -1,134 +0,0 @@ -############################################################################### -# -# Actual Synthesis Script -# -# This script does the actual synthesis -# -# Author: Rudolf Usselmann -# rudi@asics.ws -# -# Revision: -# 3/7/01 RU Initial Sript -# -# -############################################################################### - -# ============================================== -# Setup Design Parameters -source ../bin/design_spec.dc - -# ============================================== -# Setup Libraries -source ../bin/lib_spec.dc - -# ============================================== -# Setup IO Files - -append log_file ../log/$active_design "_cmp.log" -append pre_comp_db_file ../out/$design_name "_pre.db" -append post_comp_db_file ../out/$design_name ".db" -append post_syn_verilog_file ../out/$design_name "_ps.v" -set junk_file /dev/null - -sh rm -f $log_file - -# ============================================== -# Setup Misc Variables - -set hdlin_enable_vpp true ;# Important - this enables 'ifdefs - -# ============================================== -# Read Design - -echo "+++++++++ Reading Design ..." >> $log_file -read_file $pre_comp_db_file >> $log_file - -# ============================================== -# Operating conditions - -echo "+++++++++ Setting up Operation Conditions ..." >> $log_file -current_design $design_name -set_operating_conditions WORST >> $log_file - -# Turn off automatic wire load selection, as this -# always (WHY ???) defaults to "zero_load" -#set auto_wire_load_selection false -#set_wire_load_mode enclosed >> $log_file -#set_wire_load_mode top >> $log_file -#set_wire_load_model -name suggested_40K >> $log_file - -# ============================================== -# Setup Clocks and Resets - -echo "+++++++++ Setting up Clocks ..." >> $log_file - -set_drive 0 wb_clk_i -set_drive 0 clk_pclk_i - -# !!! WISHBONE Clock !!! -set clock_period 5 -create_clock -period $clock_period wb_clk_i -set_clock_skew -uncertainty 0.1 wb_clk_i -set_clock_transition 0.5 wb_clk_i -set_dont_touch_network wb_clk_i - -# !!! Pixel Clock !!! -set clock_period2 20 -create_clock -period $clock_period2 clk_pclk_i -set_clock_skew -uncertainty 0.5 clk_pclk_i -set_clock_transition 0.9 clk_pclk_i -set_dont_touch_network clk_pclk_i - -# !!! Reset !!! -set_drive 0 wb_rst_i -set_dont_touch_network wb_rst_i -set_drive 0 rst_nreset_i -set_dont_touch_network rst_nreset_i - -# ============================================== -# Setup IOs - -echo "+++++++++ Setting up IOs ..." >> $log_file - -# Need to spell out external IOs - -set_driving_cell -cell NAND2D2 -pin Z [all_inputs] >> $junk_file -set_load 0.2 [all_outputs] - -set_input_delay -max 2 -clock wb_clk_i [all_inputs] -set_output_delay -max 2 -clock wb_clk_i [all_outputs] - -set_input_delay -max 2 -clock clk_pclk_i [all_inputs] -set_output_delay -max 2 -clock clk_pclk_i [all_outputs] - -# ============================================== -# Setup Area Constrains -set_max_area 0.0 -set compile_sequential_area_recovery true - -# ============================================== -# Force Ultra -set_ultra_optimization -f - -# ============================================== -# Compile Design - -echo "+++++++++ Starting Compile ..." >> $log_file -#compile -map_effort low -area_effort low >> $log_file -compile -map_effort high -area_effort high -boundary_optimization -auto_ungroup >> $log_file - -# ============================================== -# Write Out the optimized design - -echo "+++++++++ Saving Optimized Design ..." >> $log_file -write_file -hierarchy -format verilog -output $post_syn_verilog_file -write_file -hierarchy -format db -output $post_comp_db_file - -# ============================================== -# Create Some Basic Reports - -echo "+++++++++ Reporting Final Results ..." >> $log_file -report_timing -nworst 10 >> $log_file -report_area >> $log_file - - Index: trunk/vga_lcd/syn/bin/lib_spec.dc =================================================================== --- trunk/vga_lcd/syn/bin/lib_spec.dc (revision 5) +++ trunk/vga_lcd/syn/bin/lib_spec.dc (nonexistent) @@ -1,36 +0,0 @@ -############################################################################### -# -# Library Specification -# -# Author: Rudolf Usselmann -# rudi@asics.ws -# -# Revision: -# 3/7/01 RU Initial Sript -# -# -############################################################################### - -# ============================================== -# Setup Libraries - -set search_path [list $search_path . \ - /tools/dc_libraries/virtual_silicon/UMCL18U250D2_2.2/design_compiler/ \ - $hdl_src_dir] - -set snps [getenv "SYNOPSYS"] - -set synthetic_library "" -append synthetic_library $snps "/libraries/syn/dw01.sldb " -append synthetic_library $snps "/libraries/syn/dw02.sldb " -append synthetic_library $snps "/libraries/syn/dw03.sldb " -append synthetic_library $snps "/libraries/syn/dw04.sldb " -append synthetic_library $snps "/libraries/syn/dw05.sldb " -append synthetic_library $snps "/libraries/syn/dw06.sldb " -append synthetic_library $snps "/libraries/syn/dw07.sldb " - -set target_library { umcl18u250t2_typ.db } -set link_library "" -append link_library $target_library " " $synthetic_library -set symbol_library { umcl18u250t2.sdb } - Index: trunk/vga_lcd/syn/bin/design_spec.dc =================================================================== --- trunk/vga_lcd/syn/bin/design_spec.dc (revision 5) +++ trunk/vga_lcd/syn/bin/design_spec.dc (nonexistent) @@ -1,27 +0,0 @@ -############################################################################### -# -# Design Specification -# -# Author: Rudolf Usselmann -# rudi@asics.ws -# -# Revision: -# 3/7/01 RU Initial Sript -# -# -############################################################################### - -# ============================================== -# Setup Design Parameters - -set design_files {ud_cnt ro_cnt vga_fifo_dc vga_fifo vga_colproc vga_vtim vga_pgen vga_wb_master vga_tgen vga_wb_slave vga_csm_pb vga_top vga_vga_and_clut} - - -set design_name vga_vga_and_clut -set active_design vga_vga_and_clut - -# Next Statement defines all clocks and resets in the design -set special_net {rst clk_i pclk} - -set hdl_src_dir ../../rtl/verilog/ - Index: trunk/vga_lcd/syn/bin/read.dc =================================================================== --- trunk/vga_lcd/syn/bin/read.dc (revision 5) +++ trunk/vga_lcd/syn/bin/read.dc (nonexistent) @@ -1,66 +0,0 @@ -############################################################################### -# -# Pre Synthesis Script -# -# This script only reads in the design and saves it in a DB file -# -# Author: Rudolf Usselmann -# rudi@asics.ws -# -# Revision: -# 3/7/01 RU Initial Sript -# -# -############################################################################### - -# ============================================== -# Setup Design Parameters -source ../bin/design_spec.dc - -# ============================================== -# Setup Libraries -source ../bin/lib_spec.dc - -# ============================================== -# Setup IO Files - -append log_file ../log/$active_design "_pre.log" -append pre_comp_db_file ../out/$design_name "_pre.db" - -sh rm -f $log_file - -# ============================================== -# Setup Misc Variables - -set hdlin_enable_vpp true ;# Important - this enables 'ifdefs - -# ============================================== -# Read Design - -echo "+++++++++ Analyzing all design files ..." >> $log_file - -foreach module $design_files { - echo "+++++++++ Reading: $module" >> $log_file - echo +++++++++ Reading: $module - set module_file_name "" - append module_file_name $module ".v" - analyze -f verilog $module_file_name >> $log_file - elaborate $module >> $log_file - } - -current_design $active_design - -echo "+++++++++ Linking Design ..." >> $log_file -link >> $log_file - -echo "+++++++++ Uniquifying Design ..." >> $log_file -uniquify >> $log_file - -echo "+++++++++ Checking Design ..." >> $log_file -check_design >> $log_file - -# ============================================== -# Save Design -echo "+++++++++ Saving Design ..." >> $log_file -write_file -hierarchy -format db -output $pre_comp_db_file - Index: trunk/vga_lcd/software/include/oc_vga_lcd.h =================================================================== --- trunk/vga_lcd/software/include/oc_vga_lcd.h (revision 5) +++ trunk/vga_lcd/software/include/oc_vga_lcd.h (nonexistent) @@ -1,123 +0,0 @@ -/* -///////////////////////////////////////////////////////////////////// -//// //// -//// Include file for OpenCores VGA/LCD Controller //// -//// //// -//// File : oc_vga_lcd.h //// -//// Function: c-include file //// -//// //// -//// Authors: Richard Herveille (richard@asics.ws) //// -//// www.opencores.org //// -//// //// -///////////////////////////////////////////////////////////////////// -//// //// -//// Copyright (C) 2001 Richard Herveille //// -//// richard@asics.ws //// -//// www.asics.ws //// -//// //// -//// This source file may be used and distributed without //// -//// restriction provided that this copyright statement is not //// -//// removed from the file and that any derivative work contains //// -//// the original copyright notice and the associated disclaimer.//// -//// //// -//// THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY //// -//// EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED //// -//// TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS //// -//// FOR A PARTICULAR PURPOSE. IN NO EVENT SHALL THE AUTHOR //// -//// OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, //// -//// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES //// -//// (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE //// -//// GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR //// -//// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF //// -//// LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT //// -//// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT //// -//// OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE //// -//// POSSIBILITY OF SUCH DAMAGE. //// -//// //// -///////////////////////////////////////////////////////////////////// -*/ - -/* - * Definitions for the Opencores VGA/LCD Controller Core - */ - -/* --- Register definitions --- */ - -/* ----- Read-write access */ - -#define OC_VGA_CTRL 0x000 /* Control register */ -#define OC_VGA_STAT 0x004 /* Status register */ -#define OC_VGA_HTIM 0x008 /* Horizontal Timing register */ -#define OC_VGA_VTIM 0x00c /* Vertical Timing register */ -#define OC_VGA_HVLEN 0x010 /* Horizontal/Vertical length register*/ -#define OC_VGA_VBARA 0x014 /* Video Base Address register A */ -#define OC_VGA_VBARB 0x018 /* Video Base Address register B */ - -/* ----- Bits definition */ - -/* ----- Control register */ - /* bits 31-16 are reserved */ -#define OC_VGA_BL (1<<15) /* Blank level bit: */ -#define OC_VGA_CSL (1<<14) /* Composite Sync. level bit */ -#define OC_VGA_VSL (1<<13) /* Vertical Sync. level bit */ -#define OC_VGA_HSL (1<<12) /* Horizontal Sync. level bit */ - /* 0 - Positive */ - /* 1 - Negative */ -#define OC_VGA_PC (1<<11) /* Pseudo Color (only for 8bpp mode) */ - /* 0 - 8bpp gray scale */ - /* 1 - 8bpp pseudo color */ -#define OC_VGA_CD (1<< 9) /* Color Depth */ - /* 00 - 8bits per pixel */ - /* 01 - 16bits per pixel */ - /* 10 - 24bits per pixel */ - /* 11 - reserved */ -#define OC_VGA_VBL (1<< 7) /* Video burst length */ - /* 00 - 1 cycle */ - /* 01 - 2 cycle */ - /* 10 - 4 cycle */ - /* 11 - 8 cycle */ -#define OC_VGA_CBSWE (1<<6) /* CLUT Bank Switch Enable bit */ -#define OC_VGA_VBSWE (1<<5) /* Video Bank Switch Enable bit */ -#define OC_VGA_CBSIE (1<<4) /* CLUT Bank Switch Interrupt enable */ -#define OC_VGA_VBSIE (1<<3) /* Video Bank Switch Interrupt enable */ -#define OC_VGA_HIE (1<<2) /* Horizontal Interrupt enable */ -#define OC_VGA_VIE (1<<1) /* Vertical Interrupt enable */ -#define OC_VGA_VEN (1<<0) /* Video Enable bit */ - /* 1 - Enabled */ - /* 0 - Disabled */ - -/* ----- Status register */ - /* bits 31-18 are reserved */ -#define OC_VGA_ACMP (1<<17) /* Active CLUT Memory Page */ -#define OC_VGA_AVMP (1<<16) /* Active Video Memory Page */ - /* bits 15-8 are reserved */ -#define OC_VGA_CBSINT (1<<7) /* CLUT Bank Switch Interrupt pending */ -#define OC_VGA_VBSINT (1<<6) /* Bank Switch Interrupt pending */ -#define OC_VGA_HINT (1<<5) /* Horizontal Interrupt pending */ -#define OC_VGA_VINT (1<<4) /* Vertical Interrupt pending */ - /* bits 3-2 are reserved */ -#define OC_VGA_LUINT (1<<1) /* LineFIFO Underrun interrupt pending*/ -#define OC_VGA_SINT (1<<0) /* System Error Interrupt pending */ - - -/* ----- Horizontal/Vertical Timing registers */ - -#define OC_VGA_TSYNC (1<<24) /* Synchronization pulse width */ -#define OC_VGA_TGDEL (1<<16) /* Gate delay time */ -#define OC_VGA_TGATE (1<< 0) /* Gate time */ - - -/* ----- Horizontal and Vertcial Length registers */ - -#define OC_VGA_THLEN (1<<16) /* Horizontal length */ -#define OC_VGA_TVLEN (1<< 0) /* Vertical length */ - - -/* bit testing and setting macros */ - -#define OC_ISSET(reg,bitmask) ((reg)&(bitmask)) -#define OC_ISCLEAR(reg,bitmask) (!(OC_ISSET(reg,bitmask))) -#define OC_BITSET(reg,bitmask) ((reg)|(bitmask)) -#define OC_BITCLEAR(reg,bitmask) ((reg)|(~(bitmask))) -#define OC_BITTOGGLE(reg,bitmask) ((reg)^(bitmask)) -#define OC_REGMOVE(reg,value) ((reg)=(value)) \ No newline at end of file Index: trunk/vga_lcd/bench/verilog/tests.v =================================================================== --- trunk/vga_lcd/bench/verilog/tests.v (revision 5) +++ trunk/vga_lcd/bench/verilog/tests.v (nonexistent) @@ -1,1554 +0,0 @@ -///////////////////////////////////////////////////////////////////// -//// //// -//// Tests Library //// -//// //// -//// //// -//// Authors: Rudolf Usselmann, Richard Herveille //// -//// rudi@asics.ws, richard@asics.ws //// -//// //// -//// //// -//// Downloaded from: http://www.opencores.org/cores/vga_lcd/ //// -//// //// -///////////////////////////////////////////////////////////////////// -//// //// -//// Copyright (C) 2001 Rudolf Usselmann //// -//// rudi@asics.ws //// -//// //// -//// This source file may be used and distributed without //// -//// restriction provided that this copyright statement is not //// -//// removed from the file and that any derivative work contains //// -//// the original copyright notice and the associated disclaimer.//// -//// //// -//// THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY //// -//// EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED //// -//// TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS //// -//// FOR A PARTICULAR PURPOSE. IN NO EVENT SHALL THE AUTHOR //// -//// OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, //// -//// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES //// -//// (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE //// -//// GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR //// -//// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF //// -//// LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT //// -//// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT //// -//// OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE //// -//// POSSIBILITY OF SUCH DAMAGE. //// -//// //// -///////////////////////////////////////////////////////////////////// - -// CVS Log -// -// $Id: tests.v,v 1.1.1.1 2003-12-22 07:54:40 huyvo Exp $ -// -// $Date: 2003-12-22 07:54:40 $ -// $Revision: 1.1.1.1 $ -// $Author: huyvo $ -// $Locker: $ -// $State: Exp $ -// -// Change History: -// $Log: not supported by cvs2svn $ -// Revision 1.10 2003/09/23 13:09:25 markom -// all WB outputs are registered, but just when we dont use cursors -// -// Revision 1.9 2003/08/22 07:17:21 rherveille -// Removed ctrl register's clut and vide bank switch from the register test. As they get reset automatically. This may result to erroneous errors. -// -// Revision 1.8 2003/05/07 14:39:19 rherveille -// Added DVI tests -// -// Revision 1.7 2003/05/07 09:45:28 rherveille -// Numerous updates and added checks -// -// Revision 1.6 2003/03/19 12:20:53 rherveille -// Changed timing section in VGA core, changed testbench accordingly. -// Fixed bug in 'timing check' test. -// -// Revision 1.5 2002/04/20 09:57:55 rherveille -// Changed testbench to reflect modified VGA timing generator. -// -// -// -// -// - - -task show_errors; - -begin - -$display("\n"); -$display(" +--------------------+"); -$display(" | Total ERRORS: %0d |", error_cnt); -$display(" +--------------------+"); - -end -endtask - - -task reg_test; - -reg [31:0] data; -reg [31:0] pattern; -integer n; - -begin -$display("\n\n"); -$display("*****************************************************"); -$display("*** Register Test ***"); -$display("*****************************************************\n"); - - // Check reset Values - $display("Testing Reset Values ..."); - check( `CTRL, 0, 32'h0000_ffff, "CTRL "); - check( `STAT, 0, 32'h0000_0073, "STAT "); - check( `HTIM, 0, 32'hffff_ffff, "HTIM "); - check( `VTIM, 0, 32'hffff_ffff, "VTIM "); - check( `HVLEN, 0, 32'hffff_ffff, "HVLEN"); - check( `VBARA, 0, 32'hffff_ffff, "VBARA"); - check( `VBARB, 0, 32'hffff_ffff, "VBARB"); - - $display("Testing Pattern R/W ..."); -for(n=0;n<6;n=n+1) - begin - case(n) - 0: pattern = 32'h0000_0000; - 1: pattern = 32'hffff_ffff; - 2: pattern = 32'haaaa_aaaa; - 3: pattern = 32'h5555_5555; - 4: pattern = 32'hcccc_cccc; - 5: pattern = 32'h3333_3333; - endcase - - m0.wb_wr1( `CTRL, 4'hf, pattern ); - check( `CTRL, pattern, 32'hffff_ff9f, "CTRL "); - - m0.wb_wr1( `HTIM, 4'hf, pattern ); - check( `HTIM, pattern, 32'hffff_ffff, "HTIM "); - - m0.wb_wr1( `VTIM, 4'hf, pattern ); - check( `VTIM, pattern, 32'hffff_ffff, "VTIM "); - - m0.wb_wr1( `HVLEN, 4'hf, pattern ); - check( `HVLEN, pattern, 32'hffff_ffff, "HVLEN"); - - m0.wb_wr1( `VBARA, 4'hf, pattern ); - check( `VBARA, pattern, 32'hffff_fffc, "VBARA"); - - m0.wb_wr1( `VBARB, 4'hf, pattern ); - check( `VBARB, pattern, 32'hffff_fffc, "VBARB"); - - end - -repeat(10) @(posedge clk); - -show_errors; -$display("*****************************************************"); -$display("*** Test DONE ... ***"); -$display("*****************************************************\n\n"); - -end -endtask - - - -task check; -input [31:0] addr; -input [31:0] edata; -input [31:0] mask; -input [39:0] name; - -reg [31:0] data; -begin - -m0.wb_rd1( addr, 4'hf, data ); -if(( (data & mask) != (edata & mask)) | ((^data) === 1'bx) ) - begin - $display("ERROR: %s Reg: Value Mismatch. Expected %h, Got %h (%0t)", - name, edata & mask, data, $time); - error_cnt = error_cnt + 1; - end - -end -endtask - - - - -task tim_test; - -integer mode; - -begin -$display("\n\n"); -$display("*****************************************************"); -$display("*** Timing Test ***"); -$display("*****************************************************\n"); - - s0.fill_mem(0); - - repeat(10) @(posedge clk); - - m0.wb_wr1( `VBARA, 4'hf, 0 ); - m0.wb_wr1( `VBARB, 4'hf, 0 ); - -mode = 2; -for(mode=0;mode<6;mode=mode+1) - begin - - // reset core - scen = 0; - m0.wb_wr1( `CTRL, 4'hf, 32'h0000_0000); - repeat(10) @(posedge clk); - - $display("Mode: %0d", mode); - - case(mode) - 0: - begin - thsync = 0; - thgdel = 0; - thgate = 319; // gate = 320 - thlen = 345; - - tvsync = 0; - tvgdel = 0; - tvgate = 239; // vgate = 240 - tvlen = 245; - - hpol = 0; - vpol = 0; - cpol = 0; - bpol = 0; - end - - 1: - begin - thsync = 18; - thgdel = 18; - thgate = 319; // gate = 320 - thlen = 390; - - tvsync = 18; - tvgdel = 18; - tvgate = 239; // vgate = 240 - tvlen = 290; - - hpol = 1; - vpol = 0; - cpol = 0; - bpol = 0; - end - - 2: - begin - thsync = 1; - thgdel = 1; - thgate = 639; // hgate = 640 - thlen = 644; - - tvsync = 1; - tvgdel = 1; - tvgate = 479; // vgate = 480 - tvlen = 484; - - hpol = 0; - vpol = 1; - cpol = 0; - bpol = 0; - end - - 3: - begin - thsync = 0; - thgdel = 2; - thgate = 799; // hgate = 800 - thlen = 804; - - tvsync = 0; - tvgdel = 2; - tvgate = 599; // vgate = 600 - tvlen = 604; - - hpol = 0; - vpol = 0; - cpol = 1; - bpol = 0; - end - - 4: - begin - thsync = 3; - thgdel = 2; - thgate = 799; // hgate = 800 - thlen = 807; - - tvsync = 2; - tvgdel = 2; - tvgate = 599; // vgate = 600 - tvlen = 606; - - hpol = 0; - vpol = 0; - cpol = 0; - bpol = 1; - end - - 5: - begin - thsync = 6; - thgdel = 2; - thgate = 799; // hgate = 800 - thlen = 810; - - tvsync = 4; - tvgdel = 2; - tvgate = 599; // vgate = 600 - tvlen = 608; - - hpol = 1; - vpol = 1; - cpol = 1; - bpol = 1; - end - endcase - -/* - thsync = 0; - thgdel = 0; - thgate = 64; - thlen = 70; - - tvsync = 0; - tvgdel = 0; - tvgate = 64; - tvlen = 70; - - hpol = 0; - vpol = 0; - cpol = 0; - bpol = 0; -*/ - - - m0.wb_wr1( `HTIM, 4'hf, {thsync, thgdel, thgate} ); - m0.wb_wr1( `VTIM, 4'hf, {tvsync, tvgdel, tvgate} ); - m0.wb_wr1( `HVLEN, 4'hf, {thlen, tvlen} ); - m0.wb_wr1( `CTRL, 4'hf, { - 16'h0, - bpol, cpol, - vpol, hpol, - 1'b0, // PC - 2'h0, // CD - 2'h0, // VBL - 2'h0, // Reserved - 5'h01 // Bank Switch, INT, VideoEn - }); - - repeat(2) @(posedge vsync); - scen = 1; - repeat(4) @(posedge vsync); - end - -scen = 0; -repeat(10) @(posedge clk); - -show_errors; -$display("*****************************************************"); -$display("*** Test DONE ... ***"); -$display("*****************************************************\n\n"); - -end -endtask - - - - -task pd1_test; - -integer mode; -integer n, p, l; -reg [31:0] pn; -reg [31:0] pra, paa, tmp; -reg [23:0] pd; -reg [ 1:0] cd; -reg pc; -reg [31:0] data; -reg [31:0] cbar; -reg [ 7:0] vbl; -reg [ 5:0] delay; - -begin - -$display("\n\n"); -$display("*****************************************************"); -$display("*** Pixel Data Test 1 ***"); -$display("*****************************************************\n"); - - m0.wb_wr1( `VBARA, 4'hf, 0 ); - m0.wb_wr1( `VBARB, 4'hf, 123456 ); - - cbar = 32'h0000_0800; - - thsync = 0; - thgdel = 0; - thgate = 320; - thlen = 345; - - tvsync = 0; - tvgdel = 0; - tvgate = 240; - tvlen = 245; - - thsync = 39; - thgdel = 124; - thgate = 646; - thlen = 832; - - tvsync = 2; - tvgdel = 25; - tvgate = 484; - tvlen = 520; - - thsync = 6; - thgdel = 20; - thgate = 319; - thlen = 390; - - tvsync = 1; - tvgdel = 8; - tvgate = 239; - tvlen = 280; - -/* - thsync = 0; - thgdel = 0; - thgate = 63; - thlen = 70; - - tvsync = 0; - tvgdel = 0; - tvgate = 32; - tvlen = 36; - - thsync = 119; - thgdel = 61; - thgate = 805; - thlen = 1038; - - tvsync = 5; - tvgdel = 20; - tvgate = 600; - tvlen = 665; - -*/ - - hpol = 0; - vpol = 0; - cpol = 0; - bpol = 0; - - m0.wb_wr1( `HTIM, 4'hf, {thsync, thgdel, thgate} ); - m0.wb_wr1( `VTIM, 4'hf, {tvsync, tvgdel, tvgate} ); - m0.wb_wr1( `HVLEN, 4'hf, {thlen, tvlen} ); - -mode = 3; -vbl = 1; -delay = 1; - -for(delay=0;delay<6;delay=delay+1) - begin - s0.set_delay(delay); -for(vbl=0;vbl<4;vbl=vbl+1) -for(mode=0;mode<4;mode=mode+1) - begin - // ------------------------------- - // Turn Off VGA before Mode Change - - m0.wb_wr1( `CTRL, 4'hf, { - 16'h0, // Reserved - bpol, cpol, - vpol, hpol, - pc, // 1'b0, // PC - cd, // 2'h2, // CD - 2'h0, // VBL - 1'b0, // CBSWE - 1'b0, // VBSWE - 1'b0, // CBSIE - 1'b0, // VBSIE - 1'b0, // HIE - 1'b0, // VIE - 1'b0 // Video Enable - }); - - s0.fill_mem(1); - - `ifdef USE_VC - // Fill internal Color Lookup Table - repeat(10) @(posedge clk); - for(n=0;n<512;n=n+1) - begin - //m0.wb_rd1( 32'h0002_0000 + (n*4), 4'hf, data ); - data = s0.mem[ cbar[31:2] + n]; - m0.wb_wr1( 32'h0000_0800 + (n*4), 4'hf, data ); - end - repeat(10) @(posedge clk); - `endif - - case(mode) - 0: - begin - cd = 2'h2; - pc = 1'b0; - end - 1: - begin - cd = 2'h0; - pc = 1'b0; - end - 2: - begin - cd = 2'h0; - pc = 1'b1; - end - 3: - begin - cd = 2'h1; - pc = 1'b0; - end - endcase - - //repeat(50) @(posedge clk); - - // ------------------------------- - // Turn VGA back On ... - m0.wb_wr1( `CTRL, 4'hf, { - 16'h0, // Reserved - bpol, cpol, - vpol, hpol, - pc, // 1'b0, // PC - cd, // 2'h2, // CD - vbl[1:0], // VBL - 1'b0, // Reserved - 1'b0, // CBSWE - 1'b0, // VBSWE - 1'b0, // BSIE - 1'b0, // HIE - 1'b0, // VIE - 1'b1 // Video Enable - }); - - $display("VBL: %0d, Mode: %0d", vbl, mode); - repeat(2) @(posedge vsync); - - // For Each Line - for(l=0;l 10) $stop; - end - - @(posedge pclk); - - end - end end - -show_errors; -$display("*****************************************************"); -$display("*** Test DONE ... ***"); -$display("*****************************************************\n\n"); - -end -endtask - - - -task pd2_test; - -integer mode; -integer p, l; -reg [31:0] pn; -reg [31:0] pra, paa, tmp; -reg [23:0] pd; -reg [ 1:0] cd; -reg pc; -reg [31:0] cbar; -reg [31:0] vbase; -reg [31:0] cbase; -reg [31:0] vbara; -reg [31:0] vbarb; -reg [ 7:0] bank, vbl; -reg [ 5:0] delay; - -begin - -$display("\n\n"); -$display("*****************************************************"); -$display("*** Pixel Data Test 2 ***"); -$display("*****************************************************\n"); - - s0.fill_mem(1); - - repeat(10) @(posedge clk); - - vbara = 32'h0000_0000; - vbarb = 32'h0040_0000; - cbar = 32'h0000_0800; - - m0.wb_wr1( `VBARA, 4'hf, vbara ); - m0.wb_wr1( `VBARB, 4'hf, vbarb ); - - thsync = 6; - thgdel = 20; - thgate = 319; - thlen = 390; - - tvsync = 1; - tvgdel = 8; - tvgate = 239; -// tvgate = 240; - tvlen = 280; - -/* - thsync = 0; - thgdel = 0; - thgate = 63; - thlen = 70; - - tvsync = 0; - tvgdel = 0; - tvgate = 32; - tvlen = 36; - -*/ - -/* - thsync = 39; - thgdel = 124; - thgate = 645; - thlen = 832; - - tvsync = 2; - tvgdel = 25; - tvgate = 483; - tvlen = 520; -*/ - - hpol = 0; - vpol = 0; - cpol = 0; - bpol = 0; - - m0.wb_wr1( `HTIM, 4'hf, {thsync, thgdel, thgate} ); - m0.wb_wr1( `VTIM, 4'hf, {tvsync, tvgdel, tvgate} ); - m0.wb_wr1( `HVLEN, 4'hf, {thlen, tvlen} ); - - -`ifdef USE_VC -// Fill internal Color Lookup Table -repeat(10) @(posedge clk); -for(n=0;n<512;n=n+1) - begin - //m0.wb_rd1( 32'h0002_0000 + (n*4), 4'hf, data ); - data = s0.mem[ cbar[31:2] + n]; - m0.wb_wr1( 32'h0000_0800 + (n*4), 4'hf, data ); - end -repeat(10) @(posedge clk); -`endif - - -vbl = 3; -mode = 3; -delay = 2; - -for(delay=0;delay<6;delay=delay+1) - begin - s0.set_delay(delay); -for(vbl=0;vbl<4;vbl=vbl+1) -for(mode=0;mode<=4;mode=mode+1) - begin - - m0.wb_wr1( `CTRL, 4'hf, 32'h0); - repeat(100) @(posedge clk); - - case(mode) - 0: - begin - cd = 2'h2; - pc = 1'b0; - end - - 1: - begin - cd = 2'h0; - pc = 1'b0; - end - - 2: - begin - cd = 2'h0; - pc = 1'b1; - end - - 3: - begin - cd = 2'h1; - pc = 1'b0; - end - - 4: - begin - cd = 2'h3; - pc = 1'b0; - end - endcase - - m0.wb_wr1( `CTRL, 4'hf, { - 16'h0, // Reserved - bpol, cpol, - vpol, hpol, - pc, // 1'b0, // PC - cd, // 2'h2, // CD - vbl[1:0],// VBL - 1'b1, // CBSWE - 1'b1, // VBSWE - 1'b0, // CBSIE - 1'b0, // VBSIE - 1'b0, // HIE - 1'b0, // VIE - 1'b1 // Video Enable - } - ); - -bank = 0; - -//for(bank=0;bank<3;bank=bank+1) -for(bank=0;bank<2;bank=bank+1) - begin - - $display("VBL: %0d, Mode: %0d Screen: %0d", vbl, mode, bank); - @(posedge vsync); - - error_cnt=0; - // For Each Line - for(l=0; l 10) $stop; - end - - @(posedge pclk); - - end - end -end end - -show_errors; -$display("*****************************************************"); -$display("*** Test DONE ... ***"); -$display("*****************************************************\n\n"); - -end -endtask - - - -task ur_test; - -integer mode; -integer n, p, l; -reg [31:0] pn; -reg [31:0] pra, paa, tmp; -reg [23:0] pd; -reg [1:0] cd; -reg pc; -reg [31:0] cbar; -reg [31:0] data; -reg [7:0] vbl; - -begin - -$display("\n\n"); -$display("*****************************************************"); -$display("*** FIFO Underrun Test 1 ***"); -$display("*****************************************************\n"); - - s0.delay=15; - int_warn = 0; - - m0.wb_wr1( `VBARA, 4'hf, 0 ); - m0.wb_wr1( `VBARB, 4'hf, 123456 ); - - cbar = 32'h0000_0800; - - thsync = 6; - thgdel = 20; - thgate = 319; - thlen = 390; - - tvsync = 1; - tvgdel = 8; - tvgate = 239; - tvlen = 280; - - hpol = 0; - vpol = 0; - cpol = 0; - bpol = 0; - - m0.wb_wr1( `HTIM, 4'hf, {thsync, thgdel, thgate} ); - m0.wb_wr1( `VTIM, 4'hf, {tvsync, tvgdel, tvgate} ); - m0.wb_wr1( `HVLEN, 4'hf, {thlen, tvlen} ); - - mode = 0; - - // ------------------------------- - // Turn Off VGA before Mode Change - - m0.wb_wr1( `CTRL, 4'hf, 32'h0000_0000); - - s0.fill_mem(1); - -`ifdef USE_VC -// Fill internal Color Lookup Table -repeat(10) @(posedge clk); -for(n=0;n<512;n=n+1) - begin - //m0.wb_rd1( 32'h0002_0000 + (n*4), 4'hf, data ); - data = s0.mem[ cbar[31:2] + n]; - m0.wb_wr1( 32'h0000_0800 + (n*4), 4'hf, data ); - end -repeat(10) @(posedge clk); -`endif - - case(mode) - 0: - begin - cd = 2'h2; - pc = 1'b0; - end - 1: - begin - cd = 2'h0; - pc = 1'b0; - end - 2: - begin - cd = 2'h0; - pc = 1'b1; - end - 3: - begin - cd = 2'h1; - pc = 1'b0; - end - endcase - - // ------------------------------- - // Turn VGA back On ... - m0.wb_wr1( `CTRL, 4'hf, { - 16'h0, // Reserved - bpol, cpol, - vpol, hpol, - pc, // 1'b0, // PC - cd, // 2'h2, // CD - 2'b00, // VBL - 1'b0, // Reserved - 1'b0, // CBSWE - 1'b0, // VBSWE - 1'b0, // BSIE - 1'b0, // HIE - 1'b0, // VIE - 1'b1 // Video Enable - }); - - while(!int) @(posedge clk); - m0.wb_rd1( `STAT, 4'hf, data); - if(data[1] !== 1'b1) - begin - $display("ERROR: Did not get Line FIFO Interrupt. (%0t)", - $time); - end - -show_errors; -$display("*****************************************************"); -$display("*** Test DONE ... ***"); -$display("*****************************************************\n\n"); - -m0.wb_wr1( `CTRL, 4'hf, 32'h0000_0000); -int_warn = 1; -s0.delay=1; -repeat(10) @(posedge clk); - -end -endtask - - -////////////////////////////////////// -// -// DVI test section -// - - -task dvi_pd_test; - -integer mode; -integer n, p, l; -reg [ 2:0] dvi_odf; -reg [31:0] pn; -reg [31:0] pra, paa, tmp; -reg [23:0] pd; -reg [11:0] pda, pdb; -reg [ 1:0] cd; -reg pc; -reg [31:0] data; -reg [31:0] cbar; -reg [ 7:0] vbl; -reg [ 5:0] delay; - -begin - -$display("\n\n"); -$display("*****************************************************"); -$display("*** DVI Pixel Data Test ***"); -$display("*****************************************************\n"); - - m0.wb_wr1( `VBARA, 4'hf, 0 ); - m0.wb_wr1( `VBARB, 4'hf, 123456 ); - - cbar = 32'h0000_0800; - - thsync = 0; - thgdel = 0; - thgate = 320; - thlen = 345; - - tvsync = 0; - tvgdel = 0; - tvgate = 240; - tvlen = 245; - - thsync = 39; - thgdel = 124; - thgate = 646; - thlen = 832; - - tvsync = 2; - tvgdel = 25; - tvgate = 484; - tvlen = 520; - - thsync = 6; - thgdel = 20; - thgate = 319; - thlen = 390; - - tvsync = 1; - tvgdel = 8; - tvgate = 239; - tvlen = 280; - - hpol = 0; - vpol = 0; - cpol = 0; - bpol = 0; - - m0.wb_wr1( `HTIM, 4'hf, {thsync, thgdel, thgate} ); - m0.wb_wr1( `VTIM, 4'hf, {tvsync, tvgdel, tvgate} ); - m0.wb_wr1( `HVLEN, 4'hf, {thlen, tvlen} ); - -// Choose mode, vbl, and delay -// These should have been tested & verified by previous tests -mode = 3; -vbl = 4; -delay = 0; -s0.set_delay(delay); - -for(dvi_odf=0; dvi_odf<4;dvi_odf=dvi_odf +1) - begin - // ------------------------------- - // Turn Off VGA before Mode Change - - m0.wb_wr1( `CTRL, 4'hf, { - 2'h0, // Reserved - dvi_odf[1:0], - 12'h0, // Reserved - bpol, - cpol, - vpol, - hpol, - pc, // PC - cd, // CD - 2'h0, // VBL - 1'b0, // CBSWE - 1'b0, // VBSWE - 1'b0, // CBSIE - 1'b0, // VBSIE - 1'b0, // HIE - 1'b0, // VIE - 1'b0 // Video Enable - }); - - s0.fill_mem(1); - - `ifdef USE_VC - // Fill internal Color Lookup Table - repeat(10) @(posedge clk); - for(n=0;n<512;n=n+1) - begin - //m0.wb_rd1( 32'h0002_0000 + (n*4), 4'hf, data ); - data = s0.mem[ cbar[31:2] + n]; - m0.wb_wr1( 32'h0000_0800 + (n*4), 4'hf, data ); - end - repeat(10) @(posedge clk); - `endif - - case(mode) - 0: - begin - cd = 2'h2; - pc = 1'b0; - end - 1: - begin - cd = 2'h0; - pc = 1'b0; - end - 2: - begin - cd = 2'h0; - pc = 1'b1; - end - 3: - begin - cd = 2'h1; - pc = 1'b0; - end - endcase - - //repeat(50) @(posedge clk); - - // ------------------------------- - // Turn VGA back On ... - m0.wb_wr1( `CTRL, 4'hf, { - 2'h0, // Reserved - dvi_odf[1:0], - 12'h0, // Reserved - bpol, - cpol, - vpol, - hpol, - pc, // PC - cd, // CD - 2'h0, // VBL - 1'b0, // CBSWE - 1'b0, // VBSWE - 1'b0, // CBSIE - 1'b0, // VBSIE - 1'b0, // HIE - 1'b0, // VIE - 1'b1 // Video Enable - }); - - $display("DVI output data format: %0h", dvi_odf); - repeat(2) @(posedge vsync); - - // For Each Line - for(l=0;l 10) $stop; - end - - @(negedge pclk_i); - - // falling edge data - if (pdb !== dvi_d_o) - begin - $display("ERROR: Pixel Data Mismatch: Expected: %h, Got: %h", - pdb, dvi_d_o); - $display(" pixel=%0d, line=%0d, (%0t)",p,l,$time); - error_cnt = error_cnt + 1; - if(error_cnt > 10) $stop; - end - @(posedge pclk_i); -`else - - // compare data - if ({pdb, pda} !== dvi_d_o) - begin - $display("ERROR: Pixel Data Mismatch: Expected: %h, Got: %h", - {pdb, pda}, dvi_d_o); - $display(" pixel=%0d, line=%0d, (%0t)",p,l,$time); - error_cnt = error_cnt + 1; - if(error_cnt > 10) $stop; - end - - @(negedge pclk_i); - @(posedge pclk_i); -`endif - end - end - -show_errors; -$display("*****************************************************"); -$display("*** Test DONE ... ***"); -$display("*****************************************************\n\n"); - -end -endtask Index: trunk/vga_lcd/bench/verilog/wb_model_defines.v =================================================================== --- trunk/vga_lcd/bench/verilog/wb_model_defines.v (revision 5) +++ trunk/vga_lcd/bench/verilog/wb_model_defines.v (nonexistent) @@ -1,67 +0,0 @@ -///////////////////////////////////////////////////////////////////// -//// //// -//// WISHBONE Model Definitions //// -//// //// -//// //// -//// Author: Rudolf Usselmann //// -//// rudi@asics.ws //// -//// //// -//// //// -//// Downloaded from: http://www.opencores.org/cores/wb_dma/ //// -//// //// -///////////////////////////////////////////////////////////////////// -//// //// -//// Copyright (C) 2001 Rudolf Usselmann //// -//// rudi@asics.ws //// -//// //// -//// This source file may be used and distributed without //// -//// restriction provided that this copyright statement is not //// -//// removed from the file and that any derivative work contains //// -//// the original copyright notice and the associated disclaimer.//// -//// //// -//// THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY //// -//// EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED //// -//// TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS //// -//// FOR A PARTICULAR PURPOSE. IN NO EVENT SHALL THE AUTHOR //// -//// OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, //// -//// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES //// -//// (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE //// -//// GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR //// -//// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF //// -//// LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT //// -//// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT //// -//// OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE //// -//// POSSIBILITY OF SUCH DAMAGE. //// -//// //// -///////////////////////////////////////////////////////////////////// - -// CVS Log -// -// $Id: wb_model_defines.v,v 1.1.1.1 2003-12-22 07:54:41 huyvo Exp $ -// -// $Date: 2003-12-22 07:54:41 $ -// $Revision: 1.1.1.1 $ -// $Author: huyvo $ -// $Locker: $ -// $State: Exp $ -// -// Change History: -// $Log: not supported by cvs2svn $ -// Revision 1.2 2003/03/19 12:20:53 rherveille -// Changed timing section in VGA core, changed testbench accordingly. -// Fixed bug in 'timing check' test. -// -// Revision 1.1 2001/08/21 05:42:32 rudi -// -// - Changed Directory Structure -// - Added verilog Source Code -// - Changed IO pin names and defines statements -// -// Revision 1.1.1.1 2001/03/19 13:12:48 rudi -// Initial Release -// -// -// - -`timescale 1ns / 10ps -//`timescale 1ns / 1ns Index: trunk/vga_lcd/bench/verilog/sync_check.v =================================================================== --- trunk/vga_lcd/bench/verilog/sync_check.v (revision 5) +++ trunk/vga_lcd/bench/verilog/sync_check.v (nonexistent) @@ -1,237 +0,0 @@ -///////////////////////////////////////////////////////////////////// -//// //// -//// Top Level Test Bench //// -//// //// -//// //// -//// Author: Rudolf Usselmann //// -//// rudi@asics.ws //// -//// //// -//// //// -//// Downloaded from: http://www.opencores.org/cores/vga_lcd/ //// -//// //// -///////////////////////////////////////////////////////////////////// -//// //// -//// Copyright (C) 2001 Rudolf Usselmann //// -//// rudi@asics.ws //// -//// //// -//// This source file may be used and distributed without //// -//// restriction provided that this copyright statement is not //// -//// removed from the file and that any derivative work contains //// -//// the original copyright notice and the associated disclaimer.//// -//// //// -//// THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY //// -//// EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED //// -//// TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS //// -//// FOR A PARTICULAR PURPOSE. IN NO EVENT SHALL THE AUTHOR //// -//// OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, //// -//// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES //// -//// (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE //// -//// GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR //// -//// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF //// -//// LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT //// -//// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT //// -//// OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE //// -//// POSSIBILITY OF SUCH DAMAGE. //// -//// //// -///////////////////////////////////////////////////////////////////// - -// CVS Log -// -// $Id: sync_check.v,v 1.1.1.1 2003-12-22 07:54:39 huyvo Exp $ -// -// $Date: 2003-12-22 07:54:39 $ -// $Revision: 1.1.1.1 $ -// $Author: huyvo $ -// $Locker: $ -// $State: Exp $ -// -// Change History: -// $Log: not supported by cvs2svn $ -// Revision 1.5 2003/09/23 13:09:25 markom -// all WB outputs are registered, but just when we dont use cursors -// -// Revision 1.4 2003/05/07 09:45:28 rherveille -// Numerous updates and added checks -// -// Revision 1.3 2003/03/19 12:20:53 rherveille -// Changed timing section in VGA core, changed testbench accordingly. -// Fixed bug in 'timing check' test. -// -// Revision 1.2 2001/11/15 07:04:15 rherveille -// Updated testbench for VGA/LCD Core version 2.0 -// -// -// -// -// - -`timescale 1ns / 10ps -`include "vga_defines.v" - -module sync_check( pclk, rst, enable, hsync, vsync, csync, blanc, - hpol, vpol, cpol, bpol, - thsync, thgdel, thgate, thlen, - tvsync, tvgdel, tvgate, tvlen); - -input pclk, rst, enable, hsync, vsync, csync, blanc; -input hpol, vpol, cpol, bpol; -input [7:0] thsync, thgdel; -input [15:0] thgate, thlen; -input [7:0] tvsync, tvgdel; -input [15:0] tvgate, tvlen; - - -time last_htime; -reg hvalid; -time htime; -time hhtime; - -time last_vtime; -reg vvalid; -time vtime; -time vhtime; - -wire [31:0] htime_exp; -wire [31:0] hhtime_exp; -wire [31:0] vtime_exp; -wire [31:0] vhtime_exp; - -wire hcheck; -wire vcheck; - -wire [31:0] bh_start; -wire [31:0] bh_end; -wire [31:0] bv_start; -wire [31:0] bv_end; - -integer bdel1; -reg bval1; -reg bval; -integer bdel2; -wire bcheck; - -//initial hvalid=0; -//initial vvalid=0; - -parameter clk_time = 40; - -assign hcheck = enable; -assign vcheck = enable; -assign hhtime_exp = (thsync +1) * clk_time; -assign htime_exp = (thlen +1) * clk_time; -assign vhtime_exp = (htime_exp * (tvsync +1)); -assign vtime_exp = htime_exp * (tvlen +1); - -always @(posedge pclk) - if(!rst | !enable) - begin - hvalid = 0; - vvalid = 0; - end - -// Verify HSYNC Timing -always @(hsync) - if(hcheck) - begin - if(hsync == ~hpol) - begin - htime = $time - last_htime; - //if(hvalid) $display("HSYNC length time: %0t", htime); - if(hvalid & (htime != htime_exp)) - $display("HSYNC length ERROR: Expected: %0d Got: %0d (%0t)", - htime_exp, htime, $time); - last_htime = $time; - hvalid = 1; - end - - if(hsync == hpol) - begin - hhtime = $time - last_htime; - //if(hvalid) $display("HSYNC pulse time: %0t", hhtime); - if(hvalid & (hhtime != hhtime_exp)) - $display("HSYNC Pulse ERROR: Expected: %0d Got: %0d (%0t)", - hhtime_exp, hhtime, $time); - end - end - - -// Verify VSYNC Timing -always @(vsync) - if(vcheck) - begin - if(vsync == ~vpol) - begin - vtime = $time - last_vtime; - //if(vvalid) $display("VSYNC length time: %0t", vtime); - if(vvalid & (vtime != vtime_exp)) - $display("VSYNC length ERROR: Expected: %0d Got: %0d (%0t)", - vtime_exp, vtime, $time); - last_vtime = $time; - vvalid = 1; - end - - if(vsync == vpol) - begin - vhtime = $time - last_vtime; - //if(vvalid) $display("VSYNC pulse time: %0t", vhtime); - if(vvalid & (vhtime != vhtime_exp)) - $display("VSYNC Pulse ERROR: Expected: %0d Got: %0d (%0t)", - vhtime_exp, vhtime, $time); - end - end - -`ifdef VGA_12BIT_DVI -`else -// Verify BLANC Timing -//assign bv_start = tvsync + tvgdel + 2; -//assign bv_end = bv_start + tvgate + 2; - -//assign bh_start = thsync + thgdel + 1; -//assign bh_end = bh_start + thgate + 2; -assign bv_start = tvsync + tvgdel + 1; -assign bv_end = bv_start + tvgate + 2; - -assign bh_start = thsync + thgdel + 1; -assign bh_end = bh_start + thgate + 2; - -assign bcheck = enable; - -always @(vsync) - if(vsync == ~vpol) - bdel1 = 0; - -always @(hsync) - if(hsync == ~hpol) - bdel1 = bdel1 + 1; - -always @(bdel1) - bval1 = (bdel1 > bv_start) & (bdel1 < bv_end); - -always @(hsync) - if(hsync == ~hpol) - bdel2 = 0; - -always @(posedge pclk) - bdel2 = bdel2 + 1; - -initial bval = 1; -always @(bdel2) - bval = #1 !(bval1 & (bdel2 > bh_start) & (bdel2 < bh_end)); - -always @(bval or blanc) - #0.01 - if(enable) - if(( (blanc ^ bpol) != bval) & bcheck) - $display("BLANK ERROR: Expected: %0d Got: %0d (%0t)", - bval, (blanc ^ bpol), $time); - -// verify CSYNC -always @(csync or vsync or hsync) - if(enable) - if( (csync ^ cpol) != ( (vsync ^ vpol) | (hsync ^ hpol) ) ) - $display("CSYNC ERROR: Expected: %0d Got: %0d (%0t)", - ( (vsync ^ vpol) | (hsync ^ hpol) ), (csync ^ cpol), $time); -`endif - -endmodule - Index: trunk/vga_lcd/bench/verilog/wb_b3_check.v =================================================================== --- trunk/vga_lcd/bench/verilog/wb_b3_check.v (revision 5) +++ trunk/vga_lcd/bench/verilog/wb_b3_check.v (nonexistent) @@ -1,199 +0,0 @@ -///////////////////////////////////////////////////////////////////// -//// //// -//// WISHBONE revB.3 Registered Feedback Cycle checker //// -//// //// -//// //// -//// Author: Richard Herveille //// -//// richard@ascis.ws //// -//// //// -//// Downloaded from: http://www.opencores.org/cores/vga_lcd/ //// -//// //// -///////////////////////////////////////////////////////////////////// -//// //// -//// Copyright (C) 2003 Richard Herveille //// -//// richard@asics.ws //// -//// //// -//// This source file may be used and distributed without //// -//// restriction provided that this copyright statement is not //// -//// removed from the file and that any derivative work contains //// -//// the original copyright notice and the associated disclaimer.//// -//// //// -//// THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY //// -//// EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED //// -//// TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS //// -//// FOR A PARTICULAR PURPOSE. IN NO EVENT SHALL THE AUTHOR //// -//// OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, //// -//// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES //// -//// (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE //// -//// GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR //// -//// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF //// -//// LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT //// -//// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT //// -//// OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE //// -//// POSSIBILITY OF SUCH DAMAGE. //// -//// //// -///////////////////////////////////////////////////////////////////// - -module wb_b3_check (clk_i, cyc_i, stb_i, we_i, cti_i, bte_i, ack_i, err_i, rty_i); - -input clk_i; -input cyc_i; -input stb_i; -input [2:0] cti_i; -input [1:0] bte_i; -input we_i; -input ack_i; -input err_i; -input rty_i; - - -parameter [2:0] cti_classic = 3'b000; -parameter [2:0] cti_streaming = 3'b001; -parameter [2:0] cti_inc_burst = 3'b010; -parameter [2:0] cti_eob = 3'b111; - -// check CTI, BTE -reg [2:0] pcti; // previous cti -reg [1:0] pbte; // previous bte -reg pwe; // previous we -reg chk; - -integer wb_b3_err; - -initial -begin - chk = 0; - wb_b3_err = 0; - - $display ("**********************************************"); - $display ("** **"); - $display ("** WISBONE RevB.3 sanity check instantiated **"); - $display ("** (C) 2003 Richard Herveille **"); - $display ("** **"); - $display ("**********************************************"); -end - - -always @(posedge clk_i) - begin - pcti <= #1 cti_i; - pbte <= #1 bte_i; - pwe <= #1 we_i; - end - - -always @(posedge clk_i) - if (cyc_i) begin - chk <= #1 1'b1; - end else - chk <= #1 1'b0; - - - -// -// Check CTI_I -always @(cti_i) - if (chk) - if (cyc_i) begin - if (ack_i) - case (cti_i) - cti_eob: ; // ok - - default: - if ( (cti_i !== pcti) && (pcti !== cti_eob) ) begin - $display("\nWISHBONE revB.3 Burst error. CTI change from %b to %b not allowed. (%t)\n", - pcti, cti_i, $time); - - wb_b3_err = wb_b3_err +1; - end - endcase - else - if ( (cti_i !== pcti) && (pcti !== cti_eob) ) begin - $display("\nWISHBONE revB.3 Burst error. Illegal CTI change during burst transfer. (%t)\n", - $time); - - wb_b3_err = wb_b3_err +1; - end - end else - case (pcti) - cti_classic: ; //ok - cti_eob: ; // ok - - default: begin - $display("\nWISHBONE revB.3 Burst error. Cycle negated without EOB (CTI=%b). (%t)\n", - pcti, $time); - - wb_b3_err = wb_b3_err +1; - end - endcase - - -// -// Check BTE_I -always @(bte_i) - if (chk & cyc_i) - if (ack_i) begin - if ( (pcti !== cti_eob) && (bte_i !== pbte) ) begin - $display("\nWISHBONE revB.3 Burst ERROR. BTE change from %b to %b not allowed. (%t)\n", - pbte, bte_i, $time); - - wb_b3_err = wb_b3_err +1; - end - end else begin - $display("\nWISHBONE revB.3 Burst error. Illegal BTE change in burst cycle. (%t)\n", - $time); - - wb_b3_err = wb_b3_err +1; - end - -// -// Check WE_I -always @(we_i) - if (chk & cyc_i & stb_i) - if (ack_i) begin - if ( (pcti !== cti_eob) && (we_i !== pwe)) begin - $display("\nWISHBONE revB.3 Burst ERROR. WE change from %b to %b not allowed. (%t)\n", - pwe, we_i, $time); - - wb_b3_err = wb_b3_err +1; - end - end else begin - $display("\nWISHBONE revB.3 Burst error. Illegal WE change in burst cycle. (%t)\n", - $time); - - wb_b3_err = wb_b3_err +1; - end - - - -// -// Check ACK_I, ERR_I, RTY_I -always @(posedge clk_i) -if (cyc_i & stb_i) - case ({ack_i, err_i, rty_i}) - 3'b000: ; - 3'b001: ; - 3'b010: ; - 3'b100: ; - - default: begin - $display("\n WISHBONE revB.3 ERROR. Either ack(%0b), rty(%0b), or err(%0b) may be asserted. (%t)", - ack_i, rty_i, err_i, $time); - - wb_b3_err = wb_b3_err +1; - end - endcase - -// -// check errors -always @(wb_b3_err) - if (chk && (wb_b3_err > 10) ) begin - $display ("**********************************************"); - $display ("** **"); - $display ("** More than 10 WISBONE RevB.3 errors found **"); - $display ("** Simulation stopped **"); - $display ("** **"); - $display ("**********************************************"); - $stop; - end -endmodule Index: trunk/vga_lcd/bench/verilog/wb_mast_model.v =================================================================== --- trunk/vga_lcd/bench/verilog/wb_mast_model.v (revision 5) +++ trunk/vga_lcd/bench/verilog/wb_mast_model.v (nonexistent) @@ -1,364 +0,0 @@ -///////////////////////////////////////////////////////////////////// -//// //// -//// WISHBONE Master Model //// -//// //// -//// //// -//// Author: Rudolf Usselmann //// -//// rudi@asics.ws //// -//// //// -//// //// -//// Downloaded from: http://www.opencores.org/cores/wb_dma/ //// -//// //// -///////////////////////////////////////////////////////////////////// -//// //// -//// Copyright (C) 2001 Rudolf Usselmann //// -//// rudi@asics.ws //// -//// //// -//// This source file may be used and distributed without //// -//// restriction provided that this copyright statement is not //// -//// removed from the file and that any derivative work contains //// -//// the original copyright notice and the associated disclaimer.//// -//// //// -//// THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY //// -//// EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED //// -//// TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS //// -//// FOR A PARTICULAR PURPOSE. IN NO EVENT SHALL THE AUTHOR //// -//// OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, //// -//// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES //// -//// (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE //// -//// GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR //// -//// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF //// -//// LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT //// -//// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT //// -//// OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE //// -//// POSSIBILITY OF SUCH DAMAGE. //// -//// //// -///////////////////////////////////////////////////////////////////// - -// CVS Log -// -// $Id: wb_mast_model.v,v 1.1.1.1 2003-12-22 07:54:41 huyvo Exp $ -// -// $Date: 2003-12-22 07:54:41 $ -// $Revision: 1.1.1.1 $ -// $Author: huyvo $ -// $Locker: $ -// $State: Exp $ -// -// Change History: -// $Log: not supported by cvs2svn $ -// Revision 1.2 2003/09/23 13:09:25 markom -// all WB outputs are registered, but just when we dont use cursors -// -// Revision 1.1 2001/08/21 05:42:32 rudi -// -// - Changed Directory Structure -// - Added verilog Source Code -// - Changed IO pin names and defines statements -// -// -// -// - -`include "wb_model_defines.v" - -module wb_mast(clk, rst, adr, din, dout, cyc, stb, sel, we, ack, err, rty); - -input clk, rst; -output [31:0] adr; -input [31:0] din; -output [31:0] dout; -output cyc, stb; -output [3:0] sel; -output we; -input ack, err, rty; - -//////////////////////////////////////////////////////////////////// -// -// Local Wires -// - -reg [31:0] adr; -reg [31:0] dout; -reg cyc, stb; -reg [3:0] sel; -reg we; - -//////////////////////////////////////////////////////////////////// -// -// Memory Logic -// - -initial - begin - //adr = 32'hxxxx_xxxx; - //adr = 0; - adr = 32'hffff_ffff; - dout = 32'hxxxx_xxxx; - cyc = 0; - stb = 0; - sel = 4'hx; - we = 1'hx; - #1; - $display("\nINFO: WISHBONE MASTER MODEL INSTANTIATED (%m)\n"); - end - -//////////////////////////////////////////////////////////////////// -// -// Write 1 Word Task -// - -task wb_wr1; -input [31:0] a; -input [3:0] s; -input [31:0] d; - -begin -@(posedge clk); -#1; -adr = a; -dout = d; -cyc = 1; -stb = 1; -we=1; -sel = s; - -@(posedge clk); -while(~ack) @(posedge clk); -#1; -cyc=0; -stb=0; -adr = 32'hxxxx_xxxx; -dout = 32'hxxxx_xxxx; -we = 1'hx; -sel = 4'hx; - -//@(posedge clk); -end -endtask - - -//////////////////////////////////////////////////////////////////// -// -// Write 4 Words Task -// - -task wb_wr4; -input [31:0] a; -input [3:0] s; -input delay; -input [31:0] d1; -input [31:0] d2; -input [31:0] d3; -input [31:0] d4; - -integer delay; - -begin - -@(posedge clk); -#1; -cyc = 1; -sel = s; - -repeat(delay) - begin - @(posedge clk); - #1; - end -adr = a; -dout = d1; -stb = 1; -we=1; -while(~ack) @(posedge clk); -#2; -stb=0; -we=1'bx; -dout = 32'hxxxx_xxxx; - - -repeat(delay) - begin - @(posedge clk); - #1; - end -stb=1; -adr = a+4; -dout = d2; -we=1; -@(posedge clk); -while(~ack) @(posedge clk); -#2; -stb=0; -we=1'bx; -dout = 32'hxxxx_xxxx; - -repeat(delay) - begin - @(posedge clk); - #1; - end -stb=1; -adr = a+8; -dout = d3; -we=1; -@(posedge clk); -while(~ack) @(posedge clk); -#2; -stb=0; -we=1'bx; -dout = 32'hxxxx_xxxx; - -repeat(delay) - begin - @(posedge clk); - #1; - end -stb=1; -adr = a+12; -dout = d4; -we=1; -@(posedge clk); -while(~ack) @(posedge clk); -#1; -stb=0; -cyc=0; - -adr = 32'hxxxx_xxxx; -dout = 32'hxxxx_xxxx; -we = 1'hx; -sel = 4'hx; - -end -endtask - - -//////////////////////////////////////////////////////////////////// -// -// Read 1 Word Task -// - -task wb_rd1; -input [31:0] a; -input [3:0] s; -output [31:0] d; - -begin - -@(posedge clk); -#1; -adr = a; -cyc = 1; -stb = 1; -we = 0; -sel = s; - -//@(posedge clk); -while(~ack) @(posedge clk); -d = din; -#1; -cyc=0; -stb=0; -//adr = 32'hxxxx_xxxx; -//adr = 0; -adr = 32'hffff_ffff; -dout = 32'hxxxx_xxxx; -we = 1'hx; -sel = 4'hx; - -end -endtask - - -//////////////////////////////////////////////////////////////////// -// -// Read 4 Words Task -// - - -task wb_rd4; -input [31:0] a; -input [3:0] s; -input delay; -output [31:0] d1; -output [31:0] d2; -output [31:0] d3; -output [31:0] d4; - -integer delay; -begin - -@(posedge clk); -#1; -cyc = 1; -we = 0; -sel = s; -repeat(delay) @(posedge clk); - -adr = a; -stb = 1; -while(~ack) @(posedge clk); -d1 = din; -#2; -stb=0; -we = 1'hx; -sel = 4'hx; -repeat(delay) - begin - @(posedge clk); - #1; - end -we = 0; -sel = s; - -adr = a+4; -stb = 1; -@(posedge clk); -while(~ack) @(posedge clk); -d2 = din; -#2; -stb=0; -we = 1'hx; -sel = 4'hx; -repeat(delay) - begin - @(posedge clk); - #1; - end -we = 0; -sel = s; - - -adr = a+8; -stb = 1; -@(posedge clk); -while(~ack) @(posedge clk); -d3 = din; -#2; -stb=0; -we = 1'hx; -sel = 4'hx; -repeat(delay) - begin - @(posedge clk); - #1; - end -we = 0; -sel = s; - -adr = a+12; -stb = 1; -@(posedge clk); -while(~ack) @(posedge clk); -d4 = din; -#1; -stb=0; -cyc=0; -we = 1'hx; -sel = 4'hx; -adr = 32'hffff_ffff; -end -endtask - - -endmodule Index: trunk/vga_lcd/bench/verilog/wb_slv_model.v =================================================================== --- trunk/vga_lcd/bench/verilog/wb_slv_model.v (revision 5) +++ trunk/vga_lcd/bench/verilog/wb_slv_model.v (nonexistent) @@ -1,173 +0,0 @@ -///////////////////////////////////////////////////////////////////// -//// //// -//// WISHBONE Slave Model //// -//// //// -//// //// -//// Author: Rudolf Usselmann //// -//// rudi@asics.ws //// -//// //// -//// //// -//// Downloaded from: http://www.opencores.org/cores/vga_lcd/ //// -//// //// -///////////////////////////////////////////////////////////////////// -//// //// -//// Copyright (C) 2001 Rudolf Usselmann //// -//// rudi@asics.ws //// -//// //// -//// This source file may be used and distributed without //// -//// restriction provided that this copyright statement is not //// -//// removed from the file and that any derivative work contains //// -//// the original copyright notice and the associated disclaimer.//// -//// //// -//// THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY //// -//// EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED //// -//// TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS //// -//// FOR A PARTICULAR PURPOSE. IN NO EVENT SHALL THE AUTHOR //// -//// OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, //// -//// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES //// -//// (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE //// -//// GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR //// -//// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF //// -//// LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT //// -//// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT //// -//// OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE //// -//// POSSIBILITY OF SUCH DAMAGE. //// -//// //// -///////////////////////////////////////////////////////////////////// - -// CVS Log -// -// $Id: wb_slv_model.v,v 1.1.1.1 2003-12-22 07:54:42 huyvo Exp $ -// -// $Date: 2003-12-22 07:54:42 $ -// $Revision: 1.1.1.1 $ -// $Author: huyvo $ -// $Locker: $ -// $State: Exp $ -// -// Change History: -// $Log: not supported by cvs2svn $ -// Revision 1.3 2003/05/07 09:45:28 rherveille -// Numerous updates and added checks -// -// Revision 1.2 2002/02/07 05:38:32 rherveille -// Added wb_ack delay section to testbench -// -// Revision 1.1 2001/08/21 05:42:32 rudi -// -// - Changed Directory Structure -// - Added verilog Source Code -// - Changed IO pin names and defines statements -// -// -// -// - -`include "wb_model_defines.v" - -module wb_slv(clk, rst, adr, din, dout, cyc, stb, sel, we, ack, err, rty); - -input clk, rst; -input [31:0] adr, din; -output [31:0] dout; -input cyc, stb; -input [3:0] sel; -input we; -output ack, err, rty; - -//////////////////////////////////////////////////////////////////// -// -// Local Wires -// - -parameter mem_size = 13; -parameter sz = (1<9000) - begin - $display("\n\n*************************************\n"); - $display("ERROR: Watch Dog Counter Expired\n"); - $display("*************************************\n\n\n"); - $finish; - end - - -always @(posedge int) - if(int_warn) - begin - $display("\n\n*************************************\n"); - $display("WARNING: Recieved Interrupt (%0t)", $time); - $display("*************************************\n\n\n"); - end - -always #2.4 clk = ~clk; -always #(PCLK_C/2) pclk_i = ~pclk_i; - -///////////////////////////////////////////////////////////////////// -// -// WISHBONE VGA/LCD IP Core -// - - -// Module Prototype - -`ifdef VGA_12BIT_DVI -vga_dvi_top #(1'b0, LINE_FIFO_AWIDTH) u0 ( -`else -vga_enh_top #(1'b0, LINE_FIFO_AWIDTH) u0 ( -`endif - .wb_clk_i ( clk ), - .wb_rst_i ( 1'b0 ), - .rst_i ( rst ), - .wb_inta_o ( int ), - - //-- slave signals - .wbs_adr_i ( wb_addr_i[11:0] ), - .wbs_dat_i ( wb_data_i ), - .wbs_dat_o ( wb_data_o ), - .wbs_sel_i ( wb_sel_i ), - .wbs_we_i ( wb_we_i ), - .wbs_stb_i ( wb_stb_i ), - .wbs_cyc_i ( wb_cyc_i ), - .wbs_ack_o ( wb_ack_o ), - .wbs_rty_o ( wb_rty_o ), - .wbs_err_o ( wb_err_o ), - - //-- master signals - .wbm_adr_o ( wb_addr_o[31:0] ), - .wbm_dat_i ( wbm_data_i ), - .wbm_sel_o ( wb_sel_o ), - .wbm_we_o ( wb_we_o ), - .wbm_stb_o ( wb_stb_o ), - .wbm_cyc_o ( wb_cyc_o ), - .wbm_cti_o ( wb_cti_o ), - .wbm_bte_o ( wb_bte_o ), - .wbm_ack_i ( wb_ack_i ), - .wbm_err_i ( wb_err_i ), - - //-- VGA signals - .clk_p_i ( pclk_i ) - `ifdef VGA_24BIT_DVI - , .dvi_hsync_o ( ihsync ), - .dvi_vsync_o ( ivsync ), - .dvi_de_o ( dvi_de_o ), - .dvi_d_o ( dvi_d_o ) - `endif - `ifdef VGA_12BIT_DVI - `else - , .hsync_pad_o ( hsync ), - .vsync_pad_o ( vsync ), - .csync_pad_o ( csync ), - .blank_pad_o ( blanc ), - .r_pad_o ( red ), - .g_pad_o ( green ), - .b_pad_o ( blue ) - `endif - - `ifdef VGA_BIST - /* BIST signals */ - , .scanb_rst(1'b1), - .scanb_clk(1'b0), - .scanb_si (1'b0), - .scanb_en (1'b0), - .scanb_so () - `endif - ); - -assign pclk = pclk_i; - -`ifdef VGA_12BIT_DVI -assign hsync = !ihsync; -assign vsync = !ivsync; -`endif - -wb_mast m0( .clk( clk ), - .rst( rst ), - .adr( wb_addr_i ), - .din( wb_data_o ), - .dout( wb_data_i ), - .cyc( wb_cyc_i ), - .stb( wb_stb_i ), - .sel( wb_sel_i ), - .we( wb_we_i ), - .ack( wb_ack_o ), - .err( wb_err_o ), - .rty( 1'b0 ) - ); - -wb_slv #(24) s0(.clk( clk ), - .rst( rst ), - .adr( {1'b0, wb_addr_o[30:0]} ), - .din( 32'h0 ), - .dout( wbm_data_i ), - .cyc( wb_cyc_o ), - .stb( wb_stb_o ), - .sel( wb_sel_o ), - .we( wb_we_o ), - .ack( wb_ack_i ), - .err( wb_err_i ), - .rty( ) - ); - -`include "tests.v" - -endmodule

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