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URL https://opencores.org/ocsvn/802154phycore/802154phycore/trunk

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/rtl/rz_enc.vhd
0,0 → 1,34
-- Copyright (c) 2010 Antonio de la Piedra
-- This program is free software: you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation, either version 3 of the License, or
-- (at your option) any later version.
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
-- You should have received a copy of the GNU General Public License
-- along with this program. If not, see <http://www.gnu.org/licenses/>.
 
-- A VHDL model of the IEEE 802.15.4 physical layer.
 
 
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
 
entity rz_enc is
Port( rz_encoder_input: in std_logic_vector(9 downto 0);
rz_output: out std_logic);
end rz_enc;
 
architecture Behavioral of rz_enc is
 
begin
rz_output <= '1' when signed(rz_encoder_input) > 0 else '0';
end Behavioral;
 
/rtl/rx_core.vhd
0,0 → 1,118
-- Copyright (c) 2010 Antonio de la Piedra
-- This program is free software: you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation, either version 3 of the License, or
-- (at your option) any later version.
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
-- You should have received a copy of the GNU General Public License
-- along with this program. If not, see <http://www.gnu.org/licenses/>.
 
-- A VHDL model of the IEEE 802.15.4 physical layer.
 
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
use ieee.numeric_std.ALL;
 
entity rx_core is
port (clk_1_mhz: in std_logic;
clk_8_mhz: in std_logic;
rx_core_start: in std_logic;
rx_core_rst: in std_logic;
rx_core_input_i: in std_logic_vector(9 downto 0);
rx_core_input_q: in std_logic_vector(9 downto 0);
rx_sym_out : out std_logic_vector(3 downto 0));
end rx_core;
 
architecture Behavioral of rx_core is
signal rx_core_input_i_delayed : std_logic_vector(9 downto 0);
signal mfilter_ch_i, mfilter_ch_q : std_logic_vector(9 downto 0);
signal down_ch_i, down_ch_q : std_logic_vector(9 downto 0);
signal rz_ch_i, rz_ch_q : std_logic;
signal corr_s_1, corr_s_2 : std_logic;
 
constant N : integer := 5;
 
type delay_buffer_t is array(N-1 downto 0) of
std_logic_vector(9 downto 0);
 
signal delay_buffer_ch_i : delay_buffer_t;
 
signal corr_sym : std_logic_vector(3 downto 0);
signal corr_start_delayed : std_logic_vector(2 downto 0);
begin
 
FIR_RX_CH_I : entity work.rx_fir(Behavioral) port map (rx_core_input_i_delayed,
clk_8_mhz,
rx_core_rst,
mfilter_ch_i);
 
FIR_RX_CH_Q : entity work.rx_fir(Behavioral) port map (rx_core_input_q,
clk_8_mhz,
rx_core_rst,
mfilter_ch_q);
 
DOWNSAMPLER_CH_I : entity work.downsampler(Behavioral) port map (clk_1_mhz,
rx_core_start,
mfilter_ch_i,
down_ch_i);
 
 
DOWNSAMPLER_CH_Q : entity work.downsampler(Behavioral) port map (clk_1_mhz,
rx_core_start,
mfilter_ch_q,
down_ch_q);
 
RZ_ENCODER_CH_I : entity work.rz_enc(Behavioral) port map (down_ch_i,
rz_ch_i);
 
RZ_ENCODER_CH_Q : entity work.rz_enc(Behavioral) port map (down_ch_q,
rz_ch_q);
 
SYM_CORR : entity work.sym_corr(Behavioral) port map (corr_start_delayed(2),
clk_1_mhz,
rx_core_rst,
rz_ch_q,
rx_sym_out);
 
-- Symbol correlator start signal is delayed by 2 us
-- before it can start detecting symbols.
corr_start_delayed(0) <= rx_core_start;
 
gen_delay_corr: for i in 1 to 2 generate
corr_delay: process(clk_1_mhz)
begin
if rising_edge(clk_1_mhz) then
corr_start_delayed(i) <= corr_start_delayed(i-1);
end if;
end process corr_delay;
end generate gen_delay_corr;
-- I Channel is delayed to perform demodulation at the same
-- time that Q Channel (delayed by Tx) arrives.
delay_buffer_ch_i(0) <= rx_core_input_i;
gen_delay_ch_i: for i in 1 to N-1 generate
i_ch_delay: process(clk_8_mhz)
begin
if rising_edge(clk_8_mhz) then
delay_buffer_ch_i(i) <= delay_buffer_ch_i(i-1);
end if;
end process i_ch_delay;
end generate gen_delay_ch_i;
rx_core_input_i_delayed <= delay_buffer_ch_i(N-1);
 
end Behavioral;
 
/rtl/tx_core.vhd
0,0 → 1,92
-- Copyright (c) 2010 Antonio de la Piedra
-- This program is free software: you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation, either version 3 of the License, or
-- (at your option) any later version.
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
-- You should have received a copy of the GNU General Public License
-- along with this program. If not, see <http://www.gnu.org/licenses/>.
 
-- A VHDL model of the IEEE 802.15.4 physical layer.
 
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
 
entity tx_core is
 
port( clk_1_mhz : in std_logic;
clk_8_mhz : in std_logic;
tx_core_start : in std_logic;
tx_core_rst : in std_logic;
tx_core_symbol : in std_logic_vector(3 downto 0);
tx_core_i_out : out std_logic_vector(9 downto 0);
tx_core_q_out : out std_logic_vector(9 downto 0));
 
end tx_core;
 
architecture Behavioral of tx_core is
constant N : integer := 5;
 
type delay_buffer_t is array(N-1 downto 0) of
std_logic_vector(9 downto 0);
 
signal chip_i, chip_q : std_logic;
signal upsampler_i, upsampler_q : std_logic_vector(1 downto 0);
signal tx_core_q_out_tmp : std_logic_vector(9 downto 0);
signal delay_buffer : delay_buffer_t;
 
begin
 
CHIP_GEN : entity work.chip_gen(Behavioral) port map (tx_core_rst,
clk_1_mhz,
tx_core_symbol,
chip_i,
chip_q);
UPSAMPLER_CH_I : entity work.upsampler(Behavioral) port map (upsampler_i,
chip_i,
clk_8_mhz,
tx_core_start);
UPSAMPLER_CH_Q : entity work.upsampler(Behavioral) port map (upsampler_q,
chip_q,
clk_8_mhz,
tx_core_start);
FIR_CH_I : entity work.tx_fir(Behavioral) port map (upsampler_i,
clk_8_mhz,
tx_core_rst,
tx_core_i_out);
FIR_CH_Q : entity work.tx_fir(Behavioral) port map (upsampler_q,
clk_8_mhz,
tx_core_rst,
tx_core_q_out_tmp);
 
-- Q Channel delay by T_sym/2: O-QPSK modulator will need the Q channel
-- delayed by T_sym/2 (0.5 us).
delay_buffer(0) <= tx_core_q_out_tmp;
gen_delay: for i in 1 to N-1 generate
q_ch_delay: process(clk_8_mhz)
begin
if rising_edge(clk_8_mhz) then
delay_buffer(i) <= delay_buffer(i-1);
end if;
end process q_ch_delay;
end generate gen_delay;
tx_core_q_out <= delay_buffer(N-1);
end Behavioral;
 
/rtl/ieee_802_15_4_phy.vhd
0,0 → 1,65
-- Copyright (c) 2010 Antonio de la Piedra
-- This program is free software: you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation, either version 3 of the License, or
-- (at your option) any later version.
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
-- You should have received a copy of the GNU General Public License
-- along with this program. If not, see <http://www.gnu.org/licenses/>.
 
-- A VHDL model of the IEEE 802.15.4 physical layer.
 
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
 
entity ieee_802_15_4_phy is
port( clk_1_mhz : in std_logic;
clk_8_mhz : in std_logic;
rst : in std_logic;
tx_start : in std_logic;
tx_symbol :in std_logic_vector(3 downto 0);
tx_i_out : out std_logic_vector(9 downto 0);
tx_q_out : out std_logic_vector(9 downto 0);
rx_start : in std_logic;
rx_i_in : in std_logic_vector(9 downto 0);
rx_q_in : in std_logic_vector(9 downto 0);
rx_sym_out : out std_logic_vector(3 downto 0));
 
end ieee_802_15_4_phy;
 
architecture Behavioral of ieee_802_15_4_phy is
 
begin
 
TX : entity work.tx_core(Behavioral) port map (clk_1_mhz,
clk_8_mhz,
tx_start,
rst,
tx_symbol,
tx_i_out,
tx_q_out);
 
RX : entity work.rx_core(Behavioral) port map (clk_1_mhz,
clk_8_mhz,
rx_start,
rst,
rx_i_in,
rx_q_in,
rx_sym_out);
end Behavioral;
 
/rtl/upsampler.vhd
0,0 → 1,57
-- Copyright (c) 2010 Antonio de la Piedra
-- This program is free software: you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation, either version 3 of the License, or
-- (at your option) any later version.
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
-- You should have received a copy of the GNU General Public License
-- along with this program. If not, see <http://www.gnu.org/licenses/>.
 
-- A VHDL model of the IEEE 802.15.4 physical layer.
 
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
 
entity upsampler is
 
generic (factor : integer := 7);
Port( upsampler_output: OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
upsampler_input: IN STD_LOGIC;
upsampler_clk: IN STD_LOGIC;
upsampler_start: IN STD_LOGIC);
 
end upsampler;
 
architecture Behavioral of upsampler is
signal count_temp: integer range 0 to factor + 1;
begin
 
counter: process(upsampler_clk, upsampler_start)
variable count: integer range 0 to factor + 1;
begin
if (upsampler_start = '1' and rising_edge(upsampler_clk)) then
if (count = factor) then
count := 0;
else
count := count + 1;
end if;
end if;
count_temp <= count;
end process;
upsampler_output <= (not upsampler_input) & '1' when (upsampler_start = '1' and count_temp = 1)
else "00";
end Behavioral;
 
 
/rtl/rx_fir.vhd
0,0 → 1,93
-- Copyright (c) 2010 Antonio de la Piedra
-- This program is free software: you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation, either version 3 of the License, or
-- (at your option) any later version.
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
-- You should have received a copy of the GNU General Public License
-- along with this program. If not, see <http://www.gnu.org/licenses/>.
 
-- A VHDL model of the IEEE 802.15.4 physical layer.
 
--
-- Coeficientes del filtro representados sobre 10 bits en C-2,
-- 5 para la parte entera y 5 para la parte fraccionaria.
--
--
-- h0 = 0 -> 0000000000
-- h1 = 0.3826 -> 0000001100
-- h2 = 0.7071 -> 0000010111
-- h3 = 0.9238 -> 0000011110
-- h4 = 1 -> 0000100000
-- h5 = 0.9238 -> 0000011110
-- h6 = 0.7071 -> 0000010111
-- h7 = 0.3826 -> 0000001100
--
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.numeric_std.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
 
 
entity rx_fir is
 
port (mfilter_input: in std_logic_vector(9 downto 0);
mfilter_clk: in std_logic;
mfilter_rst: in std_logic;
mfilter_output: out std_logic_vector(9 downto 0));
end rx_fir;
 
architecture Behavioral of rx_fir is
type registers is array (6 downto 0) of signed(9 downto 0);
type coefficients is array (7 downto 0) of signed(9 downto 0);
signal reg: registers;
signal output_temp: std_logic_vector(9 downto 0);
constant coef: coefficients := ("0000001100",
"0000010111",
"0000011110",
"0000100000",
"0000011110",
"0000010111",
"0000001100",
"0000000000");
begin
process (mfilter_clk, mfilter_rst)
variable acc, prod: signed(19 downto 0) := (others => '0');
begin
if (mfilter_rst = '1') then
for i in 6 downto 0 loop
reg(i) <= (others => '0');
end loop;
elsif rising_edge(mfilter_clk) then
acc := coef(0)*signed(mfilter_input);
for i in 1 to 7 loop
prod := coef(i)*reg(7-i);
acc := acc + prod;
end loop;
reg <= signed(mfilter_input) & reg(6 DOWNTO 1);
end if;
output_temp <= std_logic_vector(resize(acc, mfilter_output'length));
 
end process;
mfilter_output <= output_temp;
end Behavioral;
 
 
/rtl/downsampler.vhd
0,0 → 1,42
-- Copyright (c) 2010 Antonio de la Piedra
-- This program is free software: you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation, either version 3 of the License, or
-- (at your option) any later version.
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
-- You should have received a copy of the GNU General Public License
-- along with this program. If not, see <http://www.gnu.org/licenses/>.
 
-- A VHDL model of the IEEE 802.15.4 physical layer.
 
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
 
entity downsampler is
port (downsampler_clk: in std_logic;
downsampler_start: in std_logic;
downsampler_input: in std_logic_vector(9 downto 0);
downsampler_output: out std_logic_vector(9 downto 0));
end downsampler;
 
architecture Behavioral of downsampler is
begin
process(downsampler_clk, downsampler_start, downsampler_input)
begin
if rising_edge(downsampler_clk) and downsampler_start = '1' then
downsampler_output <= downsampler_input;
end if;
end process;
end Behavioral;
 
/rtl/tx_fir.vhd
0,0 → 1,108
-- Copyright (c) 2010 Antonio de la Piedra
-- This program is free software: you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation, either version 3 of the License, or
-- (at your option) any later version.
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
-- You should have received a copy of the GNU General Public License
-- along with this program. If not, see <http://www.gnu.org/licenses/>.
 
-- A VHDL model of the IEEE 802.15.4 physical layer.
 
-- Half-cosine pulse shapping filter [1] implemented as FIR structure.
-- FIR implementation based on [2].
 
-- [1] IEEE, 802.15.4. Part 15.4: Wireless Medium Access Control (MAC) and Physical Layer (PHY)
-- Specifications for Low-Rate Wireless Personal Area Networks (LR-WPANs).
 
-- [2] Volnei A. Pedroni. Circuit Design with VHDL.
 
 
-- Filter coefficientes represented over 10 bits in 2's complement.
-- h0 = 0 -> 0000000000
-- h1 = 0.3826 -> 0000001100
-- h2 = 0.7071 -> 0000010111
-- h3 = 0.9238 -> 0000011110
-- h4 = 1 -> 0000100000
-- h5 = 0.9238 -> 0000011110
-- h6 = 0.7071 -> 0000010111
-- h7 = 0.3826 -> 0000001100
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.numeric_std.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
 
 
entity tx_fir is
 
port (mfilter_input: in std_logic_vector(1 downto 0);
mfilter_clk: in std_logic;
mfilter_rst: in std_logic;
mfilter_output: out std_logic_vector(9 downto 0));
end tx_fir;
 
architecture Behavioral of tx_fir is
type registers is array (6 downto 0) of signed(1 downto 0);
type coefficients is array (7 downto 0) of signed(9 downto 0);
signal reg: registers;
signal output_temp: std_logic_vector(9 downto 0);
constant coef: coefficients := ("0000001100",
"0000010111",
"0000011110",
"0000100000",
"0000011110",
"0000010111",
"0000001100",
"0000000000");
begin
process (mfilter_clk, mfilter_rst)
variable acc: signed(9 downto 0) := (others => '0');
begin
if (mfilter_rst = '1') then
for i in 6 downto 0 loop
reg(i) <= (others => '0');
end loop;
elsif rising_edge(mfilter_clk) then
 
if (mfilter_input = "01") then
acc := resize(coef(0), acc'length);
elsif (mfilter_input = "11") then
acc := resize(-coef(0), acc'length);
else
acc := (others => '0');
end if;
for i in 1 to 7 loop
if (reg(7-i) = "01") then
acc := resize(acc + coef(i), acc'length);
elsif (reg(7-i)= "11") then
acc := resize(acc - coef(i), acc'length);
end if;
end loop;
reg <= signed(mfilter_input) & reg(6 DOWNTO 1);
 
end if;
output_temp <= std_logic_vector(acc);
end process;
mfilter_output <= output_temp;
end Behavioral;
 
/rtl/chip_gen.vhd
0,0 → 1,122
-- Copyright (c) 2010 Antonio de la Piedra
-- This program is free software: you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation, either version 3 of the License, or
-- (at your option) any later version.
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
-- You should have received a copy of the GNU General Public License
-- along with this program. If not, see <http://www.gnu.org/licenses/>.
 
-- A VHDL model of the IEEE 802.15.4 physical layer.
 
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
use IEEE.numeric_std.ALL;
 
entity chip_gen is
 
Port( chip_gen_rst : IN STD_LOGIC;
chip_gen_clk : IN STD_LOGIC;
chip_gen_symbol: IN STD_LOGIC_VECTOR(3 downto 0);
chip_gen_iOut: OUT STD_LOGIC;
chip_gen_qOut: OUT STD_LOGIC);
 
end chip_gen;
 
architecture Behavioral of chip_gen is
TYPE symbol_array is ARRAY (7 downto 0) OF STD_LOGIC_VECTOR (3 downto 0);
CONSTANT symbols: symbol_array := ( "0111",
"0110",
"0101",
"0100",
"0011",
"0010",
"0001",
"0000");
CONSTANT symbol_zero_i : STD_LOGIC_VECTOR (15 downto 0) := "1010100100010111";
CONSTANT symbol_zero_q : STD_LOGIC_VECTOR (15 downto 0) := "1101100111000010";
 
SIGNAL muxIout, muxQout: STD_LOGIC;
SIGNAL sr1, sr2 : STD_LOGIC_VECTOR(15 downto 0);
begin
 
shr: process(chip_gen_clk, chip_gen_rst)
begin
IF (chip_gen_rst = '1') then
sr1 <= symbol_zero_i;
sr2 <= symbol_zero_q;
elsif rising_edge(chip_gen_clk) then
 
sr1 <= std_logic_vector(unsigned(sr1) rol 1);
sr2 <= std_logic_vector(unsigned(sr2) rol 1);
 
end if;
end process;
 
muxI: process(chip_gen_symbol, sr1)
begin
IF (chip_gen_symbol(2 downto 0) = symbols(0)(2 downto 0)) then
muxIout <= sr1(0);
elsif (chip_gen_symbol(2 downto 0) = symbols(1)(2 downto 0)) then
muxIout <= sr1(2);
elsif (chip_gen_symbol(2 downto 0) = symbols(2)(2 downto 0)) then
muxIout <= sr1(4);
elsif (chip_gen_symbol(2 downto 0) = symbols(3)(2 downto 0)) then
muxIout <= sr1(6);
elsif (chip_gen_symbol(2 downto 0) = symbols(4)(2 downto 0)) then
muxIout <= sr1(8);
elsif (chip_gen_symbol(2 downto 0) = symbols(5)(2 downto 0)) then
muxIout <= sr1(10);
elsif (chip_gen_symbol(2 downto 0) = symbols(6)(2 downto 0)) then
muxIout <= sr1(12);
elsif (chip_gen_symbol(2 downto 0) = symbols(7)(2 downto 0)) then
muxIout <= sr1(14);
end if;
end process;
muxQ: process(chip_gen_symbol, sr2)
begin
IF (chip_gen_symbol(2 downto 0) = symbols(0)(2 downto 0)) then
muxQout <= sr2(0) xor chip_gen_symbol(3);
elsif (chip_gen_symbol(2 downto 0) = symbols(1)(2 downto 0)) then
muxQout <= sr2(2) xor chip_gen_symbol(3);
elsif (chip_gen_symbol(2 downto 0) = symbols(2)(2 downto 0)) then
muxQout <= sr2(4) xor chip_gen_symbol(3);
elsif (chip_gen_symbol(2 downto 0) = symbols(3)(2 downto 0)) then
muxQout <= sr2(6) xor chip_gen_symbol(3);
elsif (chip_gen_symbol(2 downto 0) = symbols(4)(2 downto 0)) then
muxQout <= sr2(8) xor chip_gen_symbol(3);
elsif (chip_gen_symbol(2 downto 0) = symbols(5)(2 downto 0)) then
muxQout <= sr2(10) xor chip_gen_symbol(3);
elsif (chip_gen_symbol(2 downto 0) = symbols(6)(2 downto 0)) then
muxQout <= sr2(12) xor chip_gen_symbol(3);
elsif (chip_gen_symbol(2 downto 0) = symbols(7)(2 downto 0)) then
muxQout <= sr2(14) xor chip_gen_symbol(3);
end if;
end process;
chip_gen_iOut <= muxIout;
chip_gen_qOut <= muxQout;
end Behavioral;
 
 
 
/rtl/sym_corr.vhd
0,0 → 1,176
-- Copyright (c) 2010 Antonio de la Piedra
-- This program is free software: you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation, either version 3 of the License, or
-- (at your option) any later version.
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
-- You should have received a copy of the GNU General Public License
-- along with this program. If not, see <http://www.gnu.org/licenses/>.
 
-- A VHDL model of the IEEE 802.15.4 physical layer.
 
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
use IEEE.numeric_std.ALL;
 
entity sym_corr is
generic (t_symbol: integer := 16);
port( correlator_start :in std_logic;
correlator_clk: in std_logic;
correlator_rst: in std_logic;
correlator_input_q: in std_logic;
correlator_symbol: out std_logic_vector(3 downto 0));
end sym_corr;
 
architecture Behavioral of sym_corr is
signal count_temp: integer range 0 to 17;
signal chip_shr: std_logic_vector(15 downto 0);
type sym_t is array (15 downto 0) of std_logic_vector(15 downto 0);
type symbol_table is array (15 downto 0) of std_logic_vector(3 downto 0);
type corr_value_t is array (15 downto 0) of integer;
type max_fun_output is array (1 downto 0) of integer range 0 to 16;
constant symbol_zero_q : std_logic_vector(15 downto 0) := "1101100111000010";
 
constant symbol_table_q: symbol_table := ("1111",
"1110",
"1101",
"1100",
"1011",
"1010",
"1001",
"1000",
"0111",
"0110",
"0101",
"0100",
"0011",
"0010",
"0001",
"0000");
 
function bit_to_integer(input_value: std_logic) return integer is
begin
if (input_value = '0' ) then
return 0;
else
return 1;
end if;
end function bit_to_integer;
function max_vector(vector: corr_value_t ) return max_fun_output is
variable temp: integer range 0 to 8;
variable pos: integer range 0 to 16;
begin
temp := 0;
for i in vector'range loop
if vector(i) > temp then
temp := vector(i);
pos := i;
end if;
end loop;
return max_fun_output'(temp, pos);
end function max_vector;
begin
 
corr_shr: process(correlator_start, correlator_clk, correlator_rst)
variable chip_reg: std_logic_vector(15 downto 0);
begin
if (correlator_rst = '1') then
chip_reg := symbol_zero_q;
elsif (rising_edge(correlator_clk) and correlator_start = '1') then
chip_reg := std_logic_vector(unsigned(chip_reg) rol 1);
end if;
chip_shr <= chip_reg;
end process;
 
corr_counter: process(correlator_start, correlator_clk)
variable count: integer range 0 to t_symbol + 1:= 0;
begin
if (rising_edge(correlator_clk) and correlator_start = '1') then
count := count + 1;
if (count = t_symbol + 1) then
count := 1;
end if;
end if;
count_temp <= count;
end process;
corr: process(correlator_start, correlator_clk, correlator_rst)
variable reg: std_logic_vector(15 downto 0) := (others => '0');
variable sym: sym_t;
variable corr_value: corr_value_t;
variable sym_pos: max_fun_output;
begin
if (correlator_rst = '1') then
for i in 0 to 15 loop
sym(i):= (others =>'0');
corr_value(i) := 0;
end loop;
reg := (others => '0');
elsif (rising_edge(correlator_clk) and correlator_start = '1') then
reg := reg(14 downto 0) & correlator_input_q;
sym(0):= sym(0)(14 downto 0) & chip_shr(0);
sym(1):= sym(1)(14 downto 0) & chip_shr(2);
sym(2):= sym(2)(14 downto 0) & chip_shr(4);
sym(3):= sym(3)(14 downto 0) & chip_shr(6);
sym(4):= sym(4)(14 downto 0) & chip_shr(8);
sym(5):= sym(5)(14 downto 0) & chip_shr(10);
sym(6):= sym(6)(14 downto 0) & chip_shr(12);
sym(7):= sym(7)(14 downto 0) & chip_shr(14);
sym(8):= sym(8)(14 downto 0) & not chip_shr(0);
sym(9):= sym(9)(14 downto 0) & not chip_shr(2);
sym(10):= sym(10)(14 downto 0) & not chip_shr(4);
sym(11):= sym(11)(14 downto 0) & not chip_shr(6);
sym(12):= sym(12)(14 downto 0) & not chip_shr(8);
sym(13):= sym(13)(14 downto 0) & not chip_shr(10);
sym(14):= sym(14)(14 downto 0) & not chip_shr(12);
sym(15):= sym(15)(14 downto 0) & not chip_shr(14);
-- We've got a new symbol !
if (count_temp = t_symbol) then
for i in 0 to 15 loop
for j in 0 to 15 loop
corr_value(i) := corr_value(i) + bit_to_integer(reg(j) and sym(i)(j));
end loop;
end loop;
sym_pos := max_vector(corr_value);
correlator_symbol <= symbol_table_q(sym_pos(0));
for i in 0 to 15 loop
corr_value(i) := 0;
end loop;
end if;
end if;
end process;
end Behavioral;
 
/tb/tb_ieee_802_15_4_phy.vhd
0,0 → 1,135
--------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 15:52:31 12/15/2010
-- Design Name:
-- Module Name: /home/vmr/aes_playground/tb_pr_serial.vhd
-- Project Name: aes_playground
-- Target Device:
-- Tool versions:
-- Description:
--
-- VHDL Test Bench Created by ISE for module: pr_serial
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
-- Notes:
-- This testbench has been automatically generated using types std_logic and
-- std_logic_vector for the ports of the unit under test. Xilinx recommends
-- that these types always be used for the top-level I/O of a design in order
-- to guarantee that the testbench will bind correctly to the post-implementation
-- simulation model.
--------------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--USE ieee.numeric_std.ALL;
ENTITY tb_ieee_802_15_4_phy IS
END tb_ieee_802_15_4_phy;
ARCHITECTURE behavior OF tb_ieee_802_15_4_phy IS
constant clk_250_khz_period : time := 4 us;
constant clk_1_mhz_period : time := 1 us;
constant clk_8_mhz_period : time := 0.125 us;
 
signal clk_1_mhz : std_logic := '0';
signal clk_8_mhz : std_logic := '0';
signal rst : std_logic := '0';
signal tx_start : std_logic := '0';
signal tx_symbol : std_logic_vector(3 downto 0) := (others => '0');
signal tx_i_out : std_logic_vector(9 downto 0);
signal tx_q_out : std_logic_vector(9 downto 0);
signal rx_start : std_logic := '0';
signal rx_i_in : std_logic_vector(9 downto 0) := (others => '0');
signal rx_q_in : std_logic_vector(9 downto 0) := (others => '0');
signal rx_sym_out : std_logic_vector(3 downto 0) := (others => '0');
 
BEGIN
 
rx_i_in <= tx_i_out;
rx_q_in <= tx_q_out;
-- Instantiate the Unit Under Test (UUT)
uut: entity work.ieee_802_15_4_phy(Behavioral) PORT MAP (
clk_1_mhz,
clk_8_mhz,
rst,
tx_start,
tx_symbol,
tx_i_out,
tx_q_out,
rx_start,
rx_i_in,
rx_q_in,
rx_sym_out);
 
-- Clock process definitions
 
clk_1_mhz_process :process
begin
clk_1_mhz <= '0';
wait for clk_1_mhz_period/2;
clk_1_mhz <= '1';
wait for clk_1_mhz_period/2;
end process;
 
clk_8_mhz_process :process
begin
clk_8_mhz <= '0';
wait for clk_8_mhz_period/2;
clk_8_mhz <= '1';
wait for clk_8_mhz_period/2;
end process;
 
-- Stimulus process
stim_proc: process
begin
wait for clk_250_khz_period + clk_250_khz_period/2;
 
rst <= '1';
wait for clk_250_khz_period;
 
rst <= '0';
tx_symbol <= "1010";
 
tx_start <= '1';
rx_start <= '1';
wait for 16 us;
 
tx_symbol <= "0010";
 
wait for 16 us;
 
tx_symbol <= "0110";
 
wait for 16 us;
 
tx_symbol <= "1010";
 
wait for 16 us;
 
tx_symbol <= "0011";
wait;
 
end process;
 
END;

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