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-------------------------------------------------------------------------------
--
-- Title : 8b/10b Encoder
-- Design : 8-bit to 10-bit Encoder
-- Project : 8000 - 8b10b_encdec
-- Author : Ken Boyette
-- Company : Critia Computer, Inc.
--
-------------------------------------------------------------------------------
--
-- File : 8b10b_enc.vhd
-- Version : 1.0
-- Generated : 09.15.2006
-- By : Itf2Vhdl ver. 1.20
--
-------------------------------------------------------------------------------
--
-- Description :
-- This module provides 8-bit to 10-bit encoding.
-- It accepts 8-bit parallel data input and generates 10-bit encoded data
-- output in accordance with the 8b/10b standard. This coding method was
-- described in the 1983 IBM publication "A DC-Balanced, Partitioned-Block,
-- 8B/10B Transmission Code" by A.X. Widmer and P.A. Franaszek and was granted
-- a U.S. Patent #4,486,739 in 1984 which has now expired.
--
-- The parallel 8-bit Binary input represent 256 possible values, called
-- characters.
-- The bits are identified as:
-- HI, GI, FI, EI, DI, CI, BI, AI (Most Significant to Least)
-- The output is a 10-bit encoded character whose bits are identified as:
-- AO, BO, CO, DO, EO, IO, FO, GO, HO, AJO (Least Significant to Most)
-- An additional 12 output characters, K, are defined for command and
-- synchronization use.
-- KI, is used to indicate that the input is for a special character.
-- All inputs and outputs are synchronous with an externally supplied
-- byte rate clock BYTECLK.
-- The encoded output is valid one clock after the input.
-- There is a reset input, RESET, to reset the logic. The next rising
-- BYTECLK after RESET is deasserted latches valid input data.
--
-- Note: This VHDL structure closely follows the discrete logic defined
-- in the original article and the subsequent patent.
-- The Figures referenced are those in the patent.
-------------------------------------------------------------------------------
-- This program is licensed under the GPL.
-------------------------------------------------------------------------------
 
library IEEE;
use IEEE.STD_LOGIC_1164.all;
 
entity enc_8b10b is
port(
RESET : in std_logic ; -- Global asynchronous reset (active high)
SBYTECLK : in std_logic ; -- Master synchronous send byte clock
KI : in std_logic ; -- Control (K) input(active high)
AI, BI, CI, DI, EI, FI, GI, HI : in std_logic ; -- Unencoded input data
JO, HO, GO, FO, IO, EO, DO, CO, BO, AO : out std_logic -- Encoded out
);
end enc_8b10b;
 
architecture behavioral of enc_8b10b is
 
-- Signals to tie things together
signal XLRESET, LRESET : std_logic ; -- Local synchronized RESET
signal L40, L04, L13, L31, L22 : std_logic ; -- Figure 3 Signals
signal F4, G4, H4, K4, S, FNEG : std_logic ; -- Figure 4 Signals
signal PD1S6, ND1S6, PD0S6, ND0S6 : std_logic ; -- Figure 5 Signals
signal ND1S4, ND0S4, PD1S4, PD0S4 : std_logic ; -- ...Figure 5
signal COMPLS4, COMPLS6, NDL6 : std_logic ; -- Figure 6 Signals
signal PDL6, LPDL6, PDL4, LPDL4 : std_logic ; -- Figure 6
signal NAO, NBO, NCO, NDO, NEO, NIO : std_logic ; -- Figure 7 Signals
signal NFO, NGO, NHO, NJO, SINT : std_logic ; -- Figure 8
 
begin
 
-- PROCESS: SYNCRST; Synchronize and delay RESET one clock for startup
 
SYNCRST: process (RESET, XLRESET, SBYTECLK)
begin
if SBYTECLK'event and SBYTECLK = '1' then
XLRESET <= RESET ;
elsif SBYTECLK'event and SBYTECLK = '0' then
LRESET <= XLRESET ;
end if ;
end process SYNCRST ;
 
--
-- 5b Input Function (Reference: Figure 3)
--
-- Four 1's
L40 <= AI and BI and CI and DI ; -- 1,1,1,1
-- Four 0's
L04 <= not AI and not BI and not CI and not DI ; -- 0,0,0,0
-- One 1 and three 0's
L13 <= (not AI and not BI and not CI and DI) -- 0,0,0,1
or (not AI and not BI and CI and not DI) -- 0,0,1,0
or (not AI and BI and not CI and not DI) -- 0,1,0,0
or (AI and not BI and not CI and not DI) ; -- 1,0,0,0
-- Three 1's and one 0
L31 <= (AI and BI and CI and not DI) -- 1,1,1,0
or (AI and BI and not CI and DI) -- 1,1,0,1
or (AI and not BI and CI and DI) -- 1,0,1,1
or (not AI and BI and CI and DI) ; -- 0,1,1,1
-- Two 1's and two 0's
L22 <= (not AI and not BI and CI and DI) -- 0,0,1,1
or (not AI and BI and CI and not DI) -- 0,1,1,0
or (AI and BI and not CI and not DI) -- 1,1,0,0
or (AI and not BI and not CI and DI) -- 1,0,0,1
or (not AI and BI and not CI and DI) -- 0,1,0,1
or (AI and not BI and CI and not DI) ; -- 1,0,1,0
 
--
-- 3b Input Function (Reference: Figure 4)
--
-- PROCESS: FN3B; Latch 3b and K inputs
FN3B: process (SBYTECLK, FI, GI, HI, KI)
begin -- Falling edge of clock latches F,G,H,K inputs
if SBYTECLK'event and SBYTECLK = '0' then
F4 <= FI ;
G4 <= GI ;
H4 <= HI ;
K4 <= KI ;
end if;
end process FN3B;
-- PROCESS: FNS; Create and latch "S" function
FNS: process (LRESET, SBYTECLK, PDL6, L31, DI, EI, NDL6, L13)
begin
if LRESET = '1' then
S <= '0' ;
elsif SBYTECLK'event and SBYTECLK = '1' then
S <= (PDL6 and L31 and DI and not EI)
or (NDL6 and L13 and EI and not DI) ;
end if;
end process FNS ;
-- Intermediate term for "F4 is Not Equal to G4"
FNEG <= F4 xor G4 ;
--
-- Disparity Control - Figure 5
--
PD1S6 <= (not L22 and not L31 and not EI)
or (L13 and DI and EI) ;
ND1S6 <= (L31 and not DI and not EI)
or (EI and not L22 and not L13)
or K4 ;
PD0S6 <= (not L22 and not L13 and EI)
or K4 ;
ND0S6 <= (not L22 and not L31 and not EI)
or (L13 and DI and EI) ;
ND1S4 <= (F4 and G4);
ND0S4 <= (not F4 and not G4);
PD1S4 <= (not F4 and not G4)
or (FNEG and K4) ;
PD0S4 <= (F4 and G4 and H4) ;
--
-- Disparity Control - Figure 6
--
PDL6 <= (PD0S6 and not COMPLS6)
or (COMPLS6 and ND0S6)
or (not ND0S6 and not PD0S6 and LPDL4) ;
NDL6 <= not PDL6 ;
PDL4 <= (LPDL6 and not PD0S4 and not ND0S4)
or (ND0S4 and COMPLS4)
or (not COMPLS4 and PD0S4) ;
-- PROCESS: CMPLS4; Disparity determines complimenting S4
CMPLS4: process (LRESET, SBYTECLK, PDL6)
begin
if LRESET = '1' then
LPDL6 <= '0' ;
elsif SBYTECLK'event and SBYTECLK = '1' then -- Rising edge
LPDL6 <= PDL6 ; -- .. latches S4
end if;
end process CMPLS4 ;
COMPLS4 <= (PD1S4 and not LPDL6)
xor (ND1S4 and LPDL6) ;
 
-- PROCESS: CMPLS6; Disparity determines complimenting S6
CMPLS6: process (LRESET, SBYTECLK, PDL4)
begin
if LRESET = '1' then
LPDL4 <= '0' ;
elsif SBYTECLK'event and SBYTECLK = '0' then -- Falling edge
LPDL4 <= PDL4 ; -- .. latches S6
end if;
end process CMPLS6;
COMPLS6 <= (ND1S6 and LPDL4)
xor (PD1S6 and not LPDL4) ;
--
-- 5b/6b Encoder - Figure 7
--
-- Logic for non-complimented (Normal) A,B,C,D,E,I outputs
NAO <= AI ;
NBO <= L04
or (BI and not L40) ;
NCO <= CI
or L04
or (L13 and DI and EI) ;
NDO <= (DI and not L40) ;
NEO <= (EI and not (L13 and DI and EI))
or (L13 and not EI) ;
NIO <= (L22 and not EI)
or (L04 and EI)
or (L13 and not DI and EI)
or (L40 and EI)
or (L22 and KI) ;
-- PROCESS: ENC5B6B; Generate and latch LS 6 encoded bits
ENC5B6B: process (LRESET, SBYTECLK, COMPLS6, NAO, NBO, NCO, NDO, NEO, NIO)
begin
if LRESET = '1' then
AO <= '0' ;
BO <= '0' ;
CO <= '0' ;
DO <= '0' ;
EO <= '0' ;
IO <= '0' ;
elsif SBYTECLK'event and SBYTECLK = '1' then
AO <= COMPLS6 XOR NAO ; -- Least significant bit 0
BO <= COMPLS6 XOR NBO ;
CO <= COMPLS6 XOR NCO ;
DO <= COMPLS6 XOR NDO ;
EO <= COMPLS6 XOR NEO ;
IO <= COMPLS6 XOR NIO ; -- Most significant bit 6
end if;
end process ENC5B6B;
--
-- 3b/4b Encoder - Figure 8
--
-- Logic for the non-complimented F,G,H,J outputs
SINT <= (S and F4 and G4 and H4)
or (K4 and F4 and G4 and H4) ;
NFO <= (F4 and not SINT) ;
NGO <= G4
or (not F4 and not G4 and not H4) ;
NHO <= H4 ;
NJO <= SINT
or (FNEG and not H4) ;
-- PROCESS: ENC3B4B; Generate and latch MS 4 encoded bits
ENC3B4B: process (LRESET, SBYTECLK, COMPLS4, NFO, NGO, NHO, NJO)
begin
if LRESET = '1' then
FO <= '0' ;
GO <= '0' ;
HO <= '0' ;
JO <= '0' ;
elsif SBYTECLK'event and SBYTECLK ='0' then
FO <= COMPLS4 XOR NFO ; -- Least significant bit 7
GO <= COMPLS4 XOR NGO ;
HO <= COMPLS4 XOR NHO ;
JO <= COMPLS4 XOR NJO ; -- Most significant bit 10
end if;
end process ENC3B4B ;
end behavioral;
 
/trunk/8b10b_encdec_v1d0.pdf Cannot display: file marked as a binary type. svn:mime-type = application/octet-stream
/trunk/8b10b_encdec_v1d0.pdf
trunk/8b10b_encdec_v1d0.pdf Property changes : Added: svn:mime-type ## -0,0 +1 ## +application/octet-stream \ No newline at end of property Index: trunk/encdec_8b10b_TB.vhd =================================================================== --- trunk/encdec_8b10b_TB.vhd (nonexistent) +++ trunk/encdec_8b10b_TB.vhd (revision 2) @@ -0,0 +1,319 @@ +------------------------------------------------------------------------------- +-- +-- Title : Test Bench for enc_8b10b and dec_8b10b +-- Design : 8b-10b Encoder/Decoder Test Bench +-- Project : 8000 - 8b10b_encdec +-- Author : Ken Boyette +-- Company : Critia Computer, Inc. +-- +------------------------------------------------------------------------------- +-- +-- File : encdec_8b10b_TB.vhd +-- Version : 1.0 +-- Generated : 09.25.2006 +-- From : y:\Projects\8000\FPGA\VHDLSource\8b10b\8b10_enc.vhd +-- By : Active-HDL Built-in Test Bench Generator ver. 1.2s +-- +------------------------------------------------------------------------------- +-- +-- Description : Test Bench for combined enc_8b10b_tb & dec_8b10b +-- +-- +-- This testbench provides a sequence of data pattern stimuli for the +-- enc_8b10b component. It latches the encoded output and provides this +-- as input to the dec_8b10b component. The test pattern generator +-- alternately drives all data patterns and then the 12 defined K patterns. +-- +------------------------------------------------------------------------------- +-- This program is licensed under the GPL +------------------------------------------------------------------------------- + +library ieee; +use ieee.std_logic_1164.all; +use ieee.std_logic_unsigned.all; + +entity endec_8b10b_tb is +end endec_8b10b_tb; + +architecture TB_ARCHITECTURE of endec_8b10b_tb is + + component enc_8b10b + port( + RESET : in std_logic; + SBYTECLK : in std_logic; + KI : in std_logic; + AI : in std_logic; + BI : in std_logic; + CI : in std_logic; + DI : in std_logic; + EI : in std_logic; + FI : in std_logic; + GI : in std_logic; + HI : in std_logic; + AO : out std_logic; + BO : out std_logic; + CO : out std_logic; + DO : out std_logic; + EO : out std_logic; + IO : out std_logic; + FO : out std_logic; + GO : out std_logic; + HO : out std_logic; + JO : out std_logic + ); + end component; + + component dec_8b10b + port( + RESET : in std_logic; + RBYTECLK : in std_logic; + AI : in std_logic; + BI : in std_logic; + CI : in std_logic; + DI : in std_logic; + EI : in std_logic; + II : in std_logic; + FI : in std_logic; + GI : in std_logic; + HI : in std_logic; + JI : in std_logic; + AO : out std_logic; + BO : out std_logic; + CO : out std_logic; + DO : out std_logic; + EO : out std_logic; + FO : out std_logic; + GO : out std_logic; + HO : out std_logic; + KO : out std_logic + ); + end component; + + -- Special character code values + constant K28d0 : std_logic_vector := "00011100"; -- Balanced + constant K28d1 : std_logic_vector := "00111100"; -- Unbalanced comma + constant K28d2 : std_logic_vector := "01011100"; -- Unbalanced + constant K28d3 : std_logic_vector := "01111100"; -- Unbalanced + constant K28d4 : std_logic_vector := "10011100"; -- Balanced + constant K28d5 : std_logic_vector := "10111100"; -- Unbalanced comma + constant K28d6 : std_logic_vector := "11011100"; -- Unbalanced + constant K28d7 : std_logic_vector := "11111100"; -- Balanced comma + constant K23d7 : std_logic_vector := "11110111"; -- Balanced + constant K27d7 : std_logic_vector := "11111011"; -- Balanced + constant K29d7 : std_logic_vector := "11111101"; -- Balanced + constant K30d7 : std_logic_vector := "11111110"; -- Balanced + + -- Stimulus signals - mapped to the input of enc_8b10b + signal TRESET : std_logic; + signal TBYTECLK : std_logic; + signal TKO : std_logic; + signal TAO : std_logic; + signal TBO : std_logic; + signal TCO : std_logic; + signal TDO : std_logic; + signal TEO : std_logic; + signal TFO : std_logic; + signal TGO : std_logic; + signal THO : std_logic; + + -- Observed signals - mapped from output of enc_8b10b + signal TA : std_logic; + signal TB : std_logic; + signal TC : std_logic; + signal TD : std_logic; + signal TE : std_logic; + signal TF : std_logic; + signal TI : std_logic; + signal TG : std_logic; + signal TH : std_logic; + signal TJ : std_logic; + + -- Observed signals - mapped from output of dec_8b10b + signal TDA : std_logic; + signal TDB : std_logic; + signal TDC : std_logic; + signal TDD : std_logic; + signal TDE : std_logic; + signal TDF : std_logic; + signal TDG : std_logic; + signal TDH : std_logic; + signal TDK : std_logic; + + -- Signals for TestBench control functions + signal tchar : std_logic_vector (7 downto 0) ; -- All character vector + signal kcounter : std_logic_vector (3 downto 0) ; -- K character counter + signal dcounter : std_logic_vector (7 downto 0) ; -- D value counter + signal tcharout, tlcharout : std_logic_vector (9 downto 0) ; -- Character output vector + signal tclken : std_logic ; -- Enables clock after short delay starting up + signal tcnten : std_logic ; -- Enables count after 1 cycle + signal tks : std_logic ; -- Use to select control function of encoder + signal dk : std_logic ; -- '0' if D, '1' if K + signal tdec : std_logic_vector (7 downto 0) ; -- Decoder output monitor + signal tdeck : std_logic ; -- Decoder K output monitor +begin + --------------------------------------------------------------------------- + -- Instantiate modules + --------------------------------------------------------------------------- + encoder : enc_8b10b + port map ( + RESET => TRESET, + SBYTECLK => TBYTECLK, + KI => TKO, + AI => TAO, + BI => TBO, + CI => TCO, + DI => TDO, + EI => TEO, + FI => TFO, + GI => TGO, + HI => THO, + AO => TA, + BO => TB, + CO => TC, + DO => TD, + EO => TE, + IO => TI, + FO => TF, + GO => TG, + HO => TH, + JO => TJ + ); + decoder : dec_8b10b + port map ( + RESET => TRESET, + RBYTECLK => TBYTECLK, + AI => tlcharout(0), -- Note: Use the latched encoded data + BI => tlcharout(1), + CI => tlcharout(2), + DI => tlcharout(3), + EI => tlcharout(4), + II => tlcharout(5), + FI => tlcharout(6), + GI => tlcharout(7), + HI => tlcharout(8), + JI => tlcharout(9), + AO => TDA, + BO => TDB, + CO => TDC, + DO => TDD, + EO => TDE, + FO => TDF, + GO => TDG, + HO => TDH, + KO => TDK + ); + +TRESET <= '1', '0' after 200 ns ; -- Start with a valid reset for 100ns +tclken <= '0', '1' after 10 ns ; -- Start clock with valid state, then 10MHz + +process (TBYTECLK, tclken) +begin + If (tclken = '0') then + TBYTECLK <= '0'; + else TBYTECLK <= (not TBYTECLK) after 50 ns ; -- Generate 10MHz byte clock + end if; +end process ; + +process (TRESET, TBYTECLK) +begin + if (TRESET = '1') then -- Delay count 1 cycle + tcnten <= '0' ; + elsif (TBYTECLK'event and TBYTECLK = '0') then + tcnten <= '1' ; + end if ; +end process ; + +process (TRESET, TBYTECLK, tks, tcnten, kcounter, dcounter, tchar) +begin + if (TRESET = '1') then + tchar <= "00000000" ; + tks <= '1' ; -- Set for K initially + dk <= '0' ; + kcounter <= "0000" ; -- Preset K counter + dcounter <= "00000000" ; -- Preset D counter + elsif (TBYTECLK'event and TBYTECLK = '1') then + dk <= tks ; + if tks = '1' then -- Output K characters + kcounter <= kcounter + tcnten ; -- Increment counter + dcounter <= "00000000" ; + case kcounter is + when "0000" => tchar <= K28d0 ; + when "0001" => tchar <= K28d1 ; + when "0010" => tchar <= K28d2 ; + when "0011" => tchar <= K28d3 ; + when "0100" => tchar <= K28d4 ; + when "0101" => tchar <= K28d5 ; + when "0110" => tchar <= K28d6 ; + when "0111" => tchar <= K28d7 ; + when "1000" => tchar <= K23d7 ; + when "1001" => tchar <= K27d7 ; + when "1010" => tchar <= K29d7 ; + when "1011" => tchar <= K30d7 ; + tks <= '0' ; -- Switch to D output + when "1100" => tchar <= "00000000" ; + when others => tchar(7 downto 0) <= K28d5 ; + end case; + else dcounter <= dcounter + tcnten ; -- Output D values + tchar <= dcounter ; + if dcounter = "11111111" then + tks <= '1' ; -- Repeat K portion + kcounter <= "0000" ; -- Reset K counter + end if; + end if ; + end if; +end process ; + +-- Latch encoder output each rising edge for simulation and input into decoder +process (TBYTECLK) +begin + if (TBYTECLK'event and TBYTECLK = '1') then + tlcharout(0) <= TA; + tlcharout(1) <= TB; + tlcharout(2) <= TC; + tlcharout(3) <= TD; + tlcharout(4) <= TE; + tlcharout(5) <= TI; + tlcharout(6) <= TF; + tlcharout(7) <= TG; + tlcharout(8) <= TH; + tlcharout(9) <= TJ; + end if; +end process ; + +-- Connect our test values to the encoder inputs +TAO <= tchar(0); +TBO <= tchar(1); +TCO <= tchar(2); +TDO <= tchar(3); +TEO <= tchar(4); +TFO <= tchar(5); +TGO <= tchar(6); +THO <= tchar(7); +TKO <= dk; + +-- Monitor encoder output +tcharout(0) <= TA; +tcharout(1) <= TB; +tcharout(2) <= TC; +tcharout(3) <= TD; +tcharout(4) <= TE; +tcharout(5) <= TI; +tcharout(6) <= TF; +tcharout(7) <= TG; +tcharout(8) <= TH; +tcharout(9) <= TJ; + +-- Monitor decoder output +tdec(0) <= TDA; +tdec(1) <= TDB; +tdec(2) <= TDC; +tdec(3) <= TDD; +tdec(4) <= TDE; +tdec(5) <= TDF; +tdec(6) <= TDG; +tdec(7) <= TDH; +tdeck <= TDK; + +end TB_ARCHITECTURE; + + Index: trunk/8b10_dec.vhd =================================================================== --- trunk/8b10_dec.vhd (nonexistent) +++ trunk/8b10_dec.vhd (revision 2) @@ -0,0 +1,224 @@ +------------------------------------------------------------------------------- +-- +-- Title : 8b/10b Decoder +-- Design : 10-bit to 8-bit Decoder +-- Project : 8000 - 8b10b_encdec +-- Author : Ken Boyette +-- Company : Critia Computer, Inc. +-- +------------------------------------------------------------------------------- +-- +-- File : 8b10b_dec.vhd +-- Version : 1.0 +-- Generated : 09.27.2006 +-- By : Itf2Vhdl ver. 1.20 +-- +------------------------------------------------------------------------------- +-- +-- Description : +-- This module provides 10-bit to 9-bit encoding. +-- It accepts 10-bit encoded parallel data input and generates 8-bit decoded +-- data output in accordance with the 8b/10b standard method. This method was +-- described in the 1983 IBM publication "A DC-Balanced, Partitioned-Block, +-- 8B/10B Transmission Code" by A.X. Widmer and P.A. Franaszek. The method +-- WAS granted a U.S. Patent #4,486,739 in 1984; now expired. +-- +-- The parallel 10-bit Binary input represent 1024 possible values, called +-- characters - only 268 of which are valid. +-- +-- The input is a 10-bit encoded character whose bits are identified as: +-- AI, BI, CI, DI, EI, II, FI, GI, HI, JI (Least Significant to Most) +-- +-- In addition to 256 data output characters, there are 12 special control +-- or K, characters defined for command and synchronization use. +-- +-- The eight data output bits are identified as: +-- HI, GI, FI, EI, DI, CI, BI, AI (Most Significant to Least) +-- +-- The output, KO, is used to indicate the output value is one of the +-- control characters. +-- +-- All inputs and outputs are synchronous with an externally supplied +-- byte rate clock BYTECLK. +-- The encoded output is valid one clock after the input. +-- There is a reset input, RESET, to reset the logic. The next rising +-- BYTECLK after RESET is deasserted latches valid input data. +-- +-- Note: This VHDL structure closely follows the discrete logic defined +-- in the original article and the subsequent patent. The Figures +-- referenced are those in the patent. +------------------------------------------------------------------------------- +-- This program is licensed under the GPL +------------------------------------------------------------------------------- + +library IEEE; +use IEEE.STD_LOGIC_1164.all; + +entity dec_8b10b is + port( + RESET : in std_logic ; -- Global asynchronous reset (AH) + RBYTECLK : in std_logic ; -- Master synchronous receive byte clock + AI, BI, CI, DI, EI, II : in std_logic ; + FI, GI, HI, JI : in std_logic ; -- Encoded input (LS..MS) + KO : out std_logic ; -- Control (K) character indicator (AH) + HO, GO, FO, EO, DO, CO, BO, AO : out std_logic -- Decoded out (MS..LS) + ); +end dec_8b10b; + +architecture behavioral of dec_8b10b is + +-- Signals to tie things together + signal ANEB, CNED, EEI, P13, P22, P31 : std_logic ; -- Figure 10 Signals + signal IKA, IKB, IKC : std_logic ; -- Figure 11 Signals + signal XA, XB, XC, XD, XE : std_logic ; -- Figure 12 Signals + signal OR121, OR122, OR123, OR124, OR125, OR126, OR127 : std_logic ; + signal XF, XG, XH : std_logic ; -- Figure 13 Signals + signal OR131, OR132, OR133, OR134, IOR134 : std_logic ; + +begin + + -- + -- 6b Input Function (Reference: Figure 10) + -- + + -- One 1 and three 0's + P13 <= (ANEB and (not CI and not DI)) + or (CNED and (not AI and not BI)) ; + -- Three 1's and one 0 + P31 <= (ANEB and CI and DI) + or (CNED and AI and BI) ; + -- Two 1's and two 0's + P22 <= (AI and BI and (not CI and not DI)) + or (CI and DI and (not AI and not BI)) + or (ANEB and CNED) ; + + -- Intermediate term for "AI is Not Equal to BI" + ANEB <= AI xor BI ; + + -- Intermediate term for "CI is Not Equal to DI" + CNED <= CI xor DI ; + + -- Intermediate term for "E is Equal to I" + EEI <= EI xnor II ; + + -- + -- K Decoder - Figure 11 + -- + + -- Intermediate terms + IKA <= (CI and DI and EI and II) + or (not CI and not DI and not EI and not II) ; + IKB <= P13 and (not EI and II and GI and HI and JI) ; + IKC <= P31 and (EI and not II and not GI and not HI and not JI) ; + + -- PROCESS: KFN; Determine K output + KFN: process (RESET, RBYTECLK, IKA, IKB, IKC) + begin + if RESET = '1' then + KO <= '0'; + elsif RBYTECLK'event and RBYTECLK = '0' then + KO <= IKA or IKB or IKC; + end if; + end process KFN; + + -- + -- 5b Decoder Figure 12 + -- + + -- Logic to determine complimenting A,B,C,D,E,I inputs + OR121 <= (P22 and (not AI and not CI and EEI)) + or (P13 and not EI) ; + OR122 <= (AI and BI and EI and II) + or (not CI and not DI and not EI and not II) + or (P31 and II) ; + OR123 <= (P31 and II) + or (P22 and BI and CI and EEI) + or (P13 and DI and EI and II) ; + OR124 <= (P22 and AI and CI and EEI) + or (P13 and not EI) ; + OR125 <= (P13 and not EI) + or (not CI and not DI and not EI and not II) + or (not AI and not BI and not EI and not II) ; + OR126 <= (P22 and not AI and not CI and EEI) + or (P13 and not II) ; + OR127 <= (P13 and DI and EI and II) + or (P22 and not BI and not CI and EEI) ; + + XA <= OR127 + or OR121 + or OR122 ; + XB <= OR122 + or OR123 + or OR124 ; + XC <= OR121 + or OR123 + or OR125 ; + XD <= OR122 + or OR124 + or OR127 ; + XE <= OR125 + or OR126 + or OR127 ; + + -- PROCESS: DEC5B; Generate and latch LS 5 decoded bits + DEC5B: process (RESET, RBYTECLK, XA, XB, XC, XD, XE, AI, BI, CI, DI, EI) + begin + if RESET = '1' then + AO <= '0' ; + BO <= '0' ; + CO <= '0' ; + DO <= '0' ; + EO <= '0' ; + elsif RBYTECLK'event and RBYTECLK = '0' then + AO <= XA XOR AI ; -- Least significant bit 0 + BO <= XB XOR BI ; + CO <= XC XOR CI ; + DO <= XD XOR DI ; + EO <= XE XOR EI ; -- Most significant bit 6 + end if; + end process DEC5B; + + -- + -- 3b Decoder - Figure 13 + -- + + -- Logic for complimenting F,G,H outputs + OR131 <= (GI and HI and JI) + or (FI and HI and JI) + or (IOR134); + OR132 <= (FI and GI and JI) + or (not FI and not GI and not HI) + or (not FI and not GI and HI and JI); + OR133 <= (not FI and not HI and not JI) + or (IOR134) + or (not GI and not HI and not JI) ; + OR134 <= (not GI and not HI and not JI) + or (FI and HI and JI) + or (IOR134) ; + IOR134 <= (not (HI and JI)) + and (not (not HI and not JI)) + and (not CI and not DI and not EI and not II) ; + + XF <= OR131 + or OR132 ; + XG <= OR132 + or OR133 ; + XH <= OR132 + or OR134 ; + + -- PROCESS: DEC3B; Generate and latch MS 3 decoded bits + DEC3B: process (RESET, RBYTECLK, XF, XG, XH, FI, GI, HI) + begin + if RESET = '1' then + FO <= '0' ; + GO <= '0' ; + HO <= '0' ; + elsif RBYTECLK'event and RBYTECLK ='0' then + FO <= XF XOR FI ; -- Least significant bit 7 + GO <= XG XOR GI ; + HO <= XH XOR HI ; -- Most significant bit 10 + end if; + end process DEC3B ; + +end behavioral; + Index: trunk/enc_8b10b_TB.vhd =================================================================== --- trunk/enc_8b10b_TB.vhd (nonexistent) +++ trunk/enc_8b10b_TB.vhd (revision 2) @@ -0,0 +1,244 @@ +------------------------------------------------------------------------------- +-- +-- Title : Test Bench for enc_8b10b +-- Design : 8b/10b Encoder Test Bench +-- Project : 8000 - 8b10b_encdec +-- Author : Ken Boyette +-- Company : Critia Computer, Inc. +-- +------------------------------------------------------------------------------- +-- +-- File : enc_8b10b_TB.vhd +-- Version : 1.0 +-- Generated : 09.25.2006 +-- From : y:\Projects\8000\FPGA\VHDLSource\8b10b\8b10_enc.vhd +-- By : Active-HDL Built-in Test Bench Generator ver. 1.2s +-- +------------------------------------------------------------------------------- +-- +-- Description : Test Bench for enc_8b10b_tb +-- +-- This testbench provides a sequence of data pattern stimuli for the +-- enc_8b10b component. It latches the encoded output and provides this +-- for waveform display during simulation. The test pattern generator +-- alternately drives all data patterns and then the 12 defined K patterns. +------------------------------------------------------------------------------- +-- This program is licensed under the GPL +------------------------------------------------------------------------------- + +library ieee; +use ieee.std_logic_1164.all; +use ieee.std_logic_unsigned.all; + +entity enc_8b10b_tb is +end enc_8b10b_tb; + +architecture TB_ARCHITECTURE of enc_8b10b_tb is + + component enc_8b10b + port( + RESET : in std_logic; + SBYTECLK : in std_logic; + KI : in std_logic; + AI : in std_logic; + BI : in std_logic; + CI : in std_logic; + DI : in std_logic; + EI : in std_logic; + FI : in std_logic; + GI : in std_logic; + HI : in std_logic; + AO : out std_logic; + BO : out std_logic; + CO : out std_logic; + DO : out std_logic; + EO : out std_logic; + FO : out std_logic; + IO : out std_logic; + GO : out std_logic; + HO : out std_logic; + JO : out std_logic + ); + end component; + + -- Special character code values + constant K28d0 : std_logic_vector := "00011100"; -- Balanced + constant K28d1 : std_logic_vector := "00111100"; -- Unbalanced comma + constant K28d2 : std_logic_vector := "01011100"; -- Unbalanced + constant K28d3 : std_logic_vector := "01111100"; -- Unbalanced + constant K28d4 : std_logic_vector := "10011100"; -- Balanced + constant K28d5 : std_logic_vector := "10111100"; -- Unbalanced comma + constant K28d6 : std_logic_vector := "11011100"; -- Unbalanced + constant K28d7 : std_logic_vector := "11111100"; -- Balanced comma + constant K23d7 : std_logic_vector := "11110111"; -- Balanced + constant K27d7 : std_logic_vector := "11111011"; -- Balanced + constant K29d7 : std_logic_vector := "11111101"; -- Balanced + constant K30d7 : std_logic_vector := "11111110"; -- Balanced + + -- Stimulus signals - mapped to the input of enc_8b10b + signal TRESET : std_logic; + signal TBYTECLK : std_logic; + signal TKO : std_logic; + signal TAO : std_logic; + signal TBO : std_logic; + signal TCO : std_logic; + signal TDO : std_logic; + signal TEO : std_logic; + signal TFO : std_logic; + signal TGO : std_logic; + signal THO : std_logic; + + -- Observed signals - mapped from output of enc_8b10b + signal TA : std_logic; + signal TB : std_logic; + signal TC : std_logic; + signal TD : std_logic; + signal TE : std_logic; + signal TF : std_logic; + signal TI : std_logic; + signal TG : std_logic; + signal TH : std_logic; + signal TJ : std_logic; + + -- Signals for TestBench control functions + signal tchar : std_logic_vector (7 downto 0) ; -- All character vector + signal kcounter : std_logic_vector (3 downto 0) ; -- K character counter + signal dcounter : std_logic_vector (7 downto 0) ; -- D value counter + signal tcharout, tlcharout : std_logic_vector (9 downto 0) ; -- Character output vector + signal tclken : std_logic ; -- Enables clock after short delay starting up + signal tcnten : std_logic ; -- Enables count after 1 cycle + signal tks : std_logic ; -- Use to select control function of encoder + signal dk : std_logic ; -- '0' if D, '1' if K + +begin + --------------------------------------------------------------------------- + -- Instantiate module + --------------------------------------------------------------------------- + encoder : enc_8b10b + port map ( + RESET => TRESET, + SBYTECLK => TBYTECLK, + KI => TKO, + AI => TAO, + BI => TBO, + CI => TCO, + DI => TDO, + EI => TEO, + FI => TFO, + GI => TGO, + HI => THO, + AO => TA, + BO => TB, + CO => TC, + DO => TD, + EO => TE, + IO => TI, + FO => TF, + GO => TG, + HO => TH, + JO => TJ + ) ; + +TRESET <= '1', '0' after 200 ns ; -- Start with a valid reset for 100ns +tclken <= '0', '1' after 10 ns ; -- Start clock with valid state, then 10MHz + +process (TBYTECLK, tclken) +begin + If (tclken = '0') then + TBYTECLK <= '0'; + else TBYTECLK <= (not TBYTECLK) after 50 ns ; -- Generate 10MHz byte clock + end if; +end process ; + +process (TRESET, TBYTECLK) +begin + if (TRESET = '1') then -- Delay count 1 cycle + tcnten <= '0' ; + elsif (TBYTECLK'event and TBYTECLK = '0') then + tcnten <= '1' ; + end if ; +end process ; + +process (TRESET, TBYTECLK, tks, tcnten, kcounter, dcounter, tchar) +begin + if (TRESET = '1') then + tchar <= "00000000" ; + tks <= '1' ; -- Set for K initially + dk <= '0' ; + kcounter <= "0000" ; -- Preset K counter + dcounter <= "00000000" ; -- Preset D counter + elsif (TBYTECLK'event and TBYTECLK = '1') then + dk <= tks ; + if tks = '1' then -- Output K characters + kcounter <= kcounter + tcnten ; -- Increment counter + dcounter <= "00000000" ; + case kcounter is + when "0000" => tchar <= K28d0 ; + when "0001" => tchar <= K28d1 ; + when "0010" => tchar <= K28d2 ; + when "0011" => tchar <= K28d3 ; + when "0100" => tchar <= K28d4 ; + when "0101" => tchar <= K28d5 ; + when "0110" => tchar <= K28d6 ; + when "0111" => tchar <= K28d7 ; + when "1000" => tchar <= K23d7 ; + when "1001" => tchar <= K27d7 ; + when "1010" => tchar <= K29d7 ; + when "1011" => tchar <= K30d7 ; + tks <= '0' ; -- Switch to D output + when "1100" => tchar <= "00000000" ; + when others => tchar(7 downto 0) <= K28d5 ; + end case; + else dcounter <= dcounter + tcnten ; -- Output D values + tchar <= dcounter ; + if dcounter = "11111111" then + tks <= '1' ; -- Repeat K portion + kcounter <= "0000" ; -- Reset K counter + end if; + end if ; + end if; +end process ; + +-- Latch encoder output each rising edge for simulation display +process (TBYTECLK) +begin + if (TBYTECLK'event and TBYTECLK = '1') then + tlcharout(0) <= TA; + tlcharout(1) <= TB; + tlcharout(2) <= TC; + tlcharout(3) <= TD; + tlcharout(4) <= TE; + tlcharout(5) <= TI; + tlcharout(6) <= TF; + tlcharout(7) <= TG; + tlcharout(8) <= TH; + tlcharout(9) <= TJ; + end if; +end process ; + +-- Connect our test values to the encoder inputs +TAO <= tchar(0); +TBO <= tchar(1); +TCO <= tchar(2); +TDO <= tchar(3); +TEO <= tchar(4); +TFO <= tchar(5); +TGO <= tchar(6); +THO <= tchar(7); +TKO <= dk; + +-- Monitor encoder output +tcharout(0) <= TA; +tcharout(1) <= TB; +tcharout(2) <= TC; +tcharout(3) <= TD; +tcharout(4) <= TE; +tcharout(5) <= TI; +tcharout(6) <= TF; +tcharout(7) <= TG; +tcharout(8) <= TH; +tcharout(9) <= TJ; + +end TB_ARCHITECTURE; + +

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