OpenCores
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/trunk/rtl/vhdl/bootrom.vhd File deleted
/trunk/rtl/vhdl/miniuart_tb.vhd File deleted
/trunk/rtl/vhdl/sbug_rom.vhd File deleted
/trunk/rtl/vhdl/trap.vhd File deleted
/trunk/rtl/vhdl/rxunit3.vhd File deleted \ No newline at end of file
/trunk/rtl/vhdl/keyboard.vhd File deleted
/trunk/rtl/vhdl/testbench5.vhd File deleted
/trunk/rtl/vhdl/testbench6.vhd File deleted
/trunk/rtl/vhdl/ram2k.vhd File deleted
/trunk/rtl/vhdl/txunit3.vhd File deleted \ No newline at end of file
/trunk/rtl/vhdl/vdu8.vhd File deleted \ No newline at end of file
/trunk/rtl/vhdl/miniUART3.vhd File deleted
/trunk/rtl/vhdl/blockram.vhd File deleted
/trunk/rtl/vhdl/ps2_keyboard.vhd File deleted
/trunk/rtl/vhdl/charrom.vhd File deleted
/trunk/rtl/vhdl/cpu09.vhd
36,52 → 36,6
-- Initial release to Open Cores
-- reversed clock edge
--
-- Version 1.1 - 29 November 2003 John kent
-- ACCA and ACCB indexed offsets are 2's complement.
-- ALU Right Mux now sign extends ACCA & ACCB offsets
-- Absolute Indirect addressing performed a read on the
-- second byte of the address rather than a fetch
-- so it formed an incorrect address. Now fixed.
--
-- Version 1.2 - 29 November 2003 John Kent
-- LEAX and LEAY affect the Z bit only
-- LEAS and LEAU do not affect any condition codes
-- added an extra ALU control for LEA.
--
-- Version 1.3 - 12 December 2003 John Kent
-- CWAI did not work, was missed a PUSH_ST on calling
-- the ANDCC_STATE. Thanks go to Ghassan Kraidy for
-- finding this fault.
--
-- Version 1.4 - 12 December 2003 John Kent
-- Missing cc_ctrl assignment in otherwise case of
-- lea_state resulted in cc_ctrl being latched in
-- that state.
-- The otherwise statement should never be reached,
-- and has been fixed simply to resolve synthesis warnings.
--
-- Version 1.5 - 17 january 2004 John kent
-- The clear instruction used "alu_ld8" to control the ALU
-- rather than "alu_clr". This mean the Carry was not being
-- cleared correctly.
--
-- Version 1.6 - 24 January 2004 John Kent
-- Fixed problems in PSHU instruction
--
-- Version 1.7 - 25 January 2004 John Kent
-- removed redundant "alu_inx" and "alu_dex'
-- Removed "test_alu" and "test_cc"
-- STD instruction did not set condition codes
-- JMP direct was not decoded properly
-- CLR direct performed an unwanted read cycle
-- Bogus "latch_md" in Page2 indexed addressing
--
-- Version 1.8 - 27 January 2004 John Kent
-- CWAI in decode1_state should increment the PC.
-- ABX is supposed to be an unsigned addition.
-- Added extra ALU function
-- ASR8 slightly changed in the ALU.
--
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
99,7 → 53,9
hold: in std_logic;
irq: in std_logic;
firq: in std_logic;
nmi: in std_logic
nmi: in std_logic;
test_alu: out std_logic_vector(15 downto 0);
test_cc: out std_logic_vector(7 downto 0)
);
end;
 
252,12 → 208,13
type alu_type is (alu_add8, alu_sub8, alu_add16, alu_sub16, alu_adc, alu_sbc,
alu_and, alu_ora, alu_eor,
alu_tst, alu_inc, alu_dec, alu_clr, alu_neg, alu_com,
alu_inx, alu_dex,
alu_lsr16, alu_lsl16,
alu_ror8, alu_rol8,
alu_asr8, alu_asl8, alu_lsr8,
alu_andcc, alu_orcc, alu_sex, alu_tfr, alu_abx,
alu_andcc, alu_orcc, alu_sex, alu_tfr,
alu_seif, alu_sei, alu_see, alu_cle,
alu_ld8, alu_st8, alu_ld16, alu_st16, alu_lea, alu_nop, alu_daa );
alu_ld8, alu_st8, alu_ld16, alu_st16, alu_nop, alu_daa );
 
signal op_code: std_logic_vector(7 downto 0);
signal pre_code: std_logic_vector(7 downto 0);
986,17 → 943,9
when two_right =>
right <= "0000000000000010";
when acca_right =>
if acca(7) = '0' then
right <= "00000000" & acca(7 downto 0);
else
right <= "11111111" & acca(7 downto 0);
end if;
right <= "00000000" & acca;
when accb_right =>
if accb(7) = '0' then
right <= "00000000" & accb(7 downto 0);
else
right <= "11111111" & accb(7 downto 0);
end if;
right <= "00000000" & accb;
when accd_right =>
right <= acca & accb;
when md_sign5_right =>
1033,8 → 982,6
when alu_adc | alu_sbc |
alu_rol8 | alu_ror8 =>
carry_in := cc(CBIT);
when alu_asr8 =>
carry_in := left(7);
when others =>
carry_in := '0';
end case;
1078,13 → 1025,13
 
case alu_ctrl is
when alu_add8 | alu_inc |
alu_add16 | alu_adc =>
alu_add16 | alu_inx |
alu_adc =>
out_alu <= left + right + ("000000000000000" & carry_in);
when alu_sub8 | alu_dec |
alu_sub16 | alu_sbc =>
alu_sub16 | alu_dex |
alu_sbc =>
out_alu <= left - right - ("000000000000000" & carry_in);
when alu_abx =>
out_alu <= left + ("00000000" & right(7 downto 0)) ;
when alu_and =>
out_alu <= left and right; -- and/bit
when alu_ora =>
1095,15 → 1042,17
out_alu <= left(14 downto 0) & carry_in; -- rol8/asl8/lsl16
when alu_lsr16 | alu_lsr8 =>
out_alu <= carry_in & left(15 downto 1); -- lsr
when alu_ror8 | alu_asr8 =>
out_alu <= "00000000" & carry_in & left(7 downto 1); -- ror8/asr8
when alu_ror8 =>
out_alu <= "00000000" & carry_in & left(7 downto 1); -- ror
when alu_asr8 =>
out_alu <= "00000000" & left(7) & left(7 downto 1); -- asr
when alu_neg =>
out_alu <= right - left; -- neg (right=0)
when alu_com =>
out_alu <= not left;
when alu_clr | alu_ld8 | alu_ld16 | alu_lea =>
when alu_clr | alu_ld8 | alu_ld16 =>
out_alu <= right; -- clr, ld
when alu_st8 | alu_st16 | alu_andcc | alu_orcc | alu_tfr =>
when alu_st8 | alu_st16 | alu_andcc | alu_orcc =>
out_alu <= left;
when alu_daa =>
out_alu <= left + ("00000000" & daa_reg);
1114,7 → 1063,7
out_alu <= "11111111" & left(7 downto 0);
end if;
when others =>
out_alu <= left; -- nop
out_alu <= left; -- nop, tfr
end case;
 
--
1158,6 → 1107,8
cc_out(CBIT) <= left(CBIT) and cc(CBIT);
when alu_orcc =>
cc_out(CBIT) <= left(CBIT) or cc(CBIT);
when alu_tfr =>
cc_out(CBIT) <= left(CBIT);
when others =>
cc_out(CBIT) <= cc(CBIT);
end case;
1176,7 → 1127,8
out_alu(3) or out_alu(2) or out_alu(1) or out_alu(0) );
when alu_add16 | alu_sub16 |
alu_lsl16 | alu_lsr16 |
alu_ld16 | alu_st16 | alu_lea =>
alu_inx | alu_dex |
alu_ld16 | alu_st16 =>
cc_out(ZBIT) <= not( out_alu(15) or out_alu(14) or out_alu(13) or out_alu(12) or
out_alu(11) or out_alu(10) or out_alu(9) or out_alu(8) or
out_alu(7) or out_alu(6) or out_alu(5) or out_alu(4) or
1185,6 → 1137,8
cc_out(ZBIT) <= left(ZBIT) and cc(ZBIT);
when alu_orcc =>
cc_out(ZBIT) <= left(ZBIT) or cc(ZBIT);
when alu_tfr =>
cc_out(ZBIT) <= left(ZBIT);
when others =>
cc_out(ZBIT) <= cc(ZBIT);
end case;
1208,6 → 1162,8
cc_out(NBIT) <= left(NBIT) and cc(NBIT);
when alu_orcc =>
cc_out(NBIT) <= left(NBIT) or cc(NBIT);
when alu_tfr =>
cc_out(NBIT) <= left(NBIT);
when others =>
cc_out(NBIT) <= cc(NBIT);
end case;
1222,6 → 1178,8
cc_out(IBIT) <= left(IBIT) or cc(IBIT);
when alu_seif | alu_sei =>
cc_out(IBIT) <= '1';
when alu_tfr =>
cc_out(IBIT) <= left(IBIT);
when others =>
cc_out(IBIT) <= cc(IBIT); -- interrupt mask
end case;
1238,6 → 1196,8
cc_out(HBIT) <= left(HBIT) and cc(HBIT);
when alu_orcc =>
cc_out(HBIT) <= left(HBIT) or cc(HBIT);
when alu_tfr =>
cc_out(HBIT) <= left(HBIT);
when others =>
cc_out(HBIT) <= cc(HBIT);
end case;
1281,6 → 1241,8
cc_out(VBIT) <= left(VBIT) and cc(VBIT);
when alu_orcc =>
cc_out(VBIT) <= left(VBIT) or cc(VBIT);
when alu_tfr =>
cc_out(VBIT) <= left(VBIT);
when others =>
cc_out(VBIT) <= cc(VBIT);
end case;
1290,6 → 1252,8
cc_out(FBIT) <= left(FBIT) and cc(FBIT);
when alu_orcc =>
cc_out(FBIT) <= left(FBIT) or cc(FBIT);
when alu_tfr =>
cc_out(FBIT) <= left(FBIT);
when alu_seif =>
cc_out(FBIT) <= '1';
when others =>
1301,6 → 1265,8
cc_out(EBIT) <= left(EBIT) and cc(EBIT);
when alu_orcc =>
cc_out(EBIT) <= left(EBIT) or cc(EBIT);
when alu_tfr =>
cc_out(EBIT) <= left(EBIT);
when alu_see =>
cc_out(EBIT) <= '1';
when alu_cle =>
1308,6 → 1274,9
when others =>
cc_out(EBIT) <= cc(EBIT);
end case;
 
test_alu <= out_alu;
test_cc <= cc_out;
end process;
 
------------------------------------
1850,7 → 1819,7
left_ctrl <= accd_left;
right_ctrl <= md_right;
alu_ctrl <= alu_st16;
cc_ctrl <= load_cc;
cc_ctrl <= latch_cc;
acca_ctrl <= latch_acca;
accb_ctrl <= latch_accb;
ix_ctrl <= latch_ix;
2000,7 → 1969,7
-- 6809 => 6 cycles
-- cpu09 => 5 cycles
-- 1 op=(pc) / pc=pc+1
-- 2 ea_hi=dp / ea_lo=(pc) / pc=pc+1
-- 2 ea_hi=0 / ea_lo=(pc) / pc=pc+1
-- 3 md_lo=(ea) / pc=pc
-- 4 alu_left=md / md=alu_out / pc=pc
-- 5 (ea)=md_lo / pc=pc
2009,7 → 1978,7
-- 6809 => 3 cycles
-- cpu09 => 3 cycles
-- 1 op=(pc) / pc=pc+1
-- 2 ea_hi=dp / ea_lo=(pc) / pc=pc+1
-- 2 ea_hi=0 / ea_lo=(pc) / pc=pc+1
-- 3 pc=ea
--
when "0000" =>
2031,14 → 2000,7
--
st_ctrl <= idle_st;
return_state <= fetch_state;
case op_code(3 downto 0) is
when "1110" => -- jmp
next_state <= jmp_state;
when "1111" => -- clr
next_state <= single_op_exec_state;
when others =>
next_state <= single_op_read_state;
end case;
next_state <= single_op_read_state;
 
-- acca / accb inherent instructions
when "0001" =>
2512,9 → 2474,7
next_state <= pull_return_hi_state;
 
--
-- add accb to index register
-- *** Note: this is an unsigned addition.
-- does not affect any condition codes
-- abx - add accb to index register
-- 6809 => 3 cycles
-- cpu09 => 2 cycles
-- 1 op=(pc) / pc=pc+1
2523,7 → 2483,7
when "1010" => -- abx
left_ctrl <= ix_left;
right_ctrl <= accb_right;
alu_ctrl <= alu_abx;
alu_ctrl <= alu_add16;
cc_ctrl <= latch_cc;
ix_ctrl <= load_ix;
--
2555,7 → 2515,7
return_state <= fetch_state;
next_state <= rti_cc_state;
 
when "1100" => -- cwai #$<cc_mask>
when "1100" => -- cwai
-- pre decrement sp
left_ctrl <= sp_left;
right_ctrl <= one_right;
2563,13 → 2523,13
cc_ctrl <= latch_cc;
sp_ctrl <= load_sp;
--
pc_ctrl <= incr_pc;
pc_ctrl <= latch_pc;
ix_ctrl <= latch_ix;
iy_ctrl <= latch_iy;
up_ctrl <= latch_up;
iv_ctrl <= latch_iv;
--
st_ctrl <= push_st;
st_ctrl <= idle_st;
return_state <= int_entire_state; -- set entire flag
next_state <= andcc_state;
 
2705,7 → 2665,7
alu_ctrl <= alu_st8;
acca_ctrl <= latch_acca;
cc_ctrl <= load_cc;
when "1110" => -- jmp (not defined)
when "1110" => -- jmp
right_ctrl <= zero_right;
alu_ctrl <= alu_nop;
acca_ctrl <= latch_acca;
2712,7 → 2672,7
cc_ctrl <= latch_cc;
when "1111" => -- clr
right_ctrl <= zero_right;
alu_ctrl <= alu_clr;
alu_ctrl <= alu_ld8;
acca_ctrl <= load_acca;
cc_ctrl <= load_cc;
when others =>
2800,7 → 2760,7
alu_ctrl <= alu_st8;
accb_ctrl <= latch_accb;
cc_ctrl <= load_cc;
when "1110" => -- jmp (undefined)
when "1110" => -- jmp
right_ctrl <= zero_right;
alu_ctrl <= alu_nop;
accb_ctrl <= latch_accb;
2807,7 → 2767,7
cc_ctrl <= latch_cc;
when "1111" => -- clr
right_ctrl <= zero_right;
alu_ctrl <= alu_clr;
alu_ctrl <= alu_ld8;
accb_ctrl <= load_accb;
cc_ctrl <= load_cc;
when others =>
3505,7 → 3465,7
next_state <= dual_op_read16_state;
 
when "1111" => -- sty <
st_ctrl <= idle_st;
st_ctrl <= push_st;
return_state <= fetch_state;
next_state <= dual_op_write16_state;
 
3639,7 → 3599,7
next_state <= dual_op_read16_state;
 
when "1111" => -- sts <
st_ctrl <= idle_st;
st_ctrl <= push_st;
return_state <= fetch_state;
next_state <= dual_op_write16_state;
 
3657,6 → 3617,7
iy_ctrl <= latch_iy;
up_ctrl <= latch_up;
sp_ctrl <= latch_sp;
md_ctrl <= latch_md;
iv_ctrl <= latch_iv;
-- idle the alu
left_ctrl <= pc_left;
4081,7 → 4042,7
when "1111" => -- clr
left_ctrl <= md_left;
right_ctrl <= zero_right;
alu_ctrl <= alu_clr;
alu_ctrl <= alu_ld8;
cc_ctrl <= load_cc;
md_ctrl <= load_md;
pc_ctrl <= latch_pc;
4389,7 → 4350,7
next_state <= saved_state;
 
--
-- md & ea holds 8 bit index offset
-- ea holds 8 bit index offet
-- calculate the effective memory address
-- using the alu
--
5264,37 → 5225,6
next_state <= indirect_state;
end if;
 
-- indexed to address
-- pick up the low byte of the address
-- advance the pc
when indexaddr_state =>
acca_ctrl <= latch_acca;
accb_ctrl <= latch_accb;
cc_ctrl <= latch_cc;
dp_ctrl <= latch_dp;
ix_ctrl <= latch_ix;
iy_ctrl <= latch_iy;
up_ctrl <= latch_up;
sp_ctrl <= latch_sp;
iv_ctrl <= latch_iv;
op_ctrl <= latch_op;
pre_ctrl <= latch_pre;
nmi_ctrl <= latch_nmi;
-- advance pc
left_ctrl <= pc_left;
right_ctrl <= zero_right;
alu_ctrl <= alu_nop;
pc_ctrl <= incr_pc;
-- fetch low byte
ea_ctrl <= latch_ea;
md_ctrl <= fetch_next_md;
addr_ctrl <= fetch_ad;
dout_ctrl <= md_lo_dout;
--
st_ctrl <= idle_st;
return_state <= fetch_state;
next_state <= indexaddr2_state;
 
-- indexed to absolute address
-- md holds address
-- ea hold indexing mode byte
5332,6 → 5262,36
next_state <= indirect_state;
end if;
 
-- indexed to address
-- pick up the low byte of the address
-- advance the pc
when indexaddr_state =>
acca_ctrl <= latch_acca;
accb_ctrl <= latch_accb;
cc_ctrl <= latch_cc;
dp_ctrl <= latch_dp;
ix_ctrl <= latch_ix;
iy_ctrl <= latch_iy;
up_ctrl <= latch_up;
sp_ctrl <= latch_sp;
iv_ctrl <= latch_iv;
op_ctrl <= latch_op;
pre_ctrl <= latch_pre;
nmi_ctrl <= latch_nmi;
ea_ctrl <= latch_ea;
-- advance pc
left_ctrl <= pc_left;
right_ctrl <= zero_right;
alu_ctrl <= alu_nop;
pc_ctrl <= incr_pc;
-- fetch low byte
md_ctrl <= fetch_next_md;
addr_ctrl <= read_ad;
dout_ctrl <= md_lo_dout;
--
st_ctrl <= idle_st;
return_state <= fetch_state;
next_state <= indexaddr2_state;
--
-- load md with high byte of indirect address
-- pointed to by ea
5464,6 → 5424,7
 
when lea_state => -- here on load effective address
op_ctrl <= latch_op;
cc_ctrl <= latch_cc;
acca_ctrl <= latch_acca;
accb_ctrl <= latch_accb;
dp_ctrl <= latch_dp;
5476,34 → 5437,29
-- load index register with effective address
left_ctrl <= pc_left;
right_ctrl <= ea_right;
alu_ctrl <= alu_lea;
alu_ctrl <= alu_ld16;
case op_code(3 downto 0) is
when "0000" => -- leax
cc_ctrl <= load_cc;
ix_ctrl <= load_ix;
iy_ctrl <= latch_iy;
up_ctrl <= latch_up;
sp_ctrl <= latch_sp;
when "0001" => -- leay
cc_ctrl <= load_cc;
ix_ctrl <= latch_ix;
iy_ctrl <= load_iy;
up_ctrl <= latch_up;
sp_ctrl <= latch_sp;
when "0010" => -- leas
cc_ctrl <= latch_cc;
ix_ctrl <= latch_ix;
iy_ctrl <= latch_iy;
up_ctrl <= latch_up;
sp_ctrl <= load_sp;
when "0011" => -- leau
cc_ctrl <= latch_cc;
ix_ctrl <= latch_ix;
iy_ctrl <= latch_iy;
up_ctrl <= load_up;
sp_ctrl <= latch_sp;
when others =>
cc_ctrl <= latch_cc;
ix_ctrl <= latch_ix;
iy_ctrl <= latch_iy;
up_ctrl <= latch_up;
7600,8 → 7556,8
pre_ctrl <= latch_pre;
nmi_ctrl <= latch_nmi;
ea_ctrl <= latch_ea;
-- decrement up if any registers to be pushed
left_ctrl <= up_left;
-- decrement sp if any registers to be pushed
left_ctrl <= sp_left;
right_ctrl <= one_right;
alu_ctrl <= alu_sub16;
if ea(7 downto 0) = "00000000" then
7653,13 → 7609,13
pre_ctrl <= latch_pre;
nmi_ctrl <= latch_nmi;
ea_ctrl <= latch_ea;
-- decrement up
-- decrement sp
left_ctrl <= up_left;
right_ctrl <= one_right;
alu_ctrl <= alu_sub16;
up_ctrl <= load_up;
-- write pc low
addr_ctrl <= pushu_ad;
addr_ctrl <= pushs_ad;
dout_ctrl <= pc_lo_dout;
--
st_ctrl <= idle_st;
7681,7 → 7637,7
pre_ctrl <= latch_pre;
nmi_ctrl <= latch_nmi;
ea_ctrl <= latch_ea;
-- decrement up
-- decrement sp
left_ctrl <= up_left;
right_ctrl <= one_right;
alu_ctrl <= alu_sub16;
8067,7 → 8023,7
pre_ctrl <= latch_pre;
nmi_ctrl <= latch_nmi;
ea_ctrl <= latch_ea;
-- idle up
-- idle sp
left_ctrl <= up_left;
right_ctrl <= one_right;
cc_ctrl <= latch_cc;
/trunk/rtl/vhdl/testbench1.vhd
32,9 → 32,6
-- Version 1.0- 6 Sep 2003 - John Kent
-- Initial release to Open Cores
--
-- Version 1.1 - 25th Jan 2004 - John Kent
-- removed "test_alu" and "test_cc"
--
--===========================================================================--
 
library ieee;
65,6 → 62,8
signal cpu_addr : Std_Logic_Vector(15 downto 0);
signal cpu_data_in : Std_Logic_Vector(7 downto 0);
signal cpu_data_out: Std_Logic_Vector(7 downto 0);
signal cpu_alu : Std_Logic_Vector(15 downto 0);
signal cpu_cc : Std_Logic_Vector(7 downto 0);
signal cpu_irq : Std_Logic;
signal cpu_nmi : std_logic;
signal cpu_firq : Std_Logic;
119,7 → 118,9
hold: in std_logic;
irq: in std_logic;
nmi: in std_logic;
firq: in std_logic
firq: in std_logic;
test_alu: out std_logic_vector(15 downto 0);
test_cc: out std_logic_vector(7 downto 0)
);
end component cpu09;
 
137,7 → 138,9
hold => '0',
irq => cpu_irq,
nmi => cpu_nmi,
firq => cpu_firq
firq => cpu_firq,
test_alu => cpu_alu,
test_cc => cpu_cc
);
 
-- *** Test Bench - User Defined Section ***
/trunk/rtl/vhdl/testbench2.vhd
32,9 → 32,6
-- Version 1.0- 6 Sep 2003 - John Kent
-- Initial release to Open Cores
--
-- Version 1.1 - 25th Jan 2004 - John Kent
-- removed "test_alu" and "test_cc"
--
--===========================================================================--
 
library ieee;
43,13 → 40,13
use IEEE.STD_LOGIC_UNSIGNED.ALL;
use ieee.numeric_std.all;
 
entity my_testbench2 is
end my_testbench2;
entity my_testbench is
end my_testbench;
 
-------------------------------------------------------------------------------
-- Architecture for memio Controller Unit
-------------------------------------------------------------------------------
architecture behavior of my_testbench2 is
architecture behavior of my_testbench is
-----------------------------------------------------------------------------
-- Signals
-----------------------------------------------------------------------------
62,6 → 59,8
signal cpu_addr : Std_Logic_Vector(15 downto 0);
signal cpu_data_in : Std_Logic_Vector(7 downto 0);
signal cpu_data_out: Std_Logic_Vector(7 downto 0);
signal cpu_alu : Std_Logic_Vector(15 downto 0);
signal cpu_cc : Std_Logic_Vector(7 downto 0);
signal cpu_irq : Std_Logic;
signal cpu_nmi : Std_Logic;
signal cpu_firq : std_logic;
243,7 → 242,9
hold: in std_logic;
irq: in std_logic;
nmi: in std_logic;
firq: in std_logic
firq: in std_logic;
test_alu: out std_logic_vector(15 downto 0);
test_cc: out std_logic_vector(7 downto 0)
);
end component cpu09;
 
261,7 → 262,9
hold => '0',
irq => cpu_irq,
nmi => cpu_nmi,
firq => cpu_firq
firq => cpu_firq,
test_alu => cpu_alu,
test_cc => cpu_cc
);
 
-- *** Test Bench - User Defined Section ***
/trunk/rtl/vhdl/testbench3.vhd
25,15 → 25,12
-- Revision History:
--===========================================================================--
--
-- Version 0.1 - 12 Apr 2003 - John Kent
-- Version 0.1 - 12st April 2003 - John Kent
-- First version
--
-- Version 1.0 - 6 Sep 2003 - John Kent
-- Initial release to Open Cores
--
-- Version 1.1 - 26 Feb 2004 - John kent
-- removed test_alu and test_cc signals from
-- CPU component.
--===========================================================================--
 
library ieee;
42,13 → 39,13
use IEEE.STD_LOGIC_UNSIGNED.ALL;
use ieee.numeric_std.all;
 
entity my_testbench3 is
end my_testbench3;
entity my_testbench is
end my_testbench;
 
-------------------------------------------------------------------------------
-- Architecture for memio Controller Unit
-------------------------------------------------------------------------------
architecture behavior of my_testbench3 is
architecture behavior of my_testbench is
-----------------------------------------------------------------------------
-- Signals
-----------------------------------------------------------------------------
64,6 → 61,8
signal cpu_addr : Std_Logic_Vector(15 downto 0);
signal cpu_data_in : Std_Logic_Vector(7 downto 0);
signal cpu_data_out: Std_Logic_Vector(7 downto 0);
signal cpu_alu : Std_Logic_Vector(15 downto 0);
signal cpu_cc : Std_Logic_Vector(7 downto 0);
 
constant width : integer := 8;
constant memsize : integer := 64;
102,11 → 101,7
"00010111", "00011000", -- F82A - 1718 FDB $1718 ; IY
"00011001", "00011010", -- F82C - 191A FDB $191A ; UP
"11111000", "00000000", -- F82E - F800 FDB RESET ; PC
-- F830 STACK EQU *
--
-- Interrupt Cectors Start Here
--
"11111000", "00000000", -- F830 - F800 FDB RESET ; RESV
"11111000", "00000000", -- F830 - F800 STACK FDB RESET ; RESV
"11111000", "00001001", -- F832 - F809 FDB SWIVEC3 ; SWI3
"11111000", "00000111", -- F834 - F807 FDB SWIVEC2 ; SWI2
"11111000", "00000000", -- F836 - F800 fdb RESET ; FIRQ
129,7 → 124,9
hold: in std_logic;
irq: in std_logic;
nmi: in std_logic;
firq: in std_logic
firq: in std_logic;
test_alu: out std_logic_vector(15 downto 0);
test_cc: out std_logic_vector(7 downto 0)
);
end component cpu09;
 
147,7 → 144,9
hold => '0',
irq => cpu_irq,
nmi => cpu_nmi,
firq => cpu_firq
firq => cpu_firq,
test_alu => cpu_alu,
test_cc => cpu_cc
);
 
-- *** Test Bench - User Defined Section ***
/trunk/rtl/vhdl/testbench4.vhd
6,10 → 6,7
--
-- John Kent 12st April 2003
--
-- Version 1.1 - 25th Jan 2004 - John Kent
-- removed "test_alu" and "test_cc"
--
--
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
40,6 → 37,8
signal cpu_data_out: Std_Logic_Vector(7 downto 0);
signal cpu_halt : Std_logic;
signal cpu_hold : Std_logic;
signal cpu_alu : Std_Logic_Vector(15 downto 0);
signal cpu_cc : Std_Logic_Vector(7 downto 0);
signal rom_data_out: Std_Logic_Vector(7 downto 0);
signal ram_data_out: Std_Logic_Vector(7 downto 0);
signal ram_cs : Std_Logic;
57,7 → 56,9
hold: in std_logic;
irq: in std_logic;
nmi: in std_logic;
firq: in std_logic
firq: in std_logic;
test_alu: out std_logic_vector(15 downto 0);
test_cc: out std_logic_vector(7 downto 0)
);
end component;
 
94,7 → 95,9
hold => cpu_hold,
irq => cpu_irq,
nmi => cpu_nmi,
firq => cpu_firq
firq => cpu_firq,
test_alu => cpu_alu,
test_cc => cpu_cc
);
 
 
/trunk/rtl/vhdl/System09.npl
1,49 → 1,37
JDF G
// Created by Project Navigator ver 1.0
JDF E
// Created by ISE ver 1.0
PROJECT System09
DESIGN system09
DESIGN system09 Normal
DEVKIT xc2s300e-6pq208
DEVFAM spartan2e
DEVFAMTIME 315558000
DEVICE xc2s300e
DEVICETIME 315558000
DEVPKG pq208
DEVPKGTIME 315558000
DEVSPEED -6
DEVSPEEDTIME 315558000
DEVTOPLEVELMODULETYPE HDL
TOPLEVELMODULETYPETIME 0
DEVSYNTHESISTOOL XST (VHDL/Verilog)
SYNTHESISTOOLTIME 0
DEVSIMULATOR Modelsim
SIMULATORTIME 0
DEVGENERATEDSIMULATIONMODEL VHDL
GENERATEDSIMULATIONMODELTIME 0
STIMULUS testbench1.vhd
STIMULUS testbench2.vhd
STIMULUS testbench3.vhd
STIMULUS System09_tb.vhd
SOURCE ioport.vhd
SOURCE cpu09.vhd
SOURCE datram.vhd
SOURCE timer.vhd
SOURCE System09.vhd
SOURCE sbug_rom.vhd
STIMULUS testbench5.vhd
SOURCE miniUART3.vhd
SOURCE rxunit3.vhd
SOURCE txunit3.vhd
STIMULUS testbench6.vhd
SOURCE trap.vhd
SOURCE vdu8.vhd
SOURCE charrom.vhd
SOURCE ps2_keyboard.vhd
SOURCE ram2k.vhd
SOURCE keyboard.vhd
DEPASSOC my_system09 system09.ucf
FLOW XST VHDL
STIMULUS testbench1.vhd Normal
STIMULUS testbench2.vhd Normal
STIMULUS testbench3.vhd Normal
STIMULUS System09_tb.vhd Normal
MODULE ioport.vhd
MODSTYLE ioport Normal
MODULE rxunit2.vhd
MODSTYLE rxunit Normal
MODULE txunit2.vhd
MODSTYLE txunit Normal
MODULE cpu09.vhd
MODSTYLE cpu09 Normal
MODULE clkunit2.vhd
MODSTYLE clkunit Normal
MODULE datram.vhd
MODSTYLE dat_ram Normal
MODULE timer.vhd
MODSTYLE timer Normal
MODULE System09.vhd
MODSTYLE system09 Normal
MODULE sbug.vhd
MODSTYLE boot_rom Normal
MODULE miniUART2.vhd
MODSTYLE miniuart Normal
 
[STRATEGY-LIST]
Normal=True, 1062166682
 
[Normal]
p_impactConfigMode=xstvhd, spartan2e, Implementation.t_impactProgrammingTool, 1068866286, Boundary Scan
p_ModelSimSimRunTime_tbw=xstvhd, spartan2e, Bencher Waveform.t_MSimulateBehavioralVhdlModel, 315558000, 1000ns
[STATUS-ALL]
cpu09.ngcFile=ERRORS,0
[STRATEGY-LIST]
Normal=True
p_impactConfigMode=xstvhd, SPARTAN2E, Implementation.t_impactProgrammingTool, 1031246025, Slave Serial
/trunk/rtl/vhdl/miniUART2.vhd
0,0 → 1,288
--===========================================================================--
--
-- S Y N T H E Z I A B L E miniUART C O R E
--
-- www.OpenCores.Org - January 2000
-- This core adheres to the GNU public license
--
-- Design units : miniUART core for the System68
--
-- File name : miniuart2.vhd
--
-- Purpose : Implements an miniUART device for communication purposes
-- between the CPU68 processor and the Host computer through
-- an RS-232 communication protocol.
--
-- Dependencies : ieee.std_logic_1164
-- ieee.numeric_std
--
--===========================================================================--
-------------------------------------------------------------------------------
-- Revision list
-- Version Author Date Changes
--
-- 0.1 Ovidiu Lupas 15 January 2000 New model
-- 1.0 Ovidiu Lupas January 2000 Synthesis optimizations
-- 2.0 Ovidiu Lupas April 2000 Bugs removed - RSBusCtrl
-- the RSBusCtrl did not process all possible situations
--
-- olupas@opencores.org
--
-- 3.0 John Kent October 2002 Changed Status bits to match mc6805
-- Added CTS, RTS, Baud rate control
-- & Software Reset
-- 3.1 John Kent 5 January 2003 Added Word Format control a'la mc6850
-- 3.2 John Kent 19 July 2003 Latched Data input to UART
-- 3.3 John Kent 6 September 2003 Changed Clock Edge.
-- dilbert57@opencores.org
--
-------------------------------------------------------------------------------
-- Entity for miniUART Unit - 9600 baudrate --
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
 
entity miniUART is
port (
SysClk : in Std_Logic; -- System Clock
rst : in Std_Logic; -- Reset input (active high)
cs : in Std_Logic;
rw : in Std_Logic;
RxD : in Std_Logic;
TxD : out Std_Logic;
CTS_n : in Std_Logic;
RTS_n : out Std_Logic;
Irq : out Std_Logic; -- interrupt
Addr : in Std_Logic; -- Register Select
DataIn : in Std_Logic_Vector(7 downto 0); --
DataOut : out Std_Logic_Vector(7 downto 0)); --
end; --================== End of entity ==============================--
-------------------------------------------------------------------------------
-- Architecture for miniUART Controller Unit
-------------------------------------------------------------------------------
architecture uart of miniUART is
-----------------------------------------------------------------------------
-- Signals
-----------------------------------------------------------------------------
signal RxData : Std_Logic_Vector(7 downto 0); --
signal TxData : Std_Logic_Vector(7 downto 0); --
signal StatReg : Std_Logic_Vector(7 downto 0); -- status register
-- StatReg detailed
-----------+--------+--------+--------+--------+--------+--------+--------+
-- Irq | PErr | ORErr | FErr | CTS | DCD | TBufE | DRdy |
-----------+--------+--------+--------+--------+--------+--------+--------+
signal CtrlReg : Std_Logic_Vector(7 downto 0); -- control register
-- CtrlReg detailed
-----------+--------+--------+--------+--------+--------+--------+--------+
-- IrqEnb |TxCtl(1)|TxCtl(0)|WdFmt(2)|WdFmt(1)|WdFmt(0)|BdCtl(1)|BdCtl(0)|
-----------+--------+--------+--------+--------+--------+--------+--------+
-- IrqEnb
-- 0 - Rx Interrupt disabled
-- 1 - Rx Interrupt enabled
-- TxCtl
-- 0 1 - Tx Interrupt Enable
-- 1 0 - RTS high
-- WdFmt
-- 0 0 0 - 7 data, even parity, 2 stop
-- 0 0 1 - 7 data, odd parity, 2 stop
-- 0 1 0 - 7 data, even parity, 1 stop
-- 0 1 1 - 7 data, odd parity, 1 stop
-- 1 0 0 - 8 data, no parity, 2 stop
-- 1 0 1 - 8 data, no parity, 1 stop
-- 1 1 0 - 8 data, even parity, 1 stop
-- 1 1 1 - 8 data, odd parity, 1 stop
-- BdCtl
-- 0 0 - Baud Clk divide by 1 (not implemented)
-- 0 1 - Baud Clk divide by 16
-- 1 0 - Baud Clk divide by 64
-- 1 1 - reset
signal EnabRx : Std_Logic; -- Enable RX unit
signal EnabTx : Std_Logic; -- Enable TX unit
signal DRdy : Std_Logic; -- Receive Data ready
signal TBufE : Std_Logic; -- Transmit buffer empty
signal FErr : Std_Logic; -- Frame error
signal OErr : Std_Logic; -- Output error
signal PErr : Std_Logic; -- Parity Error
signal Read : Std_Logic; -- Read receive buffer
signal Load : Std_Logic; -- Load transmit buffer
signal Int : Std_Logic; -- Interrupt bit
signal Reset : Std_Logic; -- Reset (Software & Hardware)
-----------------------------------------------------------------------------
-- Baud rate Generator
-----------------------------------------------------------------------------
component ClkUnit
port (
Clk : in Std_Logic; -- System Clock
Reset : in Std_Logic; -- Reset input
EnableRX : out Std_Logic; -- Control signal
EnableTX : out Std_Logic; -- Control signal
BaudRate : in Std_Logic_Vector(1 downto 0));
end component;
-----------------------------------------------------------------------------
-- Receive Unit
-----------------------------------------------------------------------------
component RxUnit
port (
Clk : in Std_Logic; -- Clock signal
Reset : in Std_Logic; -- Reset input
Enable : in Std_Logic; -- Enable input
RxD : in Std_Logic; -- RS-232 data input
ReadD : in Std_Logic; -- Read data signal
Format : in Std_Logic_Vector(2 downto 0); -- word format
FRErr : out Std_Logic; -- Status signal
ORErr : out Std_Logic; -- Status signal
PAErr : out Std_logic; -- Status signal
DARdy : out Std_Logic; -- Status signal
DAOut : out Std_Logic_Vector(7 downto 0));
end component;
-----------------------------------------------------------------------------
-- Transmitter Unit
-----------------------------------------------------------------------------
component TxUnit
port (
Clk : in Std_Logic; -- Clock signal
Reset : in Std_Logic; -- Reset input
Enable : in Std_Logic; -- Enable input
LoadD : in Std_Logic; -- Load transmit data
Format : in Std_Logic_Vector(2 downto 0); -- word format
TxD : out Std_Logic; -- RS-232 data output
TBE : out Std_Logic; -- Tx buffer empty
DataO : in Std_Logic_Vector(7 downto 0));
end component;
begin
-----------------------------------------------------------------------------
-- Instantiation of internal components
-----------------------------------------------------------------------------
 
ClkDiv : ClkUnit port map (
Clk => SysClk,
EnableRx => EnabRX,
EnableTx => EnabTX,
BaudRate => CtrlReg(1 downto 0),
Reset => Reset);
TxDev : TxUnit port map (
Clk => SysClk,
Reset => Reset,
Enable => EnabTX,
LoadD => Load,
Format => CtrlReg(4 downto 2),
TxD => TxD,
TBE => TBufE,
DataO => TxData);
 
RxDev : RxUnit port map (
Clk => SysClk,
Reset => Reset,
Enable => EnabRX,
RxD => RxD,
ReadD => Read,
Format => CtrlReg(4 downto 2),
FRErr => FErr,
ORErr => OErr,
PAErr => PErr,
DARdy => DRdy,
DAOut => RxData);
 
-----------------------------------------------------------------------------
-- Implements the controller for Rx&Tx units
-----------------------------------------------------------------------------
RSBusCtrl : process(SysClk, Reset, DRdy, TBufE, FErr, OErr, CTS_n, PErr, Int, CtrlReg)
variable StatM : Std_Logic_Vector(7 downto 0);
begin
if SysClk'event and SysClk='0' then
if Reset = '1' then
StatM := "00000000";
Int <= '0';
else
StatM(0) := DRdy;
StatM(1) := TBufE;
StatM(2) := '0'; -- DCD
StatM(3) := CTS_n;
StatM(4) := FErr; -- Framing error
StatM(5) := OErr; -- Overrun error
StatM(6) := PErr; -- Parity error
StatM(7) := Int;
Int <= (CtrlReg(7) and DRdy) or
((not CtrlReg(6)) and CtrlReg(5) and TBufE);
end if;
 
RTS_n <= CtrlReg(6) and not CtrlReg(5);
Irq <= Int;
StatReg <= StatM;
end if;
end process;
 
-----------------------------------------------------------------------------
-- Combinational section
-----------------------------------------------------------------------------
 
control_strobe: process(SysClk, Reset, cs, rw, Addr, DataIn, CtrlReg, TxData )
begin
if SysClk'event and SysClk='0' then
if (reset = '1') then
CtrlReg <= "00000000";
Load <= '0';
Read <= '0';
else
if cs = '1' then
if Addr = '1' then
CtrlReg <= CtrlReg;
if rw = '0' then -- write data register
TxData <= DataIn;
Load <= '1';
Read <= '0';
else -- read Data Register
TxData <= TxData;
Load <= '0';
Read <= '1';
end if; -- rw
else -- read Status Register
TxData <= TxData;
Load <= '0';
Read <= '0';
if rw = '0' then -- write control register
CtrlReg <= DataIn;
else -- read control Register
CtrlReg <= CtrlReg;
end if; -- rw
end if; -- Addr
else -- not selected
Load <= '0';
Read <= '0';
CtrlReg <= CtrlReg;
end if; -- cs
end if; -- reset
end if; -- SysClk
end process;
 
---------------------------------------------------------------
--
-- set data output mux
--
--------------------------------------------------------------
 
data_port: process(Addr, StatReg, RxData )
begin
if Addr = '1' then
DataOut <= RxData; -- read data register
else
DataOut <= StatReg; -- read status register
end if; -- Addr
end process;
 
---------------------------------------------------------------
--
-- reset may be hardware or software
--
---------------------------------------------------------------
 
uart_reset: process(CtrlReg, rst )
begin
Reset <= (CtrlReg(1) and CtrlReg(0)) or rst;
end process;
 
end uart; --===================== End of architecture =======================--
 
/trunk/rtl/vhdl/rxunit2.vhd
0,0 → 1,341
--===========================================================================--
--
-- S Y N T H E Z I A B L E miniUART C O R E
--
-- www.OpenCores.Org - January 2000
-- This core adheres to the GNU public license
--
-- Design units : miniUART core for the System68
--
-- File name : rxunit2.vhd
--
-- Purpose : Implements an miniUART device for communication purposes
-- between the cpu68 cpu and the Host computer through
-- an RS-232 communication protocol.
--
-- Dependencies : ieee.std_logic_1164.all;
-- ieee.numeric_std.all;
--
--===========================================================================--
-------------------------------------------------------------------------------
-- Revision list
-- Version Author Date Changes
--
-- 0.1 Ovidiu Lupas 15 January 2000 New model
-- 2.0 Ovidiu Lupas 17 April 2000 samples counter cleared for bit 0
-- olupas@opencores.org
--
-- 3.0 John Kent 5 January 2003 Added 6850 word format control
-- 3.1 John Kent 12 January 2003 Significantly revamped receive code.
-- 3.3 John Kent 6 September 2003 Changed Clock Edge.
-- dilbert57@opencores.org
-------------------------------------------------------------------------------
-- Description : Implements the receive unit of the miniUART core. Samples
-- 16 times the RxD line and retain the value in the middle of
-- the time interval.
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
 
-------------------------------------------------------------------------------
-- Receive unit
-------------------------------------------------------------------------------
entity RxUnit is
port (
Clk : in Std_Logic; -- system clock signal
Reset : in Std_Logic; -- Reset input
Enable : in Std_Logic; -- Enable input
RxD : in Std_Logic; -- RS-232 data input
ReadD : in Std_Logic; -- Read data signal
Format : in Std_Logic_Vector(2 downto 0);
FRErr : out Std_Logic; -- Status signal
ORErr : out Std_Logic; -- Status signal
PAErr : out Std_logic; -- Status Signal
DARdy : out Std_Logic; -- Status signal
DAOut : out Std_Logic_Vector(7 downto 0)
);
end; --================== End of entity ==============================--
-------------------------------------------------------------------------------
-- Architecture for receive Unit
-------------------------------------------------------------------------------
architecture Behaviour of RxUnit is
-----------------------------------------------------------------------------
-- Signals
-----------------------------------------------------------------------------
signal RxStart : Std_Logic; -- Start Receive Request
signal RxFinish : Std_Logic; -- Receive finished
signal RxValid : Std_Logic; -- Receive data valid
signal RxFalse : Std_Logic; -- False start flag
signal tmpRxD : Std_Logic; -- RxD buffer
signal tmpRxC : Std_Logic; -- Rx clock
signal tmpDRdy : Std_Logic; -- Data Ready flag
signal tmpRxVal : Std_Logic; -- Rx Data Valid
signal tmpRxFin : Std_Logic; -- Rx Finish
signal outErr : Std_Logic; -- Over run error bit
signal frameErr : Std_Logic; -- Framing error bit
signal ParityErr : Std_Logic; -- Parity Error Bit
signal RxParity : Std_Logic; -- Calculated RX parity bit
signal RxState : Std_Logic_Vector(3 downto 0); -- receive bit state
signal SampleCnt : Std_Logic_Vector(3 downto 0); -- samples on one bit counter
signal ShtReg : Std_Logic_Vector(7 downto 0); -- Shift Register
signal DataOut : Std_Logic_Vector(7 downto 0); -- Data Output register
 
constant CntOne : Std_Logic_Vector(3 downto 0):= "0001";
constant CntZero : Std_Logic_Vector(3 downto 0):= "0000";
 
begin
---------------------------------------------------------------------
-- Receiver Read process
---------------------------------------------------------------------
RcvRead : process(Clk, Reset, ReadD, RxValid, tmpRxVal, tmpDRdy )
begin
if Clk'event and Clk='0' then
if Reset = '1' then
tmpDRdy <= '0';
tmpRxVal <= '0';
else
if ReadD = '1' then
tmpDRdy <= '0'; -- Data was read
tmpRxVal <= tmpRxVal;
else
if RxValid = '1' and tmpRxVal = '0' then
tmpDRdy <= '1'; -- Data was received
tmpRxVal <= '1';
else
tmpDRdy <= tmpDRdy;
if RxValid = '0' and tmpRxVal = '1' then
tmpRxVal <= '0';
else
tmpRxVal <= tmpRxVal;
end if;
end if; -- RxValid
end if; -- ReadD
end if; -- reset
end if; -- clk
end process;
 
---------------------------------------------------------------------
-- Receiver Synchronisation process
---------------------------------------------------------------------
RcvSync : process(Clk, Reset, Enable, RxStart, RxFalse, RxFinish, RxD, SampleCnt )
variable CntIni : Std_Logic_Vector(3 downto 0);
variable CntAdd : Std_Logic_Vector(3 downto 0);
begin
if Clk'event and Clk='0' then
if Reset = '1' then
RxStart <= '0';
SampleCnt <= "0000";
CntIni := SampleCnt;
CntAdd := CntZero;
else
if Enable = '1' then
if RxFinish = '1' and RxStart = '0' then -- Are we looking for a start bit ?
if RxD = '0' then -- yes, look for Start Edge
RxStart <= '1'; -- we have a start edge
CntIni := CntZero;
CntAdd := CntZero;
else
RxStart <= '0'; -- no start, spin sample count
CntIni := SampleCnt;
CntAdd := CntOne;
end if;
else
if RxFinish = '0' and RxStart = '1' then -- have we received a start bit ?
RxStart <= '0'; -- yes, reset start request
else
if RxFalse = '1' and RxStart = '1' then -- false start ?
RxStart <= '0'; -- yep, reset start request
else
RxStart <= RxStart;
end if;
end if;
CntIni := SampleCnt;
CntAdd := CntOne;
end if; -- RxStart
else
CntIni := SampleCnt;
CntAdd := CntZero;
RxStart <= RxStart;
end if; -- enable
end if; -- reset
SampleCnt <= CntIni + CntAdd;
end if; -- clk
end process;
 
 
---------------------------------------------------------------------
-- Receiver Clock process
---------------------------------------------------------------------
RcvClock : process(Clk, Reset, SampleCnt, RxD, tmpRxD )
begin
if Clk'event and Clk='0' then
if Reset = '1' then
tmpRxC <= '0';
tmpRxD <= '1';
else
if SampleCnt = "1000" then
tmpRxD <= RxD;
else
tmpRxD <= tmpRxD;
end if;
 
if SampleCnt = "1111" then
tmpRxC <= '1';
else
tmpRxC <= '0';
end if;
end if; -- reset
end if; -- clk
end process;
 
---------------------------------------------------------------------
-- Receiver process
---------------------------------------------------------------------
RcvProc : process(Clk, Reset, RxState, tmpRxC, Enable, tmpRxD, RxStart,
frameErr, outErr, DataOut, tmpDRdy,
ShtReg, RxParity, parityErr, Format,
RxValid, RxFalse, RxFinish
)
begin
if Clk'event and Clk='0' then
if Reset = '1' then
frameErr <= '0';
outErr <= '0';
parityErr <= '0';
 
ShtReg <= "00000000"; -- Shift register
RxParity <= '0'; -- Parity bit
RxFinish <= '1'; -- Data RX finish flag
RxValid <= '0'; -- Data RX data valid flag
RxFalse <= '0';
RxState <= "1111";
DataOut <= "00000000";
else
if tmpRxC = '1' and Enable = '1' then
case RxState is
when "0000" | "0001" | "0010" | "0011" |
"0100" | "0101" | "0110" => -- data bits 0 to 6
ShtReg <= tmpRxD & ShtReg(7 downto 1);
RxParity <= RxParity xor tmpRxD;
parityErr <= parityErr;
frameErr <= frameErr;
outErr <= outErr;
RxValid <= '0';
DataOut <= DataOut;
RxFalse <= '0';
RxFinish <= '0';
if RxState = "0110" then
if Format(2) = '0' then
RxState <= "1000"; -- 7 data + parity
else
RxState <= "0111"; -- 8 data bits
end if; -- Format(2)
else
RxState <= RxState + CntOne;
end if; -- RxState
when "0111" => -- data bit 7
ShtReg <= tmpRxD & ShtReg(7 downto 1);
RxParity <= RxParity xor tmpRxD;
parityErr <= parityErr;
frameErr <= frameErr;
outErr <= outErr;
RxValid <= '0';
DataOut <= DataOut;
RxFalse <= '0';
RxFinish <= '0';
if Format(1) = '1' then -- parity bit ?
RxState <= "1000"; -- yes, go to parity
else
RxState <= "1001"; -- no, must be 2 stop bit bits
end if;
when "1000" => -- parity bit
if Format(2) = '0' then
ShtReg <= tmpRxD & ShtReg(7 downto 1); -- 7 data + parity
else
ShtReg <= ShtReg; -- 8 data + parity
end if;
RxParity <= RxParity;
if Format(0) = '0' then -- parity polarity ?
if RxParity = tmpRxD then -- check even parity
parityErr <= '1';
else
parityErr <= '0';
end if;
else
if RxParity = tmpRxD then -- check for odd parity
parityErr <= '0';
else
parityErr <= '1';
end if;
end if;
frameErr <= frameErr;
outErr <= outErr;
RxValid <= '0';
DataOut <= DataOut;
RxFalse <= '0';
RxFinish <= '0';
RxState <= "1001";
when "1001" => -- stop bit (Only one required for RX)
ShtReg <= ShtReg;
RxParity <= RxParity;
parityErr <= parityErr;
if tmpRxD = '1' then -- stop bit expected
frameErr <= '0'; -- yes, no framing error
else
frameErr <= '1'; -- no, framing error
end if;
if tmpDRdy = '1' then -- Has previous data been read ?
outErr <= '1'; -- no, overrun error
else
outErr <= '0'; -- yes, no over run error
end if;
RxValid <= '1';
DataOut <= ShtReg;
RxFalse <= '0';
RxFinish <= '1';
RxState <= "1111";
when others => -- this is the idle state
ShtReg <= ShtReg;
RxParity <= RxParity;
parityErr <= parityErr;
frameErr <= frameErr;
outErr <= outErr;
RxValid <= '0';
DataOut <= DataOut;
if RxStart = '1' and tmpRxD = '0' then -- look for start request
RxFalse <= '0';
RxFinish <= '0';
RxState <= "0000"; -- yes, read data
else
if RxStart = '1' and tmpRxD = '1' then -- start request, but no start bit
RxFalse <= '1';
else
RxFalse <= '0';
end if;
RxFinish <= '1';
RxState <= "1111"; -- otherwise idle
end if;
end case; -- RxState
else
ShtReg <= ShtReg;
RxParity <= RxParity;
parityErr <= parityErr;
frameErr <= frameErr;
outErr <= outErr;
RxValid <= RxValid;
DataOut <= DataOut;
RxFalse <= RxFalse;
RxFinish <= RxFinish;
RxState <= RxState;
end if; -- tmpRxC
end if; -- reset
end if; -- clk
end process;
 
DARdy <= tmpDRdy;
DAOut <= DataOut;
FRErr <= frameErr;
ORErr <= outErr;
PAErr <= parityErr;
 
end Behaviour; --==================== End of architecture ====================--
/trunk/rtl/vhdl/txunit2.vhd
0,0 → 1,232
--===========================================================================--
--
-- S Y N T H E Z I A B L E miniUART C O R E
--
-- www.OpenCores.Org - January 2000
-- This core adheres to the GNU public license
--
-- Design units : miniUART core for the System68
--
-- File name : txunit2.vhd
--
-- Purpose : Implements an miniUART device for communication purposes
-- between the CPU68 processor and the Host computer through
-- an RS-232 communication protocol.
--
-- Dependencies : IEEE.Std_Logic_1164
--
--===========================================================================--
-------------------------------------------------------------------------------
-- Revision list
-- Version Author Date Changes
--
-- 0.1 Ovidiu Lupas 15 January 2000 New model
-- 2.0 Ovidiu Lupas 17 April 2000 unnecessary variable removed
-- olupas@opencores.org
--
-- 3.0 John Kent 5 January 2003 added 6850 word format control
-- 3.1 John Kent 12 January 2003 Rearranged state machine code
-- 3.2 John Kent 30 March 2003 Revamped State machine
-- 3.3 John Kent 6 September 2003 Changed Clock Edge.
--
-- dilbert57@opencores.org
--
-------------------------------------------------------------------------------
-- Description :
-------------------------------------------------------------------------------
-- Entity for the Tx Unit --
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use ieee.std_logic_unsigned.all;
 
-------------------------------------------------------------------------------
-- Transmitter unit
-------------------------------------------------------------------------------
entity TxUnit is
port (
Clk : in Std_Logic; -- Clock signal
Reset : in Std_Logic; -- Reset input
Enable : in Std_Logic; -- Enable input
LoadD : in Std_Logic; -- Load transmit data
Format : in Std_Logic_Vector(2 downto 0); -- word format
TxD : out Std_Logic; -- RS-232 data output
TBE : out Std_Logic; -- Tx buffer empty
DataO : in Std_Logic_Vector(7 downto 0));
end; --================== End of entity ==============================--
-------------------------------------------------------------------------------
-- Architecture for TxUnit
-------------------------------------------------------------------------------
architecture Behaviour of TxUnit is
type TxStateType is (TxReset_State, TxIdle_State, Start_State, Data_State, Parity_State, Stop_State );
-----------------------------------------------------------------------------
-- Signals
-----------------------------------------------------------------------------
signal TBuff : Std_Logic_Vector(7 downto 0); -- transmit buffer
signal tmpTBufE : Std_Logic; -- Transmit Buffer Empty
 
signal TReg : Std_Logic_Vector(7 downto 0); -- transmit register
signal TxParity : Std_logic; -- Parity Bit
signal DataCnt : Std_Logic_Vector(3 downto 0); -- Data Bit Counter
signal tmpTRegE : Std_Logic; -- Transmit Register empty
signal TxState : TxStateType;
 
signal NextTReg : Std_Logic_Vector(7 downto 0); -- transmit register
signal NextTxParity : Std_logic; -- Parity Bit
signal NextDataCnt : Std_Logic_Vector(3 downto 0); -- Data Bit Counter
signal NextTRegE : Std_Logic; -- Transmit Register empty
signal NextTxState : TxStateType;
begin
---------------------------------------------------------------------
-- Transmitter activation process
---------------------------------------------------------------------
TxSync : process(Clk, Reset, Enable, LoadD, DataO, tmpTBufE, tmpTRegE, TBuff )
begin
if Clk'event and Clk = '0' then
if Reset = '1' then
tmpTBufE <= '1';
TBuff <= "00000000";
else
if LoadD = '1' then
TBuff <= DataO;
tmpTBufE <= '0';
else
TBuff <= TBuff;
if (Enable = '1') and (tmpTBufE = '0') and (tmpTRegE = '1') then
tmpTBufE <= '1';
else
tmpTBufE <= tmpTBufE;
end if;
end if;
end if; -- reset
end if; -- clk
TBE <= tmpTBufE;
 
end process;
 
-----------------------------------------------------------------------------
-- Implements the Tx unit
-----------------------------------------------------------------------------
TxProc : process(TxState, TBuff, TReg, TxParity, DataCnt, Format, tmpTRegE, tmpTBufE)
begin
case TxState is
when TxReset_State =>
TxD <= '1';
NextTReg <= "00000000";
NextTxParity <= '0';
NextDataCnt <= "0000";
NextTRegE <= '1';
NextTxState <= TxIdle_State;
 
when Start_State =>
TxD <= '0'; -- Start bit
NextTReg <= TReg;
NextTxParity <= '0';
if Format(2) = '0' then
NextDataCnt <= "0110"; -- 7 data + parity
else
NextDataCnt <= "0111"; -- 8 data
end if;
NextTRegE <= '0';
NextTxState <= Data_State;
 
when Data_State =>
TxD <= TReg(0);
NextTReg <= '1' & TReg(7 downto 1);
NextTxParity <= TxParity xor TReg(0);
NextTRegE <= '0';
NextDataCnt <= DataCnt - "0001";
if DataCnt = "0000" then
if (Format(2) = '1') and (Format(1) = '0') then
if Format(0) = '0' then -- 8 data bits
NextTxState <= Stop_State; -- 2 stops
else
NextTxState <= TxIdle_State; -- 1 stop
end if;
else
NextTxState <= Parity_State; -- parity
end if;
else
NextTxState <= Data_State;
end if;
 
when Parity_State => -- 7/8 data + parity bit
if Format(0) = '0' then
TxD <= not( TxParity ); -- even parity
else
TXD <= TxParity; -- odd parity
end if;
NextTreg <= Treg;
NextTxParity <= '0';
NextTRegE <= '0';
NextDataCnt <= "0000";
if Format(1) = '0' then
NextTxState <= Stop_State; -- 2 stops
else
NextTxState <= TxIdle_State; -- 1 stop
end if;
 
when Stop_State => -- first stop bit
TxD <= '1'; -- 2 stop bits
NextTreg <= Treg;
NextTxParity <= '0';
NextDataCnt <= "0000";
NextTRegE <= '0';
NextTxState <= TxIdle_State;
 
when others => -- TxIdle_State (2nd Stop bit)
TxD <= '1';
NextTreg <= TBuff;
NextTxParity <= '0';
NextDataCnt <= "0000";
if (tmpTBufE = '0') and (tmpTRegE = '1') then
NextTRegE <= '0';
NextTxState <= Start_State;
else
NextTRegE <= '1';
NextTxState <= TxIdle_State;
end if;
 
end case; -- TxState
 
end process;
 
--
-- Tx State Machine
-- Slowed down by "Enable"
--
TX_State_Machine: process( Clk, Reset, Enable,
Treg, NextTReg,
TxParity, NextTxParity,
DataCnt, NextDataCnt,
tmpTRegE, NextTRegE,
TxState, NextTxState )
begin
if Clk'event and Clk = '0' then
if Reset = '1' then
Treg <= "00000000";
TxParity <= '0';
DataCnt <= "0000";
tmpTRegE <= '1';
TxState <= TxReset_State;
else
if Enable = '1' then
Treg <= NextTreg;
TxParity <= NextTxParity;
DataCnt <= NextDataCnt;
tmpTRegE <= NextTRegE;
TxState <= NextTxState;
else
Treg <= Treg;
TxParity <= TxParity;
DataCnt <= DataCnt;
tmpTRegE <= tmpTRegE;
TxState <= TxState;
end if;
end if;
end if;
 
end process;
 
end Behaviour; --=================== End of architecture ====================--
/trunk/rtl/vhdl/system09.ucf
43,188 → 43,246
#NET "cf_iordy" LOC = "P48" ; #J2-18
NET "cf_rst_n" LOC = "P49" ; #J2-19
#
# For B5-Peripheral-Connectors
# I/O Port
# Connector C
#
NET "v_drive" LOC = "p55" ; #pin 3
NET "h_drive" LOC = "p56" ; #pin 4
NET "blue_lo" LOC = "p58" ; #pin 5
NET "blue_hi" LOC = "p59" ; #pin 6
NET "green_lo" LOC = "p60" ; #pin 7
NET "green_hi" LOC = "p61" ; #pin 8
NET "red_lo" LOC = "p62" ; #pin 9
NET "red_hi" LOC = "p63" ; #pin 10
NET "kb_clock" LOC = "p64" ; #pin 11
NET "kb_data" LOC = "p68" ; #pin 12
#NET "mouse-clock" LOC = "p69" ; #pin 13
#NET "mouse_data" LOC = "p70" ; #pin 14
#NET "buzzer" LOC = "p71" ; #pin 15
NET "cts_n" LOC = "p73" ; #pin 16
NET "rxbit" LOC = "p74" ; #pin 17
NET "txbit" LOC = "p75" ; #pin 18
NET "rts_n" LOC = "p81" ; #pin 19
#NET "porta<0>" LOC = "p55" ; #pin 3
#NET "porta<1>" LOC = "p56" ; #pin 4
#NET "porta<2>" LOC = "p58" ; #pin 5
#NET "porta<3>" LOC = "p59" ; #pin 6
#NET "porta<4>" LOC = "p60" ; #pin 7
#NET "porta<5>" LOC = "p61" ; #pin 8
#NET "porta<6>" LOC = "p62" ; #pin 8
#NET "porta<7>" LOC = "p63" ; #pin 10
#NET "portb<0>" LOC = "p64" ; #pin 11
#NET "portb<1>" LOC = "p68" ; #pin 12
#NET "portb<2>" LOC = "p69" ; #pin 13
#NET "portb<3>" LOC = "p70" ; #pin 14
#NET "portb<4>" LOC = "p71" ; #pin 15
#NET "portb<5>" LOC = "p73" ; #pin 16
#NET "portb<6>" LOC = "p74" ; #pin 17
#NET "portb<7>" LOC = "p75" ; #pin 18
#NET "timer_out" LOC = "p81" ; #pin 19
#
# I/O Port
# For B3-FPGA-CPU-IO
# Connector D
#
#NET "pin2clk" LOC = "p80" ; #pin 2 (Clock input)
NET "led" LOC = "p82" ; #pin 3
NET "porta<0>" LOC = "p83" ; #pin 4
NET "porta<1>" LOC = "p84" ; #pin 5
NET "porta<2>" LOC = "p86" ; #pin 6
NET "porta<3>" LOC = "p87" ; #pin 7
NET "porta<4>" LOC = "p88" ; #pin 8
NET "porta<5>" LOC = "p89" ; #pin 9
NET "porta<6>" LOC = "p93" ; #pin 10
NET "porta<7>" LOC = "p94" ; #pin 11
NET "portb<0>" LOC = "p95" ; #pin 12
NET "portb<1>" LOC = "p96" ; #pin 13
NET "portb<2>" LOC = "p97" ; #pin 14
NET "portb<3>" LOC = "p98" ; #pin 15
NET "portb<4>" LOC = "p99" ; #pin 16
NET "portb<5>" LOC = "p100"; #pin 17
NET "portb<6>" LOC = "p101"; #pin 18
NET "portb<7>" LOC = "p102"; #pin 19
#NET "aux_clock" LOC = "p80" ; #pin 2
#NET "buzzer" LOC = "p82" ; #pin 3
NET "led" LOC = "p82" ; #pin 3
#NET "mouse_clock" LOC = "p83" ; #pin 4
#NET "mouse_data" LOC = "p84" ; #pin 5
NET "cts_n" LOC = "p86" ; #pin 6
NET "rts_n" LOC = "p87" ; #pin 7
NET "txbit" LOC = "p88" ; #pin 8
NET "rxbit" LOC = "p89" ; #pin 9
#NET "kb_clock" LOC = "p93" ; #pin 10
#NET "kb_data" LOC = "p94" ; #pin 11
#NET "v_drive" LOC = "p95" ; #pin 12
#NET "h_drive" LOC = "p96" ; #pin 13
#NET "blue_lo" LOC = "p97" ; #pin 14
#NET "blue_hi" LOC = "p98" ; #pin 15
#NET "green_lo" LOC = "p99" ; #pin 16
#NET "green_hi" LOC = "p100"; #pin 17
#NET "red_lo" LOC = "p101"; #pin 18
#NET "red_hi" LOC = "p102"; #pin 19
#
# For B5-SRAM
# For modified B3-SRAM
# Connector E
#
NET "ram_csn" LOC = "p108"; #J1.2
NET "ram_addr<16>" LOC = "p109"; #J1.3
NET "ram_addr<15>" LOC = "p110"; #J1.4
NET "ram_addr<14>" LOC = "p111"; #J1.5
NET "ram_addr<13>" LOC = "p112"; #J1.6
NET "ram_addr<12>" LOC = "p113"; #J1.7
NET "ram_addr<11>" LOC = "p114"; #J1.8
NET "ram_addr<10>" LOC = "p115"; #J1.9
NET "ram_addr<9>" LOC = "p116"; #J1.10
NET "ram_addr<0>" LOC = "p108"; #J1.2
NET "ram_addr<1>" LOC = "p109"; #J1.3
NET "ram_addr<2>" LOC = "p110"; #J1.4
NET "ram_addr<3>" LOC = "p111"; #J1.5
NET "ram_addr<4>" LOC = "p112"; #J1.6
NET "ram_addr<5>" LOC = "p113"; #J1.7
NET "ram_addr<6>" LOC = "p114"; #J1.8
NET "ram_addr<7>" LOC = "p115"; #J1.9
NET "ram_csn" LOC = "p116"; #J1.10
NET "ram_addr<8>" LOC = "p120"; #J1.11
NET "ram_addr<7>" LOC = "p121"; #J1.12
NET "ram_addr<6>" LOC = "p122"; #J1.13
NET "ram_addr<5>" LOC = "p123"; #J1.14
NET "ram_addr<4>" LOC = "p125"; #J1.15
NET "ram_addr<3>" LOC = "p126"; #J1.16
NET "ram_addr<2>" LOC = "p127"; #J1.17
NET "ram_addr<1>" LOC = "p129"; #J1.18
NET "ram_addr<0>" LOC = "p132"; #J1.19
NET "ram_addr<9>" LOC = "p121"; #J1.12
NET "ram_addr<10>" LOC = "p122"; #J1.13
NET "ram_addr<11>" LOC = "p123"; #J1.14
NET "ram_addr<12>" LOC = "p125"; #J1.15
NET "ram_addr<13>" LOC = "p126"; #J1.16
NET "ram_addr<14>" LOC = "p127"; #J1.17
NET "ram_addr<15>" LOC = "p129"; #J1.18
NET "ram_addr<16>" LOC = "p132"; #J1.19
#
# For B5-SRAM
# For modified B3-SRAM
# Connector F
#
NET "ram_wrun" LOC = "p133"; #J2.2
NET "ram_wrln" LOC = "p134"; #J2.3
NET "ram_data<15>" LOC = "p135"; #J2.4
NET "ram_data<14>" LOC = "p136"; #J2.5
NET "ram_data<13>" LOC = "p138"; #J2.6
NET "ram_data<12>" LOC = "p139"; #J2.7
NET "ram_data<11>" LOC = "p140"; #J2.8
NET "ram_data<10>" LOC = "p141"; #J2.9
NET "ram_data<9>" LOC = "p145"; #J2.10
NET "ram_data<8>" LOC = "p146"; #J2.11
NET "ram_data<7>" LOC = "p147"; #J2.12
NET "ram_data<6>" LOC = "p148"; #J2.13
NET "ram_data<5>" LOC = "p149"; #J2.14
NET "ram_data<4>" LOC = "p150"; #J2.15
NET "ram_data<3>" LOC = "p151"; #J2.16
NET "ram_data<2>" LOC = "p152"; #J2.17
NET "ram_data<1>" LOC = "p153"; #J2.18
NET "ram_data<0>" LOC = "p154"; #J2.19
NET "ram_data<0>" LOC = "p133"; #J2.2
NET "ram_data<1>" LOC = "p134"; #J2.3
NET "ram_data<2>" LOC = "p135"; #J2.4
NET "ram_data<3>" LOC = "p136"; #J2.5
NET "ram_data<4>" LOC = "p138"; #J2.6
NET "ram_data<5>" LOC = "p139"; #J2.7
NET "ram_data<6>" LOC = "p140"; #J2.8
NET "ram_data<7>" LOC = "p141"; #J2.9
NET "ram_data<8>" LOC = "p145"; #J2.10
NET "ram_data<9>" LOC = "p146"; #J2.11
NET "ram_data<10>" LOC = "p147"; #J2.12
NET "ram_data<11>" LOC = "p148"; #J2.13
NET "ram_data<12>" LOC = "p149"; #J2.14
NET "ram_data<13>" LOC = "p150"; #J2.15
NET "ram_data<14>" LOC = "p151"; #J2.16
NET "ram_data<15>" LOC = "p152"; #J2.17
NET "ram_wrun" LOC = "p153"; #J2.18
NET "ram_wrln" LOC = "p154"; #J2.19
#
# Connector G
#
#NET "pin2" LOC = "p182"; #pin 2 (clk input)
NET "bus_addr<0>" LOC = "p160"; #pin 3
NET "bus_addr<1>" LOC = "p161"; #pin 4
NET "bus_addr<2>" LOC = "p162"; #pin 5
NET "bus_addr<3>" LOC = "p163"; #pin 6
NET "bus_addr<4>" LOC = "p164"; #pin 7
NET "bus_addr<5>" LOC = "p165"; #pin 8
NET "bus_addr<6>" LOC = "p166"; #pin 9
NET "bus_addr<7>" LOC = "p167"; #pin 10
NET "bus_addr<8>" LOC = "p168"; #pin 11
NET "bus_addr<9>" LOC = "p169"; #pin 12
NET "bus_addr<10>" LOC = "p173"; #pin 13
NET "bus_addr<11>" LOC = "p174"; #pin 14
NET "bus_addr<12>" LOC = "p175"; #pin 15
NET "bus_addr<13>" LOC = "p176"; #pin 16
NET "bus_addr<14>" LOC = "p178"; #pin 17
NET "bus_addr<15>" LOC = "p179"; #pin 18
NET "bus_cs" LOC = "p180"; #pin 19
#NET "pin2" LOC = "p182"; #pin 2 (clk input)
NET "test_alu<0>" LOC = "p160"; #pin 3
NET "test_alu<1>" LOC = "p161"; #pin 4
NET "test_alu<2>" LOC = "p162"; #pin 5
NET "test_alu<3>" LOC = "p163"; #pin 6
NET "test_alu<4>" LOC = "p164"; #pin 7
NET "test_alu<5>" LOC = "p165"; #pin 8
NET "test_alu<6>" LOC = "p166"; #pin 9
NET "test_alu<7>" LOC = "p167"; #pin 10
NET "test_alu<8>" LOC = "p168"; #pin 11
NET "test_alu<9>" LOC = "p169"; #pin 12
NET "test_alu<10>" LOC = "p173"; #pin 13
NET "test_alu<11>" LOC = "p174"; #pin 14
NET "test_alu<12>" LOC = "p175"; #pin 15
NET "test_alu<13>" LOC = "p176"; #pin 16
NET "test_alu<14>" LOC = "p178"; #pin 17
NET "test_alu<15>" LOC = "p179"; #pin 18
#NET "pin19" LOC = "p180"; #pin 19
#
# Connector H
#
#NET "pin2" LOC = "p185"; #pin 2 (clk input)
NET "bus_clk" LOC = "p181"; #pin 3
NET "bus_reset" LOC = "p187"; #pin 4
#NET "pin5" LOC = "p188"; #pin 5
#NET "pin6" LOC = "p189"; #pin 6
#NET "pin7" LOC = "p191"; #pin 7
#NET "pin3" LOC = "p181"; #pin 3
#NET "uart_csn" LOC = "p187"; #pin 4
#NET "test_rw" LOC = "p188"; #pin 5
#NET "test_d0" LOC = "p189"; #pin 6
#NET "test_d1" LOC = "p191"; #pin 7
#NET "pin8" LOC = "p192"; #pin 8
#NET "pin9" LOC = "p193"; #pin 9
NET "timer_out" LOC = "p194"; #pin 10
NET "bus_data<0>" LOC = "p198"; #pin 11
NET "bus_data<1>" LOC = "p199"; #pin 12
NET "bus_data<2>" LOC = "p200"; #pin 13
NET "bus_data<3>" LOC = "p201"; #pin 14
NET "bus_data<4>" LOC = "p202"; #pin 15
NET "bus_data<5>" LOC = "p203"; #pin 16
NET "bus_data<6>" LOC = "p204"; #pin 17
NET "bus_data<7>" LOC = "p205"; #pin 18
NET "bus_rw" LOC = "p206"; #pin 19
#NET "pin10" LOC = "p194"; #pin 10
NET "test_cc<0>" LOC = "p198"; #pin 11
NET "test_cc<1>" LOC = "p199"; #pin 12
NET "test_cc<2>" LOC = "p200"; #pin 13
NET "test_cc<3>" LOC = "p201"; #pin 14
NET "test_cc<4>" LOC = "p202"; #pin 15
NET "test_cc<5>" LOC = "p203"; #pin 16
NET "test_cc<6>" LOC = "p204"; #pin 17
NET "test_cc<7>" LOC = "p205"; #pin 18
#NET "pin19" LOC = "p206"; #pin 19
#
# Timing Groups
#
INST "ram_addr<0>" TNM = "gram_addr";
INST "ram_addr<1>" TNM = "gram_addr";
INST "ram_addr<2>" TNM = "gram_addr";
INST "ram_addr<3>" TNM = "gram_addr";
INST "ram_addr<4>" TNM = "gram_addr";
INST "ram_addr<5>" TNM = "gram_addr";
INST "ram_addr<6>" TNM = "gram_addr";
INST "ram_addr<7>" TNM = "gram_addr";
INST "ram_addr<8>" TNM = "gram_addr";
INST "ram_addr<9>" TNM = "gram_addr";
INST "ram_addr<10>" TNM = "gram_addr";
INST "ram_addr<11>" TNM = "gram_addr";
INST "ram_addr<12>" TNM = "gram_addr";
INST "ram_addr<13>" TNM = "gram_addr";
INST "ram_addr<14>" TNM = "gram_addr";
INST "ram_addr<15>" TNM = "gram_addr";
INST "ram_addr<16>" TNM = "gram_addr";
INST "ram_data<0>" TNM = "gram_data";
INST "ram_data<1>" TNM = "gram_data";
INST "ram_data<2>" TNM = "gram_data";
INST "ram_data<3>" TNM = "gram_data";
INST "ram_data<4>" TNM = "gram_data";
INST "ram_data<5>" TNM = "gram_data";
INST "ram_data<6>" TNM = "gram_data";
INST "ram_data<7>" TNM = "gram_data";
INST "ram_data<8>" TNM = "gram_data";
INST "ram_data<9>" TNM = "gram_data";
INST "ram_data<10>" TNM = "gram_data";
INST "ram_data<11>" TNM = "gram_data";
INST "ram_data<12>" TNM = "gram_data";
INST "ram_data<13>" TNM = "gram_data";
INST "ram_data<14>" TNM = "gram_data";
INST "ram_data<15>" TNM = "gram_data";
INST "ram_wrln" TNM = "gram_wr";
INST "ram_wrun" TNM = "gram_wr";
INST "ram_csn" TNM = "gram_cs";
INST "ram_addr<0>" TNM = "ram_addr";
INST "ram_addr<1>" TNM = "ram_addr";
INST "ram_addr<2>" TNM = "ram_addr";
INST "ram_addr<3>" TNM = "ram_addr";
INST "ram_addr<4>" TNM = "ram_addr";
INST "ram_addr<5>" TNM = "ram_addr";
INST "ram_addr<6>" TNM = "ram_addr";
INST "ram_addr<7>" TNM = "ram_addr";
INST "ram_addr<8>" TNM = "ram_addr";
INST "ram_addr<9>" TNM = "ram_addr";
INST "ram_addr<10>" TNM = "ram_addr";
INST "ram_addr<11>" TNM = "ram_addr";
INST "ram_addr<12>" TNM = "ram_addr";
INST "ram_addr<13>" TNM = "ram_addr";
INST "ram_addr<14>" TNM = "ram_addr";
INST "ram_addr<15>" TNM = "ram_addr";
INST "ram_addr<16>" TNM = "ram_addr";
INST "ram_data<0>" TNM = "ram_data";
INST "ram_data<1>" TNM = "ram_data";
INST "ram_data<2>" TNM = "ram_data";
INST "ram_data<3>" TNM = "ram_data";
INST "ram_data<4>" TNM = "ram_data";
INST "ram_data<5>" TNM = "ram_data";
INST "ram_data<6>" TNM = "ram_data";
INST "ram_data<7>" TNM = "ram_data";
INST "ram_data<8>" TNM = "ram_data";
INST "ram_data<9>" TNM = "ram_data";
INST "ram_data<10>" TNM = "ram_data";
INST "ram_data<11>" TNM = "ram_data";
INST "ram_data<12>" TNM = "ram_data";
INST "ram_data<13>" TNM = "ram_data";
INST "ram_data<14>" TNM = "ram_data";
INST "ram_data<15>" TNM = "ram_data";
INST "ram_wrln" TNM = "ram_wr";
INST "ram_wrun" TNM = "ram_wr";
INST "ram_csn" TNM = "ram_cs";
INST "test_alu<0>" TNM = "test_alu";
INST "test_alu<1>" TNM = "test_alu";
INST "test_alu<2>" TNM = "test_alu";
INST "test_alu<3>" TNM = "test_alu";
INST "test_alu<4>" TNM = "test_alu";
INST "test_alu<5>" TNM = "test_alu";
INST "test_alu<6>" TNM = "test_alu";
INST "test_alu<7>" TNM = "test_alu";
INST "test_alu<8>" TNM = "test_alu";
INST "test_alu<9>" TNM = "test_alu";
INST "test_alu<10>" TNM = "test_alu";
INST "test_alu<11>" TNM = "test_alu";
INST "test_alu<12>" TNM = "test_alu";
INST "test_alu<13>" TNM = "test_alu";
INST "test_alu<14>" TNM = "test_alu";
INST "test_alu<15>" TNM = "test_alu";
INST "test_cc<0>" TNM = "test_cc";
INST "test_cc<1>" TNM = "test_cc";
INST "test_cc<2>" TNM = "test_cc";
INST "test_cc<3>" TNM = "test_cc";
INST "test_cc<4>" TNM = "test_cc";
INST "test_cc<5>" TNM = "test_cc";
INST "test_cc<6>" TNM = "test_cc";
INST "test_cc<7>" TNM = "test_cc";
#
# Timing Constraints
#
#TIMEGRP "gram_cs" OFFSET = OUT 40 ns AFTER "sysclk";
#TIMEGRP "gram_wr" OFFSET = OUT 40 ns AFTER "sysclk";
#TIMEGRP "gram_addr" OFFSET = OUT 40 ns AFTER "sysclk";
#TIMEGRP "gram_data" OFFSET = OUT 40 ns AFTER "sysclk";
#TIMEGRP "gram_data" OFFSET = IN 15 ns BEFORE "sysclk";
#TIMEGRP "gtest_alu" OFFSET = OUT 90 ns AFTER "sysclk";
#TIMEGRP "gtest_cc" OFFSET = OUT 95 ns AFTER "sysclk";
TIMEGRP "ram_cs" OFFSET = OUT 40 ns AFTER "sysclk";
TIMEGRP "ram_wr" OFFSET = OUT 40 ns AFTER "sysclk";
TIMEGRP "ram_addr" OFFSET = OUT 40 ns AFTER "sysclk";
TIMEGRP "ram_data" OFFSET = OUT 40 ns AFTER "sysclk";
TIMEGRP "ram_data" OFFSET = IN 15 ns BEFORE "sysclk";
TIMEGRP "test_alu" OFFSET = OUT 90 ns AFTER "sysclk";
TIMEGRP "test_cc" OFFSET = OUT 95 ns AFTER "sysclk";
NET "sysclk" TNM_NET = "sysclk";
TIMESPEC "TS_sysclk" = PERIOD "sysclk" 100 ns LOW 50 %;
#
# Fast I/O Pins
#
NET "ram_addr<0>" FAST;
NET "ram_addr<1>" FAST;
NET "ram_addr<2>" FAST;
NET "ram_addr<3>" FAST;
NET "ram_addr<4>" FAST;
NET "ram_addr<5>" FAST;
NET "ram_addr<6>" FAST;
NET "ram_addr<7>" FAST;
NET "ram_addr<8>" FAST;
NET "ram_addr<9>" FAST;
NET "ram_addr<10>" FAST;
NET "ram_addr<11>" FAST;
NET "ram_addr<12>" FAST;
NET "ram_addr<13>" FAST;
NET "ram_addr<14>" FAST;
NET "ram_addr<15>" FAST;
NET "ram_addr<16>" FAST;
NET "ram_csn" FAST;
NET "ram_data<0>" FAST;
NET "ram_data<1>" FAST;
NET "ram_data<2>" FAST;
NET "ram_data<3>" FAST;
NET "ram_data<4>" FAST;
NET "ram_data<5>" FAST;
NET "ram_data<6>" FAST;
NET "ram_data<7>" FAST;
NET "ram_data<8>" FAST;
NET "ram_data<9>" FAST;
NET "ram_data<10>" FAST;
NET "ram_data<11>" FAST;
NET "ram_data<12>" FAST;
NET "ram_data<13>" FAST;
NET "ram_data<14>" FAST;
NET "ram_data<15>" FAST;
NET "ram_wrln" FAST;
NET "ram_wrun" FAST;
/trunk/rtl/vhdl/clkunit2.vhd
0,0 → 1,138
--===========================================================================--
--
-- S Y N T H E Z I A B L E miniUART C O R E
--
-- www.OpenCores.Org - January 2000
-- This core adheres to the GNU public license
 
-- Design units : miniUART core for the System68
--
-- File name : clkunit2.vhd
--
-- Purpose : Implements an miniUART device for communication purposes
-- between the CPU68 processor and the Host computer through
-- an RS-232 communication protocol.
--
-- Dependencies : ieee.std_logic_1164
-- ieee.numeric_std
--
--===========================================================================--
-------------------------------------------------------------------------------
-- Revision list
-- Version Author Date Changes
--
-- 0.1 Ovidiu Lupas 15 January 2000 New model
-- olupas@opencores.org
--
-- 2.0 John Kent 10 November 2002 Added programmable baud rate
-- 3.0 John Kent 15 December 2002 Fix TX clock divider
-- 3.1 John kent 12 January 2003 Changed divide by 1 for 38.4Kbps
-- 3.3 John Kent 6 September 2003 Changed Clock Edge.
-- dilbert57@opencores.org
-------------------------------------------------------------------------------
-- Description : Generates the Baud clock and enable signals for RX & TX
-- units.
-------------------------------------------------------------------------------
-- Entity for Baud rate generator Unit - 9600 baudrate --
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
-------------------------------------------------------------------------------
-- Baud rate generator
-------------------------------------------------------------------------------
entity ClkUnit is
port (
Clk : in Std_Logic; -- System Clock
Reset : in Std_Logic; -- Reset input
EnableRx : out Std_Logic; -- Control signal
EnableTx : out Std_Logic; -- Control signal
BaudRate : in Std_Logic_Vector(1 downto 0));
end; --================== End of entity ==============================--
-------------------------------------------------------------------------------
-- Architecture for Baud rate generator Unit
-------------------------------------------------------------------------------
architecture Behaviour of ClkUnit is
signal tmpEnRx : std_logic;
 
begin
-----------------------------------------------------------------------------
-- Divides the system clock of 40 MHz div 260 gives 153KHz for 9600bps
-- 48 MHz div 156 gives 306KHz for 19.2Kbps
-- 24 MHz div 156 gives 153KHz for 9600bps
-- 9.8304MHz div 32 gives 306KHz for 19.2Kbps
-- 4.9152MHz div 32 gives 153KHz for 9600bps
-----------------------------------------------------------------------------
DivClk : process(Clk,Reset,tmpEnRx, BaudRate)
variable Count : unsigned(7 downto 0);
constant CntOne : Unsigned(7 downto 0):="00000001";
begin
if Clk'event and Clk = '0' then
if Reset = '1' then
Count := "00000000";
tmpEnRx <= '0';
else
if Count = "00000000" then
tmpEnRx <= '1';
case BaudRate is
when "00" =>
-- 6850 divide by 1 ((1*2)-1) (synchronous)
-- miniUart 9.83MHz div 16 = 38.4Kbps
Count := "00001111";
when "01" =>
-- 6850 divide by 16 ((16*2)-1) (9600 Baud)
-- miniUart 9.83MHz div 32 = 19.2Kbps
Count := "00011111";
when "10" =>
-- 6850 divide by 64 ((64*2)-1) (2400 Baud)
-- miniUart 9.83MHz div 128 = 4800bps
Count := "01111111";
when others =>
-- when "11" => -- reset
Count := "00000000";
null;
end case;
else
tmpEnRx <= '0';
Count := Count - CntOne;
end if;
end if;
end if;
EnableRx <= tmpEnRx;
end process;
 
-----------------------------------------------------------------------------
-- Provides the EnableTX signal, at 9.6 KHz
-- Divide by 16
-- Except it wasn't ... it counted up to "10010" (18)
-----------------------------------------------------------------------------
DivClk16 : process(Clk,Reset,tmpEnRX)
variable Cnt16 : unsigned(4 downto 0);
constant CntOne : Unsigned(4 downto 0):="00001";
begin
if Clk'event and Clk = '0' then
if Reset = '1' then
Cnt16 := "00000";
EnableTX <= '0';
else
case Cnt16 is
when "00000" =>
if tmpEnRx = '1' then
Cnt16 := "01111";
EnableTx <='1';
else
Cnt16 := Cnt16;
EnableTx <= '0';
end if;
when others =>
if tmpEnRx = '1' then
Cnt16 := Cnt16 - CntOne;
else
Cnt16 := Cnt16;
end if;
EnableTX <= '0';
end case;
end if;
end if;
end process;
end Behaviour; --==================== End of architecture ===================--
/trunk/rtl/vhdl/System09.vhd
10,7 → 10,7
-- Purpose : Top level file for 6809 compatible system on a chip
-- Designed with Xilinx XC2S300e Spartan 2+ FPGA.
-- Implemented With BurchED B5-X300 FPGA board,
-- B5-SRAM module, B5-CF module and B5-FPGA-CPU-IO module
-- B3-SRAM module, B5-CF module and B3-FPGA-CPU-IO module
--
-- Dependencies : ieee.Std_Logic_1164
-- ieee.std_logic_unsigned
20,9 → 20,10
-- Uses : boot_rom (sbug.vhd) Monitor ROM
-- cpu09 (cpu09.vhd) CPU core
-- dat_ram (datram.vhd) Dynamic Address Translation
-- miniuart (minitUART3.vhd) ACIA / MiniUART
-- (rxunit3.vhd)
-- (tx_unit3.vhd)
-- miniuart (minitUART2.vhd) ACIA / MiniUART
-- (rxunit2.vhd)
-- (tx_unit2.vhd)
-- (clkunit2.vhd)
-- timer (timer.vhd) Timer module
--
-- Author : John E. Kent
36,30 → 37,14
-- Version 0.2 - 30 March 2003
-- Version 0.3 - 29 April 2003
-- Version 0.4 - 29 June 2003
--
-- Version 0.5 - 19 July 2003
-- prints out "Hello World"
--
-- Version 0.6 - 5 September 2003
-- Runs SBUG
--
-- Version 1.0- 6 Sep 2003 - John Kent
-- Inverted SysClk
-- Initial release to Open Cores
--
-- Version 1.1 - 17 Jan 2004 - John Kent
-- Updated miniUart.
--
-- Version 1.2 - 25 Jan 2004 - John Kent
-- removed signals "test_alu" and "test_cc"
-- Trap hardware re-instated.
--
-- Version 1.3 - 11 Feb 2004 - John Kent
-- Designed forked off to produce System09_VDU
-- Added VDU component
-- VDU runs at 25MHz and divides the clock by 2 for the CPU
-- UART Runs at 57.6 Kbps
--
--===========================================================================--
library ieee;
use ieee.std_logic_1164.all;
67,7 → 52,7
use IEEE.STD_LOGIC_UNSIGNED.ALL;
use ieee.numeric_std.all;
 
entity My_System09 is
entity System09 is
port(
SysClk : in Std_Logic; -- System Clock input
Reset_n : in Std_logic; -- Master Reset input (active low)
81,11 → 66,8
ram_data : inout Std_Logic_Vector(15 downto 0);
 
-- Stuff on the peripheral board
-- aux_clock : in Std_Logic; -- FPGA-CPU-IO clock
 
-- PS/2 Keyboard
kb_clock : inout Std_logic;
kb_data : inout Std_Logic;
 
-- PS/2 Mouse interface
-- mouse_clock : in Std_Logic;
-- mouse_data : in Std_Logic;
97,14 → 79,14
cts_n : in Std_Logic;
 
-- CRTC output signals
v_drive : out Std_Logic;
h_drive : out Std_Logic;
blue_lo : out std_logic;
blue_hi : out std_logic;
green_lo : out std_logic;
green_hi : out std_logic;
red_lo : out std_logic;
red_hi : out std_logic;
-- v_drive : out Std_Logic;
-- h_drive : out Std_Logic;
-- blue_lo : out std_logic;
-- blue_hi : out std_logic;
-- green_lo : out std_logic;
-- green_hi : out std_logic;
-- red_lo : out std_logic;
-- red_hi : out std_logic;
-- buzzer : out std_logic;
 
-- Compact Flash
118,26 → 100,20
cf_d : inout std_logic_vector(15 downto 0);
 
-- Parallel I/O port
porta : inout std_logic_vector(7 downto 0);
portb : inout std_logic_vector(7 downto 0);
-- porta : inout std_logic_vector(7 downto 0);
-- portb : inout std_logic_vector(7 downto 0);
-- timer_out : out std_logic;
 
-- CPU bus
bus_clk : out std_logic;
bus_reset : out std_logic;
bus_rw : out std_logic;
bus_cs : out std_logic;
bus_addr : out std_logic_vector(15 downto 0);
bus_data : inout std_logic_vector(7 downto 0);
 
-- timer
timer_out : out std_logic
-- Test Pins
test_alu : out std_logic_vector(15 downto 0);
test_cc : out std_logic_vector(7 downto 0)
);
end My_System09;
end System09;
 
-------------------------------------------------------------------------------
-- Architecture for System09
-- Architecture for memio Controller Unit
-------------------------------------------------------------------------------
architecture my_computer of My_System09 is
architecture my_computer of System09 is
-----------------------------------------------------------------------------
-- Signals
-----------------------------------------------------------------------------
148,22 → 124,15
signal uart_data_out : Std_Logic_Vector(7 downto 0);
signal uart_cs : Std_Logic;
signal uart_irq : Std_Logic;
signal baudclk : Std_Logic;
signal DCD_n : Std_Logic;
 
-- timer
signal timer_data_out : std_logic_vector(7 downto 0);
signal timer_cs : std_logic;
signal timer_irq : std_logic;
-- signal timer_data_out : std_logic_vector(7 downto 0);
-- signal timer_cs : std_logic;
-- signal timer_irq : std_logic;
 
-- trap
signal trap_cs : std_logic;
signal trap_data_out : std_logic_vector(7 downto 0);
signal trap_irq : std_logic;
 
-- Parallel I/O port
signal ioport_data_out : std_logic_vector(7 downto 0);
signal ioport_cs : std_logic;
-- signal ioport_data_out : std_logic_vector(7 downto 0);
-- signal ioport_cs : std_logic;
 
-- compact flash port
signal cf_data_out : std_logic_vector(7 downto 0);
171,11 → 140,6
signal cf_rd : std_logic;
signal cf_wr : std_logic;
 
-- keyboard port
signal keyboard_data_out : std_logic_vector(7 downto 0);
signal keyboard_cs : std_logic;
signal keyboard_irq : std_logic;
 
-- RAM
signal ram_cs : std_logic; -- memory chip select
signal ram_wrl : std_logic; -- memory write lower
183,30 → 147,33
signal ram_data_out : std_logic_vector(7 downto 0);
 
-- CPU Interface signals
signal cpu_reset : Std_Logic;
signal cpu_clk : Std_Logic;
signal cpu_rw : std_logic;
signal cpu_vma : std_logic;
signal cpu_halt : std_logic;
signal cpu_hold : std_logic;
signal cpu_firq : std_logic;
signal cpu_irq : std_logic;
signal cpu_nmi : std_logic;
signal cpu_addr : std_logic_vector(15 downto 0);
signal cpu_data_in : std_logic_vector(7 downto 0);
signal cpu_data_out : std_logic_vector(7 downto 0);
signal cpu_reset : Std_Logic;
signal cpu_clk : Std_Logic;
signal cpu_rw : std_logic;
signal cpu_vma : std_logic;
signal cpu_halt : std_logic;
signal cpu_hold : std_logic;
signal cpu_firq : std_logic;
signal cpu_irq : std_logic;
signal cpu_nmi : std_logic;
signal cpu_addr : std_logic_vector(15 downto 0);
signal cpu_data_in : std_logic_vector(7 downto 0);
signal cpu_data_out: std_logic_vector(7 downto 0);
 
-- Dynamic address translation
signal dat_cs : std_logic;
signal dat_addr : std_logic_vector(7 downto 0);
signal dat_cs : std_logic;
signal dat_addr : std_logic_vector(7 downto 0);
 
-- Video Display Unit
signal vdu_cs : std_logic;
signal vdu_data_out : std_logic_vector(7 downto 0);
-- Boot ROM Map switch
-- signal map_cs : Std_Logic;
-- signal map_sw : Std_Logic;
 
-- synchronous RAM
-- signal xram_data_out : std_logic_vector(7 downto 0);
-- signal xram_cs : std_logic;
 
-- Flashing Led test signals
signal countL : std_logic_vector(23 downto 0);
signal BaudCount : std_logic_vector(4 downto 0);
 
-----------------------------------------------------------------
--
227,52 → 194,12
hold: in std_logic;
irq: in std_logic;
nmi: in std_logic;
firq: in std_logic
firq: in std_logic;
test_alu: out std_logic_vector(15 downto 0);
test_cc: out std_logic_vector(7 downto 0)
);
end component;
 
----------------------------------------
--
-- SBUG Slice Monitor ROM
--
----------------------------------------
--component boot_rom
-- port (
-- addr : in Std_Logic_Vector(10 downto 0); -- 2K byte boot rom
-- data : out Std_Logic_Vector(7 downto 0));
--end component;
 
----------------------------------------
--
-- SBUG Block RAM Monitor ROM
--
----------------------------------------
component sbug_rom
Port (
MEMclk : in std_logic;
MEMaddr : in std_logic_vector (10 downto 0);
MEMrdata : out std_logic_vector (7 downto 0)
);
end component;
 
----------------------------------------
--
-- Dynamic Address Translation Registers
--
----------------------------------------
component dat_ram
port (
clk: in std_logic;
rst: in std_logic;
cs: in std_logic;
rw: in std_logic;
addr_lo: in std_logic_vector(3 downto 0);
addr_hi: in std_logic_vector(3 downto 0);
data_in: in std_logic_vector(7 downto 0);
data_out: out std_logic_vector(7 downto 0)
);
end component;
 
-----------------------------------------------------------------
--
-- Open Cores Mini UART
281,24 → 208,20
 
component miniUART
port (
clk : in Std_Logic; -- System Clock
rst : in Std_Logic; -- Reset input (active high)
cs : in Std_Logic; -- miniUART Chip Select
rw : in Std_Logic; -- Read / Not Write
irq : out Std_Logic; -- Interrupt
Addr : in Std_Logic; -- Register Select
DataIn : in Std_Logic_Vector(7 downto 0); -- Data Bus In
DataOut : out Std_Logic_Vector(7 downto 0); -- Data Bus Out
RxC : in Std_Logic; -- Receive Baud Clock
TxC : in Std_Logic; -- Transmit Baud Clock
RxD : in Std_Logic; -- Receive Data
TxD : out Std_Logic; -- Transmit Data
DCD_n : in Std_Logic; -- Data Carrier Detect
CTS_n : in Std_Logic; -- Clear To Send
RTS_n : out Std_Logic ); -- Request To send
SysClk : in Std_Logic; -- System Clock
rst : in Std_Logic; -- Reset input
cs : in Std_Logic;
rw : in Std_Logic;
RxD : in Std_Logic;
TxD : out Std_Logic;
CTS_n : in Std_Logic;
RTS_n : out Std_Logic;
Irq : out Std_logic;
Addr : in Std_Logic;
DataIn : in Std_Logic_Vector(7 downto 0); --
DataOut : out Std_Logic_Vector(7 downto 0)); --
end component;
 
 
----------------------------------------
--
-- Timer module
305,112 → 228,101
--
----------------------------------------
 
component timer
port (
clk : in std_logic;
rst : in std_logic;
cs : in std_logic;
rw : in std_logic;
addr : in std_logic;
data_in : in std_logic_vector(7 downto 0);
data_out : out std_logic_vector(7 downto 0);
irq : out std_logic;
timer_in : in std_logic;
timer_out : out std_logic
);
end component;
--component timer
-- port (
-- clk : in std_logic;
-- rst : in std_logic;
-- cs : in std_logic;
-- rw : in std_logic;
-- addr : in std_logic;
-- data_in : in std_logic_vector(7 downto 0);
-- data_out : out std_logic_vector(7 downto 0);
-- irq : out std_logic;
-- timer_in : in std_logic;
-- timer_out : out std_logic
-- );
--end component;
 
------------------------------------------------------------
----------------------------------------
--
-- Bus Trap logic
-- Dual 8 bit Parallel I/O module
--
------------------------------------------------------------
----------------------------------------
--component ioport
-- port (
-- clk : in std_logic;
-- rst : in std_logic;
-- cs : in std_logic;
-- rw : in std_logic;
-- addr : in std_logic_vector(1 downto 0);
-- data_in : in std_logic_vector(7 downto 0);
-- data_out : out std_logic_vector(7 downto 0);
-- porta_io : inout std_logic_vector(7 downto 0);
-- portb_io : inout std_logic_vector(7 downto 0)
-- );
--end component;
 
component trap
port (
clk : in std_logic;
rst : in std_logic;
cs : in std_logic;
rw : in std_logic;
vma : in std_logic;
addr : in std_logic_vector(15 downto 0);
data_in : in std_logic_vector(7 downto 0);
data_out : out std_logic_vector(7 downto 0);
irq : out std_logic
);
----------------------------------------
--
-- SBUG Slice Monitor ROM
--
----------------------------------------
component boot_rom
port (
addr : in Std_Logic_Vector(10 downto 0); -- 2K byte boot rom
data : out Std_Logic_Vector(7 downto 0));
end component;
 
----------------------------------------
--
-- Dual 8 bit Parallel I/O module
-- SBUG Block RAM Monitor ROM
--
----------------------------------------
component ioport
port (
clk : in std_logic;
rst : in std_logic;
cs : in std_logic;
rw : in std_logic;
addr : in std_logic_vector(1 downto 0);
data_in : in std_logic_vector(7 downto 0);
data_out : out std_logic_vector(7 downto 0);
porta_io : inout std_logic_vector(7 downto 0);
portb_io : inout std_logic_vector(7 downto 0)
);
end component;
--component sbug_rom
-- Port (
-- MEMclk : in std_logic;
-- MEMaddr : in std_logic_vector (10 downto 0);
-- MEMrdata : out std_logic_vector (7 downto 0)
-- );
--end component;
 
----------------------------------------
--
-- PS/2 Keyboard
-- Dynamic Address Translation Registers
--
----------------------------------------
 
component keyboard
port(
clk : in std_logic;
rst : in std_logic;
cs : in std_logic;
rw : in std_logic;
addr : in std_logic;
data_in : in std_logic_vector(7 downto 0);
data_out : out std_logic_vector(7 downto 0);
irq : out std_logic;
kbd_clk : inout std_logic;
kbd_data : inout std_logic
);
component dat_ram
port (
clk: in std_logic;
rst: in std_logic;
cs: in std_logic;
rw: in std_logic;
addr_lo: in std_logic_vector(3 downto 0);
addr_hi: in std_logic_vector(3 downto 0);
data_in: in std_logic_vector(7 downto 0);
data_out: out std_logic_vector(7 downto 0)
);
end component;
 
----------------------------------------
--
-- Video Display Unit.
-- Block RAM module
--
----------------------------------------
component vdu
port(
-- control register interface
vdu_clk_in : in std_logic;
vdu_clk_out : out std_logic;
vdu_rst : in std_logic;
vdu_cs : in std_logic;
vdu_rw : in std_logic;
vdu_addr : in std_logic_vector(2 downto 0);
vdu_data_in : in std_logic_vector(7 downto 0);
vdu_data_out : out std_logic_vector(7 downto 0);
-- component block_ram
-- Port (
-- MEMclk : in std_logic;
-- MEMcs : in std_logic;
-- MEMrw : in std_logic;
-- MEMaddr : in std_logic_vector (10 downto 0);
-- MEMrdata : out std_logic_vector (7 downto 0);
-- MEMwdata : in std_logic_vector (7 downto 0)
-- );
--end component;
 
-- vga port connections
vga_red0_o : out std_logic;
vga_red1_o : out std_logic;
vga_green0_o : out std_logic;
vga_green1_o : out std_logic;
vga_blue0_o : out std_logic;
vga_blue1_o : out std_logic;
vga_hsync_o : out std_logic;
vga_vsync_o : out std_logic
);
end component;
 
-- component BUFG
-- port (
-- port (
-- i: in std_logic;
-- o: out std_logic
-- );
422,7 → 334,7
-----------------------------------------------------------------------------
 
my_cpu : cpu09 port map (
clk => cpu_clk,
clk => SysClk,
rst => cpu_reset,
rw => cpu_rw,
vma => cpu_vma,
433,130 → 345,76
hold => cpu_hold,
irq => cpu_irq,
nmi => cpu_nmi,
firq => cpu_firq
firq => cpu_firq,
test_alu => test_alu,
test_cc => test_cc
);
 
--my_rom : boot_rom port map (
-- addr => cpu_addr(10 downto 0),
-- data => rom_data_out
-- );
 
my_rom : sbug_rom port map (
MEMclk => cpu_clk,
MEMaddr => cpu_addr(10 downto 0),
MEMrdata => rom_data_out
);
 
my_dat : dat_ram port map (
clk => cpu_clk,
rst => cpu_reset,
cs => dat_cs,
rw => cpu_rw,
addr_hi => cpu_addr(15 downto 12),
addr_lo => cpu_addr(3 downto 0),
data_in => cpu_data_out,
data_out => dat_addr(7 downto 0)
);
 
my_uart : miniUART port map (
clk => cpu_clk,
SysClk => SysClk,
rst => cpu_reset,
cs => uart_cs,
rw => cpu_rw,
irq => uart_irq,
Addr => cpu_addr(0),
Datain => cpu_data_out,
DataOut => uart_data_out,
RxC => baudclk,
TxC => baudclk,
RxD => rxbit,
TxD => txbit,
DCD_n => dcd_n,
CTS_n => cts_n,
RTS_n => rts_n
RTS_n => rts_n,
Irq => uart_irq,
Addr => cpu_addr(0),
Datain => cpu_data_out,
DataOut => uart_data_out
);
 
my_timer : timer port map (
clk => cpu_clk,
rst => cpu_reset,
cs => timer_cs,
rw => cpu_rw,
addr => cpu_addr(0),
data_in => cpu_data_out,
data_out => timer_data_out,
irq => timer_irq,
timer_in => CountL(5),
timer_out => timer_out
);
--my_timer : timer port map (
-- clk => SysClk,
-- rst => cpu_reset,
-- cs => timer_cs,
-- rw => cpu_rw,
-- addr => cpu_addr(0),
-- data_in => cpu_data_out,
-- data_out => timer_data_out,
-- irq => timer_irq,
-- timer_in => CountL(5),
-- timer_out => timer_out
-- );
 
my_trap : trap port map (
clk => cpu_clk,
rst => cpu_reset,
cs => trap_cs,
rw => cpu_rw,
vma => cpu_vma,
addr => cpu_addr,
data_in => cpu_data_out,
data_out => trap_data_out,
irq => trap_irq
);
--my_ioport : ioport port map (
-- clk => SysClk,
-- rst => cpu_reset,
-- cs => ioport_cs,
-- rw => cpu_rw,
-- addr => cpu_addr(1 downto 0),
-- data_in => cpu_data_out,
-- data_out => ioport_data_out,
-- porta_io => porta,
-- portb_io => portb
-- );
 
my_ioport : ioport port map (
clk => cpu_clk,
rst => cpu_reset,
cs => ioport_cs,
rw => cpu_rw,
addr => cpu_addr(1 downto 0),
data_in => cpu_data_out,
data_out => ioport_data_out,
porta_io => porta,
portb_io => portb
my_rom : boot_rom port map (
addr => cpu_addr(10 downto 0),
data => rom_data_out
);
 
--my_rom : sbug_rom port map (
-- MEMclk => SysClk,
-- MEMaddr => cpu_addr(10 downto 0),
-- MEMrdata => rom_data_out
-- );
 
my_keyboard : keyboard port map(
clk => cpu_clk,
rst => cpu_reset,
cs => keyboard_cs,
rw => cpu_rw,
addr => cpu_addr(0),
data_in => cpu_data_out(7 downto 0),
data_out => keyboard_data_out(7 downto 0),
irq => keyboard_irq,
kbd_clk => kb_clock,
kbd_data => kb_data
);
my_dat : dat_ram port map (
clk => SysClk,
rst => cpu_reset,
cs => dat_cs,
rw => cpu_rw,
addr_hi => cpu_addr(15 downto 12),
addr_lo => cpu_addr(3 downto 0),
data_in => cpu_data_out,
data_out => dat_addr(7 downto 0)
);
 
----------------------------------------
--
-- Video Display Unit instantiation
--
----------------------------------------
my_vdu : vdu port map(
 
-- Control Registers
vdu_clk_in => SysClk, -- pixel Clock
vdu_clk_out => cpu_clk, -- memory access clock
vdu_rst => cpu_reset,
vdu_cs => vdu_cs,
vdu_rw => cpu_rw,
vdu_addr => cpu_addr(2 downto 0),
vdu_data_in => cpu_data_out,
vdu_data_out => vdu_data_out,
 
-- vga port connections
vga_red0_o => red_lo,
vga_red1_o => red_hi,
vga_green0_o => green_lo,
vga_green1_o => green_hi,
vga_blue0_o => blue_lo,
vga_blue1_o => blue_hi,
vga_hsync_o => h_drive,
vga_vsync_o => v_drive
);
 
--my_ram : block_ram port map (
-- MEMclk => cpu_clk,
-- MEMclk => SysClk,
-- MEMcs => xram_cs,
-- MEMrw => cpu_rw,
-- MEMaddr => cpu_addr(10 downto 0),
566,7 → 424,7
 
-- clk_buffer : BUFG port map(
-- i => e_clk,
-- o => cpu_clk
-- o => cpu_clk
-- );
----------------------------------------------------------------------
575,14 → 433,14
--
----------------------------------------------------------------------
 
mem_decode: process( cpu_clk, Reset_n,
mem_decode: process( SysClk, Reset_n,
cpu_addr, cpu_rw, cpu_vma,
dat_cs, dat_addr,
-- map_cs, map_sw,
rom_data_out, ram_data_out,
-- xram_data_out,
cf_data_out,
timer_data_out,
trap_data_out,
ioport_data_out,
-- timer_data_out, ioport_data_out,
uart_data_out )
begin
case cpu_addr(15 downto 11) is
591,17 → 449,50
--
when "11111" => -- $F800 - $FFFF
cpu_data_in <= rom_data_out; -- read ROM
dat_cs <= cpu_vma; -- write DAT
ram_cs <= '0';
uart_cs <= '0';
cf_cs <= '0';
timer_cs <= '0';
trap_cs <= '0';
ioport_cs <= '0';
keyboard_cs <= '0';
vdu_cs <= '0';
bus_cs <= '0';
dat_cs <= cpu_vma; -- write DAT
ram_cs <= '0';
uart_cs <= '0';
cf_cs <= '0';
-- timer_cs <= '0';
-- ioport_cs <= '0';
-- xram_cs <= '0';
-- map_cs <= '0';
 
--
-- Shadow RAM Monitor switch
--
-- when "11101" => -- $E800 - $EFFF
-- when "11111" => -- $F800 - $FFFF
-- if map_sw = '1' then
-- cpu_data_in <= rom_data_out; -- read ROM
-- dat_cs <= '0'; -- disable write to DAT
-- ram_cs <= cpu_vma; -- enable write to RAM
-- else
-- cpu_data_in <= ram_data_out; -- read RAM
-- dat_cs <= cpu_vma; -- enable write DAT
-- ram_cs <= cpu_vma and cpu_rw; -- disable write to RAM
-- end if;
-- uart_cs <= '0';
-- cf_cs <= '0';
-- timer_cs <= '0';
-- ioport_cs <= '0';
-- xram_cs <= cpu_vma;
-- map_cs <= '0';
 
--
-- Synchronous Block RAM $F000 - $F7FF
--
-- when "11110" => -- $F000 - $F7FF
-- cpu_data_in <= xram_data_out;
-- dat_cs <= '0';
-- ram_cs <= '0';
-- uart_cs <= '0';
-- cf_cs <= '0';
-- timer_cs <= '0';
-- ioport_cs <= '0';
-- xram_cs <= cpu_vma;
-- map_cs <= '0';
 
--
-- IO Devices $E000 - $E7FF
--
608,6 → 499,7
when "11100" => -- $E000 - $E7FF
dat_cs <= '0';
ram_cs <= '0';
-- xram_cs <= '0';
case cpu_addr(7 downto 4) is
--
-- UART / ACIA $E000
616,13 → 508,9
cpu_data_in <= uart_data_out;
uart_cs <= cpu_vma;
cf_cs <= '0';
timer_cs <= '0';
trap_cs <= '0';
ioport_cs <= '0';
keyboard_cs <= '0';
vdu_cs <= '0';
bus_cs <= '0';
 
-- timer_cs <= '0';
-- ioport_cs <= '0';
-- map_cs <= '0';
--
-- Compact Flash $E010 - $E01F
--
630,93 → 518,49
cpu_data_in <= cf_data_out;
uart_cs <= '0';
cf_cs <= cpu_vma;
timer_cs <= '0';
trap_cs <= '0';
ioport_cs <= '0';
keyboard_cs <= '0';
vdu_cs <= '0';
bus_cs <= '0';
 
-- timer_cs <= '0';
-- ioport_cs <= '0';
-- map_cs <= '0';
--
-- Timer $E020 - $E02F
--
when "0010" => -- $E020
cpu_data_in <= timer_data_out;
uart_cs <= '0';
cf_cs <= '0';
timer_cs <= cpu_vma;
trap_cs <= '0';
ioport_cs <= '0';
keyboard_cs <= '0';
vdu_cs <= '0';
bus_cs <= '0';
-- when "0010" => -- $E020
-- cpu_data_in <= timer_data_out;
-- uart_cs <= '0';
-- cf_cs <= '0';
-- timer_cs <= cpu_vma;
-- ioport_cs <= '0';
-- map_cs <= '0';
 
--
-- Bus Trap Logic $E030 - $E03F
-- ROM Map switch $E030
--
when "0011" => -- $E030
cpu_data_in <= trap_data_out;
uart_cs <= '0';
cf_cs <= '0';
timer_cs <= '0';
trap_cs <= cpu_vma;
ioport_cs <= '0';
keyboard_cs <= '0';
vdu_cs <= '0';
bus_cs <= '0';
-- when "0011" => -- $E030
-- cpu_data_in <= "00000000";
-- uart_cs <= '0';
-- cf_cs <= '0';
-- timer_cs <= '0';
-- ioport_cs <= '0';
-- map_cs <= cpu_vma;
 
--
-- I/O port $E040 - $E04F
--
when "0100" => -- $E040
cpu_data_in <= ioport_data_out;
uart_cs <= '0';
cf_cs <= '0';
timer_cs <= '0';
trap_cs <= '0';
ioport_cs <= cpu_vma;
keyboard_cs <= '0';
vdu_cs <= '0';
bus_cs <= '0';
-- when "0100" => -- $E040
-- cpu_data_in <= ioport_data_out;
-- uart_cs <= '0';
-- cf_cs <= '0';
-- timer_cs <= '0';
-- ioport_cs <= cpu_vma;
-- map_cs <= '0';
 
--
-- Keyboard port $E050 - $E05F
--
when "0101" => -- $E050
cpu_data_in <= keyboard_data_out;
when others => -- $E040 to $E7FF
cpu_data_in <= "00000000";
uart_cs <= '0';
cf_cs <= '0';
timer_cs <= '0';
trap_cs <= '0';
ioport_cs <= '0';
keyboard_cs <= cpu_vma;
vdu_cs <= '0';
bus_cs <= '0';
 
--
-- VDU port $E060 - $E06F
--
when "0110" => -- $E060
cpu_data_in <= vdu_data_out;
uart_cs <= '0';
cf_cs <= '0';
timer_cs <= '0';
trap_cs <= '0';
ioport_cs <= '0';
keyboard_cs <= '0';
vdu_cs <= cpu_vma;
bus_cs <= '0';
 
when others => -- $E060 to $E7FF
cpu_data_in <= bus_data;
uart_cs <= '0';
cf_cs <= '0';
timer_cs <= '0';
trap_cs <= '0';
ioport_cs <= '0';
keyboard_cs <= '0';
vdu_cs <= '0';
bus_cs <= cpu_vma;
-- timer_cs <= '0';
-- ioport_cs <= '0';
-- map_cs <= '0';
end case;
--
-- Everything else is RAM
727,32 → 571,29
dat_cs <= '0';
uart_cs <= '0';
cf_cs <= '0';
timer_cs <= '0';
trap_cs <= '0';
ioport_cs <= '0';
keyboard_cs <= '0';
vdu_cs <= '0';
bus_cs <= '0';
-- timer_cs <= '0';
-- ioport_cs <= '0';
-- xram_cs <= '0';
-- map_cs <= '0';
end case;
end process;
 
 
--
-- B5-SRAM Control
-- B3-SRAM Control
-- Processes to read and write memory based on bus signals
--
ram_process: process( cpu_clk, Reset_n,
ram_process: process( SysClk, Reset_n,
cpu_addr, cpu_rw, cpu_vma, cpu_data_out,
dat_addr,
ram_cs, ram_wrl, ram_wru, ram_data_out )
begin
ram_csn <= not( ram_cs and Reset_n );
ram_wrl <= (not cpu_addr(0)) and (not cpu_rw) and cpu_clk;
ram_wrl <= (not dat_addr(5)) and (not cpu_rw) and SysClk;
ram_wrln <= not (ram_wrl);
ram_wru <= cpu_addr(0) and (not cpu_rw) and cpu_clk;
ram_wru <= dat_addr(5) and (not cpu_rw) and SysClk;
ram_wrun <= not (ram_wru);
ram_addr(16 downto 11) <= dat_addr(5 downto 0);
ram_addr(10 downto 0) <= cpu_addr(11 downto 1);
ram_addr(16 downto 12) <= dat_addr(4 downto 0);
ram_addr(11 downto 0) <= cpu_addr(11 downto 0);
 
if ram_wrl = '1' then
ram_data(7 downto 0) <= cpu_data_out;
766,7 → 607,7
ram_data(15 downto 8) <= "ZZZZZZZZ";
end if;
 
if cpu_addr(0) = '1' then
if dat_addr(5) = '1' then
ram_data_out <= ram_data(15 downto 8);
else
ram_data_out <= ram_data(7 downto 0);
776,7 → 617,7
--
-- Compact Flash Control
--
compact_flash: process( cpu_clk, Reset_n,
compact_flash: process( SysClk, Reset_n,
cpu_addr, cpu_rw, cpu_vma, cpu_data_out,
cf_cs, cf_rd, cf_wr, cf_data_out )
begin
799,35 → 640,42
end process;
 
--
-- ROM Map switch
-- The Map switch output is initially set
-- On a Write to the Map Switch port, clear the Map Switch
-- and map the RAM in place of the boot ROM.
--
--map_proc : process( SysClk, Reset_n, map_cs, cpu_rw )
--begin
-- if SysClk'event and SysClk = '0' then
-- if Reset_n = '0' then
-- map_sw <= '1';
-- else
-- if (map_cs = '1') and (cpu_rw = '0') then
-- map_sw <= '0';
-- else
-- map_sw <= map_sw;
-- end if;
-- end if;
-- end if;
--end process;
 
--
-- Interrupts and other bus control signals
--
interrupts : process( Reset_n, uart_irq,
trap_irq, timer_irq, keyboard_irq
interrupts : process( Reset_n, uart_irq
-- ,timer_irq
)
begin
cpu_reset <= not Reset_n; -- CPU reset is active high
cpu_irq <= uart_irq or keyboard_irq;
cpu_nmi <= trap_irq;
cpu_firq <= timer_irq;
cpu_irq <= uart_irq;
-- cpu_nmi <= timer_irq;
cpu_nmi <= '0';
cpu_firq <= '0';
cpu_halt <= '0';
cpu_hold <= '0';
end process;
 
--
-- CPU bus signals
--
my_bus : process( cpu_clk, cpu_reset, cpu_rw, cpu_addr, cpu_data_out )
begin
bus_clk <= cpu_clk;
bus_reset <= cpu_reset;
bus_rw <= cpu_rw;
bus_addr <= cpu_addr;
if( cpu_rw = '1' ) then
bus_data <= "ZZZZZZZZ";
else
bus_data <= cpu_data_out;
end if;
end process;
 
--
-- flash led to indicate code is working
--
836,25 → 684,8
if(SysClk'event and SysClk = '0') then
countL <= countL + 1;
end if;
LED <= countL(23);
-- baudclk <= countL(5); -- 9.8MHz / 64 = 153,600 KHz = 9600Bd * 16
-- baudclk <= countL(4); -- 9.8MHz / 32 = 307,200 KHz = 19200Bd * 16
-- baudclk <= countL(3); -- 9.8MHz / 16 = 614,400 KHz = 38400Bd * 16
-- baudclk <= countL(2); -- 4.9MHz / 8 = 614,400 KHz = 38400Bd * 16
dcd_n <= '0';
LED <= countL(21);
end process;
 
my_clock: process( SysClk )
begin
if(SysClk'event and SysClk = '0') then
if( BaudCount = 26 ) then
BaudCount <= "00000";
else
BaudCount <= BaudCount + 1;
end if;
end if;
baudclk <= BaudCount(4); -- 25MHz / 27 = 926,000 KHz = 57,870Bd * 16
end process;
 
end my_computer; --===================== End of architecture =======================--
 

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