Subversion Repositories System09

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/branches/mkfiles_rev1/rtl/System09_Xilinx_ML506/my_system09.ise

branches/mkfiles_rev1/rtl/System09_Xilinx_ML506/my_system09.ise Property changes : Deleted: svn:mime-type ## -1 +0,0 ## -application/octet-stream \ No newline at end of property Index: branches/mkfiles_rev1/rtl/System09_Xilinx_ML506/my_system09.vhd =================================================================== --- branches/mkfiles_rev1/rtl/System09_Xilinx_ML506/my_system09.vhd (revision 56) +++ branches/mkfiles_rev1/rtl/System09_Xilinx_ML506/my_system09.vhd (nonexistent) @@ -1,958 +0,0 @@ ---===========================================================================---- --- --- S Y N T H E Z I A B L E System09 - SOC. --- --- www.OpenCores.Org - September 2003 --- This core adheres to the GNU public license --- --- File name : System09.vhd --- --- Purpose : Top level file for 6809 compatible system on a chip --- Designed with Xilinx XC3S200 Spartan 3 FPGA. --- Implemented With Digilent Xilinx Starter FPGA board, --- --- Dependencies : ieee.Std_Logic_1164 --- ieee.std_logic_unsigned --- ieee.std_logic_arith --- ieee.numeric_std --- --- Uses : mon_rom (sys09bug_rom4k_b16.vhd) Monitor ROM --- cpu09 (cpu09.vhd) CPU core --- dat_ram (datram.vhd) Dynamic Address Translation --- acia_6850 (acia_6850.vhd) ACIA (UART) --- (acia_rx.vhd) --- (acia_tx.vhd) --- keyboard (keyboard.vhd) PS/2 Keyboard --- (ps2_keyboard.vhd) --- (keymap_rom) --- vdu8 (vdu8.vhd) Video Display Unit --- (char_rom2K_b16.vhd) --- (ram2k_b16.vhd) --- seven_segment (SevenSegment.vhd) Seven Segment Display --- --- Author : John E. Kent --- dilbert57@opencores.org --- ---===========================================================================---- --- --- Revision History: ---===========================================================================-- --- Version 0.1 - 20 March 2003 --- Version 0.2 - 30 March 2003 --- Version 0.3 - 29 April 2003 --- Version 0.4 - 29 June 2003 --- --- Version 0.5 - 19 July 2003 --- prints out "Hello World" --- --- Version 0.6 - 5 September 2003 --- Runs SBUG --- --- Version 1.0- 6 Sep 2003 - John Kent --- Inverted sys_clk --- Initial release to Open Cores --- --- Version 1.1 - 17 Jan 2004 - John Kent --- Updated miniUart. --- --- Version 1.2 - 25 Jan 2004 - John Kent --- removed signals "test_alu" and "test_cc" --- Trap hardware re-instated. --- --- Version 1.3 - 11 Feb 2004 - John Kent --- Designed forked off to produce System09_VDU --- Added VDU component --- VDU runs at 25MHz and divides the clock by 2 for the CPU --- UART Runs at 57.6 Kbps --- --- Version 2.0 - 2 September 2004 - John Kent --- ported to Digilent Xilinx Spartan3 starter board --- removed Compaact Flash and Trap Logic. --- Replaced SBUG with KBug9s --- --- Version 2.1 - 21 November 2006 - John Kent --- Replaced KBug9s with Sys09bug 1.0 --- Inverted bottom nybble of DAT register outputs --- Changed ROM & I/O decoding to be compatible with SWTPc --- Upped the serial baud rate to 115.2 KBd --- added multiple global clock buffers --- (Uart would not operate correctly) --- --- Version 2.2 - 22 December 2006 - John Kent --- Increased CPU clock from 12.5MHz to 25 MHz. --- Removed some of the global clock buffers --- Added LED output register --- Changed address decoding to 4K Blocks --- --- Version 2.3 - 1 June 2007 - John Kent --- Updated VDU & ACIA --- Changed decoding for Sys09Bug --- --- Version 2.4 - 31 January 2008 - John Kent --- ACIA does not appear to work. --- Made RAM OE and WE strobes synchonous to sys_clk --- ---===========================================================================-- -library ieee; - use ieee.std_logic_1164.all; - use IEEE.STD_LOGIC_ARITH.ALL; - use IEEE.STD_LOGIC_UNSIGNED.ALL; - use ieee.numeric_std.all; - -entity my_system09 is - port( - sys_clk : in Std_Logic; -- System Clock input - rst_sw : in Std_logic; -- Master Reset input (active high) - nmi_sw : in Std_logic; - - -- Memory Interface signals - ram_addr : out Std_Logic_Vector(17 downto 0); - ram_wen : out Std_Logic; - ram_oen : out Std_Logic; - - ram1_cen : out Std_Logic; - ram1_ubn : out Std_Logic; - ram1_lbn : out Std_Logic; - ram1_data : inout Std_Logic_Vector(15 downto 0); - - ram2_cen : out Std_Logic; - ram2_ubn : out Std_Logic; - ram2_lbn : out Std_Logic; - ram2_data : inout Std_Logic_Vector(15 downto 0); - - -- PS/2 Keyboard - ps2c : inout Std_logic; - ps2d : inout Std_Logic; - - -- ACIA Interface - rxd : in Std_Logic; - txd : out Std_Logic; - - -- CRTC output signals - vs : out Std_Logic; - hs : out Std_Logic; - blue : out std_logic; - green : out std_logic; - red : out std_logic; - - -- LEDS & Switches - leds : out std_logic_vector(7 downto 0); - switches : in std_logic_vector(7 downto 0); - - -- seven segment display - segments : out std_logic_vector(7 downto 0); - digits : out std_logic_vector(3 downto 0) - ); -end my_system09; - -------------------------------------------------------------------------------- --- Architecture for System09 -------------------------------------------------------------------------------- -architecture my_computer of my_system09 is - ----------------------------------------------------------------------------- - -- constants - ----------------------------------------------------------------------------- - constant SYS_Clock_Frequency : integer := 50000000; -- FPGA System Clock - constant VGA_Clock_Frequency : integer := 25000000; -- VGA Pixel Clock - constant CPU_Clock_Frequency : integer := 25000000; -- CPU Clock - constant BAUD_Rate : integer := 57600; -- Baud Rate - constant ACIA_Clock_Frequency : integer := BAUD_Rate * 16; - - type hold_state_type is ( hold_release_state, hold_request_state ); - - ----------------------------------------------------------------------------- - -- Signals - ----------------------------------------------------------------------------- - -- BOOT ROM - signal rom_cs : Std_logic; - signal rom_data_out : Std_Logic_Vector(7 downto 0); - - -- FLEX9 RAM - signal flex_cs : Std_logic; - signal flex_data_out : Std_Logic_Vector(7 downto 0); - - -- ACIA Interface signals - signal acia_clk : std_logic; - signal acia_data_out : Std_Logic_Vector(7 downto 0); - signal acia_cs : Std_Logic; - signal acia_irq : Std_Logic; - signal acia_rxd : Std_Logic; - signal acia_txd : Std_Logic; - signal acia_dcd_n : Std_Logic; --- signal acia_rts_n : Std_Logic; - signal acia_cts_n : Std_Logic; - - -- keyboard port - signal keyboard_data_out : std_logic_vector(7 downto 0); - signal keyboard_cs : std_logic; - signal keyboard_irq : std_logic; - - -- LEDs - signal leds_data_out : std_logic_vector(7 downto 0); - signal leds_cs : std_logic; - - -- RAM - signal ram_cs : std_logic; -- memory chip select - signal ram_data_out : std_logic_vector(7 downto 0); - signal ram1_ce : std_logic; - signal ram1_ub : std_logic; - signal ram1_lb : std_logic; - signal ram2_ce : std_logic; - signal ram2_ub : std_logic; - signal ram2_lb : std_logic; - signal ram_we : std_logic; - signal ram_oe : std_logic; - - -- CPU Interface signals - signal cpu_reset : Std_Logic; - signal cpu_clk : Std_Logic; - signal cpu_rw : std_logic; - signal cpu_vma : std_logic; - signal cpu_halt : std_logic; - signal cpu_hold : std_logic; - signal cpu_firq : std_logic; - signal cpu_irq : std_logic; - signal cpu_nmi : std_logic; - signal cpu_addr : std_logic_vector(15 downto 0); - signal cpu_data_in : std_logic_vector(7 downto 0); - signal cpu_data_out : std_logic_vector(7 downto 0); - - -- Dynamic Address Translation - signal dat_cs : std_logic; - signal dat_addr : std_logic_vector(7 downto 0); - - -- Video Display Unit - signal vdu_cs : std_logic; - signal vdu_data_out : std_logic_vector(7 downto 0); - signal vga_clk : std_logic; - - -- 7 Segment Display - signal seg_cs : std_logic; - signal seg_data_out : std_logic_vector(7 downto 0); - - -- System Clock Prescaler - signal clk_count : std_logic; - ------------------------------------------------------------------ --- --- CPU09 CPU core --- ------------------------------------------------------------------ - -component cpu09 - port ( - clk : in std_logic; - rst : in std_logic; - rw : out std_logic; -- Asynchronous memory interface - vma : out std_logic; - address : out std_logic_vector(15 downto 0); - data_in : in std_logic_vector(7 downto 0); - data_out : out std_logic_vector(7 downto 0); - halt : in std_logic; - hold : in std_logic; - irq : in std_logic; - nmi : in std_logic; - firq : in std_logic - ); -end component; - - ----------------------------------------- --- --- 4KByte Block RAM Monitor ROM --- ----------------------------------------- -component mon_rom - Port ( - clk : in std_logic; - rst : in std_logic; - cs : in std_logic; - rw : in std_logic; - addr : in std_logic_vector (11 downto 0); - rdata : out std_logic_vector (7 downto 0); - wdata : in std_logic_vector (7 downto 0) - ); -end component; - ----------------------------------------- --- --- 8KBytes Block RAM for FLEX9 --- $C000 - $DFFF --- ----------------------------------------- -component flex_ram - Port ( - clk : in std_logic; - rst : in std_logic; - cs : in std_logic; - rw : in std_logic; - addr : in std_logic_vector (12 downto 0); - rdata : out std_logic_vector (7 downto 0); - wdata : in std_logic_vector (7 downto 0) - ); -end component; - ----------------------------------------- --- --- Dynamic Address Translation Registers --- ----------------------------------------- -component dat_ram - port ( - clk : in std_logic; - rst : in std_logic; - cs : in std_logic; - rw : in std_logic; - addr_lo : in std_logic_vector(3 downto 0); - addr_hi : in std_logic_vector(3 downto 0); - data_in : in std_logic_vector(7 downto 0); - data_out : out std_logic_vector(7 downto 0) - ); -end component; - ------------------------------------------------------------------ --- --- 6850 ACIA --- ------------------------------------------------------------------ - -component ACIA_6850 - port ( - clk : in Std_Logic; -- System Clock - rst : in Std_Logic; -- Reset input (active high) - cs : in Std_Logic; -- ACIA Chip Select - rw : in Std_Logic; -- Read / Not Write - irq : out Std_Logic; -- Interrupt - Addr : in Std_Logic; -- Register Select - DataIn : in Std_Logic_Vector(7 downto 0); -- Data Bus In - DataOut : out Std_Logic_Vector(7 downto 0); -- Data Bus Out - RxC : in Std_Logic; -- Receive Baud Clock - TxC : in Std_Logic; -- Transmit Baud Clock - RxD : in Std_Logic; -- Receive Data - TxD : out Std_Logic; -- Transmit Data - DCD_n : in Std_Logic; -- Data Carrier Detect - CTS_n : in Std_Logic; -- Clear To Send - RTS_n : out Std_Logic -- Request To send - ); -end component; - ------------------------------------------------------------------ --- --- ACIA Clock divider --- ------------------------------------------------------------------ - -component ACIA_Clock - generic ( - SYS_Clock_Frequency : integer := SYS_Clock_Frequency; - ACIA_Clock_Frequency : integer := ACIA_Clock_Frequency - ); - port ( - clk : in Std_Logic; -- System Clock Input - ACIA_clk : out Std_logic -- ACIA Clock output - ); -end component; - - ----------------------------------------- --- --- PS/2 Keyboard --- ----------------------------------------- - -component keyboard - generic( - KBD_Clock_Frequency : integer := CPU_Clock_Frequency - ); - port( - clk : in std_logic; - rst : in std_logic; - cs : in std_logic; - rw : in std_logic; - addr : in std_logic; - data_in : in std_logic_vector(7 downto 0); - data_out : out std_logic_vector(7 downto 0); - irq : out std_logic; - kbd_clk : inout std_logic; - kbd_data : inout std_logic - ); -end component; - ----------------------------------------- --- --- Video Display Unit. --- ----------------------------------------- -component vdu8 - generic( - VDU_CLOCK_FREQUENCY : integer := CPU_Clock_Frequency; -- HZ - VGA_CLOCK_FREQUENCY : integer := VGA_Clock_Frequency; -- HZ - VGA_HOR_CHARS : integer := 80; -- CHARACTERS - VGA_VER_CHARS : integer := 25; -- CHARACTERS - VGA_PIXELS_PER_CHAR : integer := 8; -- PIXELS - VGA_LINES_PER_CHAR : integer := 16; -- LINES - VGA_HOR_BACK_PORCH : integer := 40; -- PIXELS - VGA_HOR_SYNC : integer := 96; -- PIXELS - VGA_HOR_FRONT_PORCH : integer := 24; -- PIXELS - VGA_VER_BACK_PORCH : integer := 13; -- LINES - VGA_VER_SYNC : integer := 1; -- LINES - VGA_VER_FRONT_PORCH : integer := 36 -- LINES - ); - port( - -- control register interface - vdu_clk : in std_logic; -- CPU Clock - 12.5MHz - vdu_rst : in std_logic; - vdu_cs : in std_logic; - vdu_rw : in std_logic; - vdu_addr : in std_logic_vector(2 downto 0); - vdu_data_in : in std_logic_vector(7 downto 0); - vdu_data_out : out std_logic_vector(7 downto 0); - - -- vga port connections - vga_clk : in std_logic; -- VGA Pixel Clock - 25 MHz - vga_red_o : out std_logic; - vga_green_o : out std_logic; - vga_blue_o : out std_logic; - vga_hsync_o : out std_logic; - vga_vsync_o : out std_logic - ); -end component; - ----------------------------------------- --- --- Seven Segment Display driver --- ----------------------------------------- - -component seven_segment is - port ( - clk : in std_logic; - rst : in std_logic; - cs : in std_logic; - rw : in std_logic; - addr : in std_logic_vector(1 downto 0); - data_in : in std_logic_vector(7 downto 0); - data_out : out std_logic_vector(7 downto 0); - segments : out std_logic_vector(7 downto 0); - digits : out std_logic_vector(3 downto 0) - ); -end component; - -component BUFG - port ( - i : in std_logic; - o : out std_logic - ); -end component; - -begin - ----------------------------------------------------------------------------- - -- Instantiation of internal components - ----------------------------------------------------------------------------- - -my_cpu : cpu09 port map ( - clk => cpu_clk, - rst => cpu_reset, - rw => cpu_rw, - vma => cpu_vma, - address => cpu_addr(15 downto 0), - data_in => cpu_data_in, - data_out => cpu_data_out, - halt => cpu_halt, - hold => cpu_hold, - irq => cpu_irq, - nmi => cpu_nmi, - firq => cpu_firq - ); - -my_rom : mon_rom port map ( - clk => cpu_clk, - rst => cpu_reset, - cs => rom_cs, - rw => '1', - addr => cpu_addr(11 downto 0), - rdata => rom_data_out, - wdata => cpu_data_out - ); - -my_flex : flex_ram port map ( - clk => cpu_clk, - rst => cpu_reset, - cs => flex_cs, - rw => cpu_rw, - addr => cpu_addr(12 downto 0), - rdata => flex_data_out, - wdata => cpu_data_out - ); - -my_dat : dat_ram port map ( - clk => cpu_clk, - rst => cpu_reset, - cs => dat_cs, - rw => cpu_rw, - addr_hi => cpu_addr(15 downto 12), - addr_lo => cpu_addr(3 downto 0), - data_in => cpu_data_out, - data_out => dat_addr(7 downto 0) - ); - -my_acia : ACIA_6850 port map ( - clk => cpu_clk, - rst => cpu_reset, - cs => acia_cs, - rw => cpu_rw, - irq => acia_irq, - Addr => cpu_addr(0), - Datain => cpu_data_out, - DataOut => acia_data_out, - RxC => acia_clk, - TxC => acia_clk, - RxD => acia_rxd, - TxD => acia_txd, - DCD_n => acia_dcd_n, - CTS_n => acia_cts_n, - RTS_n => open - ); - - ----------------------------------------- --- --- ACIA Clock --- ----------------------------------------- -my_ACIA_Clock : ACIA_Clock - generic map( - SYS_Clock_Frequency => SYS_Clock_Frequency, - ACIA_Clock_Frequency => ACIA_Clock_Frequency - ) - port map( - clk => sys_clk, - acia_clk => acia_clk - ); - - ----------------------------------------- --- --- PS/2 Keyboard Interface --- ----------------------------------------- -my_keyboard : keyboard - generic map ( - KBD_Clock_Frequency => CPU_Clock_frequency - ) - port map( - clk => cpu_clk, - rst => cpu_reset, - cs => keyboard_cs, - rw => cpu_rw, - addr => cpu_addr(0), - data_in => cpu_data_out(7 downto 0), - data_out => keyboard_data_out(7 downto 0), - irq => keyboard_irq, - kbd_clk => ps2c, - kbd_data => ps2d - ); - ----------------------------------------- --- --- Video Display Unit instantiation --- ----------------------------------------- -my_vdu : vdu8 - generic map( - VDU_CLOCK_FREQUENCY => CPU_Clock_Frequency, -- HZ - VGA_CLOCK_FREQUENCY => VGA_Clock_Frequency, -- HZ - VGA_HOR_CHARS => 80, -- CHARACTERS - VGA_VER_CHARS => 25, -- CHARACTERS - VGA_PIXELS_PER_CHAR => 8, -- PIXELS - VGA_LINES_PER_CHAR => 16, -- LINES - VGA_HOR_BACK_PORCH => 40, -- PIXELS - VGA_HOR_SYNC => 96, -- PIXELS - VGA_HOR_FRONT_PORCH => 24, -- PIXELS - VGA_VER_BACK_PORCH => 13, -- LINES - VGA_VER_SYNC => 1, -- LINES - VGA_VER_FRONT_PORCH => 36 -- LINES - ) - port map( - - -- Control Registers - vdu_clk => cpu_clk, -- 12.5 MHz System Clock in - vdu_rst => cpu_reset, - vdu_cs => vdu_cs, - vdu_rw => cpu_rw, - vdu_addr => cpu_addr(2 downto 0), - vdu_data_in => cpu_data_out, - vdu_data_out => vdu_data_out, - - -- vga port connections - vga_clk => vga_clk, -- 25 MHz VDU pixel clock - vga_red_o => red, - vga_green_o => green, - vga_blue_o => blue, - vga_hsync_o => hs, - vga_vsync_o => vs - ); - - ----------------------------------------- --- --- Seven Segment Display instantiation --- ----------------------------------------- - -my_seg : seven_segment port map ( - clk => cpu_clk, - rst => cpu_reset, - cs => seg_cs, - rw => cpu_rw, - addr => cpu_addr(1 downto 0), - data_in => cpu_data_out, - data_out => seg_data_out, - segments => segments, - digits => digits - ); - - -vga_clk_buffer : BUFG port map( - i => clk_count, - o => vga_clk - ); - -cpu_clk_buffer : BUFG port map( - i => clk_count, - o => cpu_clk - ); - --- --- Clock divider --- Assumes 50 MHz system clock --- 25MHz pixel clock --- 25MHz CPU clock --- -sys09_clock : process( sys_clk, clk_count ) -begin - if sys_clk'event and sys_clk='1' then - clk_count <= not clk_count; - end if; -end process; - ----------------------------------------------------------------------- --- --- Process to decode memory map --- ----------------------------------------------------------------------- - -mem_decode: process( cpu_addr, cpu_rw, cpu_vma, - dat_cs, dat_addr, - rom_data_out, - acia_data_out, - keyboard_data_out, - vdu_data_out, - seg_data_out, - leds_data_out, - flex_data_out, - ram_data_out - ) -begin - cpu_data_in <= (others=>'0'); - dat_cs <= '0'; - rom_cs <= '0'; - acia_cs <= '0'; - keyboard_cs <= '0'; - vdu_cs <= '0'; - seg_cs <= '0'; - leds_cs <= '0'; - flex_cs <= '0'; - ram_cs <= '0'; --- timer_cs <= '0'; --- trap_cs <= '0'; --- pb_cs <= '0'; --- ide_cs <= '0'; --- ether_cs <= '0'; --- slot1_cs <= '0'; --- slot2_cs <= '0'; - - if cpu_addr( 15 downto 8 ) = "11111111" then - cpu_data_in <= rom_data_out; - dat_cs <= cpu_vma; -- write DAT - rom_cs <= cpu_vma; -- read ROM - -- - -- Sys09Bug Monitor ROM $F000 - $FFFF - -- - elsif dat_addr(3 downto 0) = "1111" then -- $XF000 - $XFFFF - -- - -- Monitor ROM $F000 - $FFFF - -- - cpu_data_in <= rom_data_out; - rom_cs <= cpu_vma; -- read ROM - - -- - -- IO Devices $E000 - $EFFF - -- - elsif dat_addr(3 downto 0) = "1110" then -- $XE000 - $XEFFF - case cpu_addr(11 downto 8) is - -- - -- SWTPC peripherals from $E000 to $E0FF - -- - when "0000" => - case cpu_addr(7 downto 4) is - -- - -- ACIA ($E000 - $E00F) - -- - when "0000" => - cpu_data_in <= acia_data_out; - acia_cs <= cpu_vma; - - -- - -- Reserved - FD1771 FDC ($E010 - $E01F) (SWTPC) - -- - - -- - -- Keyboard port ($E020 - $E02F) - -- - when "0010" => - cpu_data_in <= keyboard_data_out; - keyboard_cs <= cpu_vma; - - -- - -- VDU port ($E030 - $E03F) - -- - when "0011" => - cpu_data_in <= vdu_data_out; - vdu_cs <= cpu_vma; - - -- - -- Reserved - SWTPc MP-T ($E040 - $E04F) - -- - - -- - -- Reserved - Timer ($E050 - $E05F) (B5-X300) - -- - - -- - -- Reserved - Bus Trap Logic ($E060 - $E06F) (B5-X300) - -- - - -- - -- Reserved - I/O port ($E070 - $E07F) (B5-X300) - -- - - -- - -- Reserved - PTM 6840 ($E080 - $E08F) (SWTPC) - -- - - -- - -- Reserved - PIA Timer ($E090 - $E09F) (SWTPC) - -- - - -- - -- Read Switched port ($E0A0 - $E0AF) - -- Write LEDS - -- - when "1010" => - cpu_data_in <= leds_data_out; - leds_cs <= cpu_vma; - - -- - -- 7 segment display port ($E0B0 - $E0BF) - -- - when "1011" => - cpu_data_in <= seg_data_out; - seg_cs <= cpu_vma; - - - when others => -- $EXC0 to $EXFF - null; - end case; - -- - -- XST-3.0 Peripheral Bus goes here - -- $E100 to $E1FF - -- Four devices - -- IDE, Ethernet, Slot1, Slot2 - -- --- when "0001" => --- cpu_data_in <= pb_data_out; --- pb_cs <= cpu_vma; --- case cpu_addr(7 downto 6) is - -- - -- IDE Interface $E100 to $E13F - -- --- when "00" => --- ide_cs <= cpu_vma; - -- - -- Ethernet Interface $E140 to $E17F - -- --- when "01" => --- ether_cs <= cpu_vma; - -- - -- Slot 1 Interface $E180 to $E1BF - -- --- when "10" => --- slot1_cs <= cpu_vma; - -- - -- Slot 2 Interface $E1C0 to $E1FF - -- --- when "11" => --- slot2_cs <= cpu_vma; - -- - -- Nothing else - -- --- when others => --- null; --- end case; - -- - -- $E200 to $EFFF reserved for future use - -- - when others => - null; - end case; - -- - -- FLEX RAM $0C000 - $0DFFF - -- - elsif dat_addr(7 downto 1) = "0000110" then -- $0C000 - $0DFFF - cpu_data_in <= flex_data_out; - flex_cs <= cpu_vma; - -- - -- Everything else is RAM - -- - else - cpu_data_in <= ram_data_out; - ram_cs <= cpu_vma; - end if; -end process; - - --- --- 1M byte SRAM Control --- Processes to read and write memory based on bus signals --- -ram_process: process( cpu_reset, sys_clk, - cpu_addr, cpu_rw, cpu_vma, cpu_data_out, - dat_addr, ram_cs, - ram1_ce, ram1_ub, ram1_lb, ram1_data, - ram2_ce, ram2_ub, ram2_lb, ram2_data, - ram_we, ram_oe ) -begin - -- - -- ram_hold signal helps - -- - if( cpu_reset = '1' ) then - ram_we <= '0'; - ram_oe <= '0'; - -- - -- Clock Hold on rising edge - -- - elsif( sys_clk'event and sys_clk='1' ) then - if (ram_cs = '1') and (ram_we = '0') and (ram_oe = '0') then - ram_we <= not cpu_rw; - ram_oe <= cpu_rw; - else - ram_we <= '0'; - ram_oe <= '0'; - end if; - end if; - - ram_wen <= not ram_we; - ram_oen <= not ram_oe; - - ram1_ce <= ram_cs and (not cpu_addr(1)); - ram1_ub <= not cpu_addr(0); - ram1_lb <= cpu_addr(0); - ram1_cen <= not ram1_ce; - ram1_ubn <= not ram1_ub; - ram1_lbn <= not ram1_lb; - - ram2_ce <= ram_cs and cpu_addr(1); - ram2_ub <= not cpu_addr(0); - ram2_lb <= cpu_addr(0); - ram2_cen <= not ram2_ce; - ram2_ubn <= not ram2_ub; - ram2_lbn <= not ram2_lb; - - ram_addr(17 downto 10) <= dat_addr(7 downto 0); - ram_addr(9 downto 0) <= cpu_addr(11 downto 2); - - if ram_we = '1' and ram1_ce = '1' and ram1_lb = '1' then - ram1_data(7 downto 0) <= cpu_data_out; - else - ram1_data(7 downto 0) <= "ZZZZZZZZ"; - end if; - - if ram_we = '1' and ram1_ce = '1' and ram1_ub = '1' then - ram1_data(15 downto 8) <= cpu_data_out; - else - ram1_data(15 downto 8) <= "ZZZZZZZZ"; - end if; - - if ram_we = '1' and ram2_ce = '1' and ram2_lb = '1' then - ram2_data(7 downto 0) <= cpu_data_out; - else - ram2_data(7 downto 0) <= "ZZZZZZZZ"; - end if; - - if ram_we = '1' and ram2_ce = '1' and ram2_ub = '1' then - ram2_data(15 downto 8) <= cpu_data_out; - else - ram2_data(15 downto 8) <= "ZZZZZZZZ"; - end if; - - case cpu_addr(1 downto 0) is - when "00" => - ram_data_out <= ram1_data(15 downto 8); - when "01" => - ram_data_out <= ram1_data(7 downto 0); - when "10" => - ram_data_out <= ram2_data(15 downto 8); - when others => - ram_data_out <= ram2_data(7 downto 0); - end case; -end process; - --- --- LEDS output register --- -leds_output : process( cpu_clk, cpu_reset, switches ) -begin - if cpu_reset = '1' then - leds <= "00000000"; - elsif cpu_clk'event and cpu_clk='0' then - if leds_cs = '1' and cpu_rw = '0' then - leds <= cpu_data_out; - end if; - end if; - leds_data_out <= switches; -end process; - --- --- Interrupts and other bus control signals --- -interrupts : process( rst_sw, - acia_irq, - keyboard_irq, - nmi_sw - ) -begin - if sys_clk'event and sys_clk = '1' then - cpu_reset <= rst_sw; -- CPU reset is active high - end if; - cpu_firq <= keyboard_irq; - cpu_nmi <= nmi_sw; - cpu_irq <= acia_irq; - cpu_halt <= '0'; - cpu_hold <= '0'; -end process; - --- --- ACIA pin assignments --- -acia_assignments : process( rxd, acia_txd ) -begin - acia_dcd_n <= '0'; - acia_cts_n <= '0'; - acia_rxd <= rxd; - txd <= acia_txd; -end process; - - -end my_computer; --===================== End of architecture =======================-- - Index: branches/mkfiles_rev1/rtl/System09_Xilinx_ML506/ml50x_U1_fpga.ucf =================================================================== --- branches/mkfiles_rev1/rtl/System09_Xilinx_ML506/ml50x_U1_fpga.ucf (revision 56) +++ branches/mkfiles_rev1/rtl/System09_Xilinx_ML506/ml50x_U1_fpga.ucf (nonexistent) @@ -1,540 +0,0 @@ -NET AUDIO_BIT_CLK LOC="AF18"; # Bank 4, Vcco=3.3V, No DCI -NET AUDIO_SDATA_IN LOC="AE18"; # Bank 4, Vcco=3.3V, No DCI -NET AUDIO_SDATA_OUT LOC="AG16"; # Bank 4, Vcco=3.3V, No DCI -NET AUDIO_SYNC LOC="AF19"; # Bank 4, Vcco=3.3V, No DCI -NET BUS_ERROR_1 LOC="F6"; # Bank 12, Vcco=3.3V, DCI using 49.9 ohm resistors -NET BUS_ERROR_2 LOC="T10"; # Bank 12, Vcco=3.3V, DCI using 49.9 ohm resistors -NET CFG_ADDR_OUT0 LOC="AE12"; # Bank 2, Vcco=3.3V -NET CFG_ADDR_OUT1 LOC="AE13"; # Bank 2, Vcco=3.3V -NET CLK_27MHZ_FPGA LOC="AG18"; # Bank 4, Vcco=3.3V, No DCI -NET CLK_33MHZ_FPGA LOC="AH17"; # Bank 4, Vcco=3.3V, No DCI -NET CLK_FPGA_N LOC="K19"; # Bank 3, Vcco=2.5V, No DCI -NET CLK_FPGA_P LOC="L19"; # Bank 3, Vcco=2.5V, No DCI -NET CLKBUF_Q0_N LOC="H3"; # Bank 116, MGTREFCLKN_116, GTP_DUAL_X0Y4 -NET CLKBUF_Q0_P LOC="H4"; # Bank 116, MGTREFCLKP_116, GTP_DUAL_X0Y4 -NET CLKBUF_Q1_N LOC="J19"; # Bank 3, Vcco=2.5V, No DCI -NET CLKBUF_Q1_P LOC="K18"; # Bank 3, Vcco=2.5V, No DCI -NET CPLD_IO_1 LOC="W10"; # Bank 18, Vcco=3.3V, No DCI -NET CPU_TCK LOC="E6"; # Bank 12, Vcco=3.3V, DCI using 49.9 ohm resistors -NET CPU_TDO LOC="E7"; # Bank 12, Vcco=3.3V, DCI using 49.9 ohm resistors -NET CPU_TMS LOC="U10"; # Bank 12, Vcco=3.3V, DCI using 49.9 ohm resistors -NET CPU_TRST LOC="V10"; # Bank 18, Vcco=3.3V, No DCI -NET DDR2_A0 LOC="L30"; # Bank 15, Vcco=1.8V, DCI using 49.9 ohm resistors -NET DDR2_A1 LOC="M30"; # Bank 15, Vcco=1.8V, DCI using 49.9 ohm resistors -NET DDR2_A2 LOC="N29"; # Bank 15, Vcco=1.8V, DCI using 49.9 ohm resistors -NET DDR2_A3 LOC="P29"; # Bank 15, Vcco=1.8V, DCI using 49.9 ohm resistors -NET DDR2_A4 LOC="K31"; # Bank 15, Vcco=1.8V, DCI using 49.9 ohm resistors -NET DDR2_A5 LOC="L31"; # Bank 15, Vcco=1.8V, DCI using 49.9 ohm resistors -NET DDR2_A6 LOC="P31"; # Bank 15, Vcco=1.8V, DCI using 49.9 ohm resistors -NET DDR2_A7 LOC="P30"; # Bank 15, Vcco=1.8V, DCI using 49.9 ohm resistors -NET DDR2_A8 LOC="M31"; # Bank 15, Vcco=1.8V, DCI using 49.9 ohm resistors -NET DDR2_A9 LOC="R28"; # Bank 15, Vcco=1.8V, DCI using 49.9 ohm resistors -NET DDR2_A10 LOC="J31"; # Bank 15, Vcco=1.8V, DCI using 49.9 ohm resistors -NET DDR2_A11 LOC="R29"; # Bank 15, Vcco=1.8V, DCI using 49.9 ohm resistors -NET DDR2_A12 LOC="T31"; # Bank 15, Vcco=1.8V, DCI using 49.9 ohm resistors -NET DDR2_A13 LOC="H29"; # Bank 15, Vcco=1.8V, DCI using 49.9 ohm resistors -NET DDR2_BA0 LOC="G31"; # Bank 15, Vcco=1.8V, DCI using 49.9 ohm resistors -NET DDR2_BA1 LOC="J30"; # Bank 15, Vcco=1.8V, DCI using 49.9 ohm resistors -NET DDR2_BA2 LOC="R31"; # Bank 15, Vcco=1.8V, DCI using 49.9 ohm resistors -NET DDR2_CAS_B LOC="E31"; # Bank 15, Vcco=1.8V, DCI using 49.9 ohm resistors -NET DDR2_CKE0 LOC="T28"; # Bank 15, Vcco=1.8V, DCI using 49.9 ohm resistors -NET DDR2_CKE1 LOC="U30"; # Bank 15, Vcco=1.8V, DCI using 49.9 ohm resistors -NET DDR2_CLK0_N LOC="AJ29"; # Bank 21, Vcco=1.8V, DCI using 49.9 ohm resistors -NET DDR2_CLK0_P LOC="AK29"; # Bank 21, Vcco=1.8V, DCI using 49.9 ohm resistors -NET DDR2_CLK1_N LOC="F28"; # Bank 19, Vcco=1.8V, DCI using 49.9 ohm resistors -NET DDR2_CLK1_P LOC="E28"; # Bank 19, Vcco=1.8V, DCI using 49.9 ohm resistors -NET DDR2_CS0_B LOC="L29"; # Bank 15, Vcco=1.8V, DCI using 49.9 ohm resistors -NET DDR2_CS1_B LOC="J29"; # Bank 15, Vcco=1.8V, DCI using 49.9 ohm resistors -NET DDR2_D0 LOC="AF30"; # Bank 17, Vcco=1.8V, DCI using 49.9 ohm resistors -NET DDR2_D1 LOC="AK31"; # Bank 17, Vcco=1.8V, DCI using 49.9 ohm resistors -NET DDR2_D2 LOC="AF31"; # Bank 17, Vcco=1.8V, DCI using 49.9 ohm resistors -NET DDR2_D3 LOC="AD30"; # Bank 17, Vcco=1.8V, DCI using 49.9 ohm resistors -NET DDR2_D4 LOC="AJ30"; # Bank 17, Vcco=1.8V, DCI using 49.9 ohm resistors -NET DDR2_D5 LOC="AF29"; # Bank 17, Vcco=1.8V, DCI using 49.9 ohm resistors -NET DDR2_D6 LOC="AD29"; # Bank 17, Vcco=1.8V, DCI using 49.9 ohm resistors -NET DDR2_D7 LOC="AE29"; # Bank 17, Vcco=1.8V, DCI using 49.9 ohm resistors -NET DDR2_D8 LOC="AH27"; # Bank 21, Vcco=1.8V, DCI using 49.9 ohm resistors -NET DDR2_D9 LOC="AF28"; # Bank 21, Vcco=1.8V, DCI using 49.9 ohm resistors -NET DDR2_D10 LOC="AH28"; # Bank 21, Vcco=1.8V, DCI using 49.9 ohm resistors -NET DDR2_D11 LOC="AA28"; # Bank 21, Vcco=1.8V, DCI using 49.9 ohm resistors -NET DDR2_D12 LOC="AG25"; # Bank 21, Vcco=1.8V, DCI using 49.9 ohm resistors -NET DDR2_D13 LOC="AJ26"; # Bank 21, Vcco=1.8V, DCI using 49.9 ohm resistors -NET DDR2_D14 LOC="AG28"; # Bank 21, Vcco=1.8V, DCI using 49.9 ohm resistors -NET DDR2_D15 LOC="AB28"; # Bank 21, Vcco=1.8V, DCI using 49.9 ohm resistors -NET DDR2_D16 LOC="AC28"; # Bank 21, Vcco=1.8V, DCI using 49.9 ohm resistors -NET DDR2_D17 LOC="AB25"; # Bank 21, Vcco=1.8V, DCI using 49.9 ohm resistors -NET DDR2_D18 LOC="AC27"; # Bank 21, Vcco=1.8V, DCI using 49.9 ohm resistors -NET DDR2_D19 LOC="AA26"; # Bank 21, Vcco=1.8V, DCI using 49.9 ohm resistors -NET DDR2_D20 LOC="AB26"; # Bank 21, Vcco=1.8V, DCI using 49.9 ohm resistors -NET DDR2_D21 LOC="AA24"; # Bank 21, Vcco=1.8V, DCI using 49.9 ohm resistors -NET DDR2_D22 LOC="AB27"; # Bank 21, Vcco=1.8V, DCI using 49.9 ohm resistors -NET DDR2_D23 LOC="AA25"; # Bank 21, Vcco=1.8V, DCI using 49.9 ohm resistors -NET DDR2_D24 LOC="AC29"; # Bank 17, Vcco=1.8V, DCI using 49.9 ohm resistors -NET DDR2_D25 LOC="AB30"; # Bank 17, Vcco=1.8V, DCI using 49.9 ohm resistors -NET DDR2_D26 LOC="W31"; # Bank 17, Vcco=1.8V, DCI using 49.9 ohm resistors -NET DDR2_D27 LOC="V30"; # Bank 17, Vcco=1.8V, DCI using 49.9 ohm resistors -NET DDR2_D28 LOC="AC30"; # Bank 17, Vcco=1.8V, DCI using 49.9 ohm resistors -NET DDR2_D29 LOC="W29"; # Bank 17, Vcco=1.8V, DCI using 49.9 ohm resistors -NET DDR2_D30 LOC="V27"; # Bank 17, Vcco=1.8V, DCI using 49.9 ohm resistors -NET DDR2_D31 LOC="W27"; # Bank 17, Vcco=1.8V, DCI using 49.9 ohm resistors -NET DDR2_D32 LOC="V29"; # Bank 17, Vcco=1.8V, DCI using 49.9 ohm resistors -NET DDR2_D33 LOC="Y27"; # Bank 17, Vcco=1.8V, DCI using 49.9 ohm resistors -NET DDR2_D34 LOC="Y26"; # Bank 17, Vcco=1.8V, DCI using 49.9 ohm resistors -NET DDR2_D35 LOC="W24"; # Bank 17, Vcco=1.8V, DCI using 49.9 ohm resistors -NET DDR2_D36 LOC="V28"; # Bank 17, Vcco=1.8V, DCI using 49.9 ohm resistors -NET DDR2_D37 LOC="W25"; # Bank 17, Vcco=1.8V, DCI using 49.9 ohm resistors -NET DDR2_D38 LOC="W26"; # Bank 17, Vcco=1.8V, DCI using 49.9 ohm resistors -NET DDR2_D39 LOC="V24"; # Bank 17, Vcco=1.8V, DCI using 49.9 ohm resistors -NET DDR2_D40 LOC="R24"; # Bank 19, Vcco=1.8V, DCI using 49.9 ohm resistors -NET DDR2_D41 LOC="P25"; # Bank 19, Vcco=1.8V, DCI using 49.9 ohm resistors -NET DDR2_D42 LOC="N24"; # Bank 19, Vcco=1.8V, DCI using 49.9 ohm resistors -NET DDR2_D43 LOC="P26"; # Bank 19, Vcco=1.8V, DCI using 49.9 ohm resistors -NET DDR2_D44 LOC="T24"; # Bank 19, Vcco=1.8V, DCI using 49.9 ohm resistors -NET DDR2_D45 LOC="N25"; # Bank 19, Vcco=1.8V, DCI using 49.9 ohm resistors -NET DDR2_D46 LOC="P27"; # Bank 19, Vcco=1.8V, DCI using 49.9 ohm resistors -NET DDR2_D47 LOC="N28"; # Bank 19, Vcco=1.8V, DCI using 49.9 ohm resistors -NET DDR2_D48 LOC="M28"; # Bank 19, Vcco=1.8V, DCI using 49.9 ohm resistors -NET DDR2_D49 LOC="L28"; # Bank 19, Vcco=1.8V, DCI using 49.9 ohm resistors -NET DDR2_D50 LOC="F25"; # Bank 19, Vcco=1.8V, DCI using 49.9 ohm resistors -NET DDR2_D51 LOC="H25"; # Bank 19, Vcco=1.8V, DCI using 49.9 ohm resistors -NET DDR2_D52 LOC="K27"; # Bank 19, Vcco=1.8V, DCI using 49.9 ohm resistors -NET DDR2_D53 LOC="K28"; # Bank 19, Vcco=1.8V, DCI using 49.9 ohm resistors -NET DDR2_D54 LOC="H24"; # Bank 19, Vcco=1.8V, DCI using 49.9 ohm resistors -NET DDR2_D55 LOC="G26"; # Bank 19, Vcco=1.8V, DCI using 49.9 ohm resistors -NET DDR2_D56 LOC="G25"; # Bank 19, Vcco=1.8V, DCI using 49.9 ohm resistors -NET DDR2_D57 LOC="M26"; # Bank 19, Vcco=1.8V, DCI using 49.9 ohm resistors -NET DDR2_D58 LOC="J24"; # Bank 19, Vcco=1.8V, DCI using 49.9 ohm resistors -NET DDR2_D59 LOC="L26"; # Bank 19, Vcco=1.8V, DCI using 49.9 ohm resistors -NET DDR2_D60 LOC="J27"; # Bank 19, Vcco=1.8V, DCI using 49.9 ohm resistors -NET DDR2_D61 LOC="M25"; # Bank 19, Vcco=1.8V, DCI using 49.9 ohm resistors -NET DDR2_D62 LOC="L25"; # Bank 19, Vcco=1.8V, DCI using 49.9 ohm resistors -NET DDR2_D63 LOC="L24"; # Bank 19, Vcco=1.8V, DCI using 49.9 ohm resistors -NET DDR2_DM0 LOC="AJ31"; # Bank 17, Vcco=1.8V, DCI using 49.9 ohm resistors -NET DDR2_DM1 LOC="AE28"; # Bank 21, Vcco=1.8V, DCI using 49.9 ohm resistors -NET DDR2_DM2 LOC="Y24"; # Bank 21, Vcco=1.8V, DCI using 49.9 ohm resistors -NET DDR2_DM3 LOC="Y31"; # Bank 17, Vcco=1.8V, DCI using 49.9 ohm resistors -NET DDR2_DM4 LOC="V25"; # Bank 17, Vcco=1.8V, DCI using 49.9 ohm resistors -NET DDR2_DM5 LOC="P24"; # Bank 19, Vcco=1.8V, DCI using 49.9 ohm resistors -NET DDR2_DM6 LOC="F26"; # Bank 19, Vcco=1.8V, DCI using 49.9 ohm resistors -NET DDR2_DM7 LOC="J25"; # Bank 19, Vcco=1.8V, DCI using 49.9 ohm resistors -NET DDR2_DQS0_N LOC="AA30"; # Bank 17, Vcco=1.8V, DCI using 49.9 ohm resistors -NET DDR2_DQS0_P LOC="AA29"; # Bank 17, Vcco=1.8V, DCI using 49.9 ohm resistors -NET DDR2_DQS1_N LOC="AK27"; # Bank 21, Vcco=1.8V, DCI using 49.9 ohm resistors -NET DDR2_DQS1_P LOC="AK28"; # Bank 21, Vcco=1.8V, DCI using 49.9 ohm resistors -NET DDR2_DQS2_N LOC="AJ27"; # Bank 21, Vcco=1.8V, DCI using 49.9 ohm resistors -NET DDR2_DQS2_P LOC="AK26"; # Bank 21, Vcco=1.8V, DCI using 49.9 ohm resistors -NET DDR2_DQS3_N LOC="AA31"; # Bank 17, Vcco=1.8V, DCI using 49.9 ohm resistors -NET DDR2_DQS3_P LOC="AB31"; # Bank 17, Vcco=1.8V, DCI using 49.9 ohm resistors -NET DDR2_DQS4_N LOC="Y29"; # Bank 17, Vcco=1.8V, DCI using 49.9 ohm resistors -NET DDR2_DQS4_P LOC="Y28"; # Bank 17, Vcco=1.8V, DCI using 49.9 ohm resistors -NET DDR2_DQS5_N LOC="E27"; # Bank 19, Vcco=1.8V, DCI using 49.9 ohm resistors -NET DDR2_DQS5_P LOC="E26"; # Bank 19, Vcco=1.8V, DCI using 49.9 ohm resistors -NET DDR2_DQS6_N LOC="G28"; # Bank 19, Vcco=1.8V, DCI using 49.9 ohm resistors -NET DDR2_DQS6_P LOC="H28"; # Bank 19, Vcco=1.8V, DCI using 49.9 ohm resistors -NET DDR2_DQS7_N LOC="H27"; # Bank 19, Vcco=1.8V, DCI using 49.9 ohm resistors -NET DDR2_DQS7_P LOC="G27"; # Bank 19, Vcco=1.8V, DCI using 49.9 ohm resistors -NET DDR2_ODT0 LOC="F31"; # Bank 15, Vcco=1.8V, DCI using 49.9 ohm resistors -NET DDR2_ODT1 LOC="F30"; # Bank 15, Vcco=1.8V, DCI using 49.9 ohm resistors -NET DDR2_RAS_B LOC="H30"; # Bank 15, Vcco=1.8V, DCI using 49.9 ohm resistors -NET DDR2_SCL LOC="E29"; # Bank 15, Vcco=1.8V, DCI using 49.9 ohm resistors -NET DDR2_SDA LOC="F29"; # Bank 15, Vcco=1.8V, DCI using 49.9 ohm resistors -NET DDR2_WE_B LOC="K29"; # Bank 15, Vcco=1.8V, DCI using 49.9 ohm resistors -NET DVI_D0 LOC="AB8"; # Bank 22, Vcco=3.3V, DCI using 49.9 ohm resistors -NET DVI_D1 LOC="AC8"; # Bank 22, Vcco=3.3V, DCI using 49.9 ohm resistors -NET DVI_D2 LOC="AN12"; # Bank 22, Vcco=3.3V, DCI using 49.9 ohm resistors -NET DVI_D3 LOC="AP12"; # Bank 22, Vcco=3.3V, DCI using 49.9 ohm resistors -NET DVI_D4 LOC="AA9"; # Bank 22, Vcco=3.3V, DCI using 49.9 ohm resistors -NET DVI_D5 LOC="AA8"; # Bank 22, Vcco=3.3V, DCI using 49.9 ohm resistors -NET DVI_D6 LOC="AM13"; # Bank 22, Vcco=3.3V, DCI using 49.9 ohm resistors -NET DVI_D7 LOC="AN13"; # Bank 22, Vcco=3.3V, DCI using 49.9 ohm resistors -NET DVI_D8 LOC="AA10"; # Bank 22, Vcco=3.3V, DCI using 49.9 ohm resistors -NET DVI_D9 LOC="AB10"; # Bank 22, Vcco=3.3V, DCI using 49.9 ohm resistors -NET DVI_D10 LOC="AP14"; # Bank 22, Vcco=3.3V, DCI using 49.9 ohm resistors -NET DVI_D11 LOC="AN14"; # Bank 22, Vcco=3.3V, DCI using 49.9 ohm resistors -NET DVI_DE LOC="AE8"; # Bank 22, Vcco=3.3V, DCI using 49.9 ohm resistors -NET DVI_GPIO1 LOC="N30"; # Bank 15, Vcco=1.8V, DCI using 49.9 ohm resistors -NET DVI_H LOC="AM12"; # Bank 22, Vcco=3.3V, DCI using 49.9 ohm resistors -NET DVI_RESET_B LOC="AK6"; # Bank 18, Vcco=3.3V, No DCI -NET DVI_V LOC="AM11"; # Bank 22, Vcco=3.3V, DCI using 49.9 ohm resistors -NET DVI_XCLK_N LOC="AL10"; # Bank 22, Vcco=3.3V, DCI using 49.9 ohm resistors -NET DVI_XCLK_P LOC="AL11"; # Bank 22, Vcco=3.3V, DCI using 49.9 ohm resistors -NET FAN_ALERT_B LOC="T30"; # Bank 15, Vcco=1.8V, DCI using 49.9 ohm resistors -NET FLASH_ADV_B LOC="F13"; # Bank 20, Vcco=3.3V, DCI using 49.9 ohm resistors -NET FLASH_AUDIO_RESET_B LOC="AG17"; # Bank 4, Vcco=3.3V, No DCI -NET FLASH_CE_B LOC="AE14"; # Bank 2, Vcco=3.3V -NET FLASH_CLK LOC="N9"; # Bank 20, Vcco=3.3V, DCI using 49.9 ohm resistors -NET FLASH_OE_B LOC="AF14"; # Bank 2, Vcco=3.3V -NET FLASH_WAIT LOC="G13"; # Bank 20, Vcco=3.3V, DCI using 49.9 ohm resistors -NET FPGA_AVDD LOC="T18"; # Bank 0, Vcco=3.3V -NET FPGA_CCLK-R LOC="N15"; # Bank 0, Vcco=3.3V -NET FPGA_CPU_RESET_B LOC="E9"; # Bank 20, Vcco=3.3V, DCI using 49.9 ohm resistors -NET FPGA_CS_B LOC="N22"; # Bank 0, Vcco=3.3V -NET FPGA_CS0_B LOC="AF21"; # Bank 2, Vcco=3.3V -NET FPGA_DIFF_CLK_OUT_N LOC="J21"; # Bank 3, Vcco=2.5V, No DCI -NET FPGA_DIFF_CLK_OUT_P LOC="J20"; # Bank 3, Vcco=2.5V, No DCI -NET FPGA_DIN LOC="P15"; # Bank 0, Vcco=3.3V -NET FPGA_DONE LOC="M15"; # Bank 0, Vcco=3.3V -NET FPGA_DOUT_BUSY LOC="AD15"; # Bank 0, Vcco=3.3V -NET FPGA_DX_N LOC="W17"; # Bank 0, Vcco=3.3V -NET FPGA_DX_P LOC="W18"; # Bank 0, Vcco=3.3V -NET FPGA_EXP_TCK LOC="AB15"; # Bank 0, Vcco=3.3V -NET FPGA_EXP_TMS LOC="AC14"; # Bank 0, Vcco=3.3V -NET FPGA_HSWAPEN LOC="M23"; # Bank 0, Vcco=3.3V -NET FPGA_INIT_B LOC="N14"; # Bank 0, Vcco=3.3V -NET FPGA_M0 LOC="AD21"; # Bank 0, Vcco=3.3V -NET FPGA_M1 LOC="AC22"; # Bank 0, Vcco=3.3V -NET FPGA_M2 LOC="AD22"; # Bank 0, Vcco=3.3V -NET FPGA_PROG_B LOC="M22"; # Bank 0, Vcco=3.3V -NET FPGA_RDWR_B LOC="N23"; # Bank 0, Vcco=3.3V -NET FPGA_ROTARY_INCA LOC="AH30"; # Bank 17, Vcco=1.8V, DCI using 49.9 ohm resistors -NET FPGA_ROTARY_INCB LOC="AG30"; # Bank 17, Vcco=1.8V, DCI using 49.9 ohm resistors -NET FPGA_ROTARY_PUSH LOC="AH29"; # Bank 17, Vcco=1.8V, DCI using 49.9 ohm resistors -NET FPGA_SERIAL1_RX LOC="AG15"; # Bank 4, Vcco=3.3V, No DCI -NET FPGA_SERIAL1_TX LOC="AG20"; # Bank 4, Vcco=3.3V, No DCI -NET FPGA_SERIAL2_RX LOC="G10"; # Bank 20, Vcco=3.3V, DCI using 49.9 ohm resistors -NET FPGA_SERIAL2_TX LOC="F10"; # Bank 20, Vcco=3.3V, DCI using 49.9 ohm resistors -NET FPGA_TDI LOC="AC15"; # Bank 0, Vcco=3.3V -NET FPGA_TDO LOC="AD14"; # Bank 0, Vcco=3.3V -NET FPGA_V_N LOC="V17"; # Bank 0, Vcco=3.3V (SYSMON External Input: VN) J9-10 -NET FPGA_V_P LOC="U18"; # Bank 0, Vcco=3.3V (SYSMON External Input: VP) J9-9 -NET FPGA_VBATT LOC="L23"; # Bank 0, Vcco=3.3V -NET FPGA_VREFP LOC="V18"; # Bank 0, Vcco=3.3V -NET FPGA_VRN_B11 LOC="N33"; # Bank 11, Vcco=2.5V or 3.3V user selectable by J20 -NET FPGA_VRN_B13 LOC="AG33"; # Bank 13, Vcco=2.5V or 3.3V user selectable by J20 -NET FPGA_VRN_B17 LOC="AD31"; # Bank 17, Vcco=1.8V, DCI using 49.9 ohm resistors -NET FPGA_VRN_B19 LOC="N27"; # Bank 19, Vcco=1.8V, DCI using 49.9 ohm resistors -NET FPGA_VRN_B20 LOC="L10"; # Bank 20, Vcco=3.3V, DCI using 49.9 ohm resistors -NET FPGA_VRN_B21 LOC="AJ25"; # Bank 21, Vcco=1.8V, DCI using 49.9 ohm resistors -NET FPGA_VRN_B22 LOC="AF8"; # Bank 22, Vcco=3.3V, DCI using 49.9 ohm resistors -NET FPGA_VRP_B11 LOC="M33"; # Bank 11, Vcco=2.5V or 3.3V user selectable by J20 -NET FPGA_VRP_B13 LOC="AH33"; # Bank 13, Vcco=2.5V or 3.3V user selectable by J20 -NET FPGA_VRP_B17 LOC="AE31"; # Bank 17, Vcco=1.8V, DCI using 49.9 ohm resistors -NET FPGA_VRP_B19 LOC="M27"; # Bank 19, Vcco=1.8V, DCI using 49.9 ohm resistors -NET FPGA_VRP_B20 LOC="L11"; # Bank 20, Vcco=3.3V, DCI using 49.9 ohm resistors -NET FPGA_VRP_B21 LOC="AH25"; # Bank 21, Vcco=1.8V, DCI using 49.9 ohm resistors -NET FPGA_VRP_B22 LOC="AE9"; # Bank 22, Vcco=3.3V, DCI using 49.9 ohm resistors -NET GPIO_DIP_SW1 LOC="U25"; # Bank 15, Vcco=1.8V, DCI using 49.9 ohm resistors -NET GPIO_DIP_SW2 LOC="AG27"; # Bank 21, Vcco=1.8V, DCI using 49.9 ohm resistors -NET GPIO_DIP_SW3 LOC="AF25"; # Bank 21, Vcco=1.8V, DCI using 49.9 ohm resistors -NET GPIO_DIP_SW4 LOC="AF26"; # Bank 21, Vcco=1.8V, DCI using 49.9 ohm resistors -NET GPIO_DIP_SW5 LOC="AE27"; # Bank 21, Vcco=1.8V, DCI using 49.9 ohm resistors -NET GPIO_DIP_SW6 LOC="AE26"; # Bank 21, Vcco=1.8V, DCI using 49.9 ohm resistors -NET GPIO_DIP_SW7 LOC="AC25"; # Bank 21, Vcco=1.8V, DCI using 49.9 ohm resistors -NET GPIO_DIP_SW8 LOC="AC24"; # Bank 21, Vcco=1.8V, DCI using 49.9 ohm resistors -NET GPIO_LED_0 LOC="H18"; # Bank 3, Vcco=2.5V, No DCI -NET GPIO_LED_1 LOC="L18"; # Bank 3, Vcco=2.5V, No DCI -NET GPIO_LED_2 LOC="G15"; # Bank 3, Vcco=2.5V, No DCI -NET GPIO_LED_3 LOC="AD26"; # Bank 21, Vcco=1.8V, DCI using 49.9 ohm resistors -NET GPIO_LED_4 LOC="G16"; # Bank 3, Vcco=2.5V, No DCI -NET GPIO_LED_5 LOC="AD25"; # Bank 21, Vcco=1.8V, DCI using 49.9 ohm resistors -NET GPIO_LED_6 LOC="AD24"; # Bank 21, Vcco=1.8V, DCI using 49.9 ohm resistors -NET GPIO_LED_7 LOC="AE24"; # Bank 21, Vcco=1.8V, DCI using 49.9 ohm resistors -NET GPIO_LED_C LOC="E8"; # Bank 20, Vcco=3.3V, DCI using 49.9 ohm resistors -NET GPIO_LED_E LOC="AG23"; # Bank 2, Vcco=3.3V -NET GPIO_LED_N LOC="AF13"; # Bank 2, Vcco=3.3V -NET GPIO_LED_S LOC="AG12"; # Bank 2, Vcco=3.3V -NET GPIO_LED_W LOC="AF23"; # Bank 2, Vcco=3.3V -NET GPIO_SW_C LOC="AJ6"; # Bank 18, Vcco=3.3V, No DCI -NET GPIO_SW_E LOC="AK7"; # Bank 18, Vcco=3.3V, No DCI -NET GPIO_SW_N LOC="U8"; # Bank 18, Vcco=3.3V, No DCI -NET GPIO_SW_S LOC="V8"; # Bank 18, Vcco=3.3V, No DCI -NET GPIO_SW_W LOC="AJ7"; # Bank 18, Vcco=3.3V, No DCI -NET HDR1_2 LOC="H33"; # Bank 11, Vcco=2.5V or 3.3V user selectable by J20 -NET HDR1_4 LOC="F34"; # Bank 11, Vcco=2.5V or 3.3V user selectable by J20 -NET HDR1_6 LOC="H34"; # Bank 11, Vcco=2.5V or 3.3V user selectable by J20 -NET HDR1_8 LOC="G33"; # Bank 11, Vcco=2.5V or 3.3V user selectable by J20 -NET HDR1_10 LOC="G32"; # Bank 11, Vcco=2.5V or 3.3V user selectable by J20 -NET HDR1_12 LOC="H32"; # Bank 11, Vcco=2.5V or 3.3V user selectable by J20 -NET HDR1_14 LOC="J32"; # Bank 11, Vcco=2.5V or 3.3V user selectable by J20 -NET HDR1_16 LOC="J34"; # Bank 11, Vcco=2.5V or 3.3V user selectable by J20 -NET HDR1_18 LOC ="L33"; # Bank 11, Vcco=2.5V or 3.3V user selectable by J20 -NET HDR1_20 LOC="M32"; # Bank 11, Vcco=2.5V or 3.3V user selectable by J20 -NET HDR1_22 LOC="P34"; # Bank 11, Vcco=2.5V or 3.3V user selectable by J20 -NET HDR1_24 LOC="N34"; # Bank 11, Vcco=2.5V or 3.3V user selectable by J20 -NET HDR1_26 LOC="AA34"; # Bank 13, Vcco=2.5V or 3.3V user selectable by J20 (SYSMON External Input: VAUXP[5]) J6-26 -NET HDR1_28 LOC="AD32"; # Bank 13, Vcco=2.5V or 3.3V user selectable by J20 -NET HDR1_30 LOC="Y34"; # Bank 13, Vcco=2.5V or 3.3V user selectable by J20 (SYSMON External Input: VAUXN[5]) J6-30 -NET HDR1_32 LOC="Y32"; # Bank 13, Vcco=2.5V or 3.3V user selectable by J20 -NET HDR1_34 LOC="W32"; # Bank 13, Vcco=2.5V or 3.3V user selectable by J20 -NET HDR1_36 LOC="AH34"; # Bank 13, Vcco=2.5V or 3.3V user selectable by J20 -NET HDR1_38 LOC="AE32"; # Bank 13, Vcco=2.5V or 3.3V user selectable by J20 -NET HDR1_40 LOC="AG32"; # Bank 13, Vcco=2.5V or 3.3V user selectable by J20 -NET HDR1_42 LOC="AH32"; # Bank 13, Vcco=2.5V or 3.3V user selectable by J20 -NET HDR1_44 LOC="AK34"; # Bank 13, Vcco=2.5V or 3.3V user selectable by J20 -NET HDR1_46 LOC="AK33"; # Bank 13, Vcco=2.5V or 3.3V user selectable by J20 -NET HDR1_48 LOC="AJ32"; # Bank 13, Vcco=2.5V or 3.3V user selectable by J20 -NET HDR1_50 LOC="AK32"; # Bank 13, Vcco=2.5V or 3.3V user selectable by J20 -NET HDR1_52 LOC="AL34"; # Bank 13, Vcco=2.5V or 3.3V user selectable by J20 -NET HDR1_54 LOC="AL33"; # Bank 13, Vcco=2.5V or 3.3V user selectable by J20 -NET HDR1_56 LOC="AM33"; # Bank 13, Vcco=2.5V or 3.3V user selectable by J20 -NET HDR1_58 LOC="AJ34"; # Bank 13, Vcco=2.5V or 3.3V user selectable by J20 -NET HDR1_60 LOC="AM32"; # Bank 13, Vcco=2.5V or 3.3V user selectable by J20 -NET HDR1_62 LOC="AN34"; # Bank 13, Vcco=2.5V or 3.3V user selectable by J20 -NET HDR1_64 LOC="AN33"; # Bank 13, Vcco=2.5V or 3.3V user selectable by J20 -NET HDR2_2_SM_8_N LOC="K34"; # Bank 11, Vcco=2.5V or 3.3V user selectable by J20 (SYSMON External Input: VAUXN[15]) J4-2 -NET HDR2_4_SM_8_P LOC="L34"; # Bank 11, Vcco=2.5V or 3.3V user selectable by J20 (SYSMON External Input: VAUXP[15]) J4-4 -NET HDR2_6_SM_7_N LOC="K32"; # Bank 11, Vcco=2.5V or 3.3V user selectable by J20 (SYSMON External Input: VAUXN[14]) J4-6 -NET HDR2_8_SM_7_P LOC="K33"; # Bank 11, Vcco=2.5V or 3.3V user selectable by J20 (SYSMON External Input: VAUXP[14]) J4-8 -NET HDR2_10_DIFF_0_N LOC="N32"; # Bank 11, Vcco=2.5V or 3.3V user selectable by J20 (SYSMON External Input: VAUXN[13]) J4-10 -NET HDR2_12_DIFF_0_P LOC="P32"; # Bank 11, Vcco=2.5V or 3.3V user selectable by J20 (SYSMON External Input: VAUXP[13]) J4-12 -NET HDR2_14_DIFF_1_N LOC="R34"; # Bank 11, Vcco=2.5V or 3.3V user selectable by J20 (SYSMON External Input: VAUXN[12]) J4-14 -NET HDR2_16_DIFF_1_P LOC="T33"; # Bank 11, Vcco=2.5V or 3.3V user selectable by J20 (SYSMON External Input: VAUXP[12]) J4-16 -NET HDR2_18_DIFF_2_N LOC="R32"; # Bank 11, Vcco=2.5V or 3.3V user selectable by J20 (SYSMON External Input: VAUXN[11]) J4-18 -NET HDR2_20_DIFF_2_P LOC="R33"; # Bank 11, Vcco=2.5V or 3.3V user selectable by J20 (SYSMON External Input: VAUXP[11]) J4-20 -NET HDR2_22_SM_10_N LOC="T34"; # Bank 11, Vcco=2.5V or 3.3V user selectable by J20 (SYSMON External Input: VAUXN[10]) J4-22 -NET HDR2_24_SM_10_P LOC="U33"; # Bank 11, Vcco=2.5V or 3.3V user selectable by J20 (SYSMON External Input: VAUXP[10]) J4-24 -NET HDR2_26_SM_11_N LOC="U31"; # Bank 11, Vcco=2.5V or 3.3V user selectable by J20 (SYSMON External Input: VAUXN[9]) J4-26 -NET HDR2_28_SM_11_P LOC="U32"; # Bank 11, Vcco=2.5V or 3.3V user selectable by J20 (SYSMON External Input: VAUXP[9]) J4-28 -NET HDR2_30_DIFF_3_N LOC="V33"; # Bank 13, Vcco=2.5V or 3.3V user selectable by J20 (SYSMON External Input: VAUXN[8]) J4-30 -NET HDR2_32_DIFF_3_P LOC="V32"; # Bank 13, Vcco=2.5V or 3.3V user selectable by J20 (SYSMON External Input: VAUXP[8]) J4-32 -NET HDR2_34_SM_15_N LOC="V34"; # Bank 13, Vcco=2.5V or 3.3V user selectable by J20 (SYSMON External Input: VAUXN[7]) J4-34 -NET HDR2_36_SM_15_P LOC="W34"; # Bank 13, Vcco=2.5V or 3.3V user selectable by J20 (SYSMON External Input: VAUXP[7]) J4-36 -NET HDR2_38_SM_6_N LOC="AA33"; # Bank 13, Vcco=2.5V or 3.3V user selectable by J20 (SYSMON External Input: VAUXN[6]) J4-38 -NET HDR2_40_SM_6_P LOC="Y33"; # Bank 13, Vcco=2.5V or 3.3V user selectable by J20 (SYSMON External Input: VAUXP[6]) J4-40 -NET HDR2_42_SM_14_N LOC="AE34"; # Bank 13, Vcco=2.5V or 3.3V user selectable by J20 (SYSMON External Input: VAUXN[0]) J4-42 -NET HDR2_44_SM_14_P LOC="AF34"; # Bank 13, Vcco=2.5V or 3.3V user selectable by J20 (SYSMON External Input: VAUXP[0]) J4-44 -NET HDR2_46_SM_12_N LOC="AE33"; # Bank 13, Vcco=2.5V or 3.3V user selectable by J20 (SYSMON External Input: VAUXN[1]) J4-46 -NET HDR2_48_SM_12_P LOC="AF33"; # Bank 13, Vcco=2.5V or 3.3V user selectable by J20 (SYSMON External Input: VAUXP[1]) J4-48 -NET HDR2_50_SM_5_N LOC="AD34"; # Bank 13, Vcco=2.5V or 3.3V user selectable by J20 (SYSMON External Input: VAUXN[4]) J4-50 -NET HDR2_52_SM_5_P LOC="AC34"; # Bank 13, Vcco=2.5V or 3.3V user selectable by J20 (SYSMON External Input: VAUXP[4]) J4-52 -NET HDR2_54_SM_13_N LOC="AB32"; # Bank 13, Vcco=2.5V or 3.3V user selectable by J20 (SYSMON External Input: VAUXN[3]) J4-54 -NET HDR2_56_SM_13_P LOC="AC32"; # Bank 13, Vcco=2.5V or 3.3V user selectable by J20 (SYSMON External Input: VAUXP[3]) J4-56 -NET HDR2_58_SM_4_N LOC="AB33"; # Bank 13, Vcco=2.5V or 3.3V user selectable by J20 (SYSMON External Input: VAUXN[2]) J4-58 -NET HDR2_60_SM_4_P LOC="AC33"; # Bank 13, Vcco=2.5V or 3.3V user selectable by J20 (SYSMON External Input: VAUXP[2]) J4-60 -NET HDR2_62_SM_9_N LOC="AP32"; # Bank 13, Vcco=2.5V or 3.3V user selectable by J20 -NET HDR2_64_SM_9_P LOC="AN32"; # Bank 13, Vcco=2.5V or 3.3V user selectable by J20 -NET IIC_SCL_MAIN LOC="F9"; # Bank 20, Vcco=3.3V, DCI using 49.9 ohm resistors -NET IIC_SCL_SFP LOC="R26"; # Bank 15, Vcco=1.8V, DCI using 49.9 ohm resistors -NET IIC_SCL_VIDEO LOC="U27"; # Bank 15, Vcco=1.8V, DCI using 49.9 ohm resistors -NET IIC_SDA_MAIN LOC="F8"; # Bank 20, Vcco=3.3V, DCI using 49.9 ohm resistors -NET IIC_SDA_SFP LOC="U28"; # Bank 15, Vcco=1.8V, DCI using 49.9 ohm resistors -NET IIC_SDA_VIDEO LOC="T29"; # Bank 15, Vcco=1.8V, DCI using 49.9 ohm resistors -NET KEYBOARD_CLK LOC="T26"; # Bank 15, Vcco=1.8V, DCI using 49.9 ohm resistors -NET KEYBOARD_DATA LOC="T25"; # Bank 15, Vcco=1.8V, DCI using 49.9 ohm resistors -NET LCD_FPGA_DB4 LOC="T9"; # Bank 12, Vcco=3.3V, DCI using 49.9 ohm resistors -NET LCD_FPGA_DB5 LOC="G7"; # Bank 12, Vcco=3.3V, DCI using 49.9 ohm resistors -NET LCD_FPGA_DB6 LOC="G6"; # Bank 12, Vcco=3.3V, DCI using 49.9 ohm resistors -NET LCD_FPGA_DB7 LOC="T11"; # Bank 12, Vcco=3.3V, DCI using 49.9 ohm resistors -NET LCD_FPGA_E LOC="AC9"; # Bank 22, Vcco=3.3V, DCI using 49.9 ohm resistors -NET LCD_FPGA_RS LOC="J17"; # Bank 3, Vcco=2.5V, No DCI -NET LCD_FPGA_RW LOC="AC10"; # Bank 22, Vcco=3.3V, DCI using 49.9 ohm resistors -NET LOOPBK_114_N LOC="AG1"; # Bank 118, MGTRXN1_118, GTP_DUAL_X0Y1 -NET LOOPBK_114_N LOC="AH2"; # Bank 118, MGTTXN1_118, GTP_DUAL_X0Y1 -NET LOOPBK_114_P LOC="AH1"; # Bank 118, MGTRXP1_118, GTP_DUAL_X0Y1 -NET LOOPBK_114_P LOC="AJ2"; # Bank 118, MGTTXP1_118, GTP_DUAL_X0Y1 -NET LOOPBK_116_N LOC="R1"; # Bank 112, MGTRXN1_112, GTP_DUAL_X0Y3 -NET LOOPBK_116_N LOC="T2"; # Bank 112, MGTTXN1_112, GTP_DUAL_X0Y3 -NET LOOPBK_116_P LOC="T1"; # Bank 112, MGTRXP1_112, GTP_DUAL_X0Y3 -NET LOOPBK_116_P LOC="U2"; # Bank 112, MGTTXP1_112, GTP_DUAL_X0Y3 -NET MOUSE_CLK LOC="R27"; # Bank 15, Vcco=1.8V, DCI using 49.9 ohm resistors -NET MOUSE_DATA LOC="U26"; # Bank 15, Vcco=1.8V, DCI using 49.9 ohm resistors -NET PC4_HALT_B LOC="W9"; # Bank 18, Vcco=3.3V, No DCI -NET PCIE_CLK_QO_N LOC="AF3"; # Bank 118, MGTREFCLKN_118, GTP_DUAL_X0Y1 -NET PCIE_CLK_QO_P LOC="AF4"; # Bank 118, MGTREFCLKP_118, GTP_DUAL_X0Y1 -NET PCIE_PRSNT_B_FPGA LOC="AF24"; # Bank 21, Vcco=1.8V, DCI using 49.9 ohm resistors -NET PCIE_RX_N LOC="AF1"; # Bank 118, MGTRXN0_118, GTP_DUAL_X0Y1 -NET PCIE_RX_P LOC="AE1"; # Bank 118, MGTRXP0_118, GTP_DUAL_X0Y1 -NET PCIE_TX_N LOC="AE2"; # Bank 118, MGTTXN0_118, GTP_DUAL_X0Y1 -NET PCIE_TX_P LOC="AD2"; # Bank 118, MGTTXP0_118, GTP_DUAL_X0Y1 -NET PHY_COL LOC="B32"; # Bank 11, Vcco=2.5V or 3.3V user selectable by J20 -NET PHY_CRS LOC="E34"; # Bank 11, Vcco=2.5V or 3.3V user selectable by J20 -NET PHY_INT LOC="H20"; # Bank 3, Vcco=2.5V, No DCI -NET PHY_MDC LOC="H19"; # Bank 3, Vcco=2.5V, No DCI -NET PHY_MDIO LOC="H13"; # Bank 3, Vcco=2.5V, No DCI -NET PHY_RESET LOC="J14"; # Bank 3, Vcco=2.5V, No DCI -NET PHY_RXCLK LOC="H17"; # Bank 3, Vcco=2.5V, No DCI -NET PHY_RXCTL_RXDV LOC="E32"; # Bank 11, Vcco=2.5V or 3.3V user selectable by J20 -NET PHY_RXD0 LOC="A33"; # Bank 11, Vcco=2.5V or 3.3V user selectable by J20 -NET PHY_RXD1 LOC="B33"; # Bank 11, Vcco=2.5V or 3.3V user selectable by J20 -NET PHY_RXD2 LOC="C33"; # Bank 11, Vcco=2.5V or 3.3V user selectable by J20 -NET PHY_RXD3 LOC="C32"; # Bank 11, Vcco=2.5V or 3.3V user selectable by J20 -NET PHY_RXD4 LOC="D32"; # Bank 11, Vcco=2.5V or 3.3V user selectable by J20 -NET PHY_RXD5 LOC="C34"; # Bank 11, Vcco=2.5V or 3.3V user selectable by J20 -NET PHY_RXD6 LOC="D34"; # Bank 11, Vcco=2.5V or 3.3V user selectable by J20 -NET PHY_RXD7 LOC="F33"; # Bank 11, Vcco=2.5V or 3.3V user selectable by J20 -NET PHY_RXER LOC="E33"; # Bank 11, Vcco=2.5V or 3.3V user selectable by J20 -NET PHY_TXC_GTXCLK LOC="J16"; # Bank 3, Vcco=2.5V, No DCI -NET PHY_TXCLK LOC="K17"; # Bank 3, Vcco=2.5V, No DCI -NET PHY_TXCTL_TXEN LOC="AJ10"; # Bank 22, Vcco=3.3V, DCI using 49.9 ohm resistors -NET PHY_TXD0 LOC="AF11"; # Bank 22, Vcco=3.3V, DCI using 49.9 ohm resistors -NET PHY_TXD1 LOC="AE11"; # Bank 22, Vcco=3.3V, DCI using 49.9 ohm resistors -NET PHY_TXD2 LOC="AH9"; # Bank 22, Vcco=3.3V, DCI using 49.9 ohm resistors -NET PHY_TXD3 LOC="AH10"; # Bank 22, Vcco=3.3V, DCI using 49.9 ohm resistors -NET PHY_TXD4 LOC="AG8"; # Bank 22, Vcco=3.3V, DCI using 49.9 ohm resistors -NET PHY_TXD5 LOC="AH8"; # Bank 22, Vcco=3.3V, DCI using 49.9 ohm resistors -NET PHY_TXD6 LOC="AG10"; # Bank 22, Vcco=3.3V, DCI using 49.9 ohm resistors -NET PHY_TXD7 LOC="AG11"; # Bank 22, Vcco=3.3V, DCI using 49.9 ohm resistors -NET PHY_TXER LOC="AJ9"; # Bank 22, Vcco=3.3V, DCI using 49.9 ohm resistors -NET PIEZO_SPEAKER LOC="G30"; # Bank 15, Vcco=1.8V, DCI using 49.9 ohm resistors -NET RESERVED1 LOC="AB23"; # Bank 0, Vcco=3.3V -NET RESERVED2 LOC="AC23"; # Bank 0, Vcco=3.3V -NET RREF LOC="V4"; # Bank 112, MGTRREF_112, GTP_DUAL_X0Y3 -NET SATA1_RX_N LOC="Y1"; # Bank 114, MGTRXN0_114, GTP_DUAL_X0Y2 -NET SATA1_RX_P LOC="W1"; # Bank 114, MGTRXP0_114, GTP_DUAL_X0Y2 -NET SATA1_TX_N LOC="W2"; # Bank 114, MGTTXN0_114, GTP_DUAL_X0Y2 -NET SATA1_TX_P LOC="V2"; # Bank 114, MGTTXP0_114, GTP_DUAL_X0Y2 -NET SATA2_RX_N LOC="AA1"; # Bank 114, MGTRXN1_114, GTP_DUAL_X0Y2 -NET SATA2_RX_P LOC="AB1"; # Bank 114, MGTRXP1_114, GTP_DUAL_X0Y2 -NET SATA2_TX_N LOC="AB2"; # Bank 114, MGTTXN1_114, GTP_DUAL_X0Y2 -NET SATA2_TX_P LOC="AC2"; # Bank 114, MGTTXP1_114, GTP_DUAL_X0Y2 -NET SATACLK_QO_N LOC="Y3"; # Bank 114, MGTREFCLKN_114, GTP_DUAL_X0Y2 -NET SATACLK_QO_P LOC="Y4"; # Bank 114, MGTREFCLKP_114, GTP_DUAL_X0Y2 -NET SFP_RX_N LOC="H1"; # Bank 116, MGTRXN0_116, GTP_DUAL_X0Y4 -NET SFP_RX_P LOC="G1"; # Bank 116, MGTRXP0_116, GTP_DUAL_X0Y4 -NET SFP_TX_DISABLE_FPGA LOC="K24"; # Bank 19, Vcco=1.8V, DCI using 49.9 ohm resistors -NET SFP_TX_N LOC="G2"; # Bank 116, MGTTXN0_116, GTP_DUAL_X0Y4 -NET SFP_TX_P LOC="F2"; # Bank 116, MGTTXP0_116, GTP_DUAL_X0Y4 -NET SGMII_RX_N LOC="P1"; # Bank 112, MGTRXN0_112, GTP_DUAL_X0Y3 -NET SGMII_RX_P LOC="N1"; # Bank 112, MGTRXP0_112, GTP_DUAL_X0Y3 -NET SGMII_TX_N LOC="N2"; # Bank 112, MGTTXN0_112, GTP_DUAL_X0Y3 -NET SGMII_TX_P LOC="M2"; # Bank 112, MGTTXP0_112, GTP_DUAL_X0Y3 -NET SGMIICLK_QO_N LOC="P3"; # Bank 112, MGTREFCLKN_112, GTP_DUAL_X0Y3 -NET SGMIICLK_QO_P LOC="P4"; # Bank 112, MGTREFCLKP_112, GTP_DUAL_X0Y3 -NET SMA_DIFF_CLK_IN_N LOC="H15"; # Bank 3, Vcco=2.5V, No DCI -NET SMA_DIFF_CLK_IN_P LOC="H14"; # Bank 3, Vcco=2.5V, No DCI -NET SMA_RX_N LOC="J1"; # Bank 116, MGTRXN1_116, GTP_DUAL_X0Y4 -NET SMA_RX_P LOC="K1"; # Bank 116, MGTRXP1_116, GTP_DUAL_X0Y4 -NET SMA_TX_N LOC="K2"; # Bank 116, MGTTXN1_116, GTP_DUAL_X0Y4 -NET SMA_TX_P LOC="L2"; # Bank 116, MGTTXP1_116, GTP_DUAL_X0Y4 -NET SPI_CE_B LOC="V9"; # Bank 18, Vcco=3.3V, No DCI -NET SRAM_ADV_LD_B LOC="H8"; # Bank 20, Vcco=3.3V, DCI using 49.9 ohm resistors -NET SRAM_BW0 LOC="D10"; # Bank 20, Vcco=3.3V, DCI using 49.9 ohm resistors -NET SRAM_BW1 LOC="D11"; # Bank 20, Vcco=3.3V, DCI using 49.9 ohm resistors -NET SRAM_BW2 LOC="J11"; # Bank 20, Vcco=3.3V, DCI using 49.9 ohm resistors -NET SRAM_BW3 LOC="K11"; # Bank 20, Vcco=3.3V, DCI using 49.9 ohm resistors -NET SRAM_CLK LOC="AG21"; # Bank 4, Vcco=3.3V, No DCI -NET SRAM_CLK LOC="G8"; # Bank 20, Vcco=3.3V, DCI using 49.9 ohm resistors -NET SRAM_CS_B LOC="J10"; # Bank 20, Vcco=3.3V, DCI using 49.9 ohm resistors -NET SRAM_D16 LOC="N10"; # Bank 20, Vcco=3.3V, DCI using 49.9 ohm resistors -NET SRAM_D17 LOC="E13"; # Bank 20, Vcco=3.3V, DCI using 49.9 ohm resistors -NET SRAM_D18 LOC="E12"; # Bank 20, Vcco=3.3V, DCI using 49.9 ohm resistors -NET SRAM_D19 LOC="L9"; # Bank 20, Vcco=3.3V, DCI using 49.9 ohm resistors -NET SRAM_D20 LOC="M10"; # Bank 20, Vcco=3.3V, DCI using 49.9 ohm resistors -NET SRAM_D21 LOC="E11"; # Bank 20, Vcco=3.3V, DCI using 49.9 ohm resistors -NET SRAM_D22 LOC="F11"; # Bank 20, Vcco=3.3V, DCI using 49.9 ohm resistors -NET SRAM_D23 LOC="L8"; # Bank 20, Vcco=3.3V, DCI using 49.9 ohm resistors -NET SRAM_D24 LOC="M8"; # Bank 20, Vcco=3.3V, DCI using 49.9 ohm resistors -NET SRAM_D25 LOC="G12"; # Bank 20, Vcco=3.3V, DCI using 49.9 ohm resistors -NET SRAM_D26 LOC="G11"; # Bank 20, Vcco=3.3V, DCI using 49.9 ohm resistors -NET SRAM_D27 LOC="C13"; # Bank 20, Vcco=3.3V, DCI using 49.9 ohm resistors -NET SRAM_D28 LOC="B13"; # Bank 20, Vcco=3.3V, DCI using 49.9 ohm resistors -NET SRAM_D29 LOC="K9"; # Bank 20, Vcco=3.3V, DCI using 49.9 ohm resistors -NET SRAM_D30 LOC="K8"; # Bank 20, Vcco=3.3V, DCI using 49.9 ohm resistors -NET SRAM_D31 LOC="J9"; # Bank 20, Vcco=3.3V, DCI using 49.9 ohm resistors -NET SRAM_DQP0 LOC="D12"; # Bank 20, Vcco=3.3V, DCI using 49.9 ohm resistors -NET SRAM_DQP1 LOC="C12"; # Bank 20, Vcco=3.3V, DCI using 49.9 ohm resistors -NET SRAM_DQP2 LOC="H10"; # Bank 20, Vcco=3.3V, DCI using 49.9 ohm resistors -NET SRAM_DQP3 LOC="H9"; # Bank 20, Vcco=3.3V, DCI using 49.9 ohm resistors -NET SRAM_FLASH_A0 LOC="K12"; # Bank 1, Vcco=3.3V -NET SRAM_FLASH_A1 LOC="K13"; # Bank 1, Vcco=3.3V -NET SRAM_FLASH_A2 LOC="H23"; # Bank 1, Vcco=3.3V -NET SRAM_FLASH_A3 LOC="G23"; # Bank 1, Vcco=3.3V -NET SRAM_FLASH_A4 LOC="H12"; # Bank 1, Vcco=3.3V -NET SRAM_FLASH_A5 LOC="J12"; # Bank 1, Vcco=3.3V -NET SRAM_FLASH_A6 LOC="K22"; # Bank 1, Vcco=3.3V -NET SRAM_FLASH_A7 LOC="K23"; # Bank 1, Vcco=3.3V -NET SRAM_FLASH_A8 LOC="K14"; # Bank 1, Vcco=3.3V -NET SRAM_FLASH_A9 LOC="L14"; # Bank 1, Vcco=3.3V -NET SRAM_FLASH_A10 LOC="H22"; # Bank 1, Vcco=3.3V -NET SRAM_FLASH_A11 LOC="G22"; # Bank 1, Vcco=3.3V -NET SRAM_FLASH_A12 LOC="J15"; # Bank 1, Vcco=3.3V -NET SRAM_FLASH_A13 LOC="K16"; # Bank 1, Vcco=3.3V -NET SRAM_FLASH_A14 LOC="K21"; # Bank 1, Vcco=3.3V -NET SRAM_FLASH_A15 LOC="J22"; # Bank 1, Vcco=3.3V -NET SRAM_FLASH_A16 LOC="L16"; # Bank 1, Vcco=3.3V -NET SRAM_FLASH_A17 LOC="L15"; # Bank 1, Vcco=3.3V -NET SRAM_FLASH_A18 LOC="L20"; # Bank 1, Vcco=3.3V -NET SRAM_FLASH_A19 LOC="L21"; # Bank 1, Vcco=3.3V -NET SRAM_FLASH_A20 LOC="AE23"; # Bank 2, Vcco=3.3V -NET SRAM_FLASH_A21 LOC="AE22"; # Bank 2, Vcco=3.3V -NET SRAM_FLASH_D0 LOC="AD19"; # Bank 2, Vcco=3.3V -NET SRAM_FLASH_D1 LOC="AE19"; # Bank 2, Vcco=3.3V -NET SRAM_FLASH_D2 LOC="AE17"; # Bank 2, Vcco=3.3V -NET SRAM_FLASH_D3 LOC="AF16"; # Bank 2, Vcco=3.3V -NET SRAM_FLASH_D4 LOC="AD20"; # Bank 2, Vcco=3.3V -NET SRAM_FLASH_D5 LOC="AE21"; # Bank 2, Vcco=3.3V -NET SRAM_FLASH_D6 LOC="AE16"; # Bank 2, Vcco=3.3V -NET SRAM_FLASH_D7 LOC="AF15"; # Bank 2, Vcco=3.3V -NET SRAM_FLASH_D8 LOC="AH13"; # Bank 4, Vcco=3.3V, No DCI -NET SRAM_FLASH_D9 LOC="AH14"; # Bank 4, Vcco=3.3V, No DCI -NET SRAM_FLASH_D10 LOC="AH19"; # Bank 4, Vcco=3.3V, No DCI -NET SRAM_FLASH_D11 LOC="AH20"; # Bank 4, Vcco=3.3V, No DCI -NET SRAM_FLASH_D12 LOC="AG13"; # Bank 4, Vcco=3.3V, No DCI -NET SRAM_FLASH_D13 LOC="AH12"; # Bank 4, Vcco=3.3V, No DCI -NET SRAM_FLASH_D14 LOC="AH22"; # Bank 4, Vcco=3.3V, No DCI -NET SRAM_FLASH_D15 LOC="AG22"; # Bank 4, Vcco=3.3V, No DCI -NET SRAM_FLASH_WE_B LOC="AF20"; # Bank 2, Vcco=3.3V -NET SRAM_MODE LOC="A13"; # Bank 20, Vcco=3.3V, DCI using 49.9 ohm resistors -NET SRAM_OE_B LOC="B12"; # Bank 20, Vcco=3.3V, DCI using 49.9 ohm resistors -NET SYSACE_MPA00 LOC="G5"; # Bank 12, Vcco=3.3V, DCI using 49.9 ohm resistors -NET SYSACE_MPA01_USB_A0 LOC="N7"; # Bank 12, Vcco=3.3V, DCI using 49.9 ohm resistors -NET SYSACE_MPA02_USB_A1 LOC="N5"; # Bank 12, Vcco=3.3V, DCI using 49.9 ohm resistors -NET SYSACE_MPA03 LOC="P5"; # Bank 12, Vcco=3.3V, DCI using 49.9 ohm resistors -NET SYSACE_MPA04 LOC="R6"; # Bank 12, Vcco=3.3V, DCI using 49.9 ohm resistors -NET SYSACE_MPA05 LOC="M6"; # Bank 12, Vcco=3.3V, DCI using 49.9 ohm resistors -NET SYSACE_MPA06 LOC="L6"; # Bank 12, Vcco=3.3V, DCI using 49.9 ohm resistors -NET SYSACE_MPBRDY LOC="H5"; # Bank 12, Vcco=3.3V, DCI using 49.9 ohm resistors -NET SYSACE_MPCE LOC="M5"; # Bank 12, Vcco=3.3V, DCI using 49.9 ohm resistors -NET SYSACE_MPIRQ LOC="M7"; # Bank 12, Vcco=3.3V, DCI using 49.9 ohm resistors -NET SYSACE_MPOE_USB_RD_B LOC="N8"; # Bank 12, Vcco=3.3V, DCI using 49.9 ohm resistors -NET SYSACE_MPWE_USB_WR_B LOC="R9"; # Bank 12, Vcco=3.3V, DCI using 49.9 ohm resistors -NET SYSACE_USB_D0 LOC="P9"; # Bank 12, Vcco=3.3V, DCI using 49.9 ohm resistors -NET SYSACE_USB_D1 LOC="T8"; # Bank 12, Vcco=3.3V, DCI using 49.9 ohm resistors -NET SYSACE_USB_D2 LOC="J7"; # Bank 12, Vcco=3.3V, DCI using 49.9 ohm resistors -NET SYSACE_USB_D3 LOC="H7"; # Bank 12, Vcco=3.3V, DCI using 49.9 ohm resistors -NET SYSACE_USB_D4 LOC="R7"; # Bank 12, Vcco=3.3V, DCI using 49.9 ohm resistors -NET SYSACE_USB_D5 LOC="U7"; # Bank 12, Vcco=3.3V, DCI using 49.9 ohm resistors -NET SYSACE_USB_D6 LOC="P7"; # Bank 12, Vcco=3.3V, DCI using 49.9 ohm resistors -NET SYSACE_USB_D7 LOC="P6"; # Bank 12, Vcco=3.3V, DCI using 49.9 ohm resistors -NET SYSACE_USB_D8 LOC="R8"; # Bank 12, Vcco=3.3V, DCI using 49.9 ohm resistors -NET SYSACE_USB_D9 LOC="L5"; # Bank 12, Vcco=3.3V, DCI using 49.9 ohm resistors -NET SYSACE_USB_D10 LOC="L4"; # Bank 12, Vcco=3.3V, DCI using 49.9 ohm resistors -NET SYSACE_USB_D11 LOC="K6"; # Bank 12, Vcco=3.3V, DCI using 49.9 ohm resistors -NET SYSACE_USB_D12 LOC="J5"; # Bank 12, Vcco=3.3V, DCI using 49.9 ohm resistors -NET SYSACE_USB_D13 LOC="T6"; # Bank 12, Vcco=3.3V, DCI using 49.9 ohm resistors -NET SYSACE_USB_D14 LOC="K7"; # Bank 12, Vcco=3.3V, DCI using 49.9 ohm resistors -NET SYSACE_USB_D15 LOC="J6"; # Bank 12, Vcco=3.3V, DCI using 49.9 ohm resistors -NET TRC_CLK LOC="AD9"; # Bank 22, Vcco=3.3V, DCI using 49.9 ohm resistors -NET TRC_TS1E LOC="AK9"; # Bank 22, Vcco=3.3V, DCI using 49.9 ohm resistors -NET TRC_TS1O LOC="AF10"; # Bank 22, Vcco=3.3V, DCI using 49.9 ohm resistors -NET TRC_TS2E LOC="AK8"; # Bank 22, Vcco=3.3V, DCI using 49.9 ohm resistors -NET TRC_TS2O LOC="AF9"; # Bank 22, Vcco=3.3V, DCI using 49.9 ohm resistors -NET TRC_TS3 LOC="AJ11"; # Bank 22, Vcco=3.3V, DCI using 49.9 ohm resistors -NET TRC_TS4 LOC="AK11"; # Bank 22, Vcco=3.3V, DCI using 49.9 ohm resistors -NET TRC_TS5 LOC="AD11"; # Bank 22, Vcco=3.3V, DCI using 49.9 ohm resistors -NET TRC_TS6 LOC="AD10"; # Bank 22, Vcco=3.3V, DCI using 49.9 ohm resistors -NET USB_CS_B LOC="P10"; # Bank 12, Vcco=3.3V, DCI using 49.9 ohm resistors -NET USB_INT LOC="F5"; # Bank 12, Vcco=3.3V, DCI using 49.9 ohm resistors -NET USB_RESET_B LOC="R11"; # Bank 12, Vcco=3.3V, DCI using 49.9 ohm resistors -NET USER_CLK LOC="AH15"; # Bank 4, Vcco=3.3V, No DCI -NET VGA_IN_BLUE0 LOC="AC4"; # Bank 18, Vcco=3.3V, No DCI -NET VGA_IN_BLUE1 LOC="AC5"; # Bank 18, Vcco=3.3V, No DCI -NET VGA_IN_BLUE2 LOC="AB6"; # Bank 18, Vcco=3.3V, No DCI -NET VGA_IN_BLUE3 LOC="AB7"; # Bank 18, Vcco=3.3V, No DCI -NET VGA_IN_BLUE4 LOC="AA5"; # Bank 18, Vcco=3.3V, No DCI -NET VGA_IN_BLUE5 LOC="AB5"; # Bank 18, Vcco=3.3V, No DCI -NET VGA_IN_BLUE6 LOC="AC7"; # Bank 18, Vcco=3.3V, No DCI -NET VGA_IN_BLUE7 LOC="AD7"; # Bank 18, Vcco=3.3V, No DCI -NET VGA_IN_CLAMP LOC="AH7"; # Bank 18, Vcco=3.3V, No DCI -NET VGA_IN_COAST LOC="AG7"; # Bank 18, Vcco=3.3V, No DCI -NET VGA_IN_DATA_CLK LOC="AH18"; # Bank 4, Vcco=3.3V, No DCI -NET VGA_IN_GREEN0 LOC="Y8"; # Bank 18, Vcco=3.3V, No DCI -NET VGA_IN_GREEN1 LOC="Y9"; # Bank 18, Vcco=3.3V, No DCI -NET VGA_IN_GREEN2 LOC="AD4"; # Bank 18, Vcco=3.3V, No DCI -NET VGA_IN_GREEN3 LOC="AD5"; # Bank 18, Vcco=3.3V, No DCI -NET VGA_IN_GREEN4 LOC="AA6"; # Bank 18, Vcco=3.3V, No DCI -NET VGA_IN_GREEN5 LOC="Y7"; # Bank 18, Vcco=3.3V, No DCI -NET VGA_IN_GREEN6 LOC="AD6"; # Bank 18, Vcco=3.3V, No DCI -NET VGA_IN_GREEN7 LOC="AE6"; # Bank 18, Vcco=3.3V, No DCI -NET VGA_IN_HSOUT LOC="AE7"; # Bank 18, Vcco=3.3V, No DCI -NET VGA_IN_ODD_EVEN_B LOC="W6"; # Bank 18, Vcco=3.3V, No DCI -NET VGA_IN_RED0 LOC="AG5"; # Bank 18, Vcco=3.3V, No DCI -NET VGA_IN_RED1 LOC="AF5"; # Bank 18, Vcco=3.3V, No DCI -NET VGA_IN_RED2 LOC="W7"; # Bank 18, Vcco=3.3V, No DCI -NET VGA_IN_RED3 LOC="V7"; # Bank 18, Vcco=3.3V, No DCI -NET VGA_IN_RED4 LOC="AH5"; # Bank 18, Vcco=3.3V, No DCI -NET VGA_IN_RED5 LOC="AG6"; # Bank 18, Vcco=3.3V, No DCI -NET VGA_IN_RED6 LOC="Y11"; # Bank 18, Vcco=3.3V, No DCI -NET VGA_IN_RED7 LOC="W11"; # Bank 18, Vcco=3.3V, No DCI -NET VGA_IN_SOGOUT LOC="AF6"; # Bank 18, Vcco=3.3V, No DCI -NET VGA_IN_VSOUT LOC="Y6"; # Bank 18, Vcco=3.3V, No DCI Index: branches/mkfiles_rev1/rtl/System09_Xilinx_ML506/my_system09.prj =================================================================== --- branches/mkfiles_rev1/rtl/System09_Xilinx_ML506/my_system09.prj (revision 56) +++ branches/mkfiles_rev1/rtl/System09_Xilinx_ML506/my_system09.prj (nonexistent) @@ -1,16 +0,0 @@ -vhdl work "../VHDL/ACIA_Clock.vhd" -vhdl work "../Spartan3/keymap_rom_slice.vhd" -vhdl work "../../src/sys09bug/sys09s3s.vhd" -vhdl work "../../src/Flex9/flex9ram.vhd" -vhdl work "../VHDL/ps2_keyboard.vhd" -vhdl work "../VHDL/ACIA_TX.vhd" -vhdl work "../VHDL/ACIA_RX.vhd" -vhdl work "../Spartan3/ram2k_b16.vhd" -vhdl work "../Spartan3/char_rom2k_b16.vhd" -vhdl work "../VHDL/vdu8.vhd" -vhdl work "../VHDL/keyboard.vhd" -vhdl work "../VHDL/datram.vhd" -vhdl work "../VHDL/cpu09.vhd" -vhdl work "../VHDL/SevenSegment.vhd" -vhdl work "../VHDL/ACIA_6850.vhd" -vhdl work "my_system09.vhd" Index: branches/mkfiles_rev1/rtl/System09_Xilinx_ML506/Makefile =================================================================== --- branches/mkfiles_rev1/rtl/System09_Xilinx_ML506/Makefile (revision 56) +++ branches/mkfiles_rev1/rtl/System09_Xilinx_ML506/Makefile (nonexistent) @@ -1,152 +0,0 @@ -#=================================================================== -# File: Makefile -# Author: David Burnette -# Created: July 5, 2007 -# -# Description: -# Makefile to build the System09 by John Kent -# -# This makefile will build John Kent's entire System09 project -# (RTL synthesis and monitor ROMs) and even download the final -# bitstream to the prototype board. -# -# You can use Xilinx ISE interactively to add new RTL source files -# to this project. -# -# Usage: -# Use 'make help' to get a list of options. -# -# Dependencies: -# Depends on makefile fragments in the 'MKFRAGS' directory. -# -# Revision History: -# dgb 2007-07-05 Original version -# -# dgb 2008-04-07 Split out files into fragments. Modified -# ROM source generation to be per src directory. -# -#=================================================================== - -MKFRAGS := ../../mkfiles -export MKFRAGS - -#=================================================================== -# User-modifiable variables -# -# This name must match the name of the design in Xilinx ISE (case -# sensitive). -DESIGN_NAME := my_system09 -# -# Constraint file (unfortunately it cannot be extracted from ISE) -UCF_FILE := my_system09.ucf -# -# Technology family (unfortunately it cannot be extracted from ISE) -FAMILY := virtex5 - -# List of ROM VHDL files -roms: - @$(MAKE) -C ../../src/sys09bug sys09s3s.vhd - @$(MAKE) -C ../../src/Flex9 flex9ram.vhd - - -#=================================================================== -# You should not need to edit anything below this line - -# XESS Tools -XSLOAD := C:/Progra~1/XSTOOLs/xsload.exe - -include ../../mkfiles/xilinx_rules.mk - -#=================================================================== -# TARGETS - -all: roms bit - -roms: $(ROMFILES) - -debug_vars: - @$(ECHO) "XST_FILE = '$(XST_FILE)'" - @$(ECHO) "PRJ_FILE = '$(PRJ_FILE)'" - @$(ECHO) "HDL_FILES = '$(HDL_FILES)'" - @$(ECHO) "PART = '$(PART)'" - @$(ECHO) "DEVICE = '$(DEVICE)'" - @$(ECHO) "SPEED = '$(SPEED)'" - @$(ECHO) "PACKAGE = '$(PACKAGE)'" - @$(ECHO) "UCF_FILE = '$(UCF_FILE)'" - @$(ECHO) "BSD_FILE = '$(BSD_FILE)'" - @$(ECHO) "XSTHDPDIR = '$(XSTHDPDIR)'" - @$(ECHO) "TMPDIR = '$(TMPDIR)'" - -bit: roms $(DESIGN_NAME).bit - -prom: $(DESIGN_NAME).mcs - -xsload: $(DESIGN_NAME).bit - @$(ECHO) - @$(ECHO) "======= Downloading bitstream to XSA-3S1000 using XSLOAD (parallel) =" - $(XSLOAD) -p 0 -b xsa-3s1000 -fpga $< - -usbxsload.bit: $(DESIGN_NAME).bit - @$(ECHO) - @$(ECHO) "======= Generating special bitstream with StartUpClk=JtagClk ========" - $(GREP) -v StartUpClk $(BITGEN_OPTIONS_FILE) >tmp.ut - $(ECHO) "-g StartUpClk:JtagClk" >>tmp.ut - $(BITGEN) $(BITGEN_FLAGS) -f tmp.ut $(DESIGN_NAME).ncd usbxsload.bit - -usbxsload: usbxsload.bit - @$(ECHO) - @$(ECHO) "======= Downloading bitstream to XSA-3S1000 using XSLOAD (USB) ======" - $(XSLOAD) -usb 0 -b xsa-3s1000 -fpga usbxsload.bit - -impact: $(DESIGN_NAME).bit - @$(ECHO) - @$(ECHO) "======= Downloading bitstream to XSA-3S1000 using Impact ============" - -@$(RM) $(DESIGN_NAME)_impact.cmd - @$(ECHO) "setMode -bscan" >>$(DESIGN_NAME)_impact.cmd - @$(ECHO) "setCable -p auto" >>$(DESIGN_NAME)_impact.cmd - @$(ECHO) "addDevice -p 1 -file $(BSD_FILE)" >>$(DESIGN_NAME)_impact.cmd - @$(ECHO) "assignFile -p 1 -file $<" >>$(DESIGN_NAME)_impact.cmd - @$(ECHO) "program -p 1" >>$(DESIGN_NAME)_impact.cmd - @$(ECHO) "quit" >>$(DESIGN_NAME)_impact.cmd - $(IMPACT) -batch $(DESIGN_NAME)_impact.cmd - -.PHONY: help -help: - @$(ECHO) "Use this Makefile to regenerate the entire System09 bitstream" - @$(ECHO) "after modifying any of the source RTL or 6809 assembler code." - @$(ECHO) "" - @$(ECHO) "This makefile uses the following project files from the Xilinx ISE" - @$(ECHO) " $(XST_FILE)" - @$(ECHO) "" - @$(ECHO) "You use Xilinx ISE interactively to add new RTL source files." - @$(ECHO) "" - @$(ECHO) " Availiable targets" - @$(ECHO) - @$(ECHO) " For building all or part of the system:" - @$(ECHO) " roms - Run asm09 and then generate the VHDL RTL rom files" - @$(ECHO) " bit - Rebuild the entire system and generate the bitstream file" - @$(ECHO) " all - Rebuild everything" - @$(ECHO) " prom - Rebuild the entire system and generate an MCS prom file" - @$(ECHO) " exo - Rebuild the entire system and generate an EXO prom file" - @$(ECHO) - @$(ECHO) " For downloading the bitstream to the board:" - @$(ECHO) " xsload - Download the bitstream to the FPGA via XSLOAD" - @$(ECHO) " usbxsload - Download the bitstream to the FPGA via XSLOAD" - @$(ECHO) " impact - Download the bitstream to the FPGA via iMPACT" - @$(ECHO) - @$(ECHO) " For project maintenance:" - @$(ECHO) " help - Print this help text" - @$(ECHO) " clean - Clean up the ISE files" - @$(ECHO) "" - -.PHONY: clean -clean: - -$(MAKE) -C ../../src/sys09bug clean - -$(MAKE) -C ../../src/Flex9 clean - -$(RM) *.ncd *.ngc *.ngd *.twr *.bit *.mcs *.stx *.ucf.untf *.mrp - -$(RM) *.ncl *.ngm *.prm *_pad.txt *.twx *.log *.syr *.par *.exo *.xpi - -$(RM) *.cmd_log *.ngr *.bld *_summary.html *.nc1 *.pcf *.bgn - -$(RM) *.pad *.placed_ncd_tracker *.routed_ncd_tracker *_pad.csv *.drc - -$(RM) *.pad_txt $(DESIGN_NAME)_impact.cmd *.unroutes - -$(RMDIR) _ngo _xmsgs - Index: branches/mkfiles_rev1/rtl/System09_Xilinx_ML506/my_system09.lso =================================================================== --- branches/mkfiles_rev1/rtl/System09_Xilinx_ML506/my_system09.lso (revision 56) +++ branches/mkfiles_rev1/rtl/System09_Xilinx_ML506/my_system09.lso (nonexistent) @@ -1 +0,0 @@ -work Index: branches/mkfiles_rev1/rtl/System09_Xilinx_ML506/my_system09.ucf =================================================================== --- branches/mkfiles_rev1/rtl/System09_Xilinx_ML506/my_system09.ucf (revision 56) +++ branches/mkfiles_rev1/rtl/System09_Xilinx_ML506/my_system09.ucf (nonexistent) @@ -1,184 +0,0 @@ -#PACE: Start of Constraints generated by PACE - -#PACE: Start of PACE I/O Pin Assignments -# sys_clk = USER_CLK -NET sys_clk LOC="AH15"; # Bank 4, Vcco=3.3V, No DCI # sys_clk 100MHz clock -# -# PUSH BUTTONS -# -# rst_sw = FPGA_CPU_RESET_B -NET rst_sw LOC="E9"; # Bank 20, Vcco=3.3V, DCI using 49.9 ohm resistors # rst_sw -# nmi_sw = GPIO_SW_C -NET nmi_sw LOC="AJ6"; # Bank 18, Vcco=3.3V, No DCI # nmi_sw -# -# LEDs -# -# leds = GPIO_LED_... -NET leds<0> LOC="H18"; # Bank 3, Vcco=2.5V, No DCI # leds<0> -NET leds<1> LOC="L18"; # Bank 3, Vcco=2.5V, No DCI # leds<1> -NET leds<2> LOC="G15"; # Bank 3, Vcco=2.5V, No DCI # leds<2> -NET leds<3> LOC="AD26"; # Bank 21, Vcco=1.8V, DCI using 49.9 ohm resistors # leds<3> -NET leds<4> LOC="G16"; # Bank 3, Vcco=2.5V, No DCI # leds<4> -NET leds<5> LOC="AD25"; # Bank 21, Vcco=1.8V, DCI using 49.9 ohm resistors # leds<5> -NET leds<6> LOC="AD24"; # Bank 21, Vcco=1.8V, DCI using 49.9 ohm resistors # leds<6> -NET leds<7> LOC="AE24"; # Bank 21, Vcco=1.8V, DCI using 49.9 ohm resistors # leds<7> -# -# Switches -# -# switches = GPIO_DIP_SW... -NET switches<0> LOC="U25"; # Bank 15, Vcco=1.8V, DCI using 49.9 ohm resistors # switches<0> -NET switches<1> LOC="AG27"; # Bank 21, Vcco=1.8V, DCI using 49.9 ohm resistors # switches<1> -NET switches<2> LOC="AF25"; # Bank 21, Vcco=1.8V, DCI using 49.9 ohm resistors # switches<2> -NET switches<3> LOC="AF26"; # Bank 21, Vcco=1.8V, DCI using 49.9 ohm resistors # switches<3> -NET switches<4> LOC="AE27"; # Bank 21, Vcco=1.8V, DCI using 49.9 ohm resistors # switches<4> -NET switches<5> LOC="AE26"; # Bank 21, Vcco=1.8V, DCI using 49.9 ohm resistors # switches<5> -NET switches<6> LOC="AC25"; # Bank 21, Vcco=1.8V, DCI using 49.9 ohm resistors # switches<6> -NET switches<7> LOC="AC24"; # Bank 21, Vcco=1.8V, DCI using 49.9 ohm resistors # switches<7> -# -# PS/2 KEYBOARD -# -NET ps2c LOC="T26"; # Bank 15, Vcco=1.8V, DCI using 49.9 ohm resistors # ps2c -NET ps2d LOC="T25"; # Bank 15, Vcco=1.8V, DCI using 49.9 ohm resistors # ps2d -# -# UART -# -NET rxd LOC="AG15"; # Bank 4, Vcco=3.3V, No DCI # rxd -NET txd LOC="AG20"; # Bank 4, Vcco=3.3V, No DCI # txd -# -# VDU -# -NET red LOC="AG23"; # Bank 2, Vcco=3.3V # red=GPIO_LED_E -NET green LOC="AF13"; # Bank 2, Vcco=3.3V # green=GPIO_LED_N -NET blue LOC="E8"; # Bank 20, Vcco=3.3V, DCI using 49.9 ohm resistors # blue=GPIO_LED_C -NET hs LOC="AG12"; # Bank 2, Vcco=3.3V # hs=GPIO_LED_S -NET vs LOC="AF23"; # Bank 2, Vcco=3.3V # vs=GPIO_LED_W - -# -# 7 SEGMENT DISPLAY -# - -# -# RAM Address bus -# -#NET SRAM_FLASH_A0 LOC="K12"; # Bank 1, Vcco=3.3V # ram_addr<0> -#NET SRAM_FLASH_A1 LOC="K13"; # Bank 1, Vcco=3.3V # ram_addr<1> -#NET SRAM_FLASH_A2 LOC="H23"; # Bank 1, Vcco=3.3V # ram_addr<2> -#NET SRAM_FLASH_A3 LOC="G23"; # Bank 1, Vcco=3.3V # ram_addr<3> -#NET SRAM_FLASH_A4 LOC="H12"; # Bank 1, Vcco=3.3V # ram_addr<4> -#NET SRAM_FLASH_A5 LOC="J12"; # Bank 1, Vcco=3.3V # ram_addr<5> -#NET SRAM_FLASH_A6 LOC="K22"; # Bank 1, Vcco=3.3V # ram_addr<6> -#NET SRAM_FLASH_A7 LOC="K23"; # Bank 1, Vcco=3.3V # ram_addr<7> -#NET SRAM_FLASH_A8 LOC="K14"; # Bank 1, Vcco=3.3V # ram_addr<8> -#NET SRAM_FLASH_A9 LOC="L14"; # Bank 1, Vcco=3.3V # ram_addr<9> -#NET SRAM_FLASH_A10 LOC="H22"; # Bank 1, Vcco=3.3V # ram_addr<10> -#NET SRAM_FLASH_A11 LOC="G22"; # Bank 1, Vcco=3.3V # ram_addr<11> -#NET SRAM_FLASH_A12 LOC="J15"; # Bank 1, Vcco=3.3V # ram_addr<12> -#NET SRAM_FLASH_A13 LOC="K16"; # Bank 1, Vcco=3.3V # ram_addr<13> -#NET SRAM_FLASH_A14 LOC="K21"; # Bank 1, Vcco=3.3V # ram_addr<14> -#NET SRAM_FLASH_A15 LOC="J22"; # Bank 1, Vcco=3.3V # ram_addr<15> -#NET SRAM_FLASH_A16 LOC="L16"; # Bank 1, Vcco=3.3V # ram_addr<16> -#NET SRAM_FLASH_A17 LOC="L15"; # Bank 1, Vcco=3.3V # ram_addr<17> -#NET SRAM_FLASH_A18 LOC="L20"; # Bank 1, Vcco=3.3V # ram_addr<18> <= GND -#NET SRAM_FLASH_A19 LOC="L21"; # Bank 1, Vcco=3.3V # ram_addr<19> <= GND -#NET SRAM_FLASH_A20 LOC="AE23"; # Bank 2, Vcco=3.3V # ram_addr<20> <= GND -#NET SRAM_FLASH_A21 LOC="AE22"; # Bank 2, Vcco=3.3V # ram_addr<21> <= GND -#NET SRAM_FLASH_WE_B LOC="AF20"; # Bank 2, Vcco=3.3V # ram_wen -#NET SRAM_OE_B LOC="B12"; # Bank 20, Vcco=3.3V, DCI using 49.9 ohm resistors # ram_oen -# -# RAM1 -# - -#NET SRAM_FLASH_D0 LOC="AD19"; # Bank 2, Vcco=3.3V # ram1_data<0> -#NET SRAM_FLASH_D1 LOC="AE19"; # Bank 2, Vcco=3.3V # ram1_data<1> -#NET SRAM_FLASH_D2 LOC="AE17"; # Bank 2, Vcco=3.3V # ram1_data<2> -#NET SRAM_FLASH_D3 LOC="AF16"; # Bank 2, Vcco=3.3V # -#NET SRAM_FLASH_D4 LOC="AD20"; # Bank 2, Vcco=3.3V # -#NET SRAM_FLASH_D5 LOC="AE21"; # Bank 2, Vcco=3.3V # -#NET SRAM_FLASH_D6 LOC="AE16"; # Bank 2, Vcco=3.3V # -#NET SRAM_FLASH_D7 LOC="AF15"; # Bank 2, Vcco=3.3V # -#NET SRAM_FLASH_D8 LOC="AH13"; # Bank 4, Vcco=3.3V, No DCI # -#NET SRAM_FLASH_D9 LOC="AH14"; # Bank 4, Vcco=3.3V, No DCI # -#NET SRAM_FLASH_D10 LOC="AH19"; # Bank 4, Vcco=3.3V, No DCI # -#NET SRAM_FLASH_D11 LOC="AH20"; # Bank 4, Vcco=3.3V, No DCI # -#NET SRAM_FLASH_D12 LOC="AG13"; # Bank 4, Vcco=3.3V, No DCI # -#NET SRAM_FLASH_D13 LOC="AH12"; # Bank 4, Vcco=3.3V, No DCI # -#NET SRAM_FLASH_D14 LOC="AH22"; # Bank 4, Vcco=3.3V, No DCI # -#NET SRAM_FLASH_D15 LOC="AG22"; # Bank 4, Vcco=3.3V, No DCI # - - - -# -# Timing Constraints -# -NET "sys_clk" TNM_NET="sys_clk"; -TIMESPEC "TS_clk"=PERIOD "sys_clk" 10 ns HIGH 50 %; - -#NET SRAM_ADV_LD_B LOC="H8"; # Bank 20, Vcco=3.3V, DCI using 49.9 ohm resistors -#NET SRAM_BW0 LOC="D10"; # Bank 20, Vcco=3.3V, DCI using 49.9 ohm resistors -#NET SRAM_BW1 LOC="D11"; # Bank 20, Vcco=3.3V, DCI using 49.9 ohm resistors -#NET SRAM_BW2 LOC="J11"; # Bank 20, Vcco=3.3V, DCI using 49.9 ohm resistors -#NET SRAM_BW3 LOC="K11"; # Bank 20, Vcco=3.3V, DCI using 49.9 ohm resistors -#NET SRAM_CLK LOC="AG21"; # Bank 4, Vcco=3.3V, No DCI -#NET SRAM_CLK LOC="G8"; # Bank 20, Vcco=3.3V, DCI using 49.9 ohm resistors -#NET SRAM_CS_B LOC="J10"; # Bank 20, Vcco=3.3V, DCI using 49.9 ohm resistors -#NET SRAM_D16 LOC="N10"; # Bank 20, Vcco=3.3V, DCI using 49.9 ohm resistors -#NET SRAM_D17 LOC="E13"; # Bank 20, Vcco=3.3V, DCI using 49.9 ohm resistors -#NET SRAM_D18 LOC="E12"; # Bank 20, Vcco=3.3V, DCI using 49.9 ohm resistors -#NET SRAM_D19 LOC="L9"; # Bank 20, Vcco=3.3V, DCI using 49.9 ohm resistors -#NET SRAM_D20 LOC="M10"; # Bank 20, Vcco=3.3V, DCI using 49.9 ohm resistors -#NET SRAM_D21 LOC="E11"; # Bank 20, Vcco=3.3V, DCI using 49.9 ohm resistors -#NET SRAM_D22 LOC="F11"; # Bank 20, Vcco=3.3V, DCI using 49.9 ohm resistors -#NET SRAM_D23 LOC="L8"; # Bank 20, Vcco=3.3V, DCI using 49.9 ohm resistors -#NET SRAM_D24 LOC="M8"; # Bank 20, Vcco=3.3V, DCI using 49.9 ohm resistors -#NET SRAM_D25 LOC="G12"; # Bank 20, Vcco=3.3V, DCI using 49.9 ohm resistors -#NET SRAM_D26 LOC="G11"; # Bank 20, Vcco=3.3V, DCI using 49.9 ohm resistors -#NET SRAM_D27 LOC="C13"; # Bank 20, Vcco=3.3V, DCI using 49.9 ohm resistors -#NET SRAM_D28 LOC="B13"; # Bank 20, Vcco=3.3V, DCI using 49.9 ohm resistors -#NET SRAM_D29 LOC="K9"; # Bank 20, Vcco=3.3V, DCI using 49.9 ohm resistors -#NET SRAM_D30 LOC="K8"; # Bank 20, Vcco=3.3V, DCI using 49.9 ohm resistors -#NET SRAM_D31 LOC="J9"; # Bank 20, Vcco=3.3V, DCI using 49.9 ohm resistors -#NET SRAM_DQP0 LOC="D12"; # Bank 20, Vcco=3.3V, DCI using 49.9 ohm resistors -#NET SRAM_DQP1 LOC="C12"; # Bank 20, Vcco=3.3V, DCI using 49.9 ohm resistors -#NET SRAM_DQP2 LOC="H10"; # Bank 20, Vcco=3.3V, DCI using 49.9 ohm resistors -#NET SRAM_DQP3 LOC="H9"; # Bank 20, Vcco=3.3V, DCI using 49.9 ohm resistors -#NET SRAM_FLASH_A0 LOC="K12"; # Bank 1, Vcco=3.3V -#NET SRAM_FLASH_A1 LOC="K13"; # Bank 1, Vcco=3.3V -#NET SRAM_FLASH_A2 LOC="H23"; # Bank 1, Vcco=3.3V -#NET SRAM_FLASH_A3 LOC="G23"; # Bank 1, Vcco=3.3V -#NET SRAM_FLASH_A4 LOC="H12"; # Bank 1, Vcco=3.3V -#NET SRAM_FLASH_A5 LOC="J12"; # Bank 1, Vcco=3.3V -#NET SRAM_FLASH_A6 LOC="K22"; # Bank 1, Vcco=3.3V -#NET SRAM_FLASH_A7 LOC="K23"; # Bank 1, Vcco=3.3V -#NET SRAM_FLASH_A8 LOC="K14"; # Bank 1, Vcco=3.3V -#NET SRAM_FLASH_A9 LOC="L14"; # Bank 1, Vcco=3.3V -#NET SRAM_FLASH_A10 LOC="H22"; # Bank 1, Vcco=3.3V -#NET SRAM_FLASH_A11 LOC="G22"; # Bank 1, Vcco=3.3V -#NET SRAM_FLASH_A12 LOC="J15"; # Bank 1, Vcco=3.3V -#NET SRAM_FLASH_A13 LOC="K16"; # Bank 1, Vcco=3.3V -#NET SRAM_FLASH_A14 LOC="K21"; # Bank 1, Vcco=3.3V -#NET SRAM_FLASH_A15 LOC="J22"; # Bank 1, Vcco=3.3V -#NET SRAM_FLASH_A16 LOC="L16"; # Bank 1, Vcco=3.3V -#NET SRAM_FLASH_A17 LOC="L15"; # Bank 1, Vcco=3.3V -#NET SRAM_FLASH_A18 LOC="L20"; # Bank 1, Vcco=3.3V -#NET SRAM_FLASH_A19 LOC="L21"; # Bank 1, Vcco=3.3V -#NET SRAM_FLASH_A20 LOC="AE23"; # Bank 2, Vcco=3.3V -#NET SRAM_FLASH_A21 LOC="AE22"; # Bank 2, Vcco=3.3V -#NET SRAM_FLASH_D0 LOC="AD19"; # Bank 2, Vcco=3.3V -#NET SRAM_FLASH_D1 LOC="AE19"; # Bank 2, Vcco=3.3V -#NET SRAM_FLASH_D2 LOC="AE17"; # Bank 2, Vcco=3.3V -#NET SRAM_FLASH_D3 LOC="AF16"; # Bank 2, Vcco=3.3V -#NET SRAM_FLASH_D4 LOC="AD20"; # Bank 2, Vcco=3.3V -#NET SRAM_FLASH_D5 LOC="AE21"; # Bank 2, Vcco=3.3V -#NET SRAM_FLASH_D6 LOC="AE16"; # Bank 2, Vcco=3.3V -#NET SRAM_FLASH_D7 LOC="AF15"; # Bank 2, Vcco=3.3V -#NET SRAM_FLASH_D8 LOC="AH13"; # Bank 4, Vcco=3.3V, No DCI -#NET SRAM_FLASH_D9 LOC="AH14"; # Bank 4, Vcco=3.3V, No DCI -#NET SRAM_FLASH_D10 LOC="AH19"; # Bank 4, Vcco=3.3V, No DCI -#NET SRAM_FLASH_D11 LOC="AH20"; # Bank 4, Vcco=3.3V, No DCI -#NET SRAM_FLASH_D12 LOC="AG13"; # Bank 4, Vcco=3.3V, No DCI -#NET SRAM_FLASH_D13 LOC="AH12"; # Bank 4, Vcco=3.3V, No DCI -#NET SRAM_FLASH_D14 LOC="AH22"; # Bank 4, Vcco=3.3V, No DCI -#NET SRAM_FLASH_D15 LOC="AG22"; # Bank 4, Vcco=3.3V, No DCI -#NET SRAM_FLASH_WE_B LOC="AF20"; # Bank 2, Vcco=3.3V -#NET SRAM_MODE LOC="A13"; # Bank 20, Vcco=3.3V, DCI using 49.9 ohm resistors -#NET SRAM_OE_B LOC="B12"; # Bank 20, Vcco=3.3V, DCI using 49.9 ohm resistors Index: branches/mkfiles_rev1/rtl/System09_Xilinx_ML506/my_system09.xst =================================================================== --- branches/mkfiles_rev1/rtl/System09_Xilinx_ML506/my_system09.xst (revision 56) +++ branches/mkfiles_rev1/rtl/System09_Xilinx_ML506/my_system09.xst (nonexistent) @@ -1,58 +0,0 @@ -set -tmpdir "./xst/projnav.tmp" -set -xsthdpdir "./xst" -run --ifn my_system09.prj --ifmt mixed --ofn my_system09 --ofmt NGC --p xc5vsx50t-3-ff1136 --top my_system09 --opt_mode Speed --opt_level 1 --power NO --iuc NO --lso my_system09.lso --keep_hierarchy NO --rtlview Yes --glob_opt AllClockNets --read_cores YES --write_timing_constraints NO --cross_clock_analysis NO --hierarchy_separator / --bus_delimiter <> --case maintain --slice_utilization_ratio 100 --bram_utilization_ratio 100 --dsp_utilization_ratio 100 --verilog2001 YES --fsm_extract YES -fsm_encoding Auto --safe_implementation No --fsm_style lut --ram_extract Yes --ram_style Auto --rom_extract Yes --mux_style Auto --decoder_extract YES --priority_extract YES --shreg_extract YES --shift_extract YES --xor_collapse YES --rom_style Auto --auto_bram_packing NO --mux_extract YES --resource_sharing YES --async_to_sync NO --use_dsp48 auto --iobuf YES --max_fanout 100000 --bufg 32 --register_duplication YES --register_balancing No --slice_packing YES --optimize_primitives NO --use_clock_enable Auto --use_sync_set Auto --use_sync_reset Auto --iob auto --equivalent_register_removal YES --slice_utilization_ratio_maxmargin 5