URL
https://opencores.org/ocsvn/System09/System09/trunk
Subversion Repositories System09
Compare Revisions
- This comparison shows the changes necessary to convert path
/System09/trunk/rtl/System09_Digilent_Atlys
- from Rev 186 to Rev 185
- ↔ Reverse comparison
Rev 186 → Rev 185
/system09.gise
76,35 → 76,35
</files> |
|
<transforms xmlns="http://www.xilinx.com/XMLSchema"> |
<transform xil_pn:end_ts="1611350962" xil_pn:name="TRAN_copyInitialToXSTAbstractSynthesis" xil_pn:start_ts="1611350962"> |
<transform xil_pn:end_ts="1611345983" xil_pn:name="TRAN_copyInitialToXSTAbstractSynthesis" xil_pn:start_ts="1611345983"> |
<status xil_pn:value="SuccessfullyRun"/> |
<status xil_pn:value="ReadyToRun"/> |
</transform> |
<transform xil_pn:end_ts="1611350962" xil_pn:name="TRAN_schematicsToHdl" xil_pn:prop_ck="3688993175894000260" xil_pn:start_ts="1611350962"> |
<transform xil_pn:end_ts="1611345983" xil_pn:name="TRAN_schematicsToHdl" xil_pn:prop_ck="3688993175894000260" xil_pn:start_ts="1611345983"> |
<status xil_pn:value="SuccessfullyRun"/> |
<status xil_pn:value="ReadyToRun"/> |
</transform> |
<transform xil_pn:end_ts="1611350962" xil_pn:name="TRAN_regenerateCores" xil_pn:prop_ck="7998624334607291317" xil_pn:start_ts="1611350962"> |
<transform xil_pn:end_ts="1611345983" xil_pn:name="TRAN_regenerateCores" xil_pn:prop_ck="7998624334607291317" xil_pn:start_ts="1611345983"> |
<status xil_pn:value="SuccessfullyRun"/> |
<status xil_pn:value="ReadyToRun"/> |
</transform> |
<transform xil_pn:end_ts="1611350962" xil_pn:name="TRAN_SubProjectAbstractToPreProxy" xil_pn:start_ts="1611350962"> |
<transform xil_pn:end_ts="1611345983" xil_pn:name="TRAN_SubProjectAbstractToPreProxy" xil_pn:start_ts="1611345983"> |
<status xil_pn:value="SuccessfullyRun"/> |
<status xil_pn:value="ReadyToRun"/> |
</transform> |
<transform xil_pn:end_ts="1611350962" xil_pn:name="TRAN_xawsTohdl" xil_pn:prop_ck="-2491246652047045050" xil_pn:start_ts="1611350962"> |
<transform xil_pn:end_ts="1611345983" xil_pn:name="TRAN_xawsTohdl" xil_pn:prop_ck="-2491246652047045050" xil_pn:start_ts="1611345983"> |
<status xil_pn:value="SuccessfullyRun"/> |
<status xil_pn:value="ReadyToRun"/> |
</transform> |
<transform xil_pn:end_ts="1611350962" xil_pn:name="TRAN_SubProjectPreToStructuralProxy" xil_pn:prop_ck="8977612015756273942" xil_pn:start_ts="1611350962"> |
<transform xil_pn:end_ts="1611345983" xil_pn:name="TRAN_SubProjectPreToStructuralProxy" xil_pn:prop_ck="8977612015756273942" xil_pn:start_ts="1611345983"> |
<status xil_pn:value="SuccessfullyRun"/> |
<status xil_pn:value="ReadyToRun"/> |
</transform> |
<transform xil_pn:end_ts="1611350962" xil_pn:name="TRAN_platgen" xil_pn:prop_ck="-1223916495889636993" xil_pn:start_ts="1611350962"> |
<transform xil_pn:end_ts="1611345983" xil_pn:name="TRAN_platgen" xil_pn:prop_ck="-1223916495889636993" xil_pn:start_ts="1611345983"> |
<status xil_pn:value="SuccessfullyRun"/> |
<status xil_pn:value="ReadyToRun"/> |
</transform> |
<transform xil_pn:end_ts="1611351010" xil_pn:in_ck="8320588413340917314" xil_pn:name="TRANEXT_xstsynthesize_spartan6" xil_pn:prop_ck="1974990584335492622" xil_pn:start_ts="1611350962"> |
<transform xil_pn:end_ts="1611346033" xil_pn:in_ck="8320588413340917314" xil_pn:name="TRANEXT_xstsynthesize_spartan6" xil_pn:prop_ck="1974990584335492622" xil_pn:start_ts="1611345983"> |
<status xil_pn:value="SuccessfullyRun"/> |
<status xil_pn:value="WarningsGenerated"/> |
<status xil_pn:value="ReadyToRun"/> |
122,11 → 122,11
<outfile xil_pn:name="webtalk_pn.xml"/> |
<outfile xil_pn:name="xst"/> |
</transform> |
<transform xil_pn:end_ts="1611351010" xil_pn:in_ck="6003168217582152378" xil_pn:name="TRAN_compileBCD2" xil_pn:prop_ck="-3128816144678396997" xil_pn:start_ts="1611351010"> |
<transform xil_pn:end_ts="1611346033" xil_pn:in_ck="6003168217582152378" xil_pn:name="TRAN_compileBCD2" xil_pn:prop_ck="-3128816144678396997" xil_pn:start_ts="1611346033"> |
<status xil_pn:value="SuccessfullyRun"/> |
<status xil_pn:value="ReadyToRun"/> |
</transform> |
<transform xil_pn:end_ts="1611351015" xil_pn:in_ck="-2676906326711859666" xil_pn:name="TRANEXT_ngdbuild_FPGA" xil_pn:prop_ck="7427287850225075136" xil_pn:start_ts="1611351010"> |
<transform xil_pn:end_ts="1611346038" xil_pn:in_ck="-2676906326711859666" xil_pn:name="TRANEXT_ngdbuild_FPGA" xil_pn:prop_ck="7427287850225075136" xil_pn:start_ts="1611346033"> |
<status xil_pn:value="SuccessfullyRun"/> |
<status xil_pn:value="ReadyToRun"/> |
<outfile xil_pn:name="_ngo"/> |
135,7 → 135,7
<outfile xil_pn:name="system09.ngd"/> |
<outfile xil_pn:name="system09_ngdbuild.xrpt"/> |
</transform> |
<transform xil_pn:end_ts="1611351033" xil_pn:in_ck="-1009016811758874705" xil_pn:name="TRANEXT_map_spartan6" xil_pn:prop_ck="7013356299669423719" xil_pn:start_ts="1611351015"> |
<transform xil_pn:end_ts="1611346057" xil_pn:in_ck="-1009016811758874705" xil_pn:name="TRANEXT_map_spartan6" xil_pn:prop_ck="7013356299669423719" xil_pn:start_ts="1611346038"> |
<status xil_pn:value="SuccessfullyRun"/> |
<status xil_pn:value="ReadyToRun"/> |
<outfile xil_pn:name="_xmsgs/map.xmsgs"/> |
148,7 → 148,7
<outfile xil_pn:name="system09_summary.xml"/> |
<outfile xil_pn:name="system09_usage.xml"/> |
</transform> |
<transform xil_pn:end_ts="1611351055" xil_pn:in_ck="-7782462315172532792" xil_pn:name="TRANEXT_par_spartan6" xil_pn:prop_ck="-3829590541433901613" xil_pn:start_ts="1611351033"> |
<transform xil_pn:end_ts="1611346079" xil_pn:in_ck="-7782462315172532792" xil_pn:name="TRANEXT_par_spartan6" xil_pn:prop_ck="-3829590541433901613" xil_pn:start_ts="1611346057"> |
<status xil_pn:value="SuccessfullyRun"/> |
<status xil_pn:value="WarningsGenerated"/> |
<status xil_pn:value="ReadyToRun"/> |
163,9 → 163,8
<outfile xil_pn:name="system09_pad.txt"/> |
<outfile xil_pn:name="system09_par.xrpt"/> |
</transform> |
<transform xil_pn:end_ts="1611351074" xil_pn:in_ck="6003168217582144753" xil_pn:name="TRANEXT_bitFile_spartan6" xil_pn:prop_ck="-5761130248037966628" xil_pn:start_ts="1611351055"> |
<transform xil_pn:end_ts="1611346096" xil_pn:in_ck="6003168217582144753" xil_pn:name="TRANEXT_bitFile_spartan6" xil_pn:prop_ck="-5761130248037966628" xil_pn:start_ts="1611346079"> |
<status xil_pn:value="SuccessfullyRun"/> |
<status xil_pn:value="WarningsGenerated"/> |
<status xil_pn:value="ReadyToRun"/> |
<outfile xil_pn:name="_xmsgs/bitgen.xmsgs"/> |
<outfile xil_pn:name="system09.bgn"/> |
176,7 → 175,7
<outfile xil_pn:name="webtalk.log"/> |
<outfile xil_pn:name="webtalk_pn.xml"/> |
</transform> |
<transform xil_pn:end_ts="1611351055" xil_pn:in_ck="190496098961729835" xil_pn:name="TRAN_postRouteTrce" xil_pn:prop_ck="-1758799009971969896" xil_pn:start_ts="1611351050"> |
<transform xil_pn:end_ts="1611346079" xil_pn:in_ck="190496098961729835" xil_pn:name="TRAN_postRouteTrce" xil_pn:prop_ck="-1758799009971969896" xil_pn:start_ts="1611346073"> |
<status xil_pn:value="SuccessfullyRun"/> |
<status xil_pn:value="ReadyToRun"/> |
<outfile xil_pn:name="_xmsgs/trce.xmsgs"/> |
/system09.ucf
231,17 → 231,15
# NET "JB<6>" LOC = "V4"; # Bank = 2, Pin name = IO_L63N, Sch name = JA-D1_N |
# NET "JB<7>" LOC = "T4"; # Bank = 2, Pin name = IO_L63P, Sch name = JA-D1_P |
|
# Using PMOD connection |
# RS-232 PMod Atlys Pmod Port JB |
# Pin Dir Function PMOD Dir PinLoc |
# 1 input CTS JB<0> output T3 |
# 2 output RTS JB<1> input R3 |
# 3 output TXD JB<2> input P6 |
# 4 input RXD JB<3> output N5 |
NET "RS232_RTS" LOC = "T3"; # Bank = 2, Pin name = IO_L62N_D6, Sch name = JA-D0_N |
NET "RS232_CTS" LOC = "R3"; # Bank = 2, Pin name = IO_L62P_D5, Sch name = JA-D0_P |
NET "RS232_RXD" LOC = "P6"; # Bank = 2, Pin name = IO_L64N_D9, Sch name = JA-D2_N |
NET "RS232_TXD" LOC = "N5"; # Bank = 2, Pin name = IO_L64P_D8, Sch name = JA-D2_P |
|
# Using PMOD connection |
# RS-232 PMod Pin Function PMOD PinLoc |
# 1 CTS JB<0> T3 |
# 2 RTS JB<1> R3 |
# 3 TXD JB<2> P6 |
# 4 RXD JB<3> N5 |
NET "RS232_RXD" LOC = "N5"; # Bank = 0, Pin name = IO_L66N_SCP0, Sch name = USBB-RXD |
NET "RS232_TXD" LOC = "P6"; # Bank = 0, Pin name = IO_L66P_SCP1, Sch name = USBB-TXD |
|
# onboard VHDCI |
# Channnel 1 connects to P signals, Channel 2 to N signals |
/system09.vhd
129,20 → 129,16
entity system09 is |
port( |
CLKA : in Std_Logic; -- 100MHz Clock input |
--RESET_N : in Std_logic; -- Master Reset input (active low) |
--NMI_N : in Std_logic; -- Non Maskable Interrupt input (active low) |
--SW2_N : in Std_logic; -- Master Reset input (active low) |
--SW3_N : in Std_logic; -- Non Maskable Interrupt input (active low) |
|
-- RS232 Port |
RS232_RTS : out std_logic; |
RS232_CTS : in std_logic; |
-- RS232 Port |
RS232_RXD : in Std_Logic; |
RS232_TXD : out Std_Logic; |
|
-- slide switches |
-- Status 7 segment LED |
sw : in std_logic_vector(7 downto 0); |
-- push buttons (Right=SS, Center=NMI, Left=RESET) |
btn : in std_logic_vector(4 downto 0); |
-- Status 7 segment LED |
btn : in std_logic_vector(4 downto 0); |
S : out std_logic_vector(7 downto 0) |
|
|
171,13 → 167,12
----------------------------------------------------------------------------- |
-- constants |
----------------------------------------------------------------------------- |
constant CLOCK_MODE : natural := 0; -- 0 means normal, 1 means single-step |
|
|
constant MEM_CLK_FREQ : natural := 100_000; -- operating frequency of Memory in KHz |
constant SYS_CLK_DIV : real := 2.0; -- divisor for FREQ (can only be 1.0, 1.5, 2.0, 2.5, 3.0, 4.0, 5.0, 8.0 or 16.0) |
|
constant SYS_CLK_FREQ : natural := ((MEM_CLK_FREQ*2)/integer(SYS_CLK_DIV*2.0))*1000; -- FPGA System Clock (in Hz) |
constant CPU_CLK_FREQ : natural := 25_000_000; -- CPU Clock (Hz) |
constant CPU_CLK_FREQ : natural := 1; --25_000_000; -- CPU Clock (Hz) |
constant CPU_CLK_DIV : natural := (SYS_CLK_FREQ/CPU_CLK_FREQ); |
constant BAUD_RATE : integer := 57600; -- Baud Rate |
constant ACIA_CLK_FREQ : integer := BAUD_RATE * 16; |
189,10 → 184,8
-- Signals |
----------------------------------------------------------------------------- |
signal pbtn : std_logic_vector(4 downto 0); |
signal NMI_N : std_logic; |
signal RESET_N : std_logic; |
signal SINGLE_STEP : std_logic; |
|
signal SW3_N : std_logic; |
signal SW2_N : std_logic; |
-- BOOT ROM |
signal rom_cs : Std_logic; |
signal rom_data_out : Std_Logic_Vector(7 downto 0); |
248,7 → 241,10
signal trap_irq : std_logic; |
|
signal rst_i : std_logic; -- internal reset signal |
signal clk_i : std_logic; -- internal master clock signal |
signal clk_i : std_logic; -- internal master clock signal |
|
signal rs232_cts : Std_Logic; |
signal rs232_rts : Std_Logic; |
|
signal CountL : std_logic_vector(23 downto 0); |
signal clk_count : natural range 0 to CPU_CLK_DIV; |
463,6 → 459,7
); |
end component; |
|
|
-- |
-- Clock buffer |
-- |
476,51 → 473,11
|
begin |
|
-- |
-- pushbutton debounce |
-- |
my_singlestep: btn_debounce |
port map ( BTN_I => btn, CLK => CLKA, BTN_O => pbtn); |
|
|
RESET_N <= pbtn(3); -- Right PB |
NMI_N <= pbtn(4); -- Center PB |
SINGLE_STEP <= pbtn(1); -- Left PB |
|
-- |
-- Generate CPU & Pixel Clock from Memory Clock |
-- |
NORMAL: if CLOCK_MODE = 0 generate |
my_prescaler : process( clk_i, clk_count ) |
begin |
if rising_edge( clk_i ) then |
if clk_count = 0 then |
clk_count <= CPU_CLK_DIV-1; |
else |
clk_count <= clk_count - 1; |
end if; |
if clk_count = 0 then |
clk25 <= '0'; |
elsif clk_count = (CPU_CLK_DIV/2) then |
clk25 <= '1'; |
end if; |
end if; |
end process; |
end generate; |
SS: if CLOCK_MODE = 1 generate |
clk25 <= SINGLE_STEP; |
end generate; |
|
-- |
-- Reset button and reset timer |
-- |
my_switch_assignments : process( rst_i, RESET_N) |
begin |
rst_i <= RESET_N; |
cpu_reset <= rst_i; |
end process; |
|
clk_i <= CLKA; |
|
|
clk_i <= CLKA; |
----------------------------------------------------------------------------- |
-- Instantiation of internal components |
----------------------------------------------------------------------------- |
597,14 → 554,13
irq => acia_irq, |
RxC => acia_clk, |
TxC => acia_clk, |
RxD => RS232_RXD, |
TxD => RS232_TXD, |
RxD => rxd, |
TxD => txd, |
DCD_n => dcd_n, |
CTS_n => RS232_CTS, |
RTS_n => RS232_RTS |
CTS_n => cts_n, |
RTS_n => rts_n |
); |
dcd_n <= '0'; |
|
|
my_ACIA_Clock : ACIA_Clock |
generic map( |
SYS_CLK_FREQ => SYS_CLK_FREQ, |
804,7 → 760,7
-- |
-- Interrupts and other bus control signals |
-- |
interrupts : process( NMI_N, |
interrupts : process( SW3_N, |
acia_irq, |
trap_irq, |
timer_irq |
811,7 → 767,7
) |
begin |
cpu_irq <= acia_irq; |
cpu_nmi <= trap_irq or not( NMI_N ); |
cpu_nmi <= trap_irq or not( SW3_N ); |
cpu_firq <= timer_irq; |
cpu_halt <= '0'; |
cpu_hold <= '0'; -- pb_hold or ram_hold; |
830,8 → 786,52
--S(7 downto 0) <= CountL(23 downto 16); |
end process; |
|
-- |
-- Generate CPU & Pixel Clock from Memory Clock |
-- |
-- my_prescaler : process( clk_i, clk_count ) |
-- begin |
-- if rising_edge( clk_i ) then |
-- if clk_count = 0 then |
-- clk_count <= CPU_CLK_DIV-1; |
-- else |
-- clk_count <= clk_count - 1; |
-- end if; |
-- if clk_count = 0 then |
-- clk25 <= '0'; |
-- elsif clk_count = (CPU_CLK_DIV/2) then |
-- clk25 <= '1'; |
-- end if; |
-- end if; |
-- end process; |
|
|
my_singlestep: btn_debounce |
port map ( BTN_I => btn, CLK => CLKA, BTN_O => pbtn); |
SW2_N <= pbtn(0); |
SW3_N <= pbtn(1); |
clk25 <= pbtn(2); |
|
-- |
-- Reset button and reset timer |
-- |
my_switch_assignments : process( rst_i, SW2_N) |
begin |
rst_i <= SW2_N; |
cpu_reset <= rst_i; |
end process; |
|
-- |
-- RS232 signals: |
-- |
my_acia_assignments : process( RS232_RXD, RS232_CTS, txd, rts_n ) |
begin |
rxd <= RS232_RXD; |
cts_n <= RS232_CTS; |
dcd_n <= '0'; |
RS232_TXD <= txd; |
RS232_RTS <= rts_n; |
end process; |
|
status_leds : process( rst_i, cpu_reset,cpu_addr, cpu_rw, sw) |
begin |