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my_system09.ise Property changes : Deleted: svn:mime-type ## -1 +0,0 ## -application/octet-stream \ No newline at end of property Index: my_system09.vhd =================================================================== --- my_system09.vhd (revision 66) +++ my_system09.vhd (nonexistent) @@ -1,1408 +0,0 @@ ---===========================================================================---- --- --- S Y N T H E Z I A B L E System09 - SOC. --- --- www.OpenCores.Org - February 2007 --- This core adheres to the GNU public license --- --- File name : System09_Xess_XSA-3S1000.vhd --- --- Purpose : Top level file for 6809 compatible system on a chip --- Designed with Xilinx XC3S1000 Spartan 3 FPGA. --- Implemented With XESS XSA-3S1000 FPGA board. --- *** Note *** --- This configuration can run Flex9 however it only has --- 32k bytes of user memory and the VDU is monochrome --- The design needs to be updated to use the SDRAM on --- the XSA-3S1000 board. --- This configuration also lacks a DAT so cannot use --- the RAM Disk features of SYS09BUG. --- --- Dependencies : ieee.Std_Logic_1164 --- ieee.std_logic_unsigned --- ieee.std_logic_arith --- ieee.numeric_std --- unisim.vcomponents --- --- Uses : mon_rom (sys09bug_rom4k_b16.vhd) Sys09Bug Monitor ROM --- cpu09 (cpu09.vhd) CPU core --- ACIA_6850 (ACIA_6850.vhd) ACIA / UART --- (ACIA_RX.vhd) --- (ACIA_TX.vhd) --- ACIA_Clock (ACIA_Clock.vhd) ACIA clock. --- keyboard (keyboard.vhd) PS/2 Keyboard interface --- (ps2_keyboard.vhd) --- (keymap_rom_slice.vhd) Key map table --- vdu8_mono (vdu8_mono.vhd) Monochrome VDU --- (char_rom2k_b16.vhd) --- (ram2k_b16.vhd) --- timer (timer.vhd) Interrupt timer --- trap (trap.vhd) Bus condition trap logic --- flex_ram (flex9_ram8k_b16.vhd) Flex operating system --- ram_32K (ram32k_b16.vhd) 32 KBytes of Block RAM --- --- --- Author : John E. Kent --- dilbert57@opencores.org --- --- Memory Map : --- --- $0000 - User program RAM (32K Bytes) --- $C000 - Flex Operating System memory (8K Bytes) --- $E000 - ACIA (SWTPc) --- $E010 - Reserved for FD1771 FDC (SWTPc) --- $E020 - Keyboard --- $E030 - VDU --- $E040 - IDE / Compact Flash interface --- $E050 - Timer --- $E060 - Bus trap --- $E070 - Reserced for Parallel I/O (B5-X300) --- $E080 - Reserved for 6821 PIA (?) (SWTPc) --- $E090 - Reserved for 6840 PTM (?) (SWTPc) --- $F000 - Sys09Bug monitor Program (4K Bytes) --- ---===========================================================================---- --- --- Revision History: ---===========================================================================-- --- Version 0.1 - 20 March 2003 --- Version 0.2 - 30 March 2003 --- Version 0.3 - 29 April 2003 --- Version 0.4 - 29 June 2003 --- --- Version 0.5 - 19 July 2003 --- prints out "Hello World" --- --- Version 0.6 - 5 September 2003 --- Runs SBUG --- --- Version 1.0- 6 Sep 2003 - John Kent --- Inverted SysClk --- Initial release to Open Cores --- --- Version 1.1 - 17 Jan 2004 - John Kent --- Updated miniUart. --- --- Version 1.2 - 25 Jan 2004 - John Kent --- removed signals "test_alu" and "test_cc" --- Trap hardware re-instated. --- --- Version 1.3 - 11 Feb 2004 - John Kent --- Designed forked off to produce System09_VDU --- Added VDU component --- VDU runs at 25MHz and divides the clock by 2 for the CPU --- UART Runs at 57.6 Kbps --- --- Version 2.0 - 2 September 2004 - John Kent --- ported to Digilent Xilinx Spartan3 starter board --- removed Compact Flash and Trap Logic. --- Replaced SBUG with KBug9s --- --- Version 3.0 - 29th August 2006 - John Kent --- Adapted to XSA-3S1000 board. --- Removed DAT and miniUART. --- Used 32KBytes of Block RAM. --- --- Version 3.1 - 15th January 2007 - John Kent --- Modified vdu8 interface --- Added a clock divider --- --- Version 3.2 - 25th February 2007 - John Kent --- reinstated ACIA_6850 and ACIA_Clock --- Updated VDU8 & Keyboard with generic parameters --- Defined Constants for clock speed calculations --- --- Version 3.3 - 1st July 2007 - John Kent --- Made VDU mono to save on one RAMB16 --- Used distributed memory for Key Map ROM to save one RAMB16 --- Added Flex RAM at $C000 to $DFFF using 4 spare RAMB16s --- Added timer and trap logic --- Added IDE Interface for Compact Flash --- Replaced KBug9s and stack with Sys09Bug. --- --- Version 4.0 - 1st February 2008 - John kent --- Replaced Block RAM with SDRAM Interface --- Modified Hold timing for SDRAM --- Added CF and Ethernet interface --- via the 16 bit peripheral bus at $E100 --- ---===========================================================================-- -library ieee; - use ieee.std_logic_1164.all; - use IEEE.STD_LOGIC_ARITH.ALL; - use IEEE.STD_LOGIC_UNSIGNED.ALL; - use ieee.numeric_std.all; -library work; - use work.common.all; - use WORK.xsasdram.all; -library unisim; - use unisim.vcomponents.all; - -entity my_system09 is - port( - CLKA : in Std_Logic; -- 100MHz Clock input - SW2_N : in Std_logic; -- Master Reset input (active low) - SW3_N : in Std_logic; -- Non Maskable Interrupt input (active low) - - -- PS/2 Keyboard - ps2_clk : inout Std_logic; - ps2_dat : inout Std_Logic; - - -- CRTC output signals - vga_vsync_n : out Std_Logic; - vga_hsync_n : out Std_Logic; - vga_blue : out std_logic_vector(2 downto 0); - vga_green : out std_logic_vector(2 downto 0); - vga_red : out std_logic_vector(2 downto 0); - - -- RS232 Port - RS232_RXD : in Std_Logic; - RS232_TXD : out Std_Logic; - RS232_CTS : in Std_Logic; - RS232_RTS : out Std_Logic; - - -- Status 7 segment LED --- S : out std_logic_vector(7 downto 0); - - -- SDRAM side - SDRAM_clkfb : in std_logic; -- feedback SDRAM clock after PCB delays - SDRAM_clkout : out std_logic; -- clock to SDRAM - SDRAM_CKE : out std_logic; -- clock-enable to SDRAM - SDRAM_CS_N : out std_logic; -- chip-select to SDRAM - SDRAM_RAS_N : out std_logic; -- SDRAM row address strobe - SDRAM_CAS_N : out std_logic; -- SDRAM column address strobe - SDRAM_WE_N : out std_logic; -- SDRAM write enable - SDRAM_BA : out std_logic_vector(1 downto 0); -- SDRAM bank address - SDRAM_A : out std_logic_vector(12 downto 0); -- SDRAM row/column address - SDRAM_D : inout std_logic_vector(15 downto 0); -- data from SDRAM - SDRAM_DQMH : out std_logic; -- enable upper-byte of SDRAM databus if true - SDRAM_DQML : out std_logic; -- enable lower-byte of SDRAM databus if true - - -- Peripheral I/O bus $E100 - $E1FF - PB_RD_N : out std_logic; - PB_WR_N : out std_logic; - PB_A : out std_logic_vector(4 downto 0); - PB_D : inout std_logic_vector(15 downto 0); - - -- IDE Compact Flash $E100 - $E13F - ide_dmack_n : out std_logic; - ide_cs0_n : out std_logic; - ide_cs1_n : out std_logic; - - -- Ethernet $E140 - $E17F - ether_cs_n : out std_logic; - ether_aen : out std_logic; -- Ethernet address enable not - ether_bhe_n : out std_logic; -- Ethernet bus high enable - ether_clk : in std_logic; -- Ethernet clock - ether_rdy : in std_logic; -- Ethernet ready - ether_irq : in std_logic; -- Ethernet irq - Shared with BAR6 - - -- Slot 1 $E180 - $E1BF - slot1_cs_n : out std_logic; --- slot1_irq : in std_logic; - - -- Slot 2 $E1C0 - $E1FF - slot2_cs_n : out std_logic; --- slot2_irq : in std_logic; - - -- Disable Flash - FLASH_CE_N : out std_logic - ); -end My_System09; - -------------------------------------------------------------------------------- --- Architecture for System09 -------------------------------------------------------------------------------- -architecture rtl of my_system09 is - - ----------------------------------------------------------------------------- - -- constants - ----------------------------------------------------------------------------- - constant SYS_Clock_Frequency : integer := 50000000; -- FPGA System Clock - constant PIX_Clock_Frequency : integer := 25000000; -- VGA Pixel Clock - constant CPU_Clock_Frequency : integer := 25000000; -- CPU Clock - constant BAUD_Rate : integer := 57600; -- Baud Rate - constant ACIA_Clock_Frequency : integer := BAUD_Rate * 16; - - type hold_state_type is ( hold_release_state, hold_request_state ); - - ----------------------------------------------------------------------------- - -- Signals - ----------------------------------------------------------------------------- - signal rst_n : Std_logic; -- Master Reset input (active low) - signal nmi_n : Std_logic; -- Non Maskable Interrupt input (active low) - - -- BOOT ROM - signal rom_cs : Std_logic; - signal rom_data_out : Std_Logic_Vector(7 downto 0); - - -- Flex Memory & Monitor Stack - signal flex_cs : Std_logic; - signal flex_data_out : Std_Logic_Vector(7 downto 0); - - -- ACIA/UART Interface signals - signal acia_data_out : Std_Logic_Vector(7 downto 0); - signal acia_cs : Std_Logic; - signal acia_irq : Std_Logic; - signal acia_clk : Std_Logic; - signal rxd : Std_Logic; - signal txd : Std_Logic; - signal DCD_n : Std_Logic; - signal RTS_n : Std_Logic; - signal CTS_n : Std_Logic; - - -- keyboard port - signal keyboard_data_out : std_logic_vector(7 downto 0); - signal keyboard_cs : std_logic; - signal keyboard_irq : std_logic; - - -- RAM - signal ram_cs : std_logic; -- memory chip select - signal ram_data_out : std_logic_vector(7 downto 0); - signal ram_hold : std_logic; -- hold off slow accesses - - -- CPU Interface signals - signal cpu_reset : Std_Logic; - signal cpu_clk : Std_Logic; - signal cpu_rw : std_logic; - signal cpu_vma : std_logic; - signal cpu_halt : std_logic; - signal cpu_hold : std_logic; - signal cpu_firq : std_logic; - signal cpu_irq : std_logic; - signal cpu_nmi : std_logic; - signal cpu_addr : std_logic_vector(15 downto 0); - signal cpu_data_in : std_logic_vector(7 downto 0); - signal cpu_data_out : std_logic_vector(7 downto 0); - - -- Dynamic Address Translation - signal dat_cs : std_logic; - signal dat_addr : std_logic_vector(7 downto 0); - - -- Video Display Unit - signal vdu_cs : std_logic; - signal vdu_data_out : std_logic_vector(7 downto 0); - signal vga_red_o : std_logic; - signal vga_green_o : std_logic; - signal vga_blue_o : std_logic; - - -- timer - signal timer_data_out : std_logic_vector(7 downto 0); - signal timer_cs : std_logic; - signal timer_irq : std_logic; - - -- trap - signal trap_cs : std_logic; - signal trap_data_out : std_logic_vector(7 downto 0); - signal trap_irq : std_logic; - - -- Peripheral Bus port - signal pb_data_out : std_logic_vector(7 downto 0); - signal pb_cs : std_logic; -- peripheral bus chip select - signal pb_wru : std_logic; -- upper byte write strobe - signal pb_wrl : std_logic; -- lower byte write strobe - signal pb_rdu : std_logic; -- upper byte read strobe - signal pb_rdl : std_logic; -- lower byte read strobe - signal pb_hold : std_logic; -- hold peripheral bus access - signal pb_release : std_logic; -- release hold of peripheral bus - signal pb_count : std_logic_vector(3 downto 0); -- hold counter - signal pb_hold_state : hold_state_type; - signal pb_wreg : std_logic_vector(7 downto 0); -- lower byte write register - signal pb_rreg : std_logic_vector(7 downto 0); -- lower byte read register - - -- Peripheral chip selects on Peripheral Bus - signal ide_cs : std_logic; -- IDE CF interface - signal ether_cs : std_logic; -- Ethernet interface - signal slot1_cs : std_logic; -- Expansion slot 1 - signal slot2_cs : std_logic; -- Expansion slot 2 - - --- SDRAM - - constant FREQ : natural := 100_000; -- operating frequency in KHz - constant CLK_DIV : real := 2.0; -- divisor for FREQ (can only be 1.0, 1.5, 2.0, 2.5, 3.0, 4.0, 5.0, 8.0 or 16.0) - constant PIPE_EN : boolean := false; -- if true, enable pipelined read operations - constant MAX_NOP : natural := 10000; -- number of NOPs before entering self-refresh - constant MULTIPLE_ACTIVE_ROWS : boolean := false; -- if true, allow an active row in each bank - constant DATA_WIDTH : natural := 16; -- host & SDRAM data width - constant NROWS : natural := 8192; -- number of rows in SDRAM array - constant NCOLS : natural := 512; -- number of columns in SDRAM array - constant HADDR_WIDTH : natural := 24; -- host-side address width - constant SADDR_WIDTH : natural := 13; -- SDRAM-side address width - - signal rst_i : std_logic; -- internal reset signal - signal clk_i : std_logic; -- internal master clock signal - signal lock : std_logic; -- SDRAM clock DLL lock indicator - - -- signals that go through the SDRAM host-side interface - signal opBegun : std_logic; -- SDRAM operation started indicator - signal earlyBegun : std_logic; -- SDRAM operation started indicator - signal ramDone : std_logic; -- SDRAM operation complete indicator - signal rdDone : std_logic; -- SDRAM read operation complete indicator - signal wrDone : std_logic; -- SDRAM write operation complete indicator - signal hAddr : std_logic_vector(HADDR_WIDTH-1 downto 0); -- host address bus - signal hDIn : std_logic_vector(DATA_WIDTH-1 downto 0); -- host-side data to SDRAM - signal hDOut : std_logic_vector(DATA_WIDTH-1 downto 0); -- host-side data from SDRAM - signal hRd : std_logic; -- host-side read control signal - signal hWr : std_logic; -- host-side write control signal - signal rdPending : std_logic; -- read operation pending in SDRAM pipeline - type ram_rd_type is (rd_state0, rd_state1, rd_state2, rd_state3); - type ram_wr_type is (wr_state0, wr_state1, wr_state2, wr_state3, wr_state4); - signal ram_rd_state : ram_rd_type; - signal ram_wr_state : ram_wr_type; - --- signal BaudCount : std_logic_vector(5 downto 0); - signal CountL : std_logic_vector(23 downto 0); - signal clk_count : std_logic_vector(0 downto 0); - signal Clk25 : std_logic; - signal pix_clk : std_logic; - ------------------------------------------------------------------ --- --- CPU09 CPU core --- ------------------------------------------------------------------ - -component cpu09 - port ( - clk: in std_logic; - rst: in std_logic; - rw: out std_logic; -- Asynchronous memory interface - vma: out std_logic; - address: out std_logic_vector(15 downto 0); - data_in: in std_logic_vector(7 downto 0); - data_out: out std_logic_vector(7 downto 0); - halt: in std_logic; - hold: in std_logic; - irq: in std_logic; - nmi: in std_logic; - firq: in std_logic - ); -end component; - - ----------------------------------------- --- --- 4K Block RAM Monitor ROM --- ----------------------------------------- -component mon_rom - Port ( - clk : in std_logic; - rst : in std_logic; - cs : in std_logic; - rw : in std_logic; - addr : in std_logic_vector (11 downto 0); - rdata : out std_logic_vector (7 downto 0); - wdata : in std_logic_vector (7 downto 0) - ); -end component; - - ----------------------------------------- --- --- 8KBytes Block RAM for FLEX9 --- $C000 - $DFFF --- ----------------------------------------- -component flex_ram - Port ( - clk : in std_logic; - rst : in std_logic; - cs : in std_logic; - rw : in std_logic; - addr : in std_logic_vector (12 downto 0); - rdata : out std_logic_vector (7 downto 0); - wdata : in std_logic_vector (7 downto 0) - ); -end component; - ------------------------------------------------------------------ --- --- 6850 Compatible ACIA / UART --- ------------------------------------------------------------------ - -component ACIA_6850 - port ( - clk : in Std_Logic; -- System Clock - rst : in Std_Logic; -- Reset input (active high) - cs : in Std_Logic; -- miniUART Chip Select - rw : in Std_Logic; -- Read / Not Write - irq : out Std_Logic; -- Interrupt - Addr : in Std_Logic; -- Register Select - DataIn : in Std_Logic_Vector(7 downto 0); -- Data Bus In - DataOut : out Std_Logic_Vector(7 downto 0); -- Data Bus Out - RxC : in Std_Logic; -- Receive Baud Clock - TxC : in Std_Logic; -- Transmit Baud Clock - RxD : in Std_Logic; -- Receive Data - TxD : out Std_Logic; -- Transmit Data - DCD_n : in Std_Logic; -- Data Carrier Detect - CTS_n : in Std_Logic; -- Clear To Send - RTS_n : out Std_Logic ); -- Request To send -end component; - - ------------------------------------------------------------------ --- --- ACIA Clock divider --- ------------------------------------------------------------------ - -component ACIA_Clock - generic ( - SYS_Clock_Frequency : integer := SYS_Clock_Frequency; - ACIA_Clock_Frequency : integer := ACIA_Clock_Frequency - ); - port ( - clk : in Std_Logic; -- System Clock Input - ACIA_clk : out Std_logic -- ACIA Clock output - ); -end component; - - ----------------------------------------- --- --- PS/2 Keyboard --- ----------------------------------------- - -component keyboard - generic( - KBD_Clock_Frequency : integer := CPU_Clock_Frequency - ); - port( - clk : in std_logic; - rst : in std_logic; - cs : in std_logic; - rw : in std_logic; - addr : in std_logic; - data_in : in std_logic_vector(7 downto 0); - data_out : out std_logic_vector(7 downto 0); - irq : out std_logic; - kbd_clk : inout std_logic; - kbd_data : inout std_logic - ); -end component; - ----------------------------------------- --- --- Video Display Unit. --- ----------------------------------------- -component vdu8 - generic( - VDU_CLOCK_FREQUENCY : integer := CPU_Clock_Frequency; -- HZ - VGA_CLOCK_FREQUENCY : integer := PIX_Clock_Frequency; -- HZ - VGA_HOR_CHARS : integer := 80; -- CHARACTERS - VGA_VER_CHARS : integer := 25; -- CHARACTERS - VGA_PIXELS_PER_CHAR : integer := 8; -- PIXELS - VGA_LINES_PER_CHAR : integer := 16; -- LINES - VGA_HOR_BACK_PORCH : integer := 40; -- PIXELS - VGA_HOR_SYNC : integer := 96; -- PIXELS - VGA_HOR_FRONT_PORCH : integer := 24; -- PIXELS - VGA_VER_BACK_PORCH : integer := 13; -- LINES - VGA_VER_SYNC : integer := 1; -- LINES - VGA_VER_FRONT_PORCH : integer := 36 -- LINES - ); - port( - -- control register interface - vdu_clk : in std_logic; -- CPU Clock - 25MHz - vdu_rst : in std_logic; - vdu_cs : in std_logic; - vdu_rw : in std_logic; - vdu_addr : in std_logic_vector(2 downto 0); - vdu_data_in : in std_logic_vector(7 downto 0); - vdu_data_out : out std_logic_vector(7 downto 0); - - -- vga port connections - vga_clk : in std_logic; -- VGA Pixel Clock - 25 MHz - vga_red_o : out std_logic; - vga_green_o : out std_logic; - vga_blue_o : out std_logic; - vga_hsync_o : out std_logic; - vga_vsync_o : out std_logic - ); -end component; - - ----------------------------------------- --- --- Timer module --- ----------------------------------------- - -component timer - port ( - clk : in std_logic; - rst : in std_logic; - cs : in std_logic; - rw : in std_logic; - addr : in std_logic; - data_in : in std_logic_vector(7 downto 0); - data_out : out std_logic_vector(7 downto 0); - irq : out std_logic - ); -end component; - ------------------------------------------------------------- --- --- Bus Trap logic --- ------------------------------------------------------------- - -component trap - port ( - clk : in std_logic; - rst : in std_logic; - cs : in std_logic; - rw : in std_logic; - vma : in std_logic; - addr : in std_logic_vector(15 downto 0); - data_in : in std_logic_vector(7 downto 0); - data_out : out std_logic_vector(7 downto 0); - irq : out std_logic - ); -end component; - - ----------------------------------------- --- --- Dynamic Address Translation Registers --- ----------------------------------------- -component dat_ram - port ( - clk : in std_logic; - rst : in std_logic; - cs : in std_logic; - rw : in std_logic; - addr_lo : in std_logic_vector(3 downto 0); - addr_hi : in std_logic_vector(3 downto 0); - data_in : in std_logic_vector(7 downto 0); - data_out : out std_logic_vector(7 downto 0) - ); -end component; - -component XSASDRAMCntl - generic( - FREQ : natural := FREQ; -- operating frequency in KHz - CLK_DIV : real := CLK_DIV; -- divisor for FREQ (can only be 1.0, 1.5, 2.0, 2.5, 3.0, 4.0, 5.0, 8.0 or 16.0) - PIPE_EN : boolean := PIPE_EN; -- if true, enable pipelined read operations - MAX_NOP : natural := MAX_NOP; -- number of NOPs before entering self-refresh - MULTIPLE_ACTIVE_ROWS : boolean := MULTIPLE_ACTIVE_ROWS; -- if true, allow an active row in each bank - DATA_WIDTH : natural := DATA_WIDTH; -- host & SDRAM data width - NROWS : natural := NROWS; -- number of rows in SDRAM array - NCOLS : natural := NCOLS; -- number of columns in SDRAM array - HADDR_WIDTH : natural := HADDR_WIDTH; -- host-side address width - SADDR_WIDTH : natural := SADDR_WIDTH -- SDRAM-side address width - ); - port( - -- host side - clk : in std_logic; -- master clock - bufclk : out std_logic; -- buffered master clock - clk1x : out std_logic; -- host clock sync'ed to master clock (and divided if CLK_DIV>1) - clk2x : out std_logic; -- double-speed host clock - lock : out std_logic; -- true when host clock is locked to master clock - rst : in std_logic; -- reset - rd : in std_logic; -- initiate read operation - wr : in std_logic; -- initiate write operation - earlyOpBegun : out std_logic; -- read/write/self-refresh op begun (async) - opBegun : out std_logic; -- read/write/self-refresh op begun (clocked) - rdPending : out std_logic; -- read operation(s) are still in the pipeline - done : out std_logic; -- read or write operation is done - rdDone : out std_logic; -- read done and data is available - hAddr : in std_logic_vector(HADDR_WIDTH-1 downto 0); -- address from host - hDIn : in std_logic_vector(DATA_WIDTH-1 downto 0); -- data from host - hDOut : out std_logic_vector(DATA_WIDTH-1 downto 0); -- data to host - status : out std_logic_vector(3 downto 0); -- diagnostic status of the FSM - - -- SDRAM side - sclkfb : in std_logic; -- clock from SDRAM after PCB delays - sclk : out std_logic; -- SDRAM clock sync'ed to master clock - cke : out std_logic; -- clock-enable to SDRAM - cs_n : out std_logic; -- chip-select to SDRAM - ras_n : out std_logic; -- SDRAM row address strobe - cas_n : out std_logic; -- SDRAM column address strobe - we_n : out std_logic; -- SDRAM write enable - ba : out std_logic_vector(1 downto 0); -- SDRAM bank address bits - sAddr : out std_logic_vector(SADDR_WIDTH-1 downto 0); -- SDRAM row/column address - sData : inout std_logic_vector(DATA_WIDTH-1 downto 0); -- SDRAM in/out databus - dqmh : out std_logic; -- high databits I/O mask - dqml : out std_logic -- low databits I/O mask - ); -end component; - --- --- Clock buffer --- -component BUFG - Port ( - i: in std_logic; - o: out std_logic - ); -end component; - -begin - ----------------------------------------------------------------------------- - -- Instantiation of internal components - ----------------------------------------------------------------------------- - -my_cpu : cpu09 port map ( - clk => cpu_clk, - rst => cpu_reset, - rw => cpu_rw, - vma => cpu_vma, - address => cpu_addr(15 downto 0), - data_in => cpu_data_in, - data_out => cpu_data_out, - halt => cpu_halt, - hold => cpu_hold, - irq => cpu_irq, - nmi => cpu_nmi, - firq => cpu_firq - ); - -my_rom : mon_rom port map ( - clk => cpu_clk, - rst => cpu_reset, - cs => rom_cs, - rw => '1', - addr => cpu_addr(11 downto 0), - wdata => cpu_data_out, - rdata => rom_data_out - ); - -my_flex : flex_ram port map ( - clk => cpu_clk, - rst => cpu_reset, - cs => flex_cs, - rw => cpu_rw, - addr => cpu_addr(12 downto 0), - rdata => flex_data_out, - wdata => cpu_data_out - ); - -my_acia : ACIA_6850 port map ( - clk => cpu_clk, - rst => cpu_reset, - cs => acia_cs, - rw => cpu_rw, - irq => acia_irq, - Addr => cpu_addr(0), - Datain => cpu_data_out, - DataOut => acia_data_out, - RxC => acia_clk, - TxC => acia_clk, - RxD => rxd, - TxD => txd, - DCD_n => dcd_n, - CTS_n => cts_n, - RTS_n => rts_n - ); - - -my_ACIA_Clock : ACIA_Clock - generic map( - SYS_Clock_Frequency => SYS_Clock_Frequency, - ACIA_Clock_Frequency => ACIA_Clock_Frequency - ) - port map( - clk => Clk_i, - acia_clk => acia_clk - ); - ----------------------------------------- --- --- PS/2 Keyboard Interface --- ----------------------------------------- -my_keyboard : keyboard - generic map ( - KBD_Clock_Frequency => CPU_Clock_frequency - ) - port map( - clk => cpu_clk, - rst => cpu_reset, - cs => keyboard_cs, - rw => cpu_rw, - addr => cpu_addr(0), - data_in => cpu_data_out(7 downto 0), - data_out => keyboard_data_out(7 downto 0), - irq => keyboard_irq, - kbd_clk => ps2_clk, - kbd_data => ps2_dat - ); - ----------------------------------------- --- --- Video Display Unit instantiation --- ----------------------------------------- -my_vdu : vdu8 - generic map( - VDU_CLOCK_FREQUENCY => CPU_Clock_Frequency, -- HZ - VGA_CLOCK_FREQUENCY => PIX_Clock_Frequency, -- HZ - VGA_HOR_CHARS => 80, -- CHARACTERS - VGA_VER_CHARS => 25, -- CHARACTERS - VGA_PIXELS_PER_CHAR => 8, -- PIXELS - VGA_LINES_PER_CHAR => 16, -- LINES - VGA_HOR_BACK_PORCH => 40, -- PIXELS - VGA_HOR_SYNC => 96, -- PIXELS - VGA_HOR_FRONT_PORCH => 24, -- PIXELS - VGA_VER_BACK_PORCH => 13, -- LINES - VGA_VER_SYNC => 1, -- LINES - VGA_VER_FRONT_PORCH => 36 -- LINES - ) - port map( - - -- Control Registers - vdu_clk => cpu_clk, -- 12.5 MHz System Clock in - vdu_rst => cpu_reset, - vdu_cs => vdu_cs, - vdu_rw => cpu_rw, - vdu_addr => cpu_addr(2 downto 0), - vdu_data_in => cpu_data_out, - vdu_data_out => vdu_data_out, - - -- vga port connections - vga_clk => pix_clk, -- 25 MHz VDU pixel clock - vga_red_o => vga_red_o, - vga_green_o => vga_green_o, - vga_blue_o => vga_blue_o, - vga_hsync_o => vga_hsync_n, - vga_vsync_o => vga_vsync_n - ); - ----------------------------------------- --- --- Timer Module --- ----------------------------------------- -my_timer : timer port map ( - clk => cpu_clk, - rst => cpu_reset, - cs => timer_cs, - rw => cpu_rw, - addr => cpu_addr(0), - data_in => cpu_data_out, - data_out => timer_data_out, - irq => timer_irq - ); - ----------------------------------------- --- --- Bus Trap Interrupt logic --- ----------------------------------------- -my_trap : trap port map ( - clk => cpu_clk, - rst => cpu_reset, - cs => trap_cs, - rw => cpu_rw, - vma => cpu_vma, - addr => cpu_addr, - data_in => cpu_data_out, - data_out => trap_data_out, - irq => trap_irq - ); - - -my_dat : dat_ram port map ( - clk => cpu_clk, - rst => cpu_reset, - cs => dat_cs, - rw => cpu_rw, - addr_hi => cpu_addr(15 downto 12), - addr_lo => cpu_addr(3 downto 0), - data_in => cpu_data_out, - data_out => dat_addr(7 downto 0) - ); - - ------------------------------------------------------------------------ - -- Instantiate the SDRAM controller that connects to the memory tester - -- module and interfaces to the external SDRAM chip. - ------------------------------------------------------------------------ - u1 : xsaSDRAMCntl - generic map( - FREQ => FREQ, - PIPE_EN => PIPE_EN, - DATA_WIDTH => DATA_WIDTH, - MULTIPLE_ACTIVE_ROWS => MULTIPLE_ACTIVE_ROWS, - NROWS => NROWS, - NCOLS => NCOLS, - HADDR_WIDTH => HADDR_WIDTH, - SADDR_WIDTH => SADDR_WIDTH - ) - port map( - -- Host Side - clk => CLKA, -- master clock from external clock source (unbuffered) - bufclk => open, -- buffered master clock output - clk1x => clk_i, -- synchronized master clock (accounts for delays to external SDRAM) - clk2x => open, -- synchronized doubled master clock - lock => lock, -- DLL lock indicator - rst => rst_i, -- reset - rd => hRd, -- host-side SDRAM read control from memory tester - wr => hWr, -- host-side SDRAM write control from memory tester - rdPending => rdPending,-- read operation to SDRAM is in progress - opBegun => opBegun, -- indicates memory read/write has begun - earlyOpBegun => earlyBegun, -- early indicator that memory operation has begun - rdDone => rdDone, -- indicates SDRAM memory read operation is done - done => ramDone, -- indicates SDRAM memory read or write operation is done - hAddr => hAddr, -- host-side address from memory tester to SDRAM - hDIn => hDIn, -- test data pattern from memory tester to SDRAM - hDOut => hDOut, -- SDRAM data output to memory tester - status => open, -- SDRAM controller state (for diagnostics) - -- SDRAM Side - sclkfb => SDRAM_clkfb, -- clock feedback with added external PCB delays - sclk => SDRAM_clkout, -- synchronized clock to external SDRAM - cke => SDRAM_cke, -- SDRAM clock enable - cs_n => SDRAM_cs_n, -- SDRAM chip-select - ras_n => SDRAM_ras_n, -- SDRAM RAS - cas_n => SDRAM_cas_n, -- SDRAM CAS - we_n => SDRAM_we_n, -- SDRAM write-enable - ba => SDRAM_ba, -- SDRAM bank address - sAddr => SDRAM_A, -- SDRAM address - sData => SDRAM_D, -- SDRAM databus - dqmh => SDRAM_dqmh, -- SDRAM DQMH - dqml => SDRAM_dqml -- SDRAM DQML - ); - -cpu_clk_buffer : BUFG port map( - i => Clk25, - o => cpu_clk - ); - -pix_clk_buffer : BUFG port map( - i => Clk25, - o => pix_clk - ); - ----------------------------------------------------------------------- --- --- Process to decode memory map --- ----------------------------------------------------------------------- - -mem_decode: process( cpu_clk, - cpu_addr, cpu_rw, cpu_vma, - dat_addr, - rom_data_out, - flex_data_out, - acia_data_out, - keyboard_data_out, - vdu_data_out, - pb_data_out, - timer_data_out, - trap_data_out, - ram_data_out - ) -begin - cpu_data_in <= (others=>'0'); - dat_cs <= '0'; - rom_cs <= '0'; - flex_cs <= '0'; - acia_cs <= '0'; - keyboard_cs <= '0'; - vdu_cs <= '0'; - timer_cs <= '0'; - trap_cs <= '0'; - pb_cs <= '0'; - ide_cs <= '0'; - ether_cs <= '0'; - slot1_cs <= '0'; - slot2_cs <= '0'; - ram_cs <= '0'; - if cpu_addr( 15 downto 8 ) = "11111111" then - cpu_data_in <= rom_data_out; - dat_cs <= cpu_vma; -- write DAT - rom_cs <= cpu_vma; -- read ROM - -- - -- Sys09Bug Monitor ROM $F000 - $FFFF - -- - elsif dat_addr(3 downto 0) = "1111" then -- $XF000 - $XFFFF - cpu_data_in <= rom_data_out; - rom_cs <= cpu_vma; - - -- - -- IO Devices $E000 - $E7FF - -- - elsif dat_addr(3 downto 0) = "1110" then -- $XE000 - $XEFFF - case cpu_addr(11 downto 8) is - -- - -- SWTPC peripherals from $E000 to $E0FF - -- - when "0000" => - case cpu_addr(7 downto 4) is - -- - -- Console Port ACIA $E000 - $E00F - -- - when "0000" => -- $E000 - cpu_data_in <= acia_data_out; - acia_cs <= cpu_vma; - - -- - -- Reserved - -- Floppy Disk Controller port $E010 - $E01F - -- - - -- - -- Keyboard port $E020 - $E02F - -- - when "0010" => -- $E020 - cpu_data_in <= keyboard_data_out; - keyboard_cs <= cpu_vma; - - -- - -- VDU port $E030 - $E03F - -- - when "0011" => -- $E030 - cpu_data_in <= vdu_data_out; - vdu_cs <= cpu_vma; - - -- - -- Reserved SWTPc MP-T Timer $E040 - $E04F - -- - when "0100" => -- $E040 - cpu_data_in <= (others=> '0'); - - -- - -- Timer $E050 - $E05F - -- - when "0101" => -- $E050 - cpu_data_in <= timer_data_out; - timer_cs <= cpu_vma; - - -- - -- Bus Trap Logic $E060 - $E06F - -- - when "0110" => -- $E060 - cpu_data_in <= trap_data_out; - trap_cs <= cpu_vma; - - -- - -- Reserved SWTPc MP-ID PIA Timer/Printer Port $E080 - $E08F - -- - - -- - -- Reserved SWTPc MP-ID PTM 6840 Timer Port $E090 - $E09F - -- - - -- - -- Remaining 6 slots reserved for non SWTPc Peripherals - -- - when others => -- $E0A0 to $E0FF - null; - end case; - -- - -- XST-3.0 Peripheral Bus goes here - -- $E100 to $E1FF - -- Four devices - -- IDE, Ethernet, Slot1, Slot2 - -- - when "0001" => - cpu_data_in <= pb_data_out; - pb_cs <= cpu_vma; - case cpu_addr(7 downto 6) is - -- - -- IDE Interface $E100 to $E13F - -- - when "00" => - ide_cs <= cpu_vma; - -- - -- Ethernet Interface $E140 to $E17F - -- - when "01" => - ether_cs <= cpu_vma; - -- - -- Slot 1 Interface $E180 to $E1BF - -- - when "10" => - slot1_cs <= cpu_vma; - -- - -- Slot 2 Interface $E1C0 to $E1FF - -- - when "11" => - slot2_cs <= cpu_vma; - -- - -- Nothing else - -- - when others => - null; - end case; - -- - -- $E200 to $EFFF reserved for future use - -- - when others => - null; - end case; - -- - -- Flex RAM $0C000 - $0DFFF - -- - elsif dat_addr(7 downto 1) = "0000110" then -- $0C000 - $0DFFF - cpu_data_in <= flex_data_out; - flex_cs <= cpu_vma; - -- - -- Everything else is RAM - -- - else - cpu_data_in <= ram_data_out; - ram_cs <= cpu_vma; - end if; -end process; - - --- --- 16-bit Peripheral Bus --- 6809 Big endian --- ISA bus little endian --- Not sure about IDE interface --- -peripheral_bus: process( clk_i, cpu_reset, cpu_rw, cpu_addr, cpu_data_out ) -begin - pb_wru <= pb_cs and (not cpu_rw) and (not cpu_addr(0)); - pb_wrl <= pb_cs and (not cpu_rw) and cpu_addr(0) ; - pb_rdu <= pb_cs and cpu_rw and (not cpu_addr(0)); - pb_rdl <= pb_cs and cpu_rw and cpu_addr(0) ; - pb_a <= cpu_addr(5 downto 1); - - -- - -- Register upper byte from CPU on first CPU write - -- and lower byte from the peripheral bus on first CPU read - -- - if cpu_reset = '1' then - pb_wreg <= (others => '0'); - pb_rreg <= (others => '0'); - elsif clk_i'event and clk_i ='1' then - if pb_wru = '1' then - pb_wreg <= cpu_data_out; - end if; - if pb_rdu = '1' then - pb_rreg <= pb_d(7 downto 0); - end if; - end if; - -- - -- Peripheral bus read and write strobes are - -- Syncronized with the 50 MHz clock - -- and are asserted until the peripheral bus hold is released - -- - if cpu_reset = '1' then - pb_wr_n <= '1'; - pb_rd_n <= '1'; - elsif clk_i'event and clk_i ='1' then - if pb_hold = '1' then - pb_wr_n <= not pb_wrl; - pb_rd_n <= not pb_rdu; - else - pb_wr_n <= '1'; - pb_rd_n <= '1'; - end if; - end if; - -- - -- The peripheral bus will be an output - -- the registered even byte on data(15 downto 8) - -- and the CPU odd bytes on data(7 downto 0) - -- on odd byte writes - -- - if pb_wrl = '1' then - pb_d <= pb_wreg & cpu_data_out; - else - pb_d <= (others => 'Z'); - end if; - - -- - -- On even byte reads, - -- the CPU reads the low (even) byte of the peripheral bus - -- On odd byte reads, - -- the CPU reads the registered (odd byte) input from the peripheral bus - -- - if pb_rdu = '1' then - pb_data_out <= pb_d(15 downto 8); - elsif pb_rdl = '1' then - pb_data_out <= pb_rreg; - else - pb_data_out <= (others => '0'); - end if; - -end process; - --- --- Hold Peripheral bus accesses for a few cycles --- -peripheral_bus_hold: process( cpu_clk, cpu_reset, pb_rdu, pb_wrl, ether_rdy ) -begin - if cpu_reset = '1' then - pb_release <= '0'; - pb_count <= "0000"; - pb_hold_state <= hold_release_state; - elsif cpu_clk'event and cpu_clk='1' then - -- - -- The perpheral bus hold signal should be generated on - -- 16 bit bus read which will be on even byte reads or - -- 16 bit bus write which will be on odd byte writes. - -- - case pb_hold_state is - when hold_release_state => - pb_release <= '0'; - if (pb_rdu = '1') or (pb_wrl = '1') then - pb_count <= "0100"; - pb_hold_state <= hold_request_state; - elsif (pb_rdl = '1') or (pb_wru = '1') then - pb_release <= '1'; - pb_hold_state <= hold_release_state; - end if; - - when hold_request_state => - if pb_count = "0000" then - if ether_rdy = '1' then - pb_release <= '1'; - pb_hold_state <= hold_release_state; - end if; - else - pb_count <= pb_count - "0001"; - end if; - when others => - null; - end case; - end if; -end process; - --- --- Compact Flash Control --- -compact_flash: process( ide_cs, cpu_addr ) -begin - ide_cs0_n <= not( ide_cs ) or cpu_addr(4); - ide_cs1_n <= not( ide_cs and cpu_addr(4)); - ide_dmack_n <= '1'; -end process; - --- --- Interrupts and other bus control signals --- -interrupts : process( lock, rst_n, nmi_n, - pb_cs, pb_hold, pb_release, - ram_cs, ram_hold, - ether_irq, - acia_irq, - keyboard_irq, - trap_irq, - timer_irq - ) -begin - cpu_reset <= (not rst_n) or (not lock); -- CPU reset is active high - pb_hold <= pb_cs and (not pb_release); - cpu_irq <= acia_irq or keyboard_irq; - cpu_nmi <= trap_irq or not( nmi_n ); - cpu_firq <= timer_irq; - cpu_halt <= '0'; - cpu_hold <= pb_hold or ram_hold; -end process; - - --- --- Flash 7 segment LEDS --- -my_led_flasher: process( Clk_i, rst_n, CountL ) -begin - if rst_n = '0' then - CountL <= "000000000000000000000000"; - elsif(Clk_i'event and Clk_i = '1') then - CountL <= CountL + 1; - end if; --- S(7 downto 0) <= CountL(23 downto 16); -end process; - --- --- Generate a 25 MHz Clock from 50 MHz --- -my_prescaler : process( Clk_i, clk_count ) -begin - if Clk_i'event and Clk_i = '1' then - clk_count(0) <= not clk_count(0); - end if; - Clk25 <= clk_count(0); -end process; - --- --- Push buttons --- -my_switch_assignments : process( SW2_N, SW3_N, rst_n ) -begin - rst_n <= SW2_N; - rst_i <= not rst_n; - nmi_n <= SW3_N; - -- - -- Disable Flash memory - -- - FLASH_CE_N <= '1'; -end process; - --- --- RS232 signals: --- -my_acia_assignments : process( RS232_RXD, RS232_CTS, txd, rts_n ) -begin - rxd <= RS232_RXD; - cts_n <= RS232_CTS; - dcd_n <= '0'; - RS232_TXD <= txd; - RS232_RTS <= rts_n; -end process; - --- --- Pin assignments for ethernet controller --- -my_ethernet_assignments : process( clk_i, cpu_reset, ether_cs ) -begin - ether_cs_n <= not ether_cs; - ether_aen <= not ether_cs; -- Ethernet address enable not - ether_bhe_n <= '1'; -- Ethernet bus high enable - 8 bit access only -end process; - --- --- I/O expansion slot assignments --- -my_slot_assignments : process( slot1_cs, slot2_cs) -begin - slot1_cs_n <= not slot1_cs; - slot2_cs_n <= not slot2_cs; -end process; - --- --- VGA ouputs --- -my_vga_assignments : process( vga_red_o, vga_green_o, vga_blue_o ) -begin - VGA_red(0) <= vga_red_o; - VGA_red(1) <= vga_red_o; - VGA_red(2) <= vga_red_o; - VGA_green(0) <= vga_green_o; - VGA_green(1) <= vga_green_o; - VGA_green(2) <= vga_green_o; - VGA_blue(0) <= vga_blue_o; - VGA_blue(1) <= vga_blue_o; - VGA_blue(2) <= vga_blue_o; -end process; - --- --- SDRAM assignments --- -my_sdram_assignments : process( cpu_clk, clk_i, cpu_reset, - opBegun, rdDone, wrDone, - ram_rd_state, ram_wr_state, - cpu_addr, dat_addr, - cpu_data_out, hDout, - ram_cs, cpu_rw, ram_hold ) -begin - if( cpu_reset = '1' ) then - hWr <= '0'; - hRd <= '0'; - wrDone <= '0'; - ram_wr_state <= wr_state0; - ram_rd_state <= rd_state0; - - elsif( clk_i'event and clk_i='0' ) then - -- - -- read state machine - -- - case ram_rd_state is - - when rd_state0 => - if (ram_hold = '1') and (cpu_rw = '1') then - hRd <= '1'; - ram_rd_state <= rd_state1; - end if; - - when rd_state1 => - if opBegun = '1' then - ram_rd_state <= rd_state2; - end if; - - when rd_state2 => - if rdDone = '1' then - hRd <= '0'; - ram_rd_state <= rd_state3; - end if; - - when rd_state3 => - if rdDone = '0' then - ram_rd_state <= rd_state0; - end if; - - when others => - hRd <= '0'; - ram_rd_state <= rd_state0; - end case; - - -- - -- Write state machine - -- - case ram_wr_state is - - when wr_state0 => - if (ram_hold = '1') and (cpu_rw = '0') then - hWr <= '1'; - wrDone <= '0'; - ram_wr_state <= wr_state1; - end if; - - when wr_state1 => - if opBegun = '1' then - hWr <= '0'; - wrDone <= '0'; - ram_wr_state <= wr_state2; - end if; - - when wr_state2 => - hWr <= '0'; - wrDone <= '0'; - ram_wr_state <= wr_state3; - - when wr_state3 => - hWr <= '0'; - wrDone <= '1'; - ram_wr_state <= wr_state4; - - when wr_state4 => - hWr <= '0'; - wrDone <= '0'; - ram_wr_state <= wr_state0; - - when others => - hWr <= '0'; - wrDone <= '0'; - ram_wr_state <= wr_state0; - - end case; - - end if; - -- - -- Strobe host RD and WR signals high on RAM select - -- Return low when cycle has started - -- - if( cpu_reset = '1' ) then - ram_hold <= '0'; - elsif( cpu_clk'event and cpu_clk='1' ) then - -- - -- Hold is intitiated when the RAM is selected - -- and released when access cycle is complete - -- - if (ram_hold = '0') and (ram_cs = '1') then - ram_hold <= '1'; - elsif (ram_hold = '1') and ((rdDone = '1') or (wrDone = '1')) then - ram_hold <= '0'; - end if; - end if; - - hAddr(23 downto 20) <= "0000"; - hAddr(19 downto 12) <= dat_addr; - hAddr(11 downto 0) <= cpu_addr(11 downto 0); - hDin(7 downto 0) <= cpu_data_out; - hDin(15 downto 8) <= (others => '0'); - ram_data_out <= hDout(7 downto 0); - -end process; - -end rtl; --===================== End of architecture =======================-- - Index: xsasdramcntl.vhd =================================================================== --- xsasdramcntl.vhd (revision 66) +++ xsasdramcntl.vhd (nonexistent) @@ -1,319 +0,0 @@ --------------------------------------------------------------------- --- Company : XESS Corp. --- Engineer : Dave Vanden Bout --- Creation Date : 05/17/2005 --- Copyright : 2005, XESS Corp --- Tool Versions : WebPACK 6.3.03i --- --- Description: --- Customizes the generic SDRAM controller module for the XSA Board. --- --- Revision: --- 1.1.0 --- --- Additional Comments: --- 1.1.0: --- Added CLK_DIV generic parameter to allow stepping-down the clock frequency. --- Added MULTIPLE_ACTIVE_ROWS generic parameter to enable/disable keeping an active row in each bank. --- 1.0.0: --- Initial release. --- --- License: --- This code can be freely distributed and modified as long as --- this header is not removed. --------------------------------------------------------------------- - - - -library IEEE, UNISIM; -use IEEE.std_logic_1164.all; -use IEEE.numeric_std.all; -use UNISIM.VComponents.all; -use WORK.common.all; -use WORK.sdram.all; - - -package XSASDRAM is - - component XSASDRAMCntl - generic( - FREQ : natural := 100_000; -- operating frequency in KHz - CLK_DIV : real := 2.0; -- divisor for FREQ (can only be 1.0, 1.5, 2.0, 2.5, 3.0, 4.0, 5.0, 8.0 or 16.0) - PIPE_EN : boolean := false; -- if true, enable pipelined read operations - MAX_NOP : natural := 10000; -- number of NOPs before entering self-refresh - MULTIPLE_ACTIVE_ROWS : boolean := false; -- if true, allow an active row in each bank - DATA_WIDTH : natural := 16; -- host & SDRAM data width - NROWS : natural := 8096; -- number of rows in SDRAM array - NCOLS : natural := 512; -- number of columns in SDRAM array - HADDR_WIDTH : natural := 24; -- host-side address width - SADDR_WIDTH : natural := 13 -- SDRAM-side address width - ); - port( - -- host side - clk : in std_logic; -- master clock - bufclk : out std_logic; -- buffered master clock - clk1x : out std_logic; -- host clock sync'ed to master clock (and divided if CLK_DIV>1) - clk2x : out std_logic; -- double-speed host clock - lock : out std_logic; -- true when host clock is locked to master clock - rst : in std_logic; -- reset - rd : in std_logic; -- initiate read operation - wr : in std_logic; -- initiate write operation - earlyOpBegun : out std_logic; -- read/write/self-refresh op begun (async) - opBegun : out std_logic; -- read/write/self-refresh op begun (clocked) - rdPending : out std_logic; -- read operation(s) are still in the pipeline - done : out std_logic; -- read or write operation is done - rdDone : out std_logic; -- read done and data is available - hAddr : in std_logic_vector(HADDR_WIDTH-1 downto 0); -- address from host - hDIn : in std_logic_vector(DATA_WIDTH-1 downto 0); -- data from host - hDOut : out std_logic_vector(DATA_WIDTH-1 downto 0); -- data to host - status : out std_logic_vector(3 downto 0); -- diagnostic status of the FSM - - -- SDRAM side - sclkfb : in std_logic; -- clock from SDRAM after PCB delays - sclk : out std_logic; -- SDRAM clock sync'ed to master clock - cke : out std_logic; -- clock-enable to SDRAM - cs_n : out std_logic; -- chip-select to SDRAM - ras_n : out std_logic; -- SDRAM row address strobe - cas_n : out std_logic; -- SDRAM column address strobe - we_n : out std_logic; -- SDRAM write enable - ba : out std_logic_vector(1 downto 0); -- SDRAM bank address bits - sAddr : out std_logic_vector(SADDR_WIDTH-1 downto 0); -- SDRAM row/column address - sData : inout std_logic_vector(DATA_WIDTH-1 downto 0); -- SDRAM in/out databus - dqmh : out std_logic; -- high databits I/O mask - dqml : out std_logic -- low databits I/O mask - ); - end component; - -end package XSASDRAM; - - - -library IEEE, UNISIM; -use IEEE.std_logic_1164.all; -use IEEE.numeric_std.all; -use UNISIM.VComponents.all; -use WORK.common.all; -use WORK.sdram.all; - -entity XSASDRAMCntl is - generic( - FREQ : natural := 100_000; -- operating frequency in KHz - CLK_DIV : real := 2.0; -- divisor for FREQ (can only be 1.0, 1.5, 2.0, 2.5, 3.0, 4.0, 5.0, 8.0 or 16.0) - PIPE_EN : boolean := false; -- if true, enable pipelined read operations - MAX_NOP : natural := 10000; -- number of NOPs before entering self-refresh - MULTIPLE_ACTIVE_ROWS : boolean := false; -- if true, allow an active row in each bank - DATA_WIDTH : natural := 16; -- host & SDRAM data width - NROWS : natural := 8192; -- number of rows in SDRAM array - NCOLS : natural := 512; -- number of columns in SDRAM array - HADDR_WIDTH : natural := 24; -- host-side address width - SADDR_WIDTH : natural := 13 -- SDRAM-side address width - ); - port( - -- host side - clk : in std_logic; -- master clock - bufclk : out std_logic; -- buffered master clock - clk1x : out std_logic; -- host clock sync'ed to master clock (and divided if CLK_DIV>1) - clk2x : out std_logic; -- double-speed host clock - lock : out std_logic; -- true when host clock is locked to master clock - rst : in std_logic; -- reset - rd : in std_logic; -- initiate read operation - wr : in std_logic; -- initiate write operation - earlyOpBegun : out std_logic; -- read/write/self-refresh op begun (async) - opBegun : out std_logic; -- read/write/self-refresh op begun (clocked) - rdPending : out std_logic; -- read operation(s) are still in the pipeline - done : out std_logic; -- read or write operation is done - rdDone : out std_logic; -- read done and data is available - hAddr : in std_logic_vector(HADDR_WIDTH-1 downto 0); -- address from host - hDIn : in std_logic_vector(DATA_WIDTH-1 downto 0); -- data from host - hDOut : out std_logic_vector(DATA_WIDTH-1 downto 0); -- data to host - status : out std_logic_vector(3 downto 0); -- diagnostic status of the FSM - - -- SDRAM side - sclkfb : in std_logic; -- clock from SDRAM after PCB delays - sclk : out std_logic; -- SDRAM clock sync'ed to master clock - cke : out std_logic; -- clock-enable to SDRAM - cs_n : out std_logic; -- chip-select to SDRAM - ras_n : out std_logic; -- SDRAM row address strobe - cas_n : out std_logic; -- SDRAM column address strobe - we_n : out std_logic; -- SDRAM write enable - ba : out std_logic_vector(1 downto 0); -- SDRAM bank address bits - sAddr : out std_logic_vector(SADDR_WIDTH-1 downto 0); -- SDRAM row/column address - sData : inout std_logic_vector(DATA_WIDTH-1 downto 0); -- SDRAM in/out databus - dqmh : out std_logic; -- high databits I/O mask - dqml : out std_logic -- low databits I/O mask - ); -end XSASDRAMCntl; - - - -architecture arch of XSASDRAMCntl is - - -- The SDRAM controller and external SDRAM chip will clock on the same edge - -- if the frequency and divided frequency are both greater than the minimum DLL lock frequency. - -- Otherwise the DLLs cannot be used so the SDRAM controller and external SDRAM clock on opposite edges - -- to try and mitigate the clock skew between the internal FPGA logic and the external SDRAM. - constant MIN_LOCK_FREQ : real := 25_000.0; - constant IN_PHASE : boolean := real(FREQ)/CLK_DIV >= MIN_LOCK_FREQ; - -- Calculate the frequency of the clock for the SDRAM. - constant SDRAM_FREQ : natural := int_select(IN_PHASE, (FREQ*integer(2.0*CLK_DIV))/2, FREQ); - -- Compute the CLKDV_DIVIDE generic paramter for the DLL modules. It defaults to 2 when CLK_DIV=1 - -- because the DLL does not support a divisor of 1 on the CLKDV output. We use the CLK0 output - -- when CLK_DIV=1 so we don't care what is output on thr CLK_DIV output of the DLL. - constant CLKDV_DIVIDE : real := real_select(CLK_DIV = 1.0, 2.0, CLK_DIV); - - signal int_clkin, -- signals for internal logic clock DLL - int_clk1x, int_clk1x_b, - int_clk2x, int_clk2x_b, - int_clkdv, int_clkdv_b : std_logic; - signal ext_clkin, sclkfb_b, ext_clk1x : std_logic; -- signals for external logic clock DLL - signal dllext_rst, dllext_rst_n : std_logic; -- external DLL reset signal - signal clk_i : std_logic; -- clock for SDRAM controller logic - signal int_lock, ext_lock, lock_i : std_logic; -- DLL lock signals - - -- bus for holding output data from SDRAM - signal sDOut : std_logic_vector(sData'range); - signal sDOutEn : std_logic; - -begin - - ----------------------------------------------------------- - -- setup the DLLs for clock generation - ----------------------------------------------------------- - - -- master clock must come from a dedicated clock pin - clkin : IBUFG port map (I => clk, O => int_clkin); - - -- The external DLL is driven from the same source as the internal DLL - -- if the clock divisor is 1. If CLK_DIV is greater than 1, then the external DLL - -- is driven by the divided clock from the internal DLL. Otherwise, the SDRAM will be - -- clocked on the opposite edge if the internal and external logic are not in-phase. - ext_clkin <= int_clkin when (IN_PHASE and (CLK_DIV = 1.0)) else - int_clkdv_b when (IN_PHASE and (CLK_DIV/=1.0)) else - not int_clkin; - - -- Generate the DLLs for sync'ing the clocks as long as the clocks - -- have a frequency high enough for the DLLs to lock - gen_dlls : if IN_PHASE generate - - -- generate an internal clock sync'ed to the master clock - dllint : CLKDLL - generic map( - CLKDV_DIVIDE => CLKDV_DIVIDE - ) - port map( - CLKIN => int_clkin, - CLKFB => int_clk1x_b, - CLK0 => int_clk1x, - RST => ZERO, - CLK90 => open, - CLK180 => open, - CLK270 => open, - CLK2X => int_clk2x, - CLKDV => int_clkdv, - LOCKED => int_lock - ); - - -- sync'ed single, doubled and divided clocks for use by internal logic - int_clk1x_buf : BUFG port map(I => int_clk1x, O => int_clk1x_b); - int_clk2x_buf : BUFG port map(I => int_clk2x, O => int_clk2x_b); - int_clkdv_buf : BUFG port map(I => int_clkdv, O => int_clkdv_b); - - -- The external DLL is held in a reset state until the internal DLL locks. - -- Then the external DLL reset is released after a delay set by this shift register. - -- This keeps the external DLL from locking onto the internal DLL clock signal - -- until it is stable. - SRL16_inst : SRL16 - generic map ( - INIT => X"0000" - ) - port map ( - CLK => clk_i, - A0 => '1', - A1 => '1', - A2 => '1', - A3 => '1', - D => int_lock, - Q => dllext_rst_n - ); - dllext_rst <= not dllext_rst when CLK_DIV/=1.0 else ZERO; - - -- generate an external SDRAM clock sync'ed to the master clock - sclkfb_buf : IBUFG port map(I => sclkfb, O => sclkfb_b); -- SDRAM clock with PCB delays --- sclkfb_buf : BUFGMUX port map(I => sclkfb, O => sclkfb_b); -- SDRAM clock with PCB delays - dllext : CLKDLL port map( - CLKIN => ext_clkin, -- this is either the master clock or the divided clock from the internal DLL - CLKFB => sclkfb_b, - CLK0 => ext_clk1x, - RST => dllext_rst, - CLK90 => open, - CLK180 => open, - CLK270 => open, - CLK2X => open, - CLKDV => open, - LOCKED => ext_lock - ); - - end generate; - - -- The buffered clock is just a buffered version of the master clock. - bufclk <= int_clkin; - -- The host-side clock comes from the CLK0 output of the internal DLL if the clock divisor is 1. - -- Otherwise it comes from the CLKDV output if the clock divisor is greater than 1. - -- Otherwise it is just a copy of the master clock if the DLLs aren't being used. - clk_i <= int_clk1x_b when (IN_PHASE and (CLK_DIV = 1.0)) else - int_clkdv_b when (IN_PHASE and (CLK_DIV/=1.0)) else - int_clkin; - clk1x <= clk_i; -- This is the output of the host-side clock - clk2x <= int_clk2x_b when IN_PHASE else int_clkin; -- this is the doubled master clock - sclk <= ext_clk1x when IN_PHASE else ext_clkin; -- this is the clock for the external SDRAM - - -- indicate the lock status of the internal and external DLL - lock_i <= int_lock and ext_lock when IN_PHASE else YES; - lock <= lock_i; -- lock signal for the host logic - - -- SDRAM memory controller module - u1 : sdramCntl - generic map( - FREQ => SDRAM_FREQ, - IN_PHASE => IN_PHASE, - PIPE_EN => PIPE_EN, - MAX_NOP => MAX_NOP, - MULTIPLE_ACTIVE_ROWS => MULTIPLE_ACTIVE_ROWS, - DATA_WIDTH => DATA_WIDTH, - NROWS => NROWS, - NCOLS => NCOLS, - HADDR_WIDTH => HADDR_WIDTH, - SADDR_WIDTH => SADDR_WIDTH - ) - port map( - clk => clk_i, -- master clock from external clock source (unbuffered) - lock => lock_i, -- valid synchronized clocks indicator - rst => rst, -- reset - rd => rd, -- host-side SDRAM read control from memory tester - wr => wr, -- host-side SDRAM write control from memory tester - rdPending => rdPending, - opBegun => opBegun, -- SDRAM memory read/write done indicator - earlyOpBegun => earlyOpBegun, -- SDRAM memory read/write done indicator - rdDone => rdDone, -- SDRAM memory read/write done indicator - done => done, - hAddr => hAddr, -- host-side address from memory tester - hDIn => hDIn, -- test data pattern from memory tester - hDOut => hDOut, -- SDRAM data output to memory tester - status => status, -- SDRAM controller state (for diagnostics) - cke => cke, -- SDRAM clock enable - ce_n => cs_n, -- SDRAM chip-select - ras_n => ras_n, -- SDRAM RAS - cas_n => cas_n, -- SDRAM CAS - we_n => we_n, -- SDRAM write-enable - ba => ba, -- SDRAM bank address - sAddr => sAddr, -- SDRAM address - sDIn => sData, -- input data from SDRAM - sDOut => sDOut, -- output data to SDRAM - sDOutEn => sDOutEn, -- enable drivers to send data to SDRAM - dqmh => dqmh, -- SDRAM DQMH - dqml => dqml -- SDRAM DQML - ); - - sData <= sDOut when sDOutEn = YES else (others => 'Z'); - -end arch; Index: sdramcntl.vhd =================================================================== --- sdramcntl.vhd (revision 66) +++ sdramcntl.vhd (nonexistent) @@ -1,1022 +0,0 @@ -library IEEE, UNISIM; -use IEEE.std_logic_1164.all; - -package sdram is - - -- SDRAM controller - component sdramCntl - generic( - FREQ : natural := 100_000; -- operating frequency in KHz - IN_PHASE : boolean := true; -- SDRAM and controller work on same or opposite clock edge - PIPE_EN : boolean := false; -- if true, enable pipelined read operations - MAX_NOP : natural := 10000; -- number of NOPs before entering self-refresh - MULTIPLE_ACTIVE_ROWS : boolean := false; -- if true, allow an active row in each bank - DATA_WIDTH : natural := 16; -- host & SDRAM data width - NROWS : natural := 8192; -- number of rows in SDRAM array - NCOLS : natural := 512; -- number of columns in SDRAM array - HADDR_WIDTH : natural := 24; -- host-side address width - SADDR_WIDTH : natural := 13 -- SDRAM-side address width - ); - port( - -- host side - clk : in std_logic; -- master clock - lock : in std_logic; -- true if clock is stable - rst : in std_logic; -- reset - rd : in std_logic; -- initiate read operation - wr : in std_logic; -- initiate write operation - earlyOpBegun : out std_logic; -- read/write/self-refresh op has begun (async) - opBegun : out std_logic; -- read/write/self-refresh op has begun (clocked) - rdPending : out std_logic; -- true if read operation(s) are still in the pipeline - done : out std_logic; -- read or write operation is done - rdDone : out std_logic; -- read operation is done and data is available - hAddr : in std_logic_vector(HADDR_WIDTH-1 downto 0); -- address from host to SDRAM - hDIn : in std_logic_vector(DATA_WIDTH-1 downto 0); -- data from host to SDRAM - hDOut : out std_logic_vector(DATA_WIDTH-1 downto 0); -- data from SDRAM to host - status : out std_logic_vector(3 downto 0); -- diagnostic status of the FSM - -- SDRAM side - cke : out std_logic; -- clock-enable to SDRAM - ce_n : out std_logic; -- chip-select to SDRAM - ras_n : out std_logic; -- SDRAM row address strobe - cas_n : out std_logic; -- SDRAM column address strobe - we_n : out std_logic; -- SDRAM write enable - ba : out std_logic_vector(1 downto 0); -- SDRAM bank address - sAddr : out std_logic_vector(SADDR_WIDTH-1 downto 0); -- SDRAM row/column address - sDIn : in std_logic_vector(DATA_WIDTH-1 downto 0); -- data from SDRAM - sDOut : out std_logic_vector(DATA_WIDTH-1 downto 0); -- data to SDRAM - sDOutEn : out std_logic; -- true if data is output to SDRAM on sDOut - dqmh : out std_logic; -- enable upper-byte of SDRAM databus if true - dqml : out std_logic -- enable lower-byte of SDRAM databus if true - ); - end component; - - -- dual-port interface to the SDRAM controller - component dualport - generic( - PIPE_EN : boolean := false; -- enable pipelined read operations - PORT_TIME_SLOTS : std_logic_vector(15 downto 0) := "1111000011110000"; - DATA_WIDTH : natural := 16; -- host & SDRAM data width - HADDR_WIDTH : natural := 23 -- host-side address width - ); - port( - clk : in std_logic; -- master clock - - -- host-side port 0 - rst0 : in std_logic; -- reset - rd0 : in std_logic; -- initiate read operation - wr0 : in std_logic; -- initiate write operation - earlyOpBegun0 : out std_logic; -- read/write op has begun (async) - opBegun0 : out std_logic; -- read/write op has begun (clocked) - rdPending0 : out std_logic; -- true if read operation(s) are still in the pipeline - done0 : out std_logic; -- read or write operation is done - rdDone0 : out std_logic; -- read operation is done and data is available - hAddr0 : in std_logic_vector(HADDR_WIDTH-1 downto 0); -- address from host to SDRAM - hDIn0 : in std_logic_vector(DATA_WIDTH-1 downto 0); -- data from host to SDRAM - hDOut0 : out std_logic_vector(DATA_WIDTH-1 downto 0); -- data from SDRAM to host - status0 : out std_logic_vector(3 downto 0); -- diagnostic status of the SDRAM controller FSM - - -- host-side port 1 - rst1 : in std_logic; - rd1 : in std_logic; - wr1 : in std_logic; - earlyOpBegun1 : out std_logic; - opBegun1 : out std_logic; - rdPending1 : out std_logic; - done1 : out std_logic; - rdDone1 : out std_logic; - hAddr1 : in std_logic_vector(HADDR_WIDTH-1 downto 0); - hDIn1 : in std_logic_vector(DATA_WIDTH-1 downto 0); - hDOut1 : out std_logic_vector(DATA_WIDTH-1 downto 0); - status1 : out std_logic_vector(3 downto 0); - - -- SDRAM controller port - rst : out std_logic; - rd : out std_logic; - wr : out std_logic; - earlyOpBegun : in std_logic; - opBegun : in std_logic; - rdPending : in std_logic; - done : in std_logic; - rdDone : in std_logic; - hAddr : out std_logic_vector(HADDR_WIDTH-1 downto 0); - hDIn : out std_logic_vector(DATA_WIDTH-1 downto 0); - hDOut : in std_logic_vector(DATA_WIDTH-1 downto 0); - status : in std_logic_vector(3 downto 0) - ); - end component; - -end package sdram; - - - - --------------------------------------------------------------------- --- Company : XESS Corp. --- Engineer : Dave Vanden Bout --- Creation Date : 05/17/2005 --- Copyright : 2005, XESS Corp --- Tool Versions : WebPACK 6.3.03i --- --- Description: --- SDRAM controller --- --- Revision: --- 1.4.0 --- --- Additional Comments: --- 1.4.0: --- Added generic parameter to enable/disable independent active rows in each bank. --- 1.3.0: --- Modified to allow independently active rows in each bank. --- 1.2.0: --- Modified to allow pipelining of read/write operations. --- 1.1.0: --- Initial release. --- --- License: --- This code can be freely distributed and modified as long as --- this header is not removed. --------------------------------------------------------------------- - -library IEEE, UNISIM; -use IEEE.std_logic_1164.all; -use IEEE.std_logic_unsigned.all; -use IEEE.numeric_std.all; -use WORK.common.all; - -entity sdramCntl is - generic( - FREQ : natural := 100_000; -- operating frequency in KHz - IN_PHASE : boolean := true; -- SDRAM and controller work on same or opposite clock edge - PIPE_EN : boolean := false; -- if true, enable pipelined read operations - MAX_NOP : natural := 10000; -- number of NOPs before entering self-refresh - MULTIPLE_ACTIVE_ROWS : boolean := false; -- if true, allow an active row in each bank - DATA_WIDTH : natural := 16; -- host & SDRAM data width - NROWS : natural := 8192; -- number of rows in SDRAM array - NCOLS : natural := 512; -- number of columns in SDRAM array - HADDR_WIDTH : natural := 24; -- host-side address width - SADDR_WIDTH : natural := 13 -- SDRAM-side address width - ); - port( - -- host side - clk : in std_logic; -- master clock - lock : in std_logic; -- true if clock is stable - rst : in std_logic; -- reset - rd : in std_logic; -- initiate read operation - wr : in std_logic; -- initiate write operation - earlyOpBegun : out std_logic; -- read/write/self-refresh op has begun (async) - opBegun : out std_logic; -- read/write/self-refresh op has begun (clocked) - rdPending : out std_logic; -- true if read operation(s) are still in the pipeline - done : out std_logic; -- read or write operation is done - rdDone : out std_logic; -- read operation is done and data is available - hAddr : in std_logic_vector(HADDR_WIDTH-1 downto 0); -- address from host to SDRAM - hDIn : in std_logic_vector(DATA_WIDTH-1 downto 0); -- data from host to SDRAM - hDOut : out std_logic_vector(DATA_WIDTH-1 downto 0); -- data from SDRAM to host - status : out std_logic_vector(3 downto 0); -- diagnostic status of the FSM - - -- SDRAM side - cke : out std_logic; -- clock-enable to SDRAM - ce_n : out std_logic; -- chip-select to SDRAM - ras_n : out std_logic; -- SDRAM row address strobe - cas_n : out std_logic; -- SDRAM column address strobe - we_n : out std_logic; -- SDRAM write enable - ba : out std_logic_vector(1 downto 0); -- SDRAM bank address - sAddr : out std_logic_vector(SADDR_WIDTH-1 downto 0); -- SDRAM row/column address - sDIn : in std_logic_vector(DATA_WIDTH-1 downto 0); -- data from SDRAM - sDOut : out std_logic_vector(DATA_WIDTH-1 downto 0); -- data to SDRAM - sDOutEn : out std_logic; -- true if data is output to SDRAM on sDOut - dqmh : out std_logic; -- enable upper-byte of SDRAM databus if true - dqml : out std_logic -- enable lower-byte of SDRAM databus if true - ); -end sdramCntl; - - - -architecture arch of sdramCntl is - - constant OUTPUT : std_logic := '1'; -- direction of dataflow w.r.t. this controller - constant INPUT : std_logic := '0'; - constant NOP : std_logic := '0'; -- no operation - constant READ : std_logic := '1'; -- read operation - constant WRITE : std_logic := '1'; -- write operation - - -- SDRAM timing parameters - constant Tinit : natural := 200; -- min initialization interval (us) - constant Tras : natural := 45; -- min interval between active to precharge commands (ns) - constant Trcd : natural := 20; -- min interval between active and R/W commands (ns) - constant Tref : natural := 64_000_000; -- maximum refresh interval (ns) - constant Trfc : natural := 66; -- duration of refresh operation (ns) - constant Trp : natural := 20; -- min precharge command duration (ns) - constant Twr : natural := 15; -- write recovery time (ns) - constant Txsr : natural := 75; -- exit self-refresh time (ns) - - -- SDRAM timing parameters converted into clock cycles (based on FREQ) - constant NORM : natural := 1_000_000; -- normalize ns * KHz - constant INIT_CYCLES : natural := 1+((Tinit*FREQ)/1000); -- SDRAM power-on initialization interval - constant RAS_CYCLES : natural := 1+((Tras*FREQ)/NORM); -- active-to-precharge interval - constant RCD_CYCLES : natural := 1+((Trcd*FREQ)/NORM); -- active-to-R/W interval - constant REF_CYCLES : natural := 1+(((Tref/NROWS)*FREQ)/NORM); -- interval between row refreshes - constant RFC_CYCLES : natural := 1+((Trfc*FREQ)/NORM); -- refresh operation interval - constant RP_CYCLES : natural := 1+((Trp*FREQ)/NORM); -- precharge operation interval - constant WR_CYCLES : natural := 1+((Twr*FREQ)/NORM); -- write recovery time - constant XSR_CYCLES : natural := 1+((Txsr*FREQ)/NORM); -- exit self-refresh time - constant MODE_CYCLES : natural := 2; -- mode register setup time - constant CAS_CYCLES : natural := 3; -- CAS latency - constant RFSH_OPS : natural := 8; -- number of refresh operations needed to init SDRAM - - -- timer registers that count down times for various SDRAM operations - signal timer_r, timer_x : natural range 0 to INIT_CYCLES; -- current SDRAM op time - signal rasTimer_r, rasTimer_x : natural range 0 to RAS_CYCLES; -- active-to-precharge time - signal wrTimer_r, wrTimer_x : natural range 0 to WR_CYCLES; -- write-to-precharge time - signal refTimer_r, refTimer_x : natural range 0 to REF_CYCLES; -- time between row refreshes - signal rfshCntr_r, rfshCntr_x : natural range 0 to NROWS; -- counts refreshes that are neede - signal nopCntr_r, nopCntr_x : natural range 0 to MAX_NOP; -- counts consecutive NOP operations - - signal doSelfRfsh : std_logic; -- active when the NOP counter hits zero and self-refresh can start - - -- states of the SDRAM controller state machine - type cntlState is ( - INITWAIT, -- initialization - waiting for power-on initialization to complete - INITPCHG, -- initialization - initial precharge of SDRAM banks - INITSETMODE, -- initialization - set SDRAM mode - INITRFSH, -- initialization - do initial refreshes - RW, -- read/write/refresh the SDRAM - ACTIVATE, -- open a row of the SDRAM for reading/writing - REFRESHROW, -- refresh a row of the SDRAM - SELFREFRESH -- keep SDRAM in self-refresh mode with CKE low - ); - signal state_r, state_x : cntlState; -- state register and next state - - -- commands that are sent to the SDRAM to make it perform certain operations - -- commands use these SDRAM input pins (ce_n,ras_n,cas_n,we_n,dqmh,dqml) - subtype sdramCmd is unsigned(5 downto 0); - constant NOP_CMD : sdramCmd := "011100"; - constant ACTIVE_CMD : sdramCmd := "001100"; - constant READ_CMD : sdramCmd := "010100"; - constant WRITE_CMD : sdramCmd := "010000"; - constant PCHG_CMD : sdramCmd := "001011"; - constant MODE_CMD : sdramCmd := "000011"; - constant RFSH_CMD : sdramCmd := "000111"; - - -- SDRAM mode register - -- the SDRAM is placed in a non-burst mode (burst length = 1) with a 3-cycle CAS - subtype sdramMode is std_logic_vector(12 downto 0); - constant MODE : sdramMode := "000" & "0" & "00" & "011" & "0" & "000"; - - -- the host address is decomposed into these sets of SDRAM address components - constant ROW_LEN : natural := log2(NROWS); -- number of row address bits - constant COL_LEN : natural := log2(NCOLS); -- number of column address bits - signal bank : std_logic_vector(ba'range); -- bank address bits - signal row : std_logic_vector(ROW_LEN - 1 downto 0); -- row address within bank - signal col : std_logic_vector(sAddr'range); -- column address within row - - -- registers that store the currently active row in each bank of the SDRAM - constant NUM_ACTIVE_ROWS : integer := int_select(MULTIPLE_ACTIVE_ROWS = false, 1, 2**ba'length); - type activeRowType is array(0 to NUM_ACTIVE_ROWS-1) of std_logic_vector(row'range); - signal activeRow_r, activeRow_x : activeRowType; - signal activeFlag_r, activeFlag_x : std_logic_vector(0 to NUM_ACTIVE_ROWS-1); -- indicates that some row in a bank is active - signal bankIndex : natural range 0 to NUM_ACTIVE_ROWS-1; -- bank address bits - signal activeBank_r, activeBank_x : std_logic_vector(ba'range); -- indicates the bank with the active row - signal doActivate : std_logic; -- indicates when a new row in a bank needs to be activated - - -- there is a command bit embedded within the SDRAM column address - constant CMDBIT_POS : natural := 10; -- position of command bit - constant AUTO_PCHG_ON : std_logic := '1'; -- CMDBIT value to auto-precharge the bank - constant AUTO_PCHG_OFF : std_logic := '0'; -- CMDBIT value to disable auto-precharge - constant ONE_BANK : std_logic := '0'; -- CMDBIT value to select one bank - constant ALL_BANKS : std_logic := '1'; -- CMDBIT value to select all banks - - -- status signals that indicate when certain operations are in progress - signal wrInProgress : std_logic; -- write operation in progress - signal rdInProgress : std_logic; -- read operation in progress - signal activateInProgress : std_logic; -- row activation is in progress - - -- these registers track the progress of read and write operations - signal rdPipeline_r, rdPipeline_x : std_logic_vector(CAS_CYCLES+1 downto 0); -- pipeline of read ops in progress - signal wrPipeline_r, wrPipeline_x : std_logic_vector(0 downto 0); -- pipeline of write ops (only need 1 cycle) - - -- registered outputs to host - signal opBegun_r, opBegun_x : std_logic; -- true when SDRAM read or write operation is started - signal hDOut_r, hDOut_x : std_logic_vector(hDOut'range); -- holds data read from SDRAM and sent to the host - signal hDOutOppPhase_r, hDOutOppPhase_x : std_logic_vector(hDOut'range); -- holds data read from SDRAM on opposite clock edge - - -- registered outputs to SDRAM - signal cke_r, cke_x : std_logic; -- clock enable - signal cmd_r, cmd_x : sdramCmd; -- SDRAM command bits - signal ba_r, ba_x : std_logic_vector(ba'range); -- SDRAM bank address bits - signal sAddr_r, sAddr_x : std_logic_vector(sAddr'range); -- SDRAM row/column address - signal sData_r, sData_x : std_logic_vector(sDOut'range); -- SDRAM out databus - signal sDataDir_r, sDataDir_x : std_logic; -- SDRAM databus direction control bit - -begin - - ----------------------------------------------------------- - -- attach some internal signals to the I/O ports - ----------------------------------------------------------- - - -- attach registered SDRAM control signals to SDRAM input pins - (ce_n, ras_n, cas_n, we_n, dqmh, dqml) <= cmd_r; -- SDRAM operation control bits - cke <= cke_r; -- SDRAM clock enable - ba <= ba_r; -- SDRAM bank address - sAddr <= sAddr_r; -- SDRAM address - sDOut <= sData_r; -- SDRAM output data bus - sDOutEn <= YES when sDataDir_r = OUTPUT else NO; -- output databus enable - - -- attach some port signals - hDOut <= hDOut_r; -- data back to host - opBegun <= opBegun_r; -- true if requested operation has begun - - - ----------------------------------------------------------- - -- compute the next state and outputs - ----------------------------------------------------------- - - combinatorial : process(rd, wr, hAddr, hDIn, hDOut_r, sDIn, state_r, opBegun_x, - activeFlag_r, activeRow_r, rdPipeline_r, wrPipeline_r, - hDOutOppPhase_r, nopCntr_r, lock, rfshCntr_r, timer_r, rasTimer_r, - wrTimer_r, refTimer_r, cmd_r, cke_r, activeBank_r, ba_r ) - begin - - ----------------------------------------------------------- - -- setup default values for signals - ----------------------------------------------------------- - - opBegun_x <= NO; -- no operations have begun - earlyOpBegun <= opBegun_x; - cke_x <= YES; -- enable SDRAM clock - cmd_x <= NOP_CMD; -- set SDRAM command to no-operation - sDataDir_x <= INPUT; -- accept data from the SDRAM - sData_x <= hDIn(sData_x'range); -- output data from host to SDRAM - state_x <= state_r; -- reload these registers and flags - activeFlag_x <= activeFlag_r; -- with their existing values - activeRow_x <= activeRow_r; - activeBank_x <= activeBank_r; - rfshCntr_x <= rfshCntr_r; - - ----------------------------------------------------------- - -- setup default value for the SDRAM address - ----------------------------------------------------------- - - -- extract bank field from host address - ba_x <= hAddr(ba'length + ROW_LEN + COL_LEN - 1 downto ROW_LEN + COL_LEN); - if MULTIPLE_ACTIVE_ROWS = true then - bank <= (others => '0'); - bankIndex <= CONV_INTEGER(ba_x); - else - bank <= ba_x; - bankIndex <= 0; - end if; - -- extract row, column fields from host address - row <= hAddr(ROW_LEN + COL_LEN - 1 downto COL_LEN); - -- extend column (if needed) until it is as large as the (SDRAM address bus - 1) - col <= (others => '0'); -- set it to all zeroes - col(COL_LEN-1 downto 0) <= hAddr(COL_LEN-1 downto 0); - -- by default, set SDRAM address to the column address with interspersed - -- command bit set to disable auto-precharge - sAddr_x <= col(col'high-1 downto CMDBIT_POS) & AUTO_PCHG_OFF - & col(CMDBIT_POS-1 downto 0); - - ----------------------------------------------------------- - -- manage the read and write operation pipelines - ----------------------------------------------------------- - - -- determine if read operations are in progress by the presence of - -- READ flags in the read pipeline - if rdPipeline_r(rdPipeline_r'high downto 1) /= 0 then - rdInProgress <= YES; - else - rdInProgress <= NO; - end if; - rdPending <= rdInProgress; -- tell the host if read operations are in progress - - -- enter NOPs into the read and write pipeline shift registers by default - rdPipeline_x <= NOP & rdPipeline_r(rdPipeline_r'high downto 1); - wrPipeline_x(0) <= NOP; - - -- transfer data from SDRAM to the host data register if a read flag has exited the pipeline - -- (the transfer occurs 1 cycle before we tell the host the read operation is done) - if rdPipeline_r(1) = READ then - hDOutOppPhase_x <= sDIn(hDOut'range); -- gets value on the SDRAM databus on the opposite phase - if IN_PHASE then - -- get the SDRAM data for the host directly from the SDRAM if the controller and SDRAM are in-phase - hDOut_x <= sDIn(hDOut'range); - else - -- otherwise get the SDRAM data that was gathered on the previous opposite clock edge - hDOut_x <= hDOutOppPhase_r(hDOut'range); - end if; - else - -- retain contents of host data registers if no data from the SDRAM has arrived yet - hDOutOppPhase_x <= hDOutOppPhase_r; - hDOut_x <= hDOut_r; - end if; - - done <= rdPipeline_r(0) or wrPipeline_r(0); -- a read or write operation is done - rdDone <= rdPipeline_r(0); -- SDRAM data available when a READ flag exits the pipeline - - ----------------------------------------------------------- - -- manage row activation - ----------------------------------------------------------- - - -- request a row activation operation if the row of the current address - -- does not match the currently active row in the bank, or if no row - -- in the bank is currently active - if (bank /= activeBank_r) or (row /= activeRow_r(bankIndex)) or (activeFlag_r(bankIndex) = NO) then - doActivate <= YES; - else - doActivate <= NO; - end if; - - ----------------------------------------------------------- - -- manage self-refresh - ----------------------------------------------------------- - - -- enter self-refresh if neither a read or write is requested for MAX_NOP consecutive cycles. - if (rd = YES) or (wr = YES) then - -- any read or write resets NOP counter and exits self-refresh state - nopCntr_x <= 0; - doSelfRfsh <= NO; - elsif nopCntr_r /= MAX_NOP then - -- increment NOP counter whenever there is no read or write operation - nopCntr_x <= nopCntr_r + 1; - doSelfRfsh <= NO; - else - -- start self-refresh when counter hits maximum NOP count and leave counter unchanged - nopCntr_x <= nopCntr_r; - doSelfRfsh <= YES; - end if; - - ----------------------------------------------------------- - -- update the timers - ----------------------------------------------------------- - - -- row activation timer - if rasTimer_r /= 0 then - -- decrement a non-zero timer and set the flag - -- to indicate the row activation is still inprogress - rasTimer_x <= rasTimer_r - 1; - activateInProgress <= YES; - else - -- on timeout, keep the timer at zero and reset the flag - -- to indicate the row activation operation is done - rasTimer_x <= rasTimer_r; - activateInProgress <= NO; - end if; - - -- write operation timer - if wrTimer_r /= 0 then - -- decrement a non-zero timer and set the flag - -- to indicate the write operation is still inprogress - wrTimer_x <= wrTimer_r - 1; - wrInPRogress <= YES; - else - -- on timeout, keep the timer at zero and reset the flag that - -- indicates a write operation is in progress - wrTimer_x <= wrTimer_r; - wrInPRogress <= NO; - end if; - - -- refresh timer - if refTimer_r /= 0 then - refTimer_x <= refTimer_r - 1; - else - -- on timeout, reload the timer with the interval between row refreshes - -- and increment the counter for the number of row refreshes that are needed - refTimer_x <= REF_CYCLES; - rfshCntr_x <= rfshCntr_r + 1; - end if; - - -- main timer for sequencing SDRAM operations - if timer_r /= 0 then - -- decrement the timer and do nothing else since the previous operation has not completed yet. - timer_x <= timer_r - 1; - status <= "0000"; - else - -- the previous operation has completed once the timer hits zero - timer_x <= timer_r; -- by default, leave the timer at zero - - ----------------------------------------------------------- - -- compute the next state and outputs - ----------------------------------------------------------- - case state_r is - - ----------------------------------------------------------- - -- let clock stabilize and then wait for the SDRAM to initialize - ----------------------------------------------------------- - when INITWAIT => - if lock = YES then - -- wait for SDRAM power-on initialization once the clock is stable - timer_x <= INIT_CYCLES; -- set timer for initialization duration - state_x <= INITPCHG; - else - -- disable SDRAM clock and return to this state if the clock is not stable - -- this insures the clock is stable before enabling the SDRAM - -- it also insures a clean startup if the SDRAM is currently in self-refresh mode - cke_x <= NO; - end if; - status <= "0001"; - - ----------------------------------------------------------- - -- precharge all SDRAM banks after power-on initialization - ----------------------------------------------------------- - when INITPCHG => - cmd_x <= PCHG_CMD; - sAddr_x(CMDBIT_POS) <= ALL_BANKS; -- precharge all banks - timer_x <= RP_CYCLES; -- set timer for precharge operation duration - rfshCntr_x <= RFSH_OPS; -- set counter for refresh ops needed after precharge - state_x <= INITRFSH; - status <= "0010"; - - ----------------------------------------------------------- - -- refresh the SDRAM a number of times after initial precharge - ----------------------------------------------------------- - when INITRFSH => - cmd_x <= RFSH_CMD; - timer_x <= RFC_CYCLES; -- set timer to refresh operation duration - rfshCntr_x <= rfshCntr_r - 1; -- decrement refresh operation counter - if rfshCntr_r = 1 then - state_x <= INITSETMODE; -- set the SDRAM mode once all refresh ops are done - end if; - status <= "0011"; - - ----------------------------------------------------------- - -- set the mode register of the SDRAM - ----------------------------------------------------------- - when INITSETMODE => - cmd_x <= MODE_CMD; - sAddr_x <= MODE; -- output mode register bits on the SDRAM address bits - timer_x <= MODE_CYCLES; -- set timer for mode setting operation duration - state_x <= RW; - status <= "0100"; - - ----------------------------------------------------------- - -- process read/write/refresh operations after initialization is done - ----------------------------------------------------------- - when RW => - ----------------------------------------------------------- - -- highest priority operation: row refresh - -- do a refresh operation if the refresh counter is non-zero - ----------------------------------------------------------- - if rfshCntr_r /= 0 then - -- wait for any row activations, writes or reads to finish before doing a precharge - if (activateInProgress = NO) and (wrInProgress = NO) and (rdInProgress = NO) then - cmd_x <= PCHG_CMD; -- initiate precharge of the SDRAM - sAddr_x(CMDBIT_POS) <= ALL_BANKS; -- precharge all banks - timer_x <= RP_CYCLES; -- set timer for this operation - activeFlag_x <= (others => NO); -- all rows are inactive after a precharge operation - state_x <= REFRESHROW; -- refresh the SDRAM after the precharge - end if; - status <= "0101"; - ----------------------------------------------------------- - -- do a host-initiated read operation - ----------------------------------------------------------- - elsif rd = YES then - -- Wait one clock cycle if the bank address has just changed and each bank has its own active row. - -- This gives extra time for the row activation circuitry. - if (ba_x = ba_r) or (MULTIPLE_ACTIVE_ROWS=false) then - -- activate a new row if the current read is outside the active row or bank - if doActivate = YES then - -- activate new row only if all previous activations, writes, reads are done - if (activateInProgress = NO) and (wrInProgress = NO) and (rdInProgress = NO) then - cmd_x <= PCHG_CMD; -- initiate precharge of the SDRAM - sAddr_x(CMDBIT_POS) <= ONE_BANK; -- precharge this bank - timer_x <= RP_CYCLES; -- set timer for this operation - activeFlag_x(bankIndex) <= NO; -- rows in this bank are inactive after a precharge operation - state_x <= ACTIVATE; -- activate the new row after the precharge is done - end if; - -- read from the currently active row if no previous read operation - -- is in progress or if pipeline reads are enabled - -- we can always initiate a read even if a write is already in progress - elsif (rdInProgress = NO) or PIPE_EN then - cmd_x <= READ_CMD; -- initiate a read of the SDRAM - -- insert a flag into the pipeline shift register that will exit the end - -- of the shift register when the data from the SDRAM is available - rdPipeline_x <= READ & rdPipeline_r(rdPipeline_r'high downto 1); - opBegun_x <= YES; -- tell the host the requested operation has begun - end if; - end if; - status <= "0110"; - ----------------------------------------------------------- - -- do a host-initiated write operation - ----------------------------------------------------------- - elsif wr = YES then - -- Wait one clock cycle if the bank address has just changed and each bank has its own active row. - -- This gives extra time for the row activation circuitry. - if (ba_x = ba_r) or (MULTIPLE_ACTIVE_ROWS=false) then - -- activate a new row if the current write is outside the active row or bank - if doActivate = YES then - -- activate new row only if all previous activations, writes, reads are done - if (activateInProgress = NO) and (wrInProgress = NO) and (rdInProgress = NO) then - cmd_x <= PCHG_CMD; -- initiate precharge of the SDRAM - sAddr_x(CMDBIT_POS) <= ONE_BANK; -- precharge this bank - timer_x <= RP_CYCLES; -- set timer for this operation - activeFlag_x(bankIndex) <= NO; -- rows in this bank are inactive after a precharge operation - state_x <= ACTIVATE; -- activate the new row after the precharge is done - end if; - -- write to the currently active row if no previous read operations are in progress - elsif rdInProgress = NO then - cmd_x <= WRITE_CMD; -- initiate the write operation - sDataDir_x <= OUTPUT; -- turn on drivers to send data to SDRAM - -- set timer so precharge doesn't occur too soon after write operation - wrTimer_x <= WR_CYCLES; - -- insert a flag into the 1-bit pipeline shift register that will exit on the - -- next cycle. The write into SDRAM is not actually done by that time, but - -- this doesn't matter to the host - wrPipeline_x(0) <= WRITE; - opBegun_x <= YES; -- tell the host the requested operation has begun - end if; - end if; - status <= "0111"; - ----------------------------------------------------------- - -- do a host-initiated self-refresh operation - ----------------------------------------------------------- - elsif doSelfRfsh = YES then - -- wait until all previous activations, writes, reads are done - if (activateInProgress = NO) and (wrInProgress = NO) and (rdInProgress = NO) then - cmd_x <= PCHG_CMD; -- initiate precharge of the SDRAM - sAddr_x(CMDBIT_POS) <= ALL_BANKS; -- precharge all banks - timer_x <= RP_CYCLES; -- set timer for this operation - activeFlag_x <= (others => NO); -- all rows are inactive after a precharge operation - state_x <= SELFREFRESH; -- self-refresh the SDRAM after the precharge - end if; - status <= "1000"; - ----------------------------------------------------------- - -- no operation - ----------------------------------------------------------- - else - state_x <= RW; -- continue to look for SDRAM operations to execute - status <= "1001"; - end if; - - ----------------------------------------------------------- - -- activate a row of the SDRAM - ----------------------------------------------------------- - when ACTIVATE => - cmd_x <= ACTIVE_CMD; - sAddr_x <= (others => '0'); -- output the address for the row to be activated - sAddr_x(row'range) <= row; - activeBank_x <= bank; - activeRow_x(bankIndex) <= row; -- store the new active SDRAM row address - activeFlag_x(bankIndex) <= YES; -- the SDRAM is now active - rasTimer_x <= RAS_CYCLES; -- minimum time before another precharge can occur - timer_x <= RCD_CYCLES; -- minimum time before a read/write operation can occur - state_x <= RW; -- return to do read/write operation that initiated this activation - status <= "1010"; - - ----------------------------------------------------------- - -- refresh a row of the SDRAM - ----------------------------------------------------------- - when REFRESHROW => - cmd_x <= RFSH_CMD; - timer_x <= RFC_CYCLES; -- refresh operation interval - rfshCntr_x <= rfshCntr_r - 1; -- decrement the number of needed row refreshes - state_x <= RW; -- process more SDRAM operations after refresh is done - status <= "1011"; - - ----------------------------------------------------------- - -- place the SDRAM into self-refresh and keep it there until further notice - ----------------------------------------------------------- - when SELFREFRESH => - if (doSelfRfsh = YES) or (lock = NO) then - -- keep the SDRAM in self-refresh mode as long as requested and until there is a stable clock - cmd_x <= RFSH_CMD; -- output the refresh command; this is only needed on the first clock cycle - cke_x <= NO; -- disable the SDRAM clock - else - -- else exit self-refresh mode and start processing read and write operations - cke_x <= YES; -- restart the SDRAM clock - rfshCntr_x <= 0; -- no refreshes are needed immediately after leaving self-refresh - activeFlag_x <= (others => NO); -- self-refresh deactivates all rows - timer_x <= XSR_CYCLES; -- wait this long until read and write operations can resume - state_x <= RW; - end if; - status <= "1100"; - - ----------------------------------------------------------- - -- unknown state - ----------------------------------------------------------- - when others => - state_x <= INITWAIT; -- reset state if in erroneous state - status <= "1101"; - - end case; - end if; - end process combinatorial; - - - ----------------------------------------------------------- - -- update registers on the appropriate clock edge - ----------------------------------------------------------- - - update : process(rst, clk) - begin - - if rst = YES then - -- asynchronous reset - state_r <= INITWAIT; - activeFlag_r <= (others => NO); - rfshCntr_r <= 0; - timer_r <= 0; - refTimer_r <= REF_CYCLES; - rasTimer_r <= 0; - wrTimer_r <= 0; - nopCntr_r <= 0; - opBegun_r <= NO; - rdPipeline_r <= (others => '0'); - wrPipeline_r <= (others => '0'); - cke_r <= NO; - cmd_r <= NOP_CMD; - ba_r <= (others => '0'); - sAddr_r <= (others => '0'); - sData_r <= (others => '0'); - sDataDir_r <= INPUT; - hDOut_r <= (others => '0'); - elsif rising_edge(clk) then - state_r <= state_x; - activeBank_r <= activeBank_x; - activeRow_r <= activeRow_x; - activeFlag_r <= activeFlag_x; - rfshCntr_r <= rfshCntr_x; - timer_r <= timer_x; - refTimer_r <= refTimer_x; - rasTimer_r <= rasTimer_x; - wrTimer_r <= wrTimer_x; - nopCntr_r <= nopCntr_x; - opBegun_r <= opBegun_x; - rdPipeline_r <= rdPipeline_x; - wrPipeline_r <= wrPipeline_x; - cke_r <= cke_x; - cmd_r <= cmd_x; - ba_r <= ba_x; - sAddr_r <= sAddr_x; - sData_r <= sData_x; - sDataDir_r <= sDataDir_x; - hDOut_r <= hDOut_x; - end if; - - -- the register that gets data from the SDRAM and holds it for the host - -- is clocked on the opposite edge. We don't use this register if IN_PHASE=TRUE. - if rst = YES then - hDOutOppPhase_r <= (others => '0'); - elsif falling_edge(clk) then - hDOutOppPhase_r <= hDOutOppPhase_x; - end if; - - end process update; - -end arch; - - - - --------------------------------------------------------------------- --- Company : XESS Corp. --- Engineer : Dave Vanden Bout --- Creation Date : 06/01/2005 --- Copyright : 2005, XESS Corp --- Tool Versions : WebPACK 6.3.03i --- --- Description: --- Dual-port front-end for SDRAM controller. Supports two --- independent I/O ports to the SDRAM. --- --- Revision: --- 1.0.0 --- --- Additional Comments: --- --- License: --- This code can be freely distributed and modified as long as --- this header is not removed. --------------------------------------------------------------------- - -library IEEE, UNISIM; -use IEEE.std_logic_1164.all; -use IEEE.std_logic_unsigned.all; -use IEEE.numeric_std.all; -use WORK.common.all; - -entity dualport is - generic( - PIPE_EN : boolean := false; -- enable pipelined read operations - PORT_TIME_SLOTS : std_logic_vector(15 downto 0) := "1111000011110000"; - DATA_WIDTH : natural := 16; -- host & SDRAM data width - HADDR_WIDTH : natural := 23 -- host-side address width - ); - port( - clk : in std_logic; -- master clock - - -- host-side port 0 - rst0 : in std_logic; -- reset - rd0 : in std_logic; -- initiate read operation - wr0 : in std_logic; -- initiate write operation - earlyOpBegun0 : out std_logic; -- read/write op has begun (async) - opBegun0 : out std_logic; -- read/write op has begun (clocked) - rdPending0 : out std_logic; -- true if read operation(s) are still in the pipeline - done0 : out std_logic; -- read or write operation is done - rdDone0 : out std_logic; -- read operation is done and data is available - hAddr0 : in std_logic_vector(HADDR_WIDTH-1 downto 0); -- address from host to SDRAM - hDIn0 : in std_logic_vector(DATA_WIDTH-1 downto 0); -- data from host to SDRAM - hDOut0 : out std_logic_vector(DATA_WIDTH-1 downto 0); -- data from SDRAM to host - status0 : out std_logic_vector(3 downto 0); -- diagnostic status of the SDRAM controller FSM - - -- host-side port 1 - rst1 : in std_logic; - rd1 : in std_logic; - wr1 : in std_logic; - earlyOpBegun1 : out std_logic; - opBegun1 : out std_logic; - rdPending1 : out std_logic; - done1 : out std_logic; - rdDone1 : out std_logic; - hAddr1 : in std_logic_vector(HADDR_WIDTH-1 downto 0); - hDIn1 : in std_logic_vector(DATA_WIDTH-1 downto 0); - hDOut1 : out std_logic_vector(DATA_WIDTH-1 downto 0); - status1 : out std_logic_vector(3 downto 0); - - -- SDRAM controller port - rst : out std_logic; - rd : out std_logic; - wr : out std_logic; - earlyOpBegun : in std_logic; - opBegun : in std_logic; - rdPending : in std_logic; - done : in std_logic; - rdDone : in std_logic; - hAddr : out std_logic_vector(HADDR_WIDTH-1 downto 0); - hDIn : out std_logic_vector(DATA_WIDTH-1 downto 0); - hDOut : in std_logic_vector(DATA_WIDTH-1 downto 0); - status : in std_logic_vector(3 downto 0) - ); -end dualport; - - - -architecture arch of dualport is - -- The door signal controls whether the read/write signal from the active port - -- is allowed through to the read/write inputs of the SDRAM controller. - type doorState is (OPENED, CLOSED); - signal door_r, door_x : doorState; - - -- The port signal indicates which port is connected to the SDRAM controller. - type portState is (PORT0, PORT1); - signal port_r, port_x : portState; - - signal switch : std_logic; -- indicates that the active port should be switched - signal inProgress : std_logic; -- the active port has a read/write op in-progress - signal rd_i : std_logic; -- read signal to the SDRAM controller (internal copy) - signal wr_i : std_logic; -- write signal to the SDRAM controller (internal copy) - signal earlyOpBegun0_i, earlyOpBegun1_i : std_logic; -- (internal copies) - signal slot_r, slot_x : std_logic_vector(PORT_TIME_SLOTS'range); -- time-slot allocation shift-register -begin - - ---------------------------------------------------------------------------- - -- multiplex the SDRAM controller port signals to/from the dual host-side ports - ---------------------------------------------------------------------------- - - -- send the SDRAM controller the address and data from the currently active port - hAddr <= hAddr0 when port_r = PORT0 else hAddr1; - hDIn <= hDIn0 when port_r = PORT0 else hDIn1; - - -- both ports get the data from the SDRAM but only the active port will use it - hDOut0 <= hDOut; - hDOut1 <= hDOut; - - -- send the SDRAM controller status to the active port and give the inactive port an inactive status code - status0 <= status when port_r = PORT0 else "1111"; - status1 <= status when port_r = PORT1 else "1111"; - - -- either port can reset the SDRAM controller - rst <= rst0 or rst1; - - -- apply the read signal from the active port to the SDRAM controller only if the door is open. - rd_i <= rd0 when (port_r = PORT0) and (door_r = OPENED) else - rd1 when (port_r = PORT1) and (door_r = OPENED) else - NO; - rd <= rd_i; - - -- apply the write signal from the active port to the SDRAM controller only if the door is open. - wr_i <= wr0 when (port_r = PORT0) and (door_r = OPENED) else - wr1 when (port_r = PORT1) and (door_r = OPENED) else - NO; - wr <= wr_i; - - -- send the status signals for various SDRAM controller operations back to the active port - earlyOpBegun0_i <= earlyOpBegun when port_r = PORT0 else NO; - earlyOpBegun0 <= earlyOpBegun0_i; - earlyOpBegun1_i <= earlyOpBegun when port_r = PORT1 else NO; - earlyOpBegun1 <= earlyOpBegun1_i; - rdPending0 <= rdPending when port_r = PORT0 else NO; - rdPending1 <= rdPending when port_r = PORT1 else NO; - done0 <= done when port_r = PORT0 else NO; - done1 <= done when port_r = PORT1 else NO; - rdDone0 <= rdDone when port_r = PORT0 else NO; - rdDone1 <= rdDone when port_r = PORT1 else NO; - - ---------------------------------------------------------------------------- - -- Indicate when the active port needs to be switched. A switch occurs if - -- a read or write operation is requested on the port that is not currently active and: - -- 1) no R/W operation is being performed on the active port or - -- 2) a R/W operation is in progress on the active port, but the time-slot allocation - -- register is giving precedence to the inactive port. (The R/W operation on the - -- active port will be completed before the switch is made.) - -- This rule keeps the active port from hogging all the bandwidth. - ---------------------------------------------------------------------------- - switch <= (rd0 or wr0) when (port_r = PORT1) and (((rd1 = NO) and (wr1 = NO)) or (slot_r(0) = '0')) else - (rd1 or wr1) when (port_r = PORT0) and (((rd0 = NO) and (wr0 = NO)) or (slot_r(0) = '1')) else - NO; - - ---------------------------------------------------------------------------- - -- Indicate when an operation on the active port is in-progress and - -- can't be interrupted by a switch to the other port. (Only read operations - -- are looked at since write operations always complete in one cycle once they - -- are initiated.) - ---------------------------------------------------------------------------- - inProgress <= rdPending or (rd_i and earlyOpBegun); - - ---------------------------------------------------------------------------- - -- Update the time-slot allocation shift-register. The port with priority is indicated by the - -- least-significant bit of the register. The register is rotated right if: - -- 1) the current R/W operation has started, and - -- 2) both ports are requesting R/W operations (indicating contention), and - -- 3) the currently active port matches the port that currently has priority. - -- Under these conditions, the current time slot port allocation has been used so - -- the shift register is rotated right to bring the next port time-slot allocation - -- bit into play. - ---------------------------------------------------------------------------- - slot_x <= slot_r(0) & slot_r(slot_r'high downto 1) when (earlyOpBegun = YES) and - ( ((rd0 = YES) or (wr0 = YES)) and ((rd1 = YES) or (wr1 = YES)) ) and - ( ((port_r = PORT0) and (slot_r(0) = '0')) or ((port_r = PORT1) and (slot_r(0) = '1')) ) - else slot_r; - - ---------------------------------------------------------------------------- - -- Determine which port will be active on the next cycle. The active port is switched if: - -- 1) the currently active port has finished its current R/W operation, and - -- 2) there are no pending operations in progress, and - -- 3) the port switch indicator is active. - ---------------------------------------------------------------------------- - port_process : process(port_r, inProgress, switch, done) - begin - port_x <= port_r; -- by default, the active port is not changed - case port_r is - when PORT0 => - if (inProgress = NO) and (switch = YES) and (PIPE_EN or (done = YES)) then - port_x <= PORT1; - end if; - when PORT1 => - if (inProgress = NO) and (switch = YES) and (PIPE_EN or (done = YES)) then - port_x <= PORT0; - end if; - when others => - port_x <= port_r; - end case; - end process port_process; - - ----------------------------------------------------------- - -- Determine if the door is open for the active port to initiate new R/W operations to - -- the SDRAM controller. If the door is open and R/W operations are in progress but - -- a switch to the other port is indicated, then the door is closed to prevent any - -- further R/W operations from the active port. The door is re-opened once all - -- in-progress operations are completed, at which time the switch to the other port - -- is also completed so it can issue its own R/W commands. - ----------------------------------------------------------- - door_process : process(door_r, inProgress, switch) - begin - door_x <= door_r; -- by default, the door remains as it is - case door_r is - when OPENED => - if (inProgress = YES) and (switch = YES) then - door_x <= CLOSED; - end if; - when CLOSED => - if inProgress = NO then - door_x <= OPENED; - end if; - when others => - door_x <= door_r; - end case; - end process door_process; - - ----------------------------------------------------------- - -- update registers on the appropriate clock edge - ----------------------------------------------------------- - update : process(rst0, rst1, clk) - begin - if (rst0 = YES) or (rst1 = YES) then - -- asynchronous reset - door_r <= CLOSED; - port_r <= PORT0; - slot_r <= PORT_TIME_SLOTS; - opBegun0 <= NO; - opBegun1 <= NO; - elsif rising_edge(clk) then - door_r <= door_x; - port_r <= port_x; - slot_r <= slot_x; - -- opBegun signals are cycle-delayed versions of earlyOpBegun signals. - -- We can't use the actual opBegun signal from the SDRAM controller - -- because it would be turned off if the active port was switched on the - -- cycle immediately after earlyOpBegun went active. - opBegun0 <= earlyOpBegun0_i; - opBegun1 <= earlyOpBegun1_i; - end if; - end process update; - -end arch; Index: common.vhd =================================================================== --- common.vhd (revision 66) +++ common.vhd (nonexistent) @@ -1,107 +0,0 @@ --------------------------------------------------------------------- --- Company : XESS Corp. --- Engineer : Dave Vanden Bout --- Creation Date : 05/17/2005 --- Copyright : 2005, XESS Corp --- Tool Versions : WebPACK 6.3.03i --- --- Description: --- Miscellaneous VHDL constants and functions --- --- Revision: --- 1.0.0 --- --- Additional Comments: --- 1.1.0: --- Added int_select() and real_select functions. --- 1.0.0: --- Initial release. --- --- License: --- This code can be freely distributed and modified as long as --- this header is not removed. --------------------------------------------------------------------- - - - -library IEEE; -use IEEE.std_logic_1164.all; -use IEEE.numeric_std.all; - -package common is - - constant YES : std_logic := '1'; - constant NO : std_logic := '0'; - constant HI : std_logic := '1'; - constant LO : std_logic := '0'; - constant ONE : std_logic := '1'; - constant ZERO : std_logic := '0'; - -- convert a Boolean to a std_logic - function boolean2stdlogic(b : in boolean) return std_logic; - -- find the base-2 logarithm of a number - function log2(v : in natural) return natural; - -- select one of two integers based on a Boolean - function int_select(s : in boolean; a : in integer; b : in integer) return integer; - -- select one of two reals based on a Boolean - function real_select(s : in boolean; a : in real; b : in real) return real; - -end package common; - - - -library IEEE; -use IEEE.std_logic_1164.all; -use IEEE.numeric_std.all; - - -package body common is - - -- convert a Boolean to a std_logic - function boolean2stdlogic(b : in boolean) return std_logic is - variable s : std_logic; - begin - if b then - s := '1'; - else - s := '0'; - end if; - return s; - end function boolean2stdlogic; - - -- find the base 2 logarithm of a number - function log2(v : in natural) return natural is - variable n : natural; - variable logn : natural; - begin - n := 1; - for i in 0 to 128 loop - logn := i; - exit when (n >= v); - n := n * 2; - end loop; - return logn; - end function log2; - - -- select one of two integers based on a Boolean - function int_select(s : in boolean; a : in integer; b : in integer) return integer is - begin - if s then - return a; - else - return b; - end if; - return a; - end function int_select; - - -- select one of two reals based on a Boolean - function real_select(s : in boolean; a : in real; b : in real) return real is - begin - if s then - return a; - else - return b; - end if; - return a; - end function real_select; - -end package body common; Index: my_system09.ut =================================================================== --- my_system09.ut (revision 66) +++ my_system09.ut (nonexistent) @@ -1,28 +0,0 @@ --w --g DebugBitstream:No --g Binary:no --g CRC:Enable --g ConfigRate:6 --g CclkPin:PullNone --g M0Pin:PullNone --g M1Pin:PullNone --g M2Pin:PullNone --g ProgPin:PullNone --g DonePin:PullNone --g TckPin:PullNone --g TdiPin:PullNone --g TdoPin:PullNone --g TmsPin:PullNone --g UnusedPin:PullNone --g UserID:0xFFFFFFFF --g DCMShutdown:Disable --g DCIUpdateMode:AsRequired --g StartUpClk:CClk --g DONE_cycle:4 --g GTS_cycle:5 --g GWE_cycle:6 --g LCK_cycle:NoWait --g Match_cycle:Auto --g Security:None --g DonePipe:No --g DriveDone:No Index: Makefile =================================================================== --- Makefile (revision 66) +++ Makefile (nonexistent) @@ -1,137 +0,0 @@ -#=================================================================== -# File: Makefile -# Author: David Burnette -# Created: July 5, 2007 -# -# Description: -# Makefile to build the System09 by John Kent -# -# This makefile will build John Kent's entire System09 project -# (RTL synthesis and monitor ROMs) and even download the final -# bitstream to the prototype board. -# -# You can use Xilinx ISE interactively to add new RTL source files -# to this project. -# -# Usage: -# Use 'make help' to get a list of options. -# -# Dependencies: -# Depends on makefile fragments in the 'MKFRAGS' directory. -# -# Revision History: -# dgb 2007-07-05 Original version -# -# dgb 2008-04-07 Split out files into fragments. Modified -# ROM source generation to be per src directory. -# -#=================================================================== - -MKFRAGS := ../../mkfiles -export MKFRAGS - -#=================================================================== -# User-modifiable variables -# -# This name must match the name of the design in Xilinx ISE (case -# sensitive). -DESIGN_NAME := my_system09 -# -# Constraint file (unfortunately it cannot be extracted from ISE) -UCF_FILE := my_system09.ucf -# -# Technology family (unfortunately it cannot be extracted from ISE) -FAMILY := spartan3 - -# List of ROM VHDL files -.PHONY: roms -roms: - @$(MAKE) -C ../../src/sys09bug sys09xes.vhd - @$(MAKE) -C ../../src/Flex9 flex9ide.vhd - -#=================================================================== -# You should not need to edit anything below this line - -# XESS Tools -XSLOAD := C:/Progra~1/XSTOOLs/xsload.exe - -include ../../mkfiles/xilinx_rules.mk - -#=================================================================== -# TARGETS - -.PHONY: all -all: bit - -.PHONY: bit -bit: roms $(DESIGN_NAME).bit - -.PHONY: impact -impact: roms bit do_impact - -prom: roms $(DESIGN_NAME).mcs - -.PHONY: xsload -xsload: roms $(DESIGN_NAME).bit - @$(ECHO) - @$(ECHO) "======= Downloading bitstream to XSA-3S1000 using XSLOAD (parallel) =" - $(XSLOAD) -p 0 -b xsa-3s1000 -fpga $< - -usbxsload.bit: roms $(DESIGN_NAME).bit - @$(ECHO) - @$(ECHO) "======= Generating special bitstream with StartUpClk=JtagClk ========" - $(GREP) -v StartUpClk $(BITGEN_OPTIONS_FILE) >tmp.ut - $(ECHO) "-g StartUpClk:JtagClk" >>tmp.ut - $(BITGEN) $(BITGEN_FLAGS) -f tmp.ut $(DESIGN_NAME).ncd usbxsload.bit - -.PHONY: usbxsload -usbxsload: roms usbxsload.bit - @$(ECHO) - @$(ECHO) "======= Downloading bitstream to XSA-3S1000 using XSLOAD (USB) ======" - $(XSLOAD) -usb 0 -b xsa-3s1000 -fpga usbxsload.bit - -.PHONY: usbflash0 -usbflash0: roms prom $(DESIGN_NAME).bit - $(XSLOAD) -usb 0 -b xsa-3s1000 -flash $(DESIGN_NAME).mcs - -.PHONY: help -help: - @$(ECHO) "Use this Makefile to regenerate the entire System09 bitstream" - @$(ECHO) "after modifying any of the source RTL or 6809 assembler code." - @$(ECHO) "" - @$(ECHO) "This makefile uses the following project files from the Xilinx ISE" - @$(ECHO) " $(XST_FILE)" - @$(ECHO) "" - @$(ECHO) "You use Xilinx ISE interactively to add new RTL source files." - @$(ECHO) "" - @$(ECHO) " Availiable targets" - @$(ECHO) - @$(ECHO) " For building all or part of the system:" - @$(ECHO) " roms - Run asm09 and then generate the VHDL RTL rom files" - @$(ECHO) " bit - Rebuild the entire system and generate the bitstream file" - @$(ECHO) " all - Rebuild everything" - @$(ECHO) " prom - Rebuild the entire system and generate an MCS prom file" - @$(ECHO) " exo - Rebuild the entire system and generate an EXO prom file" - @$(ECHO) - @$(ECHO) " For downloading the bitstream to the board:" - @$(ECHO) " xsload - Download the bitstream to the FPGA via XSLOAD" - @$(ECHO) " usbxsload - Download the bitstream to the FPGA via usbXSLOAD" - @$(ECHO) " usbflash0 - Download the bitstream Flash slot 0 via usbXSLOAD" - @$(ECHO) " impact - Download the bitstream to the FPGA via iMPACT" - @$(ECHO) - @$(ECHO) " For project maintenance:" - @$(ECHO) " help - Print this help text" - @$(ECHO) " clean - Clean up the ISE files" - @$(ECHO) "" - -.PHONY: clean -clean: - -$(MAKE) -C ../../src/sys09bug clean - -$(MAKE) -C ../../src/Flex9 clean - -$(RM) *.ncd *.ngc *.ngd *.twr *.bit *.mcs *.stx *.ucf.untf *.mrp - -$(RM) *.ncl *.ngm *.prm *_pad.txt *.twx *.log *.syr *.par *.exo *.xpi - -$(RM) *.cmd_log *.ngr *.bld *_summary.html *.nc1 *.pcf *.bgn - -$(RM) *.pad *.placed_ncd_tracker *.routed_ncd_tracker *_pad.csv *.drc - -$(RM) *.pad_txt $(DESIGN_NAME)_impact.cmd *.unroutes - -$(RMDIR) _ngo _xmsgs - Index: my_system09.ucf =================================================================== --- my_system09.ucf (revision 66) +++ my_system09.ucf (nonexistent) @@ -1,326 +0,0 @@ -##################################################### -# -# XSA-3S1000 Board FPGA pin assignment constraints -# -##################################################### -# -# Clocks -# -net CLKA loc=T9 | IOSTANDARD = LVCMOS33 ; # 100MHz -#net CLKB loc=P8 | IOSTANDARD = LVCMOS33 ; # 50MHz -#net CLKC loc=R9 | IOSTANDARD = LVCMOS33 ; # ??Mhz -# -# Push button switches -# -#NET SW1_3_N loc=K2 | IOSTANDARD = LVCMOS33 ; # Flash Block select -#NET SW1_4_N loc=J4 | IOSTANDARD = LVCMOS33 ; # Flash Block -NET SW2_N loc=E11 | IOSTANDARD = LVCMOS33 ; # active-low pushbutton -NET SW3_N loc=A13 | IOSTANDARD = LVCMOS33 ; # active-low pushbutton -# -# PS/2 Keyboard -# -net PS2_CLK loc=B16 | IOSTANDARD = LVCMOS33 ; -net PS2_DAT loc=E13 | IOSTANDARD = LVCMOS33 ; -# -# VGA Outputs -# -NET VGA_BLUE<0> LOC=C9 | IOSTANDARD = LVCMOS33 ; -NET VGA_BLUE<1> LOC=E7 | IOSTANDARD = LVCMOS33 ; -NET VGA_BLUE<2> LOC=D5 | IOSTANDARD = LVCMOS33 ; -NET VGA_GREEN<0> LOC=A8 | IOSTANDARD = LVCMOS33 ; -NET VGA_GREEN<1> LOC=A5 | IOSTANDARD = LVCMOS33 ; -NET VGA_GREEN<2> LOC=C3 | IOSTANDARD = LVCMOS33 ; -NET VGA_RED<0> LOC=C8 | IOSTANDARD = LVCMOS33 ; -NET VGA_RED<1> LOC=D6 | IOSTANDARD = LVCMOS33 ; -NET VGA_RED<2> LOC=B1 | IOSTANDARD = LVCMOS33 ; -NET VGA_HSYNC_N LOC=B7 | IOSTANDARD = LVCMOS33 ; -NET VGA_VSYNC_N LOC=D8 | IOSTANDARD = LVCMOS33 ; -# -# Manually assign locations for the DCMs along the bottom of the FPGA -# because PAR sometimes places them in opposing corners and that ruins the clocks. -# -INST "u1/gen_dlls.dllint" LOC="DCM_X0Y0"; -INST "u1/gen_dlls.dllext" LOC="DCM_X1Y0"; - -# Manually assign locations for the DCMs along the bottom of the FPGA -# because PAR sometimes places them in opposing corners and that ruins the clocks. -#INST "u2_dllint" LOC="DCM_X0Y0"; -#INST "u2_dllext" LOC="DCM_X1Y0"; -# -# SDRAM memory pin assignments -# -net SDRAM_clkfb loc=N8 | IOSTANDARD = LVCMOS33 ; # feedback SDRAM clock after PCB delays -net SDRAM_clkout loc=E10 | IOSTANDARD = LVCMOS33 ; # clock to SDRAM -net SDRAM_CKE loc=D7 | IOSTANDARD = LVCMOS33 ; # SDRAM clock enable -net SDRAM_CS_N loc=B8 | IOSTANDARD = LVCMOS33 ; # SDRAM chip-select -net SDRAM_RAS_N loc=A9 | IOSTANDARD = LVCMOS33 ; -net SDRAM_CAS_N loc=A10 | IOSTANDARD = LVCMOS33 ; -net SDRAM_WE_N loc=B10 | IOSTANDARD = LVCMOS33 ; -net SDRAM_DQMH loc=D9 | IOSTANDARD = LVCMOS33 ; -net SDRAM_DQML loc=C10 | IOSTANDARD = LVCMOS33 ; -net SDRAM_A<0> loc=B5 | IOSTANDARD = LVCMOS33 ; -net SDRAM_A<1> loc=A4 | IOSTANDARD = LVCMOS33 ; -net SDRAM_A<2> loc=B4 | IOSTANDARD = LVCMOS33 ; -net SDRAM_A<3> loc=E6 | IOSTANDARD = LVCMOS33 ; -net SDRAM_A<4> loc=E3 | IOSTANDARD = LVCMOS33 ; -net SDRAM_A<5> loc=C1 | IOSTANDARD = LVCMOS33 ; -net SDRAM_A<6> loc=E4 | IOSTANDARD = LVCMOS33 ; -net SDRAM_A<7> loc=D3 | IOSTANDARD = LVCMOS33 ; -net SDRAM_A<8> loc=C2 | IOSTANDARD = LVCMOS33 ; -net SDRAM_A<9> loc=A3 | IOSTANDARD = LVCMOS33 ; -net SDRAM_A<10> loc=B6 | IOSTANDARD = LVCMOS33 ; -net SDRAM_A<11> loc=C5 | IOSTANDARD = LVCMOS33 ; -net SDRAM_A<12> loc=C6 | IOSTANDARD = LVCMOS33 ; -net SDRAM_D<0> loc=C15 | IOSTANDARD = LVCMOS33 ; -net SDRAM_D<1> loc=D12 | IOSTANDARD = LVCMOS33 ; -net SDRAM_D<2> loc=A14 | IOSTANDARD = LVCMOS33 ; -net SDRAM_D<3> loc=B13 | IOSTANDARD = LVCMOS33 ; -net SDRAM_D<4> loc=D11 | IOSTANDARD = LVCMOS33 ; -net SDRAM_D<5> loc=A12 | IOSTANDARD = LVCMOS33 ; -net SDRAM_D<6> loc=C11 | IOSTANDARD = LVCMOS33 ; -net SDRAM_D<7> loc=D10 | IOSTANDARD = LVCMOS33 ; -net SDRAM_D<8> loc=B11 | IOSTANDARD = LVCMOS33 ; -net SDRAM_D<9> loc=B12 | IOSTANDARD = LVCMOS33 ; -net SDRAM_D<10> loc=C12 | IOSTANDARD = LVCMOS33 ; -net SDRAM_D<11> loc=B14 | IOSTANDARD = LVCMOS33 ; -net SDRAM_D<12> loc=D14 | IOSTANDARD = LVCMOS33 ; -net SDRAM_D<13> loc=C16 | IOSTANDARD = LVCMOS33 ; -net SDRAM_D<14> loc=F12 | IOSTANDARD = LVCMOS33 ; -net SDRAM_D<15> loc=F13 | IOSTANDARD = LVCMOS33 ; -net SDRAM_BA<0> loc=A7 | IOSTANDARD = LVCMOS33 ; -net SDRAM_BA<1> loc=C7 | IOSTANDARD = LVCMOS33 ; -# -# Flash memory interface -# -#net FLASH_A<0> LOC=N5 | IOSTANDARD = LVCMOS33 ; -#net FLASH_A<1> LOC=K14 | IOSTANDARD = LVCMOS33 ; -#net FLASH_A<2> LOC=K13 | IOSTANDARD = LVCMOS33 ; -#net FLASH_A<3> LOC=K12 | IOSTANDARD = LVCMOS33 ; -#net FLASH_A<4> LOC=L14 | IOSTANDARD = LVCMOS33 ; -#net FLASH_A<5> LOC=M16 | IOSTANDARD = LVCMOS33 ; -#net FLASH_A<6> LOC=L13 | IOSTANDARD = LVCMOS33 ; -#net FLASH_A<7> LOC=N16 | IOSTANDARD = LVCMOS33 ; -#net FLASH_A<8> LOC=N14 | IOSTANDARD = LVCMOS33 ; -#net FLASH_A<9> LOC=P15 | IOSTANDARD = LVCMOS33 ; -#net FLASH_A<10> LOC=R16 | IOSTANDARD = LVCMOS33 ; -#net FLASH_A<11> LOC=P14 | IOSTANDARD = LVCMOS33 ; -#net FLASH_A<12> LOC=P13 | IOSTANDARD = LVCMOS33 ; -#net FLASH_A<13> LOC=N12 | IOSTANDARD = LVCMOS33 ; -#net FLASH_A<14> LOC=T14 | IOSTANDARD = LVCMOS33 ; -#net FLASH_A<15> LOC=R13 | IOSTANDARD = LVCMOS33 ; -#net FLASH_A<16> LOC=N10 | IOSTANDARD = LVCMOS33 ; -#net FLASH_A<17> LOC=M14 | IOSTANDARD = LVCMOS33 ; -#net FLASH_A<18> LOC=K3 | IOSTANDARD = LVCMOS33 ; -#net FLASH_A<19> LOC=K4 | IOSTANDARD = LVCMOS33 ; -# -#net FLASH_D<0> LOC=M11 | IOSTANDARD = LVCMOS33 ; -#net FLASH_D<1> LOC=N11 | IOSTANDARD = LVCMOS33 ; -#net FLASH_D<2> LOC=P10 | IOSTANDARD = LVCMOS33 ; -#net FLASH_D<3> LOC=R10 | IOSTANDARD = LVCMOS33 ; -#net FLASH_D<4> LOC=T7 | IOSTANDARD = LVCMOS33 ; -#net FLASH_D<5> LOC=R7 | IOSTANDARD = LVCMOS33 ; -#net FLASH_D<6> LOC=N6 | IOSTANDARD = LVCMOS33 ; -#net FLASH_D<7> LOC=M6 | IOSTANDARD = LVCMOS33 ; -#net FLASH_D<8> LOC=T4 | IOSTANDARD = LVCMOS33 ; -#net FLASH_D<9> LOC=R5 | IOSTANDARD = LVCMOS33 ; -#net FLASH_D<10> LOC=T5 | IOSTANDARD = LVCMOS33 ; -#net FLASH_D<11> LOC=P6 | IOSTANDARD = LVCMOS33 ; -#net FLASH_D<12> LOC=M7 | IOSTANDARD = LVCMOS33 ; -#net FLASH_D<13> LOC=R6 | IOSTANDARD = LVCMOS33 ; -#net FLASH_D<14> LOC=N7 | IOSTANDARD = LVCMOS33 ; -#net FLASH_D<15> LOC=P7 | IOSTANDARD = LVCMOS33 ; -net FLASH_CE_N LOC=R4 | IOSTANDARD = LVCMOS33 ; -#net FLASH_OE_N LOC=P5 | IOSTANDARD = LVCMOS33 ; -#net FLASH_WE_N LOC=M13 | IOSTANDARD = LVCMOS33 ; -#net FLASH_BYTE_N LOC=T8 | IOSTANDARD = LVCMOS33 ; -#net FLASH_RDY LOC=L12 | IOSTANDARD = LVCMOS33 ; -#net FLASH_RST_N LOC=P16 | IOSTANDARD = LVCMOS33 ; -# -# FPGA Programming interface -# -#net FPGA_D<0> LOC=M11 | IOSTANDARD = LVCMOS33 ; # shared with FLASH_D0, S1, LED_C -#net FPGA_D<1> LOC=N11 | IOSTANDARD = LVCMOS33 ; # shared with FLASH_D1, S7, LED_DP -#net FPGA_D<2> LOC=P10 | IOSTANDARD = LVCMOS33 ; # shared with FLASH_D2, S4, LED_B -#net FPGA_D<3> LOC=R10 | IOSTANDARD = LVCMOS33 ; # shared with FLASH_D3, S6, LED_A -#net FPGA_D<4> LOC=T7 | IOSTANDARD = LVCMOS33 ; # shared with FLASH_D4, S5, LED_F -#net FPGA_D<5> LOC=R7 | IOSTANDARD = LVCMOS33 ; # shared with FLASH_D5, S3, LED_G -#net FPGA_D<6> LOC=N6 | IOSTANDARD = LVCMOS33 ; # shared with FLASH_D6, S2, LED_E -#net FPGA_D<7> LOC=M6 | IOSTANDARD = LVCMOS33 ; # shared with FLASH_D7, S0, LED_D -#net FPGA_CCLK LOC=T15 | IOSTANDARD = LVCMOS33 ; -#net FPGA_DONE LOC=R14 | IOSTANDARD = LVCMOS33 ; -#net FPGA_INIT_N LOC=N9 | IOSTANDARD = LVCMOS33 ; -#net FPGA_PROG_N LOC=B3 | IOSTANDARD = LVCMOS33 ; -#net FPGA_TCK LOC=C14 | IOSTANDARD = LVCMOS33 ; -#net FPGA_TDI LOC=A2 | IOSTANDARD = LVCMOS33 ; -#net FPGA_TDI_CSN LOC=R3 | IOSTANDARD = LVCMOS33 ; -#net FPGA_TDO LOC=A15 | IOSTANDARD = LVCMOS33 ; -#net FPGA_TDO_WRN LOC=T3 | IOSTANDARD = LVCMOS33 ; -#net FPGA_TMS LOC=C13 | IOSTANDARD = LVCMOS33 ; -#net FPGA_TMS_BSY LOC=P9 | IOSTANDARD = LVCMOS33 ; -# -# Status LED -# -#net S<0> loc=M6 | IOSTANDARD = LVCMOS33 ; # FPGA_D7, LED_D -#net S<1> loc=M11 | IOSTANDARD = LVCMOS33 ; # FPGA_D0, LED_C -#net S<2> loc=N6 | IOSTANDARD = LVCMOS33 ; # FPGA_D6, LED_E -#net S<3> loc=R7 | IOSTANDARD = LVCMOS33 ; # FPGA_D5, LED_G -#net S<4> loc=P10 | IOSTANDARD = LVCMOS33 ; # FPGA_D2, LED_B -#net S<5> loc=T7 | IOSTANDARD = LVCMOS33 ; # FPGA_D4, LED_F -#net S<6> loc=R10 | IOSTANDARD = LVCMOS33 ; # FPGA_D3, LED_A -#net S<7> loc=N11 | IOSTANDARD = LVCMOS33 ; # FPGA_D1, LED_DP -# -# Parallel Port -# -#net PPORT_load loc=N14 | IOSTANDARD = LVCMOS33 ; -#net PPORT_clk loc=P15 | IOSTANDARD = LVCMOS33 ; -#net PPORT_din<0> loc=R16 | IOSTANDARD = LVCMOS33 ; -#net PPORT_din<1> loc=P14 | IOSTANDARD = LVCMOS33 ; -#net PPORT_din<2> loc=P13 | IOSTANDARD = LVCMOS33 ; -#net PPORT_din<3> loc=N12 | IOSTANDARD = LVCMOS33 ; -# -#net PPORT_dout<0> loc=N5 | IOSTANDARD = LVCMOS33 ; -#net PPORT_dout<1> loc=K14 | IOSTANDARD = LVCMOS33 ; -#net PPORT_dout<2> loc=K13 | IOSTANDARD = LVCMOS33 ; -#net PPORT_dout<3> loc=T10 | IOSTANDARD = LVCMOS33 ; -# -#net PPORT_d<0> loc=N14 | IOSTANDARD = LVCMOS33 ; # FLASH_A<8> / PPORT_LOAD -#net PPORT_d<1> loc=P15 | IOSTANDARD = LVCMOS33 ; # FLASH_A<9> / PPORT_CLK -#net PPORT_d<2> loc=R16 | IOSTANDARD = LVCMOS33 ; # FLASH_A<10> / PPORT_DIN<0> -#net PPORT_d<3> loc=P14 | IOSTANDARD = LVCMOS33 ; # FLASH_A<11> / PPORT_DIN<1> -#net PPORT_d<4> loc=P13 | IOSTANDARD = LVCMOS33 ; # FLASH_A<12> / PPORT_DIN<2> -#net PPORT_d<5> loc=N12 | IOSTANDARD = LVCMOS33 ; # FLASH_A<13> / PPORT_DIN<3> -##net PPORT_d<6> loc=T14 | IOSTANDARD = LVCMOS33 ; # FLASH_A<14> -##net PPORT_d<7> loc=R13 | IOSTANDARD = LVCMOS33 ; # FLASH_A<15> -# -#net PPORT_s<3> loc=N5 | IOSTANDARD = LVCMOS33 ; # FLASH_A<0> / PPORT_DOUT<0> -#net PPORT_s<4> loc=K14 | IOSTANDARD = LVCMOS33 ; # FLASH_A<1> / PPORT_DOUT<1> -#net PPORT_s<5> loc=K13 | IOSTANDARD = LVCMOS33 ; # FLASH_A<2> / PPORT_DOUT<2> -#net PPORT_s<6> loc=T10 | IOSTANDARD = LVCMOS33 ; # / PPORT_DOUT<3> -# -######################################################## -# -# XST3.0 pins -# -######################################################## -# -# BAR LED -# -#net BAR<1> loc=L5 | IOSTANDARD = LVCMOS33 ; # bar led 1, PB_A0 -#net BAR<2> loc=N2 | IOSTANDARD = LVCMOS33 ; # bar led 2, PB_A1 -#net BAR<3> loc=M3 | IOSTANDARD = LVCMOS33 ; # bar led 3, PB_A2 -#net BAR<4> loc=N1 | IOSTANDARD = LVCMOS33 ; # bar led 4, PB_A3 -#net BAR<5> loc=T13 | IOSTANDARD = LVCMOS33 ; # bar led 5, PB_A4 -#net BAR<6> loc=L15 | IOSTANDARD = LVCMOS33 ; # bar led 6, ETHER_IRQ -#net BAR<7> loc=J13 | IOSTANDARD = LVCMOS33 ; # bar led 7, USB_IRQ_N -#net BAR<8> loc=H15 | IOSTANDARD = LVCMOS33 ; # bar led 8, IDE_IRQ -#net BAR<9> loc=J16 | IOSTANDARD = LVCMOS33 ; # bar led 9, SLOT1_IRQ -#net BAR<10> loc=J14 | IOSTANDARD = LVCMOS33 ; # bar led 10, SLOT2_IRQ -# -# Push Buttons -# -#net PB1_N loc=H4 | IOSTANDARD = LVCMOS33 ; # Shared with PB_D15 -#net PB2_N loc=L5 | IOSTANDARD = LVCMOS33 ; # Shared with BAR1, PB_A0 -#net PB3_N loc=N2 | IOSTANDARD = LVCMOS33 ; # Shared with BAR2, PB_A1 -#net PB4_N loc=M3 | IOSTANDARD = LVCMOS33 ; # Shared with BAR3, PB_A2 -# -# RS232 PORT -# -net RS232_TXD loc=J2 | IOSTANDARD = LVCMOS33 ; # RS232 TD pin 3 -net RS232_RXD loc=G5 | IOSTANDARD = LVCMOS33 ; # RS232 RD pin 2 -net RS232_CTS loc=D1 | IOSTANDARD = LVCMOS33 ; # RS232 CTS -net RS232_RTS loc=F4 | IOSTANDARD = LVCMOS33 ; # RS232 RTS -# -# 16 Bit Peripheral Bus -# -# 5-bit Peripheral address bus -net PB_A<0> loc=L5 | IOSTANDARD = LVCMOS33 ; # Shared with BAR1, PB2 -net PB_A<1> loc=N2 | IOSTANDARD = LVCMOS33 ; # Shared with BAR2, PB3 -net PB_A<2> loc=M3 | IOSTANDARD = LVCMOS33 ; # Shared with BAR3, PB4 -net PB_A<3> loc=N1 | IOSTANDARD = LVCMOS33 ; # Shared with BAR4 -net PB_A<4> loc=T13 | IOSTANDARD = LVCMOS33 ; # Shared with BAR5 -# 16-bit peripheral data bus -net PB_D<0> loc=P12 | IOSTANDARD = LVCMOS33 ; # Shared with DIPSW1 -net PB_D<1> loc=J1 | IOSTANDARD = LVCMOS33 ; # Shared with DIPSW2 -net PB_D<2> loc=H1 | IOSTANDARD = LVCMOS33 ; # Shared with DIPSW3 -net PB_D<3> loc=H3 | IOSTANDARD = LVCMOS33 ; # Shared with DIPSW4 -net PB_D<4> loc=G2 | IOSTANDARD = LVCMOS33 ; # Shared with DIPSW5 -net PB_D<5> loc=K15 | IOSTANDARD = LVCMOS33 ; # Shared with DIPSW6 -net PB_D<6> loc=K16 | IOSTANDARD = LVCMOS33 ; # Shared with DIPSW7 -net PB_D<7> loc=F15 | IOSTANDARD = LVCMOS33 ; # Shared with DIPSW8 -net PB_D<8> loc=E2 | IOSTANDARD = LVCMOS33 ; # Shared with LED2_A -net PB_D<9> loc=E1 | IOSTANDARD = LVCMOS33 ; # Shared with LED2_B -net PB_D<10> loc=F3 | IOSTANDARD = LVCMOS33 ; # Shared with LED2_C -net PB_D<11> loc=F2 | IOSTANDARD = LVCMOS33 ; # Shared with LED2_D -net PB_D<12> loc=G4 | IOSTANDARD = LVCMOS33 ; # Shared with LED2_E -net PB_D<13> loc=G3 | IOSTANDARD = LVCMOS33 ; # Shared with LED2_F -net PB_D<14> loc=G1 | IOSTANDARD = LVCMOS33 ; # Shared with LED2_G -net PB_D<15> loc=H4 | IOSTANDARD = LVCMOS33 ; # Shared with LED2_DP, PB1 -net PB_RD_N loc=P2 | IOSTANDARD = LVCMOS33 ; # disk I/O read control -net PB_WR_N loc=R1 | IOSTANDARD = LVCMOS33 ; # disk I/O write control -# -# IDE Interface -# -net IDE_CS0_N loc=G15 | IOSTANDARD = LVCMOS33 ; # disk register-bank select -net IDE_CS1_N loc=G14 | IOSTANDARD = LVCMOS33 ; # disk register-bank select -net IDE_DMACK_N loc=K1 | IOSTANDARD = LVCMOS33 ; # (out) IDE DMA acknowledge -#net IDE_DMARQ loc=L4 | IOSTANDARD = LVCMOS33 ; # (in) IDE DMA request -#net IDE_IORDY loc=L2 | IOSTANDARD = LVCMOS33 ; # (in) IDE IO ready -#net IDE_IRQ loc=H15 | IOSTANDARD = LVCMOS33 ; # (in) IDE interrupt # shared with BAR8 -# -# Ethernet Controller -# Disable if not used -# -net ether_cs_n loc=G13 | IOSTANDARD = LVCMOS33 ; # (out)Ethernet chip-enable -net ether_aen loc=E14 | IOSTANDARD = LVCMOS33 ; # (out) Ethernet address enable not -net ether_bhe_n loc=J3 | IOSTANDARD = LVCMOS33 ; # (out) Ethernet bus high enable -net ether_clk loc=R9 | IOSTANDARD = LVCMOS33 ; # (in) Ethernet clock -net ether_irq loc=L15 | IOSTANDARD = LVCMOS33 ; # (in) Ethernet irq - Shared with BAR6 -net ether_rdy loc=M2 | IOSTANDARD = LVCMOS33 ; # (in) Ethernet ready -# -# Expansion slots -# -net slot1_cs_n loc=E15 | IOSTANDARD = LVCMOS33 ; # (out) -#net slot1_irq loc=J16 | IOSTANDARD = LVCMOS33 ; # (in) Shared with BAR9 -net slot2_cs_n loc=D16 | IOSTANDARD = LVCMOS33 ; # (out) -#net slot2_irq loc=J14 | IOSTANDARD = LVCMOS33 ; # (in) Shared with BAR10 -# -# Audio codec -# -#net audio_lrck loc=R12 | IOSTANDARD = LVCMOS33 ; # (out) -#net audio_mclk loc=P11 | IOSTANDARD = LVCMOS33 ; # (out) -#net audio_sclk loc=T12 | IOSTANDARD = LVCMOS33 ; # (out) -#net audio_sdti loc=M10 | IOSTANDARD = LVCMOS33 ; # (out) -#net audio_sdto loc=K5 | IOSTANDARD = LVCMOS33 ; # (in) -# -# i2c -# -#net i2c_scl loc=F5 | IOSTANDARD = LVCMOS33 ; #(out) -#net i2c_sda loc=D2 | IOSTANDARD = LVCMOS33 ; # (in/out) -# -# USB -# -#NET USB_CLK LOC=M1 | IOSTANDARD = LVCMOS33 ; # (IN) -#NET USB_IRQ_N LOC=J13 | IOSTANDARD = LVCMOS33 ; # (IN) Shared with BAR7 -#NET USB_SUSPEND LOC=l3 | IOSTANDARD = LVCMOS33 ; # (IN) -# -# VIDEO DIGITIZER -# -#NET VIDIN_AVID LOC= | IOSTANDARD = LVCMOS33 ; # (IN) -#NET VIDIN_CLK LOC=H16 | IOSTANDARD = LVCMOS33 ; # (IN) -#NET VIDIN_FID LOC= | IOSTANDARD = LVCMOS33 ; # (IN) -#NET VIDIN_HSYNC LOC= | IOSTANDARD = LVCMOS33 ; # (IN) -#NET VIDIN_IRQ LOC= | IOSTANDARD = LVCMOS33 ; # (IN) -#NET VIDIN_VSYNC LOC= | IOSTANDARD = LVCMOS33 ; # (IN) -#NET VIDIN_Y<0> LOC=H14 | IOSTANDARD = LVCMOS33 ; # (IN) Shared with LED1_A -#NET VIDIN_Y<1> LOC=M4 | IOSTANDARD = LVCMOS33 ; # (IN) Shared with LED1_B -#NET VIDIN_Y<2> LOC=P1 | IOSTANDARD = LVCMOS33 ; # (IN) Shared with LED1_C -#NET VIDIN_Y<3> LOC=N3 | IOSTANDARD = LVCMOS33 ; # (IN) Shared with LED1_D -#NET VIDIN_Y<4> LOC=M15 | IOSTANDARD = LVCMOS33 ; # (IN) Shared with LED1_E -#NET VIDIN_Y<5> LOC=H13 | IOSTANDARD = LVCMOS33 ; # (IN) Shared with LED1_F -#NET VIDIN_Y<6> LOC=G16 | IOSTANDARD = LVCMOS33 ; # (IN) Shared with LED1_G -#NET VIDIN_Y<7> LOC=N15 | IOSTANDARD = LVCMOS33 ; # (IN) Shared with LED1_DP -# -# Timing Constraints -# -NET "CLKA" TNM_NET="CLKA"; -TIMESPEC "TS_clk"=PERIOD "CLKA" 10 ns HIGH 50 %; Index: . =================================================================== --- . (revision 66) +++ . (nonexistent)

. Property changes : Deleted: svn:ignore ## -1,32 +0,0 ## -*.ngr -*.ngd -*.ncd -*.msk -*.par -*.pad -*.stx -*.syr -*.twx -*.twr -*.ntrc_log -*.ngm -*.mrp -*.xpi -*.unroutes -*.log -*.bit -*.bld -*.bgn -xst_tmp_dirs -xst -*.prm -*.pcf -*.ngc -*.mcs -*.drc -*_pad.txt -*_pad.csv -_ngo -*_usage.xml -tmp.ut -*_impact.cmd

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