URL
https://opencores.org/ocsvn/System09/System09/trunk
Subversion Repositories System09
Compare Revisions
- This comparison shows the changes necessary to convert path
/System09/trunk/rtl/Testbench
- from Rev 122 to Rev 66
- ↔ Reverse comparison
Rev 122 → Rev 66
/vdu8_tb.vhd
File deleted
/Testbench.ise
Cannot display: file marked as a binary type.
svn:mime-type = application/octet-stream
Testbench.ise
Property changes :
Deleted: svn:mime-type
## -1 +0,0 ##
-application/octet-stream
\ No newline at end of property
Index: testbench1.vhd
===================================================================
--- testbench1.vhd (revision 122)
+++ testbench1.vhd (revision 66)
@@ -1,9 +1,10 @@
---===========================================================================--
--- --
--- TESTBENCH testbench1 - CPU09 Testbench. --
--- --
---===========================================================================--
+--===========================================================================----
--
+-- T E S T B E N C H tesetbench1 - CPU09 Testbench.
+--
+-- www.OpenCores.Org - September 2003
+-- This core adheres to the GNU public license
+--
-- File name : Testbench1.vhd
--
-- Purpose : cpu09 Microprocessor Test Bench 1
@@ -19,35 +20,22 @@
--
-- Author : John E. Kent
-- dilbert57@opencores.org
---
--- Copyright (C) 2003 - 2010 John Kent
---
--- This program is free software: you can redistribute it and/or modify
--- it under the terms of the GNU General Public License as published by
--- the Free Software Foundation, either version 3 of the License, or
--- (at your option) any later version.
---
--- This program is distributed in the hope that it will be useful,
--- but WITHOUT ANY WARRANTY; without even the implied warranty of
--- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
--- GNU General Public License for more details.
---
--- You should have received a copy of the GNU General Public License
--- along with this program. If not, see
/testbench2.vhd
1,9 → 1,10
--===========================================================================-- |
-- -- |
-- TESTBENCH testbench2 - CPU09 Testbench. -- |
-- -- |
--===========================================================================-- |
--===========================================================================---- |
-- |
-- T E S T B E N C H tesetbench2 - CPU09 Testbench. |
-- |
-- www.OpenCores.Org - September 2003 |
-- This core adheres to the GNU public license |
-- |
-- File name : Testbench2.vhd |
-- |
-- Purpose : cpu09 Microprocessor Test Bench 2 |
19,35 → 20,22
-- |
-- Author : John E. Kent |
-- dilbert57@opencores.org |
-- |
-- Copyright (C) 2003 - 2010 John Kent |
-- |
-- This program is free software: you can redistribute it and/or modify |
-- it under the terms of the GNU General Public License as published by |
-- the Free Software Foundation, either version 3 of the License, or |
-- (at your option) any later version. |
-- |
-- This program is distributed in the hope that it will be useful, |
-- but WITHOUT ANY WARRANTY; without even the implied warranty of |
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
-- GNU General Public License for more details. |
-- |
-- You should have received a copy of the GNU General Public License |
-- along with this program. If not, see <http://www.gnu.org/licenses/>. |
-- |
--===========================================================================-- |
-- -- |
-- Revision History -- |
-- -- |
--===========================================================================-- |
-- |
-- Rev Date Author Changes |
-- 0.1 2003-04-12 John Kent First version |
-- 1.0 2003-09-06 John Kent Initial release to Opencores.org |
-- 1.1 2004-01-25 John Kent removed "test_alu" and "test_cc" from CPU component |
-- 1.2 2011-10-09 John Kent renamed address to addr on CPU component, updated header |
--===========================================================================---- |
-- |
-- Revision History: |
--===========================================================================-- |
-- |
-- Version 0.1 - 12st April 2003 - John Kent |
-- First version |
-- |
-- Version 1.0- 6 Sep 2003 - John Kent |
-- Initial release to Open Cores |
-- |
-- Version 1.1 - 25th Jan 2004 - John Kent |
-- removed "test_alu" and "test_cc" |
-- |
--===========================================================================-- |
|
library ieee; |
use ieee.std_logic_1164.all; |
248,7 → 236,7
rst: in std_logic; |
rw: out std_logic; -- Asynchronous memory interface |
vma: out std_logic; |
addr: out std_logic_vector(15 downto 0); |
address: out std_logic_vector(15 downto 0); |
data_in: in std_logic_vector(7 downto 0); |
data_out: out std_logic_vector(7 downto 0); |
halt: in std_logic; |
266,7 → 254,7
rst => cpu_reset, |
rw => cpu_rw, |
vma => cpu_vma, |
addr => cpu_addr(15 downto 0), |
address => cpu_addr(15 downto 0), |
data_in => cpu_data_in, |
data_out => cpu_data_out, |
halt => '0', |
/ACIA_tb.vhd
1,52 → 1,11
--===========================================================================-- |
-- -- |
-- VHDL 6850 ACIA TestBench -- |
-- -- |
--===========================================================================-- |
-- |
-- |
-- File name : ACIA_tb.vhd |
-- |
-- Entity name : ACIA6850_testbench |
-- |
-- Purpose : VHDL testbench for acia6850 |
-- |
-- Dependencies : ieee.std_logic_1164 |
-- ieee.std_logic_unsigned |
-- ieee.std_logic_arith |
-- ieee.numeric_std |
-- |
-- Author : John E. Kent |
-- |
-- Email : dilbert57@opencores.org |
-- |
-- Web : http://opencores.org/project,system09 |
-- |
-- Copyright (C) 2007 - 2011 John Kent |
-- |
-- This program is free software: you can redistribute it and/or modify |
-- it under the terms of the GNU General Public License as published by |
-- the Free Software Foundation, either version 3 of the License, or |
-- (at your option) any later version. |
-- |
-- This program is distributed in the hope that it will be useful, |
-- but WITHOUT ANY WARRANTY; without even the implied warranty of |
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
-- GNU General Public License for more details. |
-- |
-- You should have received a copy of the GNU General Public License |
-- along with this program. If not, see <http://www.gnu.org/licenses/>. |
-- |
--===========================================================================-- |
-- -- |
-- Revision History -- |
-- -- |
--===========================================================================-- |
-- |
-- Rev Date Author Notes |
-- 0.1 2007-02-06 John Kent Initial Version |
-- 0.2 2011-10-09 John Kent Renamed acia_6850 to acia6850 |
-- ACIA 6850 Test Bench |
-- |
-- |
-- John Kent 6th February 2007 |
-- |
-- |
------------------------------------------------------------------------------- |
library ieee; |
use ieee.std_logic_1164.all; |
54,13 → 13,13
use IEEE.STD_LOGIC_UNSIGNED.ALL; |
use ieee.numeric_std.all; |
|
entity ACIA6850_testbench is |
end ACIA6850_testbench; |
entity ACIA_6850_testbench is |
end ACIA_6850_testbench; |
|
------------------------------------------------------------------------------- |
-- Architecture for ACIA 6850 Unit |
------------------------------------------------------------------------------- |
architecture behavior of ACIA6850_testbench is |
architecture behavior of ACIA_6850_testbench is |
----------------------------------------------------------------------------- |
-- Signals |
----------------------------------------------------------------------------- |
86,29 → 45,29
-- ACIA 6850 UART |
-- |
----------------------------------------------------------------- |
component ACIA6850 |
component ACIA_6850 |
port ( |
-- |
-- CPU signals |
-- |
clk : in std_logic; -- System Clock |
rst : in std_logic; -- Reset input (active high) |
cs : in std_logic; -- miniUART Chip Select |
rw : in std_logic; -- Read / Not Write |
addr : in std_logic; -- Register Select |
data_in : in std_logic_vector(7 downto 0); -- Data Bus In |
data_out : out std_logic_vector(7 downto 0); -- Data Bus Out |
irq : out std_logic; -- Interrupt |
clk : in Std_Logic; -- System Clock |
rst : in Std_Logic; -- Reset input (active high) |
cs : in Std_Logic; -- miniUART Chip Select |
rw : in Std_Logic; -- Read / Not Write |
irq : out Std_Logic; -- Interrupt |
Addr : in Std_Logic; -- Register Select |
DataIn : in Std_Logic_Vector(7 downto 0); -- Data Bus In |
DataOut : out Std_Logic_Vector(7 downto 0); -- Data Bus Out |
-- |
-- Uart Signals |
-- |
RxC : in std_logic; -- Receive Baud Clock |
TxC : in std_logic; -- Transmit Baud Clock |
RxD : in std_logic; -- Receive Data |
TxD : out std_logic; -- Transmit Data |
DCD_n : in std_logic; -- Data Carrier Detect |
CTS_n : in std_logic; -- Clear To Send |
RTS_n : out std_logic ); -- Request To send |
RxC : in Std_Logic; -- Receive Baud Clock |
TxC : in Std_Logic; -- Transmit Baud Clock |
RxD : in Std_Logic; -- Receive Data |
TxD : out Std_Logic; -- Transmit Data |
DCD_n : in Std_Logic; -- Data Carrier Detect |
CTS_n : in Std_Logic; -- Clear To Send |
RTS_n : out Std_Logic ); -- Request To send |
end component; --================== End of entity ==============================-- |
|
begin |
117,15 → 76,15
-- Instantiation of internal components |
----------------------------------------------------------------------------- |
|
my_acia : ACIA6850 port map ( |
my_acia : ACIA_6850 port map ( |
clk => SysClk, |
rst => uart_reset, |
cs => uart_cs, |
rw => uart_rw, |
addr => uart_addr, |
data_in => uart_data_in, |
data_out => uart_data_out, |
irq => uart_irq, |
Irq => uart_irq, |
Addr => uart_addr, |
Datain => uart_data_in, |
DataOut => uart_data_out, |
RxC => rxclk, |
TxC => txclk, |
RxD => rxbit, |
/testbench3.vhd
1,9 → 1,10
--===========================================================================-- |
-- -- |
-- TESTBENCH testbench3 - CPU09 Testbench. -- |
-- -- |
--===========================================================================-- |
--===========================================================================---- |
-- |
-- T E S T B E N C H tesetbench3 - CPU09 Testbench. |
-- |
-- www.OpenCores.Org - September 2003 |
-- This core adheres to the GNU public license |
-- |
-- File name : Testbench3.vhd |
-- |
-- Purpose : cpu09 Microprocessor Test Bench 3 |
18,35 → 19,22
-- |
-- Author : John E. Kent |
-- dilbert57@opencores.org |
-- |
-- Copyright (C) 2003 - 2010 John Kent |
-- |
-- This program is free software: you can redistribute it and/or modify |
-- it under the terms of the GNU General Public License as published by |
-- the Free Software Foundation, either version 3 of the License, or |
-- (at your option) any later version. |
-- |
-- This program is distributed in the hope that it will be useful, |
-- but WITHOUT ANY WARRANTY; without even the implied warranty of |
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
-- GNU General Public License for more details. |
-- |
-- You should have received a copy of the GNU General Public License |
-- along with this program. If not, see <http://www.gnu.org/licenses/>. |
-- |
--===========================================================================-- |
-- -- |
-- Revision History -- |
-- -- |
--===========================================================================-- |
-- |
-- Rev Date Author Changes |
-- 0.1 2003-04-12 John Kent First version |
-- 1.0 2003-09-06 John Kent Initial release to Opencores.org |
-- 1.1 2004-02-26 John kent removed test_alu and test_cc signals from CPU component. |
-- 1.2 2011-10-09 John Kent renamed address to addr on CPU component, updated header |
--===========================================================================---- |
-- |
-- Revision History: |
--===========================================================================-- |
-- |
-- Version 0.1 - 12 Apr 2003 - John Kent |
-- First version |
-- |
-- Version 1.0 - 6 Sep 2003 - John Kent |
-- Initial release to Open Cores |
-- |
-- Version 1.1 - 26 Feb 2004 - John kent |
-- removed test_alu and test_cc signals from |
-- CPU component. |
--===========================================================================-- |
|
library ieee; |
use ieee.std_logic_1164.all; |
134,7 → 122,7
rst: in std_logic; |
rw: out std_logic; -- Asynchronous memory interface |
vma: out std_logic; |
addr: out std_logic_vector(15 downto 0); |
address: out std_logic_vector(15 downto 0); |
data_in: in std_logic_vector(7 downto 0); |
data_out: out std_logic_vector(7 downto 0); |
halt: in std_logic; |
152,7 → 140,7
rst => cpu_reset, |
rw => cpu_rw, |
vma => cpu_vma, |
addr => cpu_addr(15 downto 0), |
address => cpu_addr(15 downto 0), |
data_in => cpu_data_in, |
data_out => cpu_data_out, |
halt => '0', |
/testbench4.vhd
1,67 → 1,28
--===========================================================================-- |
-- -- |
-- TESTBENCH testbench4 - CPU09 Testbench. -- |
-- -- |
--===========================================================================-- |
-- |
-- File name : Testbench4.vhd |
-- MC6809 Microprocessor Test Bench 4 |
-- Test Software - SBUG ROM |
-- |
-- Purpose : cpu09 Microprocessor Test Bench 4 |
-- Contains SBUG ROM |
-- |
-- Dependencies : ieee.Std_Logic_1164 |
-- ieee.std_logic_unsigned |
-- ieee.std_logic_arith |
-- ieee.numeric_std |
-- John Kent 12st April 2003 |
-- |
-- Uses : cpu09 (..\VHDL\cpu09.vhd) CPU core |
-- ram_2k (..\Spartan3\ram2k_b16.vhd) 2KB block RAM |
-- mon_rom (..\Spartan3\sbug_rom2k_b16.vhd) 2KB SBUG block ROM |
-- |
-- Author : John E. Kent |
-- dilbert57@opencores.org |
-- |
-- Copyright (C) 2003 - 2011 John Kent |
-- |
-- This program is free software: you can redistribute it and/or modify |
-- it under the terms of the GNU General Public License as published by |
-- the Free Software Foundation, either version 3 of the License, or |
-- (at your option) any later version. |
-- |
-- This program is distributed in the hope that it will be useful, |
-- but WITHOUT ANY WARRANTY; without even the implied warranty of |
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
-- GNU General Public License for more details. |
-- |
-- You should have received a copy of the GNU General Public License |
-- along with this program. If not, see <http://www.gnu.org/licenses/>. |
-- |
--===========================================================================-- |
-- -- |
-- Revision History -- |
-- -- |
--===========================================================================-- |
-- Version 1.1 - 25th Jan 2004 - John Kent |
-- removed "test_alu" and "test_cc" |
-- |
-- Rev Date Author Changes |
-- 0.1 2003-04-12 John Kent First version |
-- 1.0 2003-09-06 John Kent Initial release to Opencores.org |
-- 1.1 2004-02-25 John kent removed test_alu and test_cc signals from CPU component. |
-- 1.2 2011-10-09 John Kent renamed address to addr on CPU component, updated header |
-- |
--===========================================================================-- |
|
------------------------------------------------------------------------------- |
library ieee; |
use ieee.std_logic_1164.all; |
use IEEE.STD_LOGIC_ARITH.ALL; |
use ieee.numeric_std.all; |
|
entity my_testbench4 is |
end my_testbench4; |
entity my_testbench is |
end my_testbench; |
|
------------------------------------------------------------------------------- |
-- Architecture for memio Controller Unit |
------------------------------------------------------------------------------- |
architecture behavior of my_testbench4 is |
architecture behavior of my_testbench is |
----------------------------------------------------------------------------- |
-- Signals |
----------------------------------------------------------------------------- |
89,7 → 50,7
rst: in std_logic; |
rw: out std_logic; -- Asynchronous memory interface |
vma: out std_logic; |
addr: out std_logic_vector(15 downto 0); |
address: out std_logic_vector(15 downto 0); |
data_in: in std_logic_vector(7 downto 0); |
data_out: out std_logic_vector(7 downto 0); |
halt: in std_logic; |
101,27 → 62,22
end component; |
|
|
component mon_rom |
component sbug_rom |
Port ( |
clk : in std_logic; |
rst : in std_logic; |
cs : in std_logic; |
rw : in std_logic; |
addr : in std_logic_vector (10 downto 0); |
data_in : in std_logic_vector (7 downto 0); |
data_out : out std_logic_vector (7 downto 0) |
MEMclk : in std_logic; |
MEMaddr : in std_logic_vector (10 downto 0); |
MEMrdata : out std_logic_vector (7 downto 0) |
); |
end component; |
|
component ram_2k |
|
component block_ram |
Port ( |
clk : in std_logic; |
rst : in std_logic; |
cs : in std_logic; |
addr : in std_logic_vector (10 downto 0); |
rw : in std_logic; |
data_in : in std_logic_vector (7 downto 0); |
data_out : out std_logic_vector (7 downto 0) |
MEMclk : in std_logic; |
MEMcs : in std_logic; |
MEMrw : in std_logic; |
MEMaddr : in std_logic_vector (10 downto 0); |
MEMrdata : out std_logic_vector (7 downto 0); |
MEMwdata : in std_logic_vector (7 downto 0) |
); |
end component; |
|
131,7 → 87,7
rst => cpu_reset, |
rw => cpu_rw, |
vma => cpu_vma, |
addr => cpu_addr(15 downto 0), |
address => cpu_addr(15 downto 0), |
data_in => cpu_data_in, |
data_out => cpu_data_out, |
halt => cpu_halt, |
142,27 → 98,21
); |
|
|
my_rom : mon_rom port map ( |
clk => SysClk, |
rst => cpu_reset, |
cs => ram_cs, |
rw => cpu_rw, |
addr => cpu_addr(10 downto 0), |
data_in => cpu_data_out, |
data_out => rom_data_out |
my_ram : block_ram port map ( |
MEMclk => SysClk, |
MEMcs => ram_cs, |
MEMrw => cpu_rw, |
MEMaddr => cpu_addr(10 downto 0), |
MEMrdata => ram_data_out, |
MEMwdata => cpu_data_out |
); |
|
my_rom : sbug_rom port map ( |
MEMclk => SysClk, |
MEMaddr => cpu_addr(10 downto 0), |
MEMrdata => rom_data_out |
); |
|
my_ram : ram_2k port map ( |
clk => SysClk, |
rst => cpu_reset, |
cs => ram_cs, |
rw => cpu_rw, |
addr => cpu_addr(10 downto 0), |
data_in => cpu_data_out, |
data_out => ram_data_out |
); |
|
-- *** Test Bench - User Defined Section *** |
tb : PROCESS |
variable count : integer; |
/testbench5.vhd
1,12 → 1,13
--===========================================================================-- |
-- -- |
-- TESTBENCH testbench5 - CPU09 Testbench. -- |
-- -- |
--===========================================================================-- |
--===========================================================================---- |
-- |
-- T E S T B E N C H tesetbench3 - CPU09 Testbench. |
-- |
-- www.OpenCores.Org - September 2003 |
-- This core adheres to the GNU public license |
-- |
-- File name : Testbench5.vhd |
-- |
-- Purpose : cpu09 Microprocessor Test Bench 5 |
-- Purpose : cpu09 Microprocessor Test Bench 3 |
-- Contains ROM to test interrupts |
-- |
-- Dependencies : ieee.Std_Logic_1164 |
14,39 → 15,26
-- ieee.std_logic_arith |
-- ieee.numeric_std |
-- |
-- Uses : cpu09 (..\VHDL\cpu09.vhd) CPU core |
-- Uses : cpu09 (cpu09.vhd) CPU core |
-- |
-- Author : John E. Kent |
-- dilbert57@opencores.org |
-- |
-- Copyright (C) 2003 - 2011 John Kent |
-- |
-- This program is free software: you can redistribute it and/or modify |
-- it under the terms of the GNU General Public License as published by |
-- the Free Software Foundation, either version 3 of the License, or |
-- (at your option) any later version. |
-- |
-- This program is distributed in the hope that it will be useful, |
-- but WITHOUT ANY WARRANTY; without even the implied warranty of |
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
-- GNU General Public License for more details. |
-- |
-- You should have received a copy of the GNU General Public License |
-- along with this program. If not, see <http://www.gnu.org/licenses/>. |
-- |
--===========================================================================-- |
-- -- |
-- Revision History -- |
-- -- |
--===========================================================================-- |
-- |
-- Rev Date Author Changes |
-- 0.1 2003-04-12 John Kent First version |
-- 1.0 2003-09-06 John Kent Initial release to Opencores.org |
-- 1.1 2004-02-25 John kent removed test_alu and test_cc signals from CPU component. |
-- 1.2 2011-10-09 John Kent renamed address to addr on CPU component, updated header |
--===========================================================================---- |
-- |
-- Revision History: |
--===========================================================================-- |
-- |
-- Version 0.1 - 12st April 2003 - John Kent |
-- First version |
-- |
-- Version 1.0 - 6 Sep 2003 - John Kent |
-- Initial release to Open Cores |
-- |
-- Version 1.1 - 25th Jan 2004 - John Kent |
-- removed "test_alu" and "test_cc" |
-- |
--===========================================================================-- |
|
library ieee; |
use ieee.std_logic_1164.all; |
138,7 → 126,7
rst: in std_logic; |
rw: out std_logic; -- Asynchronous memory interface |
vma: out std_logic; |
addr: out std_logic_vector(15 downto 0); |
address: out std_logic_vector(15 downto 0); |
data_in: in std_logic_vector(7 downto 0); |
data_out: out std_logic_vector(7 downto 0); |
halt: in std_logic; |
156,7 → 144,7
rst => cpu_reset, |
rw => cpu_rw, |
vma => cpu_vma, |
addr => cpu_addr(15 downto 0), |
address => cpu_addr(15 downto 0), |
data_in => cpu_data_in, |
data_out => cpu_data_out, |
halt => '0', |
/testbench6.vhd
1,9 → 1,10
--===========================================================================-- |
-- -- |
-- TESTBENCH testbench6 - CPU09 Testbench. -- |
-- -- |
--===========================================================================-- |
--===========================================================================---- |
-- |
-- T E S T B E N C H tesetbench3 - CPU09 Testbench. |
-- |
-- www.OpenCores.Org - September 2003 |
-- This core adheres to the GNU public license |
-- |
-- File name : Testbench6.vhd |
-- |
-- Purpose : cpu09 Microprocessor Test Bench 6 |
14,39 → 15,26
-- ieee.std_logic_arith |
-- ieee.numeric_std |
-- |
-- Uses : cpu09 (..\VHDL\cpu09.vhd) CPU core |
-- Uses : cpu09 (cpu09.vhd) CPU core |
-- |
-- Author : John E. Kent |
-- dilbert57@opencores.org |
-- |
-- Copyright (C) 2003 - 2011 John Kent |
-- |
-- This program is free software: you can redistribute it and/or modify |
-- it under the terms of the GNU General Public License as published by |
-- the Free Software Foundation, either version 3 of the License, or |
-- (at your option) any later version. |
-- |
-- This program is distributed in the hope that it will be useful, |
-- but WITHOUT ANY WARRANTY; without even the implied warranty of |
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
-- GNU General Public License for more details. |
-- |
-- You should have received a copy of the GNU General Public License |
-- along with this program. If not, see <http://www.gnu.org/licenses/>. |
-- |
--===========================================================================-- |
-- -- |
-- Revision History -- |
-- -- |
--===========================================================================-- |
-- |
-- Rev Date Author Changes |
-- 0.1 2003-04-12 John Kent First version |
-- 1.0 2003-09-06 John Kent Initial release to Opencores.org |
-- 1.1 2004-02-25 John kent removed test_alu and test_cc signals from CPU component. |
-- 1.2 2011-10-09 John Kent renamed address to addr on CPU component, updated header |
--===========================================================================---- |
-- |
-- Revision History: |
--===========================================================================-- |
-- |
-- Version 0.1 - 12st April 2003 - John Kent |
-- First version |
-- |
-- Version 1.0 - 6 Sep 2003 - John Kent |
-- Initial release to Open Cores |
-- |
-- Version 1.1 - 25th Jan 2004 - John Kent |
-- removed "test_alu" and "test_cc" |
-- |
--===========================================================================-- |
|
library ieee; |
use ieee.std_logic_1164.all; |
130,7 → 118,7
rst: in std_logic; |
rw: out std_logic; -- Asynchronous memory interface |
vma: out std_logic; |
addr: out std_logic_vector(15 downto 0); |
address: out std_logic_vector(15 downto 0); |
data_in: in std_logic_vector(7 downto 0); |
data_out: out std_logic_vector(7 downto 0); |
halt: in std_logic; |
148,7 → 136,7
rst => cpu_reset, |
rw => cpu_rw, |
vma => cpu_vma, |
addr => cpu_addr(15 downto 0), |
address => cpu_addr(15 downto 0), |
data_in => cpu_data_in, |
data_out => cpu_data_out, |
halt => '0', |