URL
https://opencores.org/ocsvn/System09/System09/trunk
Subversion Repositories System09
Compare Revisions
- This comparison shows the changes necessary to convert path
/System09/trunk
- from Rev 149 to Rev 148
- ↔ Reverse comparison
Rev 149 → Rev 148
/rtl/System09_Digilent_Atlys/system09.ise
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rtl/System09_Digilent_Atlys/system09.ise
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## -1 +0,0 ##
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Index: rtl/System09_Digilent_Atlys/Makefile
===================================================================
--- rtl/System09_Digilent_Atlys/Makefile (revision 149)
+++ rtl/System09_Digilent_Atlys/Makefile (revision 148)
@@ -154,3 +154,14 @@
-$(MAKE) -C ../../Tools/as09 clean
-$(MAKE) -C ../../Tools/s19tovhd clean
+XXST_FILE := $(DESIGN_NAME).xst
+#XPRJ_FILE := $(shell $(AWK) '/^-ifn/ { printf("%s",$$2) }' $(SXST_FILE))
+XPRJ_FILE := $(DESIGN_NAME).prj
+XHDL_FILES := $(subst ",,$(shell $(AWK) '{ print $$3} ' $(XPRJ_FILE)))
+
+#
+foo:
+ @echo "FOO"
+ @echo "'$(XXST_FILE)'"
+ @echo "'$(XPRJ_FILE)'"
+ @echo "'$(XHDL_FILES)'"
/rtl/System09_Digilent_Atlys/atlys.ucf
0,0 → 1,40
##################################################### |
# |
# XSA-3S1000 Board FPGA pin assignment constraints |
# |
##################################################### |
# |
# Clocks |
# |
# clock pin for Atlys rev C board |
NET "CLKA" LOC = "L15"; # Bank = 1, Pin name = IO_L42P_GCLK7_M1UDM, Type = GCLK, Sch name = GCLK |
|
# |
# Push button switches |
# |
NET "SW2_N" LOC = "N4"; # Bank = 3, Pin name = IO_L1P, Sch name = BTNU |
NET "SW3_N" LOC = "P3"; # Bank = 3, Pin name = IO_L2N, Sch name = BTND |
|
# |
# Status LED |
# |
NET "S<0>" LOC = "U18"; # Bank = 1, Pin name = IO_L52N_M1DQ15, Sch name = LD0 |
NET "S<1>" LOC = "M14"; # Bank = 1, Pin name = IO_L53P, Sch name = LD1 |
NET "S<2>" LOC = "N14"; # Bank = 1, Pin name = IO_L53N_VREF, Sch name = LD2 |
NET "S<3>" LOC = "L14"; # Bank = 1, Pin name = IO_L61P, Sch name = LD3 |
NET "S<4>" LOC = "M13"; # Bank = 1, Pin name = IO_L61N, Sch name = LD4 |
NET "S<5>" LOC = "D4"; # Bank = 0, Pin name = IO_L1P_HSWAPEN_0, Sch name = HSWAP/LD5 |
NET "S<6>" LOC = "P16"; # Bank = 1, Pin name = IO_L74N_DOUT_BUSY_1, Sch name = LD6 |
NET "S<7>" LOC = "N12"; # Bank = 2, Pin name = IO_L13P_M1_2, Sch name = M1/LD7 |
|
# |
# RS232 PORT |
# |
NET "RS232_RXD" LOC = "A16"; # Bank = 0, Pin name = IO_L66N_SCP0, Sch name = USBB-RXD |
NET "RS232_TXD" LOC = "B16"; # Bank = 0, Pin name = IO_L66P_SCP1, Sch name = USBB-TXD |
|
# |
# Timing Constraints |
# |
NET "CLKA" TNM_NET="CLKA"; |
TIMESPEC "TS_clk"=PERIOD "CLKA" 10 ns HIGH 50 %; |
/rtl/System09_Digilent_Atlys/system09.gise
107,11 → 107,17
<status xil_pn:value="SuccessfullyRun"/> |
<status xil_pn:value="WarningsGenerated"/> |
<status xil_pn:value="ReadyToRun"/> |
<status xil_pn:value="OutOfDateForInputs"/> |
<status xil_pn:value="OutOfDateForOutputs"/> |
<status xil_pn:value="InputAdded"/> |
<status xil_pn:value="InputRemoved"/> |
<status xil_pn:value="OutputRemoved"/> |
<outfile xil_pn:name="_xmsgs/xst.xmsgs"/> |
<outfile xil_pn:name="system09.lso"/> |
<outfile xil_pn:name="system09.ngc"/> |
<outfile xil_pn:name="system09.ngr"/> |
<outfile xil_pn:name="system09.prj"/> |
<outfile xil_pn:name="system09.stx"/> |
<outfile xil_pn:name="system09.syr"/> |
<outfile xil_pn:name="system09.xst"/> |
<outfile xil_pn:name="system09_xst.xrpt"/> |
<outfile xil_pn:name="webtalk_pn.xml"/> |
<outfile xil_pn:name="xst"/> |
</transform> |
<transform xil_pn:end_ts="1518994687" xil_pn:in_ck="6003168217582152378" xil_pn:name="TRAN_compileBCD2" xil_pn:prop_ck="-3128816144678396997" xil_pn:start_ts="1518994687"> |
<status xil_pn:value="SuccessfullyRun"/> |
119,11 → 125,9
</transform> |
<transform xil_pn:end_ts="1518994692" xil_pn:in_ck="-2676906326711859666" xil_pn:name="TRANEXT_ngdbuild_FPGA" xil_pn:prop_ck="3664377249183397421" xil_pn:start_ts="1518994687"> |
<status xil_pn:value="SuccessfullyRun"/> |
<status xil_pn:value="NotReadyToRun"/> |
<status xil_pn:value="ReadyToRun"/> |
<status xil_pn:value="OutOfDateForInputs"/> |
<status xil_pn:value="OutOfDateForPredecessor"/> |
<status xil_pn:value="OutOfDateForOutputs"/> |
<status xil_pn:value="InputRemoved"/> |
<status xil_pn:value="OutputRemoved"/> |
</transform> |
<transform xil_pn:end_ts="1518994711" xil_pn:in_ck="190496098961729835" xil_pn:name="TRAN_postRouteTrce" xil_pn:prop_ck="445577401284416186" xil_pn:start_ts="1518994707"> |
130,6 → 134,7
<status xil_pn:value="SuccessfullyRun"/> |
<status xil_pn:value="NotReadyToRun"/> |
<status xil_pn:value="OutOfDateForInputs"/> |
<status xil_pn:value="OutOfDateForPredecessor"/> |
<status xil_pn:value="OutOfDateForOutputs"/> |
<status xil_pn:value="InputRemoved"/> |
<status xil_pn:value="OutputRemoved"/> |