OpenCores
URL https://opencores.org/ocsvn/System09/System09/trunk

Subversion Repositories System09

Compare Revisions

  • This comparison shows the changes necessary to convert path
    /System09/trunk
    from Rev 184 to Rev 185
    Reverse comparison

Rev 184 → Rev 185

/rtl/System09_Digilent_Atlys/btn_debounce.vhd
0,0 → 1,178
----------------------------------------------------------------------------
-- btn_debounce.vhd -- Button Debouncer
----------------------------------------------------------------------------
-- Author: Sam Bobrowicz
-- Copyright 2011 Digilent, Inc.
----------------------------------------------------------------------------
--
----------------------------------------------------------------------------
-- This component is used to debounce signals generated by external push
-- buttons. It is designed to independently debounce 5 Push button signals.
-- Debouncing is done by only registering a change in a button state if
-- it remains constant for 2^16 clock cycles.
--
-- Port Descriptions:
--
-- BTN_I - The input button signals
-- CLK - Behavior is optimized for a 100 MHz clock
-- BTN_O - The debounced button signals
--
----------------------------------------------------------------------------
--
----------------------------------------------------------------------------
-- Revision History:
-- 08/08/2011(SamB): Created using Xilinx Tools 13.2
----------------------------------------------------------------------------
 
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.std_logic_unsigned.all;
 
entity btn_debounce is
Port ( BTN_I : in STD_LOGIC_VECTOR (4 downto 0);
CLK : in STD_LOGIC;
BTN_O : out STD_LOGIC_VECTOR (4 downto 0));
end btn_debounce;
 
architecture Behavioral of btn_debounce is
 
constant CNTR_MAX : std_logic_vector(15 downto 0) := (others => '1');
 
signal btn0_cntr : std_logic_vector(15 downto 0) := (others => '0');
signal btn1_cntr : std_logic_vector(15 downto 0) := (others => '0');
signal btn2_cntr : std_logic_vector(15 downto 0) := (others => '0');
signal btn3_cntr : std_logic_vector(15 downto 0) := (others => '0');
signal btn4_cntr : std_logic_vector(15 downto 0) := (others => '0');
 
signal btn0_reg : std_logic := '0';
signal btn1_reg : std_logic := '0';
signal btn2_reg : std_logic := '0';
signal btn3_reg : std_logic := '0';
signal btn4_reg : std_logic := '0';
 
begin
 
btn0_debounce_process : process (CLK)
begin
if (rising_edge(CLK)) then
if (btn0_cntr = CNTR_MAX) then
btn0_reg <= not(btn0_reg);
end if;
end if;
end process;
 
btn0_counter_process : process (CLK)
begin
if (rising_edge(CLK)) then
if ((btn0_reg = '1') xor (BTN_I(0) = '1')) then
if (btn0_cntr = CNTR_MAX) then
btn0_cntr <= (others => '0');
else
btn0_cntr <= btn0_cntr + 1;
end if;
else
btn0_cntr <= (others => '0');
end if;
end if;
end process;
 
btn1_debounce_process : process (CLK)
begin
if (rising_edge(CLK)) then
if (btn1_cntr = CNTR_MAX) then
btn1_reg <= not(btn1_reg);
end if;
end if;
end process;
 
btn1_counter_process : process (CLK)
begin
if (rising_edge(CLK)) then
if ((btn1_reg = '1') xor (BTN_I(1) = '1')) then
if (btn1_cntr = CNTR_MAX) then
btn1_cntr <= (others => '0');
else
btn1_cntr <= btn1_cntr + 1;
end if;
else
btn1_cntr <= (others => '0');
end if;
end if;
end process;
 
btn2_debounce_process : process (CLK)
begin
if (rising_edge(CLK)) then
if (btn2_cntr = CNTR_MAX) then
btn2_reg <= not(btn2_reg);
end if;
end if;
end process;
 
btn2_counter_process : process (CLK)
begin
if (rising_edge(CLK)) then
if ((btn2_reg = '1') xor (BTN_I(2) = '1')) then
if (btn2_cntr = CNTR_MAX) then
btn2_cntr <= (others => '0');
else
btn2_cntr <= btn2_cntr + 1;
end if;
else
btn2_cntr <= (others => '0');
end if;
end if;
end process;
 
btn3_debounce_process : process (CLK)
begin
if (rising_edge(CLK)) then
if (btn3_cntr = CNTR_MAX) then
btn3_reg <= not(btn3_reg);
end if;
end if;
end process;
 
btn3_counter_process : process (CLK)
begin
if (rising_edge(CLK)) then
if ((btn3_reg = '1') xor (BTN_I(3) = '1')) then
if (btn3_cntr = CNTR_MAX) then
btn3_cntr <= (others => '0');
else
btn3_cntr <= btn3_cntr + 1;
end if;
else
btn3_cntr <= (others => '0');
end if;
end if;
end process;
 
btn4_debounce_process : process (CLK)
begin
if (rising_edge(CLK)) then
if (btn4_cntr = CNTR_MAX) then
btn4_reg <= not(btn4_reg);
end if;
end if;
end process;
 
btn4_counter_process : process (CLK)
begin
if (rising_edge(CLK)) then
if ((btn4_reg = '1') xor (BTN_I(4) = '1')) then
if (btn4_cntr = CNTR_MAX) then
btn4_cntr <= (others => '0');
else
btn4_cntr <= btn4_cntr + 1;
end if;
else
btn4_cntr <= (others => '0');
end if;
end if;
end process;
 
BTN_O <= btn4_reg & btn3_reg & btn2_reg & btn1_reg & btn0_reg;
 
end Behavioral;
 
/rtl/System09_Digilent_Atlys/system09.gise
76,35 → 76,35
</files>
 
<transforms xmlns="http://www.xilinx.com/XMLSchema">
<transform xil_pn:end_ts="1611294559" xil_pn:name="TRAN_copyInitialToXSTAbstractSynthesis" xil_pn:start_ts="1611294559">
<transform xil_pn:end_ts="1611345983" xil_pn:name="TRAN_copyInitialToXSTAbstractSynthesis" xil_pn:start_ts="1611345983">
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/>
</transform>
<transform xil_pn:end_ts="1611294559" xil_pn:name="TRAN_schematicsToHdl" xil_pn:prop_ck="3688993175894000260" xil_pn:start_ts="1611294559">
<transform xil_pn:end_ts="1611345983" xil_pn:name="TRAN_schematicsToHdl" xil_pn:prop_ck="3688993175894000260" xil_pn:start_ts="1611345983">
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/>
</transform>
<transform xil_pn:end_ts="1611294559" xil_pn:name="TRAN_regenerateCores" xil_pn:prop_ck="7998624334607291317" xil_pn:start_ts="1611294559">
<transform xil_pn:end_ts="1611345983" xil_pn:name="TRAN_regenerateCores" xil_pn:prop_ck="7998624334607291317" xil_pn:start_ts="1611345983">
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/>
</transform>
<transform xil_pn:end_ts="1611294559" xil_pn:name="TRAN_SubProjectAbstractToPreProxy" xil_pn:start_ts="1611294559">
<transform xil_pn:end_ts="1611345983" xil_pn:name="TRAN_SubProjectAbstractToPreProxy" xil_pn:start_ts="1611345983">
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/>
</transform>
<transform xil_pn:end_ts="1611294559" xil_pn:name="TRAN_xawsTohdl" xil_pn:prop_ck="-2491246652047045050" xil_pn:start_ts="1611294559">
<transform xil_pn:end_ts="1611345983" xil_pn:name="TRAN_xawsTohdl" xil_pn:prop_ck="-2491246652047045050" xil_pn:start_ts="1611345983">
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/>
</transform>
<transform xil_pn:end_ts="1611294559" xil_pn:name="TRAN_SubProjectPreToStructuralProxy" xil_pn:prop_ck="8977612015756273942" xil_pn:start_ts="1611294559">
<transform xil_pn:end_ts="1611345983" xil_pn:name="TRAN_SubProjectPreToStructuralProxy" xil_pn:prop_ck="8977612015756273942" xil_pn:start_ts="1611345983">
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/>
</transform>
<transform xil_pn:end_ts="1611294559" xil_pn:name="TRAN_platgen" xil_pn:prop_ck="-1223916495889636993" xil_pn:start_ts="1611294559">
<transform xil_pn:end_ts="1611345983" xil_pn:name="TRAN_platgen" xil_pn:prop_ck="-1223916495889636993" xil_pn:start_ts="1611345983">
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/>
</transform>
<transform xil_pn:end_ts="1611294608" xil_pn:in_ck="4010317442951213546" xil_pn:name="TRANEXT_xstsynthesize_spartan6" xil_pn:prop_ck="1974990584335492622" xil_pn:start_ts="1611294559">
<transform xil_pn:end_ts="1611346033" xil_pn:in_ck="8320588413340917314" xil_pn:name="TRANEXT_xstsynthesize_spartan6" xil_pn:prop_ck="1974990584335492622" xil_pn:start_ts="1611345983">
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="WarningsGenerated"/>
<status xil_pn:value="ReadyToRun"/>
122,11 → 122,11
<outfile xil_pn:name="webtalk_pn.xml"/>
<outfile xil_pn:name="xst"/>
</transform>
<transform xil_pn:end_ts="1611294608" xil_pn:in_ck="6003168217582152378" xil_pn:name="TRAN_compileBCD2" xil_pn:prop_ck="-3128816144678396997" xil_pn:start_ts="1611294608">
<transform xil_pn:end_ts="1611346033" xil_pn:in_ck="6003168217582152378" xil_pn:name="TRAN_compileBCD2" xil_pn:prop_ck="-3128816144678396997" xil_pn:start_ts="1611346033">
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/>
</transform>
<transform xil_pn:end_ts="1611294613" xil_pn:in_ck="-2676906326711859666" xil_pn:name="TRANEXT_ngdbuild_FPGA" xil_pn:prop_ck="7427287850225075136" xil_pn:start_ts="1611294608">
<transform xil_pn:end_ts="1611346038" xil_pn:in_ck="-2676906326711859666" xil_pn:name="TRANEXT_ngdbuild_FPGA" xil_pn:prop_ck="7427287850225075136" xil_pn:start_ts="1611346033">
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/>
<outfile xil_pn:name="_ngo"/>
135,7 → 135,7
<outfile xil_pn:name="system09.ngd"/>
<outfile xil_pn:name="system09_ngdbuild.xrpt"/>
</transform>
<transform xil_pn:end_ts="1611294629" xil_pn:in_ck="-1009016811758874705" xil_pn:name="TRANEXT_map_spartan6" xil_pn:prop_ck="7013356299669423719" xil_pn:start_ts="1611294613">
<transform xil_pn:end_ts="1611346057" xil_pn:in_ck="-1009016811758874705" xil_pn:name="TRANEXT_map_spartan6" xil_pn:prop_ck="7013356299669423719" xil_pn:start_ts="1611346038">
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/>
<outfile xil_pn:name="_xmsgs/map.xmsgs"/>
148,8 → 148,9
<outfile xil_pn:name="system09_summary.xml"/>
<outfile xil_pn:name="system09_usage.xml"/>
</transform>
<transform xil_pn:end_ts="1611294651" xil_pn:in_ck="-7782462315172532792" xil_pn:name="TRANEXT_par_spartan6" xil_pn:prop_ck="-3829590541433901613" xil_pn:start_ts="1611294629">
<transform xil_pn:end_ts="1611346079" xil_pn:in_ck="-7782462315172532792" xil_pn:name="TRANEXT_par_spartan6" xil_pn:prop_ck="-3829590541433901613" xil_pn:start_ts="1611346057">
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="WarningsGenerated"/>
<status xil_pn:value="ReadyToRun"/>
<outfile xil_pn:name="_xmsgs/par.xmsgs"/>
<outfile xil_pn:name="system09.ncd"/>
162,7 → 163,7
<outfile xil_pn:name="system09_pad.txt"/>
<outfile xil_pn:name="system09_par.xrpt"/>
</transform>
<transform xil_pn:end_ts="1611294668" xil_pn:in_ck="6003168217582144753" xil_pn:name="TRANEXT_bitFile_spartan6" xil_pn:prop_ck="-5761130248037966628" xil_pn:start_ts="1611294651">
<transform xil_pn:end_ts="1611346096" xil_pn:in_ck="6003168217582144753" xil_pn:name="TRANEXT_bitFile_spartan6" xil_pn:prop_ck="-5761130248037966628" xil_pn:start_ts="1611346079">
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/>
<outfile xil_pn:name="_xmsgs/bitgen.xmsgs"/>
174,7 → 175,7
<outfile xil_pn:name="webtalk.log"/>
<outfile xil_pn:name="webtalk_pn.xml"/>
</transform>
<transform xil_pn:end_ts="1611294651" xil_pn:in_ck="190496098961729835" xil_pn:name="TRAN_postRouteTrce" xil_pn:prop_ck="-1758799009971969896" xil_pn:start_ts="1611294645">
<transform xil_pn:end_ts="1611346079" xil_pn:in_ck="190496098961729835" xil_pn:name="TRAN_postRouteTrce" xil_pn:prop_ck="-1758799009971969896" xil_pn:start_ts="1611346073">
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/>
<outfile xil_pn:name="_xmsgs/trce.xmsgs"/>
/rtl/System09_Digilent_Atlys/system09.prj
8,6 → 8,7
vhdl work "../VHDL/ACIA_Clock.vhd"
vhdl work "../VHDL/acia6850.vhd"
vhdl work "common.vhd"
vhdl work "btn_debounce.vhd"
vhdl work "../Spartan3/ram32k_b16.vhd"
vhdl work "../Spartan3/ram16k_b16.vhd"
vhdl work "system09.vhd"
/rtl/System09_Digilent_Atlys/system09.ucf
54,34 → 54,34
#
# SYSTEM09: Status LED
#
# NET "S<0>" LOC = "U18"; # Bank = 1, Pin name = IO_L52N_M1DQ15, Sch name = LD0
# NET "S<1>" LOC = "M14"; # Bank = 1, Pin name = IO_L53P, Sch name = LD1
# NET "S<2>" LOC = "N14"; # Bank = 1, Pin name = IO_L53N_VREF, Sch name = LD2
# NET "S<3>" LOC = "L14"; # Bank = 1, Pin name = IO_L61P, Sch name = LD3
# NET "S<4>" LOC = "M13"; # Bank = 1, Pin name = IO_L61N, Sch name = LD4
# NET "S<5>" LOC = "D4"; # Bank = 0, Pin name = IO_L1P_HSWAPEN_0, Sch name = HSWAP/LD5
# NET "S<6>" LOC = "P16"; # Bank = 1, Pin name = IO_L74N_DOUT_BUSY_1, Sch name = LD6
# NET "S<7>" LOC = "N12"; # Bank = 2, Pin name = IO_L13P_M1_2, Sch name = M1/LD7
NET "S<0>" LOC = "U18"; # Bank = 1, Pin name = IO_L52N_M1DQ15, Sch name = LD0
NET "S<1>" LOC = "M14"; # Bank = 1, Pin name = IO_L53P, Sch name = LD1
NET "S<2>" LOC = "N14"; # Bank = 1, Pin name = IO_L53N_VREF, Sch name = LD2
NET "S<3>" LOC = "L14"; # Bank = 1, Pin name = IO_L61P, Sch name = LD3
NET "S<4>" LOC = "M13"; # Bank = 1, Pin name = IO_L61N, Sch name = LD4
NET "S<5>" LOC = "D4"; # Bank = 0, Pin name = IO_L1P_HSWAPEN_0, Sch name = HSWAP/LD5
NET "S<6>" LOC = "P16"; # Bank = 1, Pin name = IO_L74N_DOUT_BUSY_1, Sch name = LD6
NET "S<7>" LOC = "N12"; # Bank = 2, Pin name = IO_L13P_M1_2, Sch name = M1/LD7
 
#
# SYSTEM09: Push button switches
#
# NET "btn<0>" LOC = "T15"; # Bank = 2, Pin name = IO_L1N_M0_CMPMISO_2, Sch name = M0/RESET
NET "RESET_N" LOC = "N4"; # Bank = 3, Pin name = IO_L1P, Sch name = BTNU
# NET "btn<1>" LOC = "P4"; # Bank = 3, Pin name = IO_L2P, Sch name = BTNL
NET "NMI_N" LOC = "P3"; # Bank = 3, Pin name = IO_L2N, Sch name = BTND
# NET "btn<3>" LOC = "F6"; # Bank = 3, Pin name = IO_L55P_M3A13, Sch name = BTNR
# NET "btn<4>" LOC = "F5"; # Bank = 3, Pin name = IO_L55N_M3A14, Sch name = BTNC
NET "btn<0>" LOC = "N4"; # Bank = 3, Pin name = IO_L1P, Sch name = BTNU
NET "btn<1>" LOC = "P4"; # Bank = 3, Pin name = IO_L2P, Sch name = BTNL
NET "btn<2>" LOC = "P3"; # Bank = 3, Pin name = IO_L2N, Sch name = BTND
NET "btn<3>" LOC = "F6"; # Bank = 3, Pin name = IO_L55P_M3A13, Sch name = BTNR
NET "btn<4>" LOC = "F5"; # Bank = 3, Pin name = IO_L55N_M3A14, Sch name = BTNC
# onBoard SWITCHES
# NET "sw<0>" LOC = "A10"; # Bank = 0, Pin name = IO_L37N_GCLK12, Sch name = SW0
# NET "sw<1>" LOC = "D14"; # Bank = 0, Pin name = IO_L65P_SCP3, Sch name = SW1
# NET "sw<2>" LOC = "C14"; # Bank = 0, Pin name = IO_L65N_SCP2, Sch name = SW2
# NET "sw<3>" LOC = "P15"; # Bank = 1, Pin name = IO_L74P_AWAKE_1, Sch name = SW3
# NET "sw<4>" LOC = "P12"; # Bank = 2, Pin name = IO_L13N_D10, Sch name = SW4
# NET "sw<5>" LOC = "R5"; # Bank = 2, Pin name = IO_L48P_D7, Sch name = SW5
# NET "sw<6>" LOC = "T5"; # Bank = 2, Pin name = IO_L48N_RDWR_B_VREF_2, Sch name = SW6
# NET "sw<7>" LOC = "E4"; # Bank = 3, Pin name = IO_L54P_M3RESET, Sch name = SW7
NET "sw<0>" LOC = "A10"; # Bank = 0, Pin name = IO_L37N_GCLK12, Sch name = SW0
NET "sw<1>" LOC = "D14"; # Bank = 0, Pin name = IO_L65P_SCP3, Sch name = SW1
NET "sw<2>" LOC = "C14"; # Bank = 0, Pin name = IO_L65N_SCP2, Sch name = SW2
NET "sw<3>" LOC = "P15"; # Bank = 1, Pin name = IO_L74P_AWAKE_1, Sch name = SW3
NET "sw<4>" LOC = "P12"; # Bank = 2, Pin name = IO_L13N_D10, Sch name = SW4
NET "sw<5>" LOC = "R5"; # Bank = 2, Pin name = IO_L48P_D7, Sch name = SW5
NET "sw<6>" LOC = "T5"; # Bank = 2, Pin name = IO_L48N_RDWR_B_VREF_2, Sch name = SW6
NET "sw<7>" LOC = "E4"; # Bank = 3, Pin name = IO_L54P_M3RESET, Sch name = SW7
 
# TEMAC Ethernet MAC
# NET "phyrst" LOC = "G13"; # Bank = 1, Pin name = IO_L32N_A16_M1A9, Sch name = E-RESET
233,16 → 233,13
 
 
# Using PMOD connection
# RS-232 PMod Atlys Pmod Port JB
# Pin Dir Function PMOD Dir PinLoc
# 1 input CTS JB<0> output T3
# 2 output RTS JB<1> input R3
# 3 output TXD JB<2> input P6
# 4 input RXD JB<3> output N5
# NET "RS232_CTS" LOC = "T3"; # Bank = 2, Pin name = IO_L62N_D6, Sch name = JA-D0_N
# NET "RS232_RTS" LOC = "R3"; # Bank = 2, Pin name = IO_L62P_D5, Sch name = JA-D0_P
NET "RS232_RXD" LOC = "P6"; # Bank = 0, Pin name = IO_L66N_SCP0, Sch name = USBB-RXD
NET "RS232_TXD" LOC = "N5"; # Bank = 0, Pin name = IO_L66P_SCP1, Sch name = USBB-TXD
# RS-232 PMod Pin Function PMOD PinLoc
# 1 CTS JB<0> T3
# 2 RTS JB<1> R3
# 3 TXD JB<2> P6
# 4 RXD JB<3> N5
NET "RS232_RXD" LOC = "N5"; # Bank = 0, Pin name = IO_L66N_SCP0, Sch name = USBB-RXD
NET "RS232_TXD" LOC = "P6"; # Bank = 0, Pin name = IO_L66P_SCP1, Sch name = USBB-TXD
 
# onboard VHDCI
# Channnel 1 connects to P signals, Channel 2 to N signals
/rtl/System09_Digilent_Atlys/system09.vhd
129,15 → 129,19
entity system09 is
port(
CLKA : in Std_Logic; -- 100MHz Clock input
RESET_N : in Std_logic; -- Master Reset input (active low)
NMI_N : in Std_logic; -- Non Maskable Interrupt input (active low)
--SW2_N : in Std_logic; -- Master Reset input (active low)
--SW3_N : in Std_logic; -- Non Maskable Interrupt input (active low)
 
-- RS232 Port
--RS232_CTS : in std_logic;
--RS232_RTS : out std_logic;
RS232_RXD : in Std_Logic; -- RS-232 data in
RS232_TXD : out Std_Logic -- RS-232 data out
-- RS232 Port
RS232_RXD : in Std_Logic;
RS232_TXD : out Std_Logic;
 
-- Status 7 segment LED
sw : in std_logic_vector(7 downto 0);
btn : in std_logic_vector(4 downto 0);
S : out std_logic_vector(7 downto 0)
 
 
-- CPU Debug Interface signals
-- cpu_reset_o : out Std_Logic;
-- cpu_clk_o : out Std_Logic;
163,16 → 167,25
-----------------------------------------------------------------------------
-- constants
-----------------------------------------------------------------------------
constant SYS_CLK_FREQ : natural := 100_000_000; -- FPGA System Clock (in Hz)
constant CPU_CLK_FREQ : natural := 25_000_000; -- CPU Clock (Hz)
 
constant MEM_CLK_FREQ : natural := 100_000; -- operating frequency of Memory in KHz
constant SYS_CLK_DIV : real := 2.0; -- divisor for FREQ (can only be 1.0, 1.5, 2.0, 2.5, 3.0, 4.0, 5.0, 8.0 or 16.0)
 
constant SYS_CLK_FREQ : natural := ((MEM_CLK_FREQ*2)/integer(SYS_CLK_DIV*2.0))*1000; -- FPGA System Clock (in Hz)
constant CPU_CLK_FREQ : natural := 1; --25_000_000; -- CPU Clock (Hz)
constant CPU_CLK_DIV : natural := (SYS_CLK_FREQ/CPU_CLK_FREQ);
constant BAUD_RATE : integer := 57600; -- Baud Rate
constant ACIA_CLK_FREQ : integer := BAUD_RATE * 16;
 
constant TRESET : natural := 300; -- min initialization interval (us)
constant RST_CYCLES : natural := 1+(TRESET*(MEM_CLK_FREQ/1_000)); -- SDRAM power-on initialization interval
 
-----------------------------------------------------------------------------
-- Signals
-----------------------------------------------------------------------------
 
signal pbtn : std_logic_vector(4 downto 0);
signal SW3_N : std_logic;
signal SW2_N : std_logic;
-- BOOT ROM
signal rom_cs : Std_logic;
signal rom_data_out : Std_Logic_Vector(7 downto 0);
233,8 → 246,17
signal rs232_cts : Std_Logic;
signal rs232_rts : Std_Logic;
signal CountL : std_logic_vector(23 downto 0);
signal clk_count : natural range 0 to CPU_CLK_DIV;
signal Clk25 : std_logic;
 
 
component btn_debounce
Port ( BTN_I : in STD_LOGIC_VECTOR (4 downto 0);
CLK : in STD_LOGIC;
BTN_O : out STD_LOGIC_VECTOR (4 downto 0));
end component;
 
 
-----------------------------------------------------------------
--
436,12 → 458,11
data_out : out std_logic_vector(7 downto 0)
);
end component;
 
----------------------------------------
 
 
--
-- Clock buffer
--
----------------------------------------
 
component BUFG
Port (
450,8 → 471,12
);
end component;
 
begin
begin
 
 
 
 
clk_i <= CLKA;
-----------------------------------------------------------------------------
-- Instantiation of internal components
538,7 → 563,7
 
my_ACIA_Clock : ACIA_Clock
generic map(
SYS_CLK_FREQ => SYS_CLK_FREQ,
SYS_CLK_FREQ => SYS_CLK_FREQ,
ACIA_CLK_FREQ => ACIA_CLK_FREQ
)
port map(
735,7 → 760,7
--
-- Interrupts and other bus control signals
--
interrupts : process( NMI_N,
interrupts : process( SW3_N,
acia_irq,
trap_irq,
timer_irq
742,7 → 767,7
)
begin
cpu_irq <= acia_irq;
cpu_nmi <= trap_irq or not( NMI_N );
cpu_nmi <= trap_irq or not( SW3_N );
cpu_firq <= timer_irq;
cpu_halt <= '0';
cpu_hold <= '0'; -- pb_hold or ram_hold;
749,30 → 774,50
end process;
 
--
-- Generate CPU & Pixel Clock from Memory Clock
-- Flash 7 segment LEDS
--
my_prescaler : process( clk_i, clk_count )
my_led_flasher: process( clk_i, rst_i, CountL )
begin
if rising_edge( clk_i ) then
if clk_count = 0 then
clk_count <= CPU_CLK_DIV-1;
else
clk_count <= clk_count - 1;
end if;
if clk_count = 0 then
clk25 <= '0';
elsif clk_count = (CPU_CLK_DIV/2) then
clk25 <= '1';
end if;
if rst_i = '1' then
CountL <= "000000000000000000000000";
elsif rising_edge(clk_i) then
CountL <= CountL + 1;
end if;
end process;
--S(7 downto 0) <= CountL(23 downto 16);
end process;
 
--
-- Generate CPU & Pixel Clock from Memory Clock
--
-- my_prescaler : process( clk_i, clk_count )
-- begin
-- if rising_edge( clk_i ) then
-- if clk_count = 0 then
-- clk_count <= CPU_CLK_DIV-1;
-- else
-- clk_count <= clk_count - 1;
-- end if;
-- if clk_count = 0 then
-- clk25 <= '0';
-- elsif clk_count = (CPU_CLK_DIV/2) then
-- clk25 <= '1';
-- end if;
-- end if;
-- end process;
 
 
my_singlestep: btn_debounce
port map ( BTN_I => btn, CLK => CLKA, BTN_O => pbtn);
SW2_N <= pbtn(0);
SW3_N <= pbtn(1);
clk25 <= pbtn(2);
 
--
-- Reset button and reset timer
--
my_switch_assignments : process( rst_i, RESET_N)
my_switch_assignments : process( rst_i, SW2_N)
begin
rst_i <= RESET_N;
rst_i <= SW2_N;
cpu_reset <= rst_i;
end process;
 
788,6 → 833,29
RS232_RTS <= rts_n;
end process;
 
status_leds : process( rst_i, cpu_reset,cpu_addr, cpu_rw, sw)
begin
S(7) <= '0';
S(6) <= cpu_rw;
S(5) <= cpu_vma;
S(4) <= '0';
case sw is
when "00000000" =>
S(3 downto 0) <= cpu_addr(3 downto 0);
when "00000001" =>
S(3 downto 0) <= cpu_addr(7 downto 4);
when "00000010" =>
S(3 downto 0) <= cpu_addr(11 downto 8);
when "00000011" =>
S(3 downto 0) <= cpu_addr(15 downto 12);
when "00000100" =>
S(3 downto 0) <= cpu_data_in(3 downto 0);
when "00000101" =>
S(3 downto 0) <= cpu_data_in(7 downto 4);
when others => S(3 downto 0) <= (others => '0');
end case;
end process;
 
-- debug_proc : process( cpu_reset, cpu_clk, cpu_rw, cpu_vma,
-- cpu_halt, cpu_hold,
-- cpu_firq, cpu_irq, cpu_nmi,
/rtl/System09_Digilent_Atlys/system09.xise
56,20 → 56,24
</file>
<file xil_pn:name="system09.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="72"/>
<association xil_pn:name="Implementation" xil_pn:seqID="13"/>
<association xil_pn:name="Implementation" xil_pn:seqID="14"/>
</file>
<file xil_pn:name="../Spartan3/ram32k_b16.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="65"/>
<association xil_pn:name="Implementation" xil_pn:seqID="11"/>
<association xil_pn:name="Implementation" xil_pn:seqID="12"/>
</file>
<file xil_pn:name="../Spartan3/ram16k_b16.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="65"/>
<association xil_pn:name="Implementation" xil_pn:seqID="12"/>
<association xil_pn:name="Implementation" xil_pn:seqID="13"/>
</file>
<file xil_pn:name="../../src/sys09bug/sys09swt.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="66"/>
<association xil_pn:name="Implementation" xil_pn:seqID="2"/>
</file>
<file xil_pn:name="btn_debounce.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="66"/>
<association xil_pn:name="Implementation" xil_pn:seqID="11"/>
</file>
</files>
 
<properties>

powered by: WebSVN 2.1.0

© copyright 1999-2022 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.