URL
https://opencores.org/ocsvn/System09/System09/trunk
Subversion Repositories System09
Compare Revisions
- This comparison shows the changes necessary to convert path
/
- from Rev 103 to Rev 104
- ↔ Reverse comparison
Rev 103 → Rev 104
/System09/trunk/rtl/System09_BurchED_B5-X300_2/System09_BurchED_B5-X300.dhp
0,0 → 1,3
XILINX-XDB 0.1 STUB 0.1 ASCII |
XILINX-XDM V1.4e |
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0`=kk1D;?4?;N52>5=Hn80:wpAi0;3xyxdc?3:1<7>50zle6?1e3g>8655@5883?!2a2m>0(8h5cc9L37<73F=:6=5@f082xIa83;pqplkb;294?6=8rdm>776;o60>==H=00;7):i:e:8 0`=kk1D;?4?;N52>5=Hn80:wpAi0;3xyx{zutwKLNu;25866=d>n?8vLMLt0|BCT~I2;3>m7B;9:4:8K00==m1D9o4;f:M6g?333F<;69h4O73911=H><0?j6A96;77?J0d2=l0C;j5669L37<3n2E<?788;N5;>1`<G>31::5@8184g>I?;32>7B6<:9c8K=5=0o1D4548c:M;=?>63F2o6:m4O9g9<4=H1;0<o6A63;:2?J?02>i0C465809L=`<0k2E2j776;Nc5>d4<Gh31mo5@a88a4>Ifm3k97Boi:`58Kg5=i;1Dn94n7:Ma<?g53Fh26l94Ocd9e7=Hk90im6Al7;a0?Jef2ji0Cno5d09Lgc<d;2Eo<7m7;Nf7>f5<Gm?1o55@d88`7>Ici3i37Bk?:b18K`7=lk1Di54j4:Mff?cc3Foi6k<4Od`9b2=Hn90n86Ai1;g:?J`22l>0Ck85e89Lbd<b<2Emn7k6;Nde>`2<G8:;6h74O025>`2<G8:<6<>>;N33a?77i2E:=<4>129L547=9820C<?>:03g?J76>3;;m6A>16824c=H98h1==o4O03`>46a3F;9<7??a:M264<68o1D=?;511c8K44128:m7B?=c;33e>I6:m0:>:5@1269566<G89<6<=6;N303?74m2E:?n4>319L56b=9:?0C<:>:013?J73:3;896A>478275=H9==1=>;4O06g>4573F;?i7?;8:M210<6=81D=86514c8K43?28?m7B?:8;350>I6=10::45@14f9507<G8?n6<;9;N356?7292E::>4>579L531=9<;0C<87:075?J71k3;>=6A>6e8213=H9>;1=8?4O051>4313F;<47?:1:M23<<6?:1D=:k51438K41a28=87B?74;365>I60<0:;>5@19c9507<G82i6<9<;N3:4?7292E:5<4>729L5<>=90>0C<7m:0;g?J7>j3;j>6A>9c82e2=H90h1=lm4O0c3>4?33F;j=7?69:M2e0<61=1D=l8518;8K4gf283?7B?nb;3:=>I6io0:595@1c295<?<G8h?6<7;;N3a1?7>12E:no4>959L5ge=9k<0C<m>:0;7?J7d:3;i:6A>c682=1=H9j21=o84O0ag>4?33F;hi7?m6:M2`6<61=1D=i:51c48K4be28n<7B?ke;3f4>I6ll0:i85@1eg95`g<G8o86<j8;N3f0?7ck2E:i54>d69L5`?=9mi0C<kk:0f4?J7bm3;oo6A>f382`2=H9o91=im4O0d:>4b03F;mm7?i4:M144<6nm1D>=:52148K7632;:i7B<?4;024>I5800:ji5@21c9654<G;:n6<hk;N03b?47:2E9=>4>fe9L642=:980C??7:0dg?J46138;>6A=1g82ba=H:;:1><o4O306>4`c3F89:7<>a:M16g<6nm1D>?m520c8K75628lo7B<<2;02e>I5;>0:ji5@22:964g<G;9m6?=m;N076?43<2E98?4=489L614=:=o0C?:8:31a?J43038?<6A=4b817g=H:=n1>9>4O372>75e3F8>>7<;0:M113<5;k1D>8952528K73c2;9i7B<:e;06<>I5>:09?o5@276960><G;<26?=m;N05e?4202E9:k4=3c9L626=:<20C?98:350?J40i38<o6A=7`81<4=H:>k1>584O35e>7143F83<7<88:M1<1<5?:1D>5;526:8K7>>2;=87B<7a;04<>I50l09;>5@29d962><G;3>6?9<;N0:2?4>82E95o4=729L6<e=:0:0C?o>:350?J4f:382<6A=a68136=H:h21>4>4O3cg>7143F8ji7<60:M1f0<5j81D>o652cc8K7d?2;hm7B<m8;0`0>I5j109o45@2cf96g7<G;hn6?l9;N0`6?4e92E9o>4=b79L6f1=:k;0C?m7:3`5?J4dk38i=6A=ce81f3=H:m;1>o?4O3f1>7d13F8o47<m1:M1`<<5l:1D>ik52c38K7ba2;n87B<j6;0f6>I5m009io5@2d;96c6<G;o26?h:;N0f=?4ai2E9ih4=e39L6``=:l=0C?h<:3g1?J4a<38n;6A=f981a7=H:o31>h94O3dg>7c53F8mi7<j7:M047<5m;1D?==52d58K66>2;o97B=?a;130>I48o09i?5@3029752<G:;<6>?<;N12e?56k2E8=l4<209L74g=;;<0C>?n:20a?J56i398<6A<1`8070=H;8l1?<=4O203>67?3F9987=>3:M060<4911D??753018K64f2:;37B==e;127>I4:o08=55@3219745<G:9?6>?7;N10<?56;2E8?44<199L76b=;890C>=j:23;?J53<39:?6A<44807c=H;=i1?964O26e>6363F9?j7=:6:M00c<4=k1D?8:535:8K6322:>o7B=:9;17<>I4=h088i5@34g971><G:?m6>:k;N156?5302E8:>4<4e9L731=;=20C>8j:24b?J50939<?6A<70803==H;>;1?:j4O252>6>53F9<=7=77:M033<4>h1D?:9537d8K61e2:<j7B=8c;15b>I40908:l5@393973`<G:2>6>8n;N1;2?51n2E84l4<6`9L7=d=;?l0C>6i:24b?J5>839=j6A<97802d=H;0=1?4?4O2;`>60f3F92h7=61:M0e7<4>h1D?l=53838K6g?2:<j7B=n9;1:5>I4il08:l5@3`d97<7<G:h?6>8n;N1a1?5>92E8nl4<6`9L7gd=;0;0C>m?:24b?J5d9392=6A<c7802d=H;j=1?4?4O2a`>60f3F9hh7=61:M0`7<4>h1D?i=53838K6b?2:<j7B=k9;1:5>I4ll08:l5@3ed97<7<G:o?6>8n;N1f1?5>92E8in4<e99L7``=;o;0C>ki:2d5?J5bn39mn6A<f580a==H;o?1?hj4O2d:>6c?3F9mm7=jd:M0b`<4m11D?kh53df8K1642:o37B:?4;1f`>I38h08i55@41`9053<G=;;6>k7;N625?27=2E?=;4<e99L041=<9?0C9?l:2g;?J26l3>;96A;2380a==H<;918=;4}AB |
/System09/trunk/rtl/System09_BurchED_B5-X300_2/_ngo/netlist.lst
0,0 → 1,2
C:\Vhdl\System09\rtl\System09_BurchED_B5-X300_2\system09.ngc 1220863442 |
OK |
/System09/trunk/rtl/System09_BurchED_B5-X300_2/work/acia_6850/rtl.psm
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System09/trunk/rtl/System09_BurchED_B5-X300_2/work/acia_6850/rtl.psm
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## -0,0 +1 ##
+application/octet-stream
\ No newline at end of property
Index: System09/trunk/rtl/System09_BurchED_B5-X300_2/work/acia_6850/rtl.dat
===================================================================
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Index: System09/trunk/rtl/System09_BurchED_B5-X300_2/work/acia_6850/rtl.dat
===================================================================
--- System09/trunk/rtl/System09_BurchED_B5-X300_2/work/acia_6850/rtl.dat (nonexistent)
+++ System09/trunk/rtl/System09_BurchED_B5-X300_2/work/acia_6850/rtl.dat (revision 104)
System09/trunk/rtl/System09_BurchED_B5-X300_2/work/acia_6850/rtl.dat
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Index: System09/trunk/rtl/System09_BurchED_B5-X300_2/work/acia_6850/_primary.dat
===================================================================
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Index: System09/trunk/rtl/System09_BurchED_B5-X300_2/work/acia_6850/_primary.dat
===================================================================
--- System09/trunk/rtl/System09_BurchED_B5-X300_2/work/acia_6850/_primary.dat (nonexistent)
+++ System09/trunk/rtl/System09_BurchED_B5-X300_2/work/acia_6850/_primary.dat (revision 104)
System09/trunk/rtl/System09_BurchED_B5-X300_2/work/acia_6850/_primary.dat
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Index: System09/trunk/rtl/System09_BurchED_B5-X300_2/work/acia_rx/rtl.psm
===================================================================
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Index: System09/trunk/rtl/System09_BurchED_B5-X300_2/work/acia_rx/rtl.psm
===================================================================
--- System09/trunk/rtl/System09_BurchED_B5-X300_2/work/acia_rx/rtl.psm (nonexistent)
+++ System09/trunk/rtl/System09_BurchED_B5-X300_2/work/acia_rx/rtl.psm (revision 104)
System09/trunk/rtl/System09_BurchED_B5-X300_2/work/acia_rx/rtl.psm
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+application/octet-stream
\ No newline at end of property
Index: System09/trunk/rtl/System09_BurchED_B5-X300_2/work/acia_rx/rtl.dat
===================================================================
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Index: System09/trunk/rtl/System09_BurchED_B5-X300_2/work/acia_rx/rtl.dat
===================================================================
--- System09/trunk/rtl/System09_BurchED_B5-X300_2/work/acia_rx/rtl.dat (nonexistent)
+++ System09/trunk/rtl/System09_BurchED_B5-X300_2/work/acia_rx/rtl.dat (revision 104)
System09/trunk/rtl/System09_BurchED_B5-X300_2/work/acia_rx/rtl.dat
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Index: System09/trunk/rtl/System09_BurchED_B5-X300_2/work/acia_rx/_primary.dat
===================================================================
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Index: System09/trunk/rtl/System09_BurchED_B5-X300_2/work/acia_rx/_primary.dat
===================================================================
--- System09/trunk/rtl/System09_BurchED_B5-X300_2/work/acia_rx/_primary.dat (nonexistent)
+++ System09/trunk/rtl/System09_BurchED_B5-X300_2/work/acia_rx/_primary.dat (revision 104)
System09/trunk/rtl/System09_BurchED_B5-X300_2/work/acia_rx/_primary.dat
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\ No newline at end of property
Index: System09/trunk/rtl/System09_BurchED_B5-X300_2/work/acia_tx/rtl.psm
===================================================================
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Index: System09/trunk/rtl/System09_BurchED_B5-X300_2/work/acia_tx/rtl.psm
===================================================================
--- System09/trunk/rtl/System09_BurchED_B5-X300_2/work/acia_tx/rtl.psm (nonexistent)
+++ System09/trunk/rtl/System09_BurchED_B5-X300_2/work/acia_tx/rtl.psm (revision 104)
System09/trunk/rtl/System09_BurchED_B5-X300_2/work/acia_tx/rtl.psm
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## -0,0 +1 ##
+application/octet-stream
\ No newline at end of property
Index: System09/trunk/rtl/System09_BurchED_B5-X300_2/work/acia_tx/rtl.dat
===================================================================
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Index: System09/trunk/rtl/System09_BurchED_B5-X300_2/work/acia_tx/rtl.dat
===================================================================
--- System09/trunk/rtl/System09_BurchED_B5-X300_2/work/acia_tx/rtl.dat (nonexistent)
+++ System09/trunk/rtl/System09_BurchED_B5-X300_2/work/acia_tx/rtl.dat (revision 104)
System09/trunk/rtl/System09_BurchED_B5-X300_2/work/acia_tx/rtl.dat
Property changes :
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## -0,0 +1 ##
+application/octet-stream
\ No newline at end of property
Index: System09/trunk/rtl/System09_BurchED_B5-X300_2/work/acia_tx/_primary.dat
===================================================================
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Index: System09/trunk/rtl/System09_BurchED_B5-X300_2/work/acia_tx/_primary.dat
===================================================================
--- System09/trunk/rtl/System09_BurchED_B5-X300_2/work/acia_tx/_primary.dat (nonexistent)
+++ System09/trunk/rtl/System09_BurchED_B5-X300_2/work/acia_tx/_primary.dat (revision 104)
System09/trunk/rtl/System09_BurchED_B5-X300_2/work/acia_tx/_primary.dat
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+application/octet-stream
\ No newline at end of property
Index: System09/trunk/rtl/System09_BurchED_B5-X300_2/work/_info
===================================================================
--- System09/trunk/rtl/System09_BurchED_B5-X300_2/work/_info (nonexistent)
+++ System09/trunk/rtl/System09_BurchED_B5-X300_2/work/_info (revision 104)
@@ -0,0 +1,119 @@
+m255
+13
+cModel Technology
+dG:\Vhdl\System09\rtl\System09_BurchED_B5-X300
+Eacia_6850
+w1170677056
+DP ieee numeric_std =NSdli^?T5OD8;4FD]V7GRb=PYXAhe35W6jP2
+OX;C;6.0a;29
+31
+o-93 -explicit -O0
+tExplicit 1GenerateLoopIterationMax 100000
+Artl
+DP ieee numeric_std =NSdli^?T5OD8;4FD]V7GRb=PYXAhe35W6jP2
+l180
+L81
+VgF9afi:]adM3
+OX;C;6.0a;29
+31
+o-93 -explicit -O0
+tExplicit 1GenerateLoopIterationMax 100000
+Artl
+DP ieee std_logic_arith GJbAT?7@hRQU9IQ702DT]2
+DP ieee std_logic_unsigned hEMVMlaNCR^3
+l81
+L63
+VLCRG_C=W9h^Tg<`lcm=Y?3
+OX;C;6.0a;29
+31
+M4 ieee std_logic_1164
+M3 ieee numeric_std
+M2 ieee std_logic_unsigned
+M1 ieee std_logic_arith
+o-93 -explicit -O0
+tExplicit 1GenerateLoopIterationMax 100000
Index: System09/trunk/rtl/System09_BurchED_B5-X300_2/work/acia_6850_testbench/behavior.dat
===================================================================
Cannot display: file marked as a binary type.
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Index: System09/trunk/rtl/System09_BurchED_B5-X300_2/work/acia_6850_testbench/behavior.dat
===================================================================
--- System09/trunk/rtl/System09_BurchED_B5-X300_2/work/acia_6850_testbench/behavior.dat (nonexistent)
+++ System09/trunk/rtl/System09_BurchED_B5-X300_2/work/acia_6850_testbench/behavior.dat (revision 104)
System09/trunk/rtl/System09_BurchED_B5-X300_2/work/acia_6850_testbench/behavior.dat
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Index: System09/trunk/rtl/System09_BurchED_B5-X300_2/work/acia_6850_testbench/_primary.dat
===================================================================
Cannot display: file marked as a binary type.
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Index: System09/trunk/rtl/System09_BurchED_B5-X300_2/work/acia_6850_testbench/_primary.dat
===================================================================
--- System09/trunk/rtl/System09_BurchED_B5-X300_2/work/acia_6850_testbench/_primary.dat (nonexistent)
+++ System09/trunk/rtl/System09_BurchED_B5-X300_2/work/acia_6850_testbench/_primary.dat (revision 104)
System09/trunk/rtl/System09_BurchED_B5-X300_2/work/acia_6850_testbench/_primary.dat
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Index: System09/trunk/rtl/System09_BurchED_B5-X300_2/work/acia_6850_testbench/behavior.psm
===================================================================
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Index: System09/trunk/rtl/System09_BurchED_B5-X300_2/work/acia_6850_testbench/behavior.psm
===================================================================
--- System09/trunk/rtl/System09_BurchED_B5-X300_2/work/acia_6850_testbench/behavior.psm (nonexistent)
+++ System09/trunk/rtl/System09_BurchED_B5-X300_2/work/acia_6850_testbench/behavior.psm (revision 104)
System09/trunk/rtl/System09_BurchED_B5-X300_2/work/acia_6850_testbench/behavior.psm
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Index: System09/trunk/rtl/System09_BurchED_B5-X300_2/System09_BurchED_B5-X300.ucf
===================================================================
--- System09/trunk/rtl/System09_BurchED_B5-X300_2/System09_BurchED_B5-X300.ucf (nonexistent)
+++ System09/trunk/rtl/System09_BurchED_B5-X300_2/System09_BurchED_B5-X300.ucf (revision 104)
@@ -0,0 +1,240 @@
+#### UCF file created by Project Navigator
+#
+NET "reset_n" LOC = "p57" ;
+NET "sysclk" LOC = "p77" ;
+#
+# Connector A
+# For modified B3-SRAM
+#
+NET "ram1_addr<0>" LOC = "P3" ; #J1-2 (I/O - not a global clock input)
+NET "ram1_addr<1>" LOC = "P4" ; #J1-3
+NET "ram1_addr<2>" LOC = "P5" ; #J1-4
+NET "ram1_addr<3>" LOC = "P6" ; #J1-5
+NET "ram1_addr<4>" LOC = "P7" ; #J1-6
+NET "ram1_addr<5>" LOC = "P8" ; #J1-7
+NET "ram1_addr<6>" LOC = "P9" ; #J1-8
+NET "ram1_addr<7>" LOC = "P10"; #J1-9
+NET "ram1_csn" LOC = "P11"; #J1-10
+NET "ram1_addr<8>" LOC = "P15"; #J1-11
+NET "ram1_addr<9>" LOC = "P16"; #J1-12
+NET "ram1_addr<10>" LOC = "P17"; #J1-13
+NET "ram1_addr<11>" LOC = "P18"; #J1-14
+NET "ram1_addr<12>" LOC = "P20"; #J1-15
+NET "ram1_addr<13>" LOC = "P21"; #J1-16
+NET "ram1_addr<14>" LOC = "P22"; #J1-17
+NET "ram1_addr<15>" LOC = "P23"; #J1-18
+NET "ram1_addr<16>" LOC = "P24"; #J1-19
+#
+# Connector B
+# For modified B3-SRAM
+#
+NET "ram1_data<0>" LOC = "P27"; #J2-2 (I/O - not a global clock input)
+NET "ram1_data<1>" LOC = "P29"; #J2-3
+NET "ram1_data<2>" LOC = "P30"; #J2-4
+NET "ram1_data<3>" LOC = "P31"; #J2-5
+NET "ram1_data<4>" LOC = "P33"; #J2-6
+NET "ram1_data<5>" LOC = "P34"; #J2-7
+NET "ram1_data<6>" LOC = "P35"; #J2-8
+NET "ram1_data<7>" LOC = "P36"; #J2-9
+NET "ram1_data<8>" LOC = "P40"; #J2-10
+NET "ram1_data<9>" LOC = "P41"; #J2-11
+NET "ram1_data<10>" LOC = "P42"; #J2-12
+NET "ram1_data<11>" LOC = "P43"; #J2-13
+NET "ram1_data<12>" LOC = "P44"; #J2-14
+NET "ram1_data<13>" LOC = "P45"; #J2-15
+NET "ram1_data<14>" LOC = "P46"; #J2-16
+NET "ram1_data<15>" LOC = "P47"; #J2-17
+NET "ram1_wrun" LOC = "P48"; #J2-18
+NET "ram1_wrln" LOC = "P49"; #J2-19
+#
+# Connector C
+# For B5-Peripheral-Connectors
+#
+NET "vga0_vs" LOC = "p55" ; #pin 3
+NET "vga0_hs" LOC = "p56" ; #pin 4
+NET "vga0_blue<0>" LOC = "p58" ; #pin 5
+NET "vga0_blue<1>" LOC = "p59" ; #pin 6
+NET "vga0_green<0>" LOC = "p60" ; #pin 7
+NET "vga0_green<1>" LOC = "p61" ; #pin 8
+NET "vga0_red<0>" LOC = "p62" ; #pin 9
+NET "vga0_red<1>" LOC = "p63" ; #pin 10
+NET "kb0_clock" LOC = "p64" ; #pin 11
+NET "kb0_data" LOC = "p68" ; #pin 12
+#NET "mouse0_clock" LOC = "p69" ; #pin 13
+#NET "mouse0_data" LOC = "p70" ; #pin 14
+#NET "buzzer0" LOC = "p71" ; #pin 15
+NET "uart0_cts_n" LOC = "p73" ; #pin 16
+NET "uart0_rxd" LOC = "p74" ; #pin 17
+NET "uart0_txd" LOC = "p75" ; #pin 18
+NET "uart0_rts_n" LOC = "p81" ; #pin 19
+#
+# Connector D
+# B3-FPGA-CPU-IO Module
+#
+#NET "aux1_clk" LOC = "P80" ; #J1-2
+#NET "buzzer1" LOC = "P82" ; #J1-3
+NET "led" LOC = "p82" ; #J1-3
+#NET "mouse1_clock" LOC = "P83" ; #J1-4
+#NET "mouse1_data" LOC = "P84" ; #J1-5
+NET "uart1_cts_n" LOC = "P86" ; #J1-6
+NET "uart1_rts_n" LOC = "P87" ; #J1-7
+NET "uart1_txd" LOC = "P88" ; #J1-8
+NET "uart1_rxd" LOC = "P89" ; #J1-9
+#NET "kb1_clock" LOC = "P93" ; #J1-10
+#NET "kb1_data" LOC = "P94" ; #J1-11
+#NET "vga1_vs" LOC = "P95" ; #J1-12
+#NET "vga1_hs" LOC = "P96" ; #J1-13
+#NET "vga1_blue<0>" LOC = "P97" ; #J1-14
+#NET "vga1_blue<1>" LOC = "P98" ; #J1-15
+#NET "vga1_green<0>" LOC = "P99" ; #J1-16
+#NET "vga1_green<1>" LOC = "P100"; #J1-17
+#NET "vga1_red<0>" LOC = "P101"; #J1-18
+#NET "vga1_red<1>" LOC = "P102"; #J1-19
+#
+# Connector E
+# For B5-SRAM
+#
+NET "ram0_csn" LOC = "p108"; #J1.2
+NET "ram0_addr<16>" LOC = "p109"; #J1.3
+NET "ram0_addr<15>" LOC = "p110"; #J1.4
+NET "ram0_addr<14>" LOC = "p111"; #J1.5
+NET "ram0_addr<13>" LOC = "p112"; #J1.6
+NET "ram0_addr<12>" LOC = "p113"; #J1.7
+NET "ram0_addr<11>" LOC = "p114"; #J1.8
+NET "ram0_addr<10>" LOC = "p115"; #J1.9
+NET "ram0_addr<9>" LOC = "p116"; #J1.10
+NET "ram0_addr<8>" LOC = "p120"; #J1.11
+NET "ram0_addr<7>" LOC = "p121"; #J1.12
+NET "ram0_addr<6>" LOC = "p122"; #J1.13
+NET "ram0_addr<5>" LOC = "p123"; #J1.14
+NET "ram0_addr<4>" LOC = "p125"; #J1.15
+NET "ram0_addr<3>" LOC = "p126"; #J1.16
+NET "ram0_addr<2>" LOC = "p127"; #J1.17
+NET "ram0_addr<1>" LOC = "p129"; #J1.18
+NET "ram0_addr<0>" LOC = "p132"; #J1.19
+#
+# Connector F
+# For B5-SRAM
+#
+NET "ram0_wrun" LOC = "p133"; #J2.2
+NET "ram0_wrln" LOC = "p134"; #J2.3
+NET "ram0_data<15>" LOC = "p135"; #J2.4
+NET "ram0_data<14>" LOC = "p136"; #J2.5
+NET "ram0_data<13>" LOC = "p138"; #J2.6
+NET "ram0_data<12>" LOC = "p139"; #J2.7
+NET "ram0_data<11>" LOC = "p140"; #J2.8
+NET "ram0_data<10>" LOC = "p141"; #J2.9
+NET "ram0_data<9>" LOC = "p145"; #J2.10
+NET "ram0_data<8>" LOC = "p146"; #J2.11
+NET "ram0_data<7>" LOC = "p147"; #J2.12
+NET "ram0_data<6>" LOC = "p148"; #J2.13
+NET "ram0_data<5>" LOC = "p149"; #J2.14
+NET "ram0_data<4>" LOC = "p150"; #J2.15
+NET "ram0_data<3>" LOC = "p151"; #J2.16
+NET "ram0_data<2>" LOC = "p152"; #J2.17
+NET "ram0_data<1>" LOC = "p153"; #J2.18
+NET "ram0_data<0>" LOC = "p154"; #J2.19
+#
+# Connector G
+# For B5-Compact-Flash:
+#
+#NET "pin2" LOC = "P182" ; #J1-2 (clk input)
+#NET "pin3" LOC = "P160" ; #J1-3
+#NET "cf_intrq" LOC = "P161" ; #J1-4
+NET "cf_wr_n" LOC = "P162" ; #J1-5
+NET "cf_rd_n" LOC = "P163" ; #J1-6
+NET "cf_cs1_n" LOC = "P164" ; #J1-7
+NET "cf_d<15>" LOC = "P165" ; #J1-8
+NET "cf_d<14>" LOC = "P166" ; #J1-9
+NET "cf_d<13>" LOC = "P167" ; #J1-10
+NET "cf_d<12>" LOC = "P168" ; #J1-11
+NET "cf_d<11>" LOC = "P169" ; #J1-12
+#NET "cf_present" LOC = "P173" ; #J1-13
+NET "cf_d<3>" LOC = "P174" ; #J1-14
+NET "cf_d<4>" LOC = "P175" ; #J1-15
+NET "cf_d<5>" LOC = "P176" ; #J1-16
+NET "cf_d<6>" LOC = "P178" ; #J1-17
+NET "cf_d<7>" LOC = "P179" ; #J1-18
+NET "cf_cs0_n" LOC = "P180" ; #J1-19
+#
+# Connector H
+# For B5-Compact-Flash:
+#
+#NET "pin2" LOC = "p185"; #J2-2 (clk input)
+#NET "pin3" LOC = "p181"; #J2-3
+#NET "pin4" LOC = "p187"; #J2-4
+#NET "pin5" LOC = "p188"; #J2-5
+NET "cf_a<2>" LOC = "P189"; #J2-6
+NET "cf_a<1>" LOC = "P191"; #J2-7
+NET "cf_a<0>" LOC = "P192"; #J2-8
+NET "cf_d<0>" LOC = "P193"; #J2-9
+NET "cf_d<1>" LOC = "P194"; #J2-10
+NET "cf_d<2>" LOC = "P198"; #J2-11
+#NET "cf_cs16_n" LOC = "P199"; #J2-12
+NET "cf_d<10>" LOC = "P200"; #J2-13
+NET "cf_d<9>" LOC = "P201"; #J2-14
+NET "cf_d<8>" LOC = "P202"; #J2-15
+#NET "cf_pdiag" LOC = "P203"; #J2-16
+#NET "cf_dase" LOC = "P204"; #J2-17
+#NET "cf_iordy" LOC = "P205"; #J2-18
+NET "cf_rst_n" LOC = "P206"; #J2-19
+#
+# Timing Groups
+#
+INST "ram0_addr<0>" TNM = "gram0_addr";
+INST "ram0_addr<1>" TNM = "gram0_addr";
+INST "ram0_addr<2>" TNM = "gram0_addr";
+INST "ram0_addr<3>" TNM = "gram0_addr";
+INST "ram0_addr<4>" TNM = "gram0_addr";
+INST "ram0_addr<5>" TNM = "gram0_addr";
+INST "ram0_addr<6>" TNM = "gram0_addr";
+INST "ram0_addr<7>" TNM = "gram0_addr";
+INST "ram0_addr<8>" TNM = "gram0_addr";
+INST "ram0_addr<9>" TNM = "gram0_addr";
+INST "ram0_addr<10>" TNM = "gram0_addr";
+INST "ram0_addr<11>" TNM = "gram0_addr";
+INST "ram0_addr<12>" TNM = "gram0_addr";
+INST "ram0_addr<13>" TNM = "gram0_addr";
+INST "ram0_addr<14>" TNM = "gram0_addr";
+INST "ram0_addr<15>" TNM = "gram0_addr";
+INST "ram0_addr<16>" TNM = "gram0_addr";
+INST "ram0_data<0>" TNM = "gram0_data";
+INST "ram0_data<1>" TNM = "gram0_data";
+INST "ram0_data<2>" TNM = "gram0_data";
+INST "ram0_data<3>" TNM = "gram0_data";
+INST "ram0_data<4>" TNM = "gram0_data";
+INST "ram0_data<5>" TNM = "gram0_data";
+INST "ram0_data<6>" TNM = "gram0_data";
+INST "ram0_data<7>" TNM = "gram0_data";
+INST "ram0_data<8>" TNM = "gram0_data";
+INST "ram0_data<9>" TNM = "gram0_data";
+INST "ram0_data<10>" TNM = "gram0_data";
+INST "ram0_data<11>" TNM = "gram0_data";
+INST "ram0_data<12>" TNM = "gram0_data";
+INST "ram0_data<13>" TNM = "gram0_data";
+INST "ram0_data<14>" TNM = "gram0_data";
+INST "ram0_data<15>" TNM = "gram0_data";
+INST "ram0_wrln" TNM = "gram0_wr";
+INST "ram0_wrun" TNM = "gram0_wr";
+INST "ram0_csn" TNM = "gram0_cs";
+#
+# Timing Constraints
+#
+#TIMEGRP "gram0_cs" OFFSET = OUT 40 ns AFTER "sysclk";
+#TIMEGRP "gram0_wr" OFFSET = OUT 40 ns AFTER "sysclk";
+#TIMEGRP "gram0_addr" OFFSET = OUT 40 ns AFTER "sysclk";
+#TIMEGRP "gram0_data" OFFSET = OUT 40 ns AFTER "sysclk";
+#TIMEGRP "gram0_data" OFFSET = IN 15 ns BEFORE "sysclk";
+#TIMEGRP "gtest_alu" OFFSET = OUT 90 ns AFTER "sysclk";
+#TIMEGRP "gtest_cc" OFFSET = OUT 95 ns AFTER "sysclk";
+NET "sysclk" TNM_NET = "sysclk";
+TIMESPEC "TS_sysclk" = PERIOD "sysclk" 20 ns LOW 50 %;
+#
+# Fast I/O Pins
+#
+NET "ram0_csn" FAST;
+NET "ram0_wrln" FAST;
+NET "ram0_wrun" FAST;
+NET "ram1_csn" FAST;
+NET "ram1_wrln" FAST;
+NET "ram1_wrun" FAST;
Index: System09/trunk/rtl/System09_BurchED_B5-X300_2/System09_BurchED_B5-X300.ipf
===================================================================
--- System09/trunk/rtl/System09_BurchED_B5-X300_2/System09_BurchED_B5-X300.ipf (nonexistent)
+++ System09/trunk/rtl/System09_BurchED_B5-X300_2/System09_BurchED_B5-X300.ipf (revision 104)
@@ -0,0 +1,32 @@
+JedecChain;
+FileRevision(JESDxxA);
+/* NoviceMode */
+/* Active Mode BS */
+/* Mode BS */
+ P ActionCode(Cfg)
+ Device
+ PartName(xc18v02)
+ File("C:\Vhdl\System09\rtl\System09_BurchED_B5-X300_2\sys09_B5-X300_2.mcs")
+ ;
+/* Mode SS */
+/* Mode SM */
+/* Mode BSFILE */
+/* Mode HW140 */
+/* Supermode FileMode */
+/* ConfigDevice PFF "xc18v02" 0 0 */
+/* PromDevice "xc18v02" 262144 */
+/* Serial */
+/* ConfigDevicePath ("C:\vhdl\system09\rtl\System09_BurchED_B5-X300_2/") */
+/* Format mcs */
+/* FillValue FF */
+/* BitSwap FALSE */
+/* LoadDirection UP */
+/* Collection "sys09_B5-X300_2" */
+/* Version 0 "0" */
+/* ConcurrentChain 0 */
+ P ActionCode(Cfg)
+ Device
+ PartName(xc2s300e)
+ File("C:\Vhdl\System09\rtl\System09_BurchED_B5-X300_2\system09.bit")
+ ;
+ChainEnd;
Index: System09/trunk/rtl/System09_BurchED_B5-X300_2/automake.log
===================================================================
Index: System09/trunk/rtl/System09_BurchED_B5-X300_2/System09_BurchED_B5-X300.ise
===================================================================
Cannot display: file marked as a binary type.
svn:mime-type = application/octet-stream
Index: System09/trunk/rtl/System09_BurchED_B5-X300_2/System09_BurchED_B5-X300.ise
===================================================================
--- System09/trunk/rtl/System09_BurchED_B5-X300_2/System09_BurchED_B5-X300.ise (nonexistent)
+++ System09/trunk/rtl/System09_BurchED_B5-X300_2/System09_BurchED_B5-X300.ise (revision 104)
System09/trunk/rtl/System09_BurchED_B5-X300_2/System09_BurchED_B5-X300.ise
Property changes :
Added: svn:mime-type
## -0,0 +1 ##
+application/octet-stream
\ No newline at end of property
Index: System09/trunk/rtl/System09_BurchED_B5-X300_2/System09_BurchED_B5-X300.vhd
===================================================================
--- System09/trunk/rtl/System09_BurchED_B5-X300_2/System09_BurchED_B5-X300.vhd (nonexistent)
+++ System09/trunk/rtl/System09_BurchED_B5-X300_2/System09_BurchED_B5-X300.vhd (revision 104)
@@ -0,0 +1,1069 @@
+--===========================================================================----
+--
+-- S Y N T H E Z I A B L E System09 - SOC.
+--
+--===========================================================================----
+--
+-- This core adheres to the GNU public license
+--
+-- File name : System09_BurchED_B5-X300.vhd
+--
+-- Purpose : Top level file for 6809 compatible system on a chip
+-- Designed with Xilinx XC2S300e Spartan 2E FPGA.
+-- Implemented With BurchED B5-X300 FPGA board,
+-- B5-SRAM module, B5-CF module and B5-FPGA-CPU-IO module
+--
+-- Dependencies : ieee.Std_Logic_1164
+-- ieee.std_logic_unsigned
+-- ieee.std_logic_arith
+-- ieee.numeric_std
+--
+-- Uses :
+-- cpu09 (cpu09.vhd) CPU core
+-- mon_rom (sys09bug_rom2k_b4.vhd) Monitor ROM
+-- dat_ram (datram.vhd) Dynamic Address Translation
+-- acia_6850 (ACIA_6850.vhd) ACIA / MiniUART
+-- (ACIA_RX.vhd)
+-- (ACIA_TX.vhd)
+-- ACIA_Clock (ACIA_Clock.vhd) ACIA Baud Clock Divider
+-- keyboard (keyboard.vhd) PS/2 Keyboard Interface
+-- vdu8 (vdu8.vhd) 80 x 25 Video Display
+-- timer (timer.vhd) Timer module
+-- trap (trap.vhd) Bus Trap interrupt
+-- uart1 (uart1.vhd) Parallel I/O port.
+--
+-- Author : John E. Kent
+-- dilbert57@opencores.org
+-- Memory Map :
+-- $E000 - ACIA (SWTPc)
+-- $E010 - Reserved for FD1771 FDC (SWTPc)
+-- $E020 - Keyboard
+-- $E030 - VDU
+-- $E040 - Compact Flash
+-- $E050 - Timer
+-- $E060 - Bus trap
+-- $E070 - Parallel I/O
+-- $E080 - Reserved for 6821 PIA (?) (SWTPc)
+-- $E090 - Reserved for 6840 PTM (?) (SWTPc)
+--
+--===========================================================================----
+--
+-- Revision History:
+--===========================================================================--
+-- Version 0.1 - 20 March 2003
+-- Version 0.2 - 30 March 2003
+-- Version 0.3 - 29 April 2003
+-- Version 0.4 - 29 June 2003
+--
+-- Version 0.5 - 19 July 2003
+-- prints out "Hello World"
+--
+-- Version 0.6 - 5 September 2003
+-- Runs SBUG
+--
+-- Version 1.0- 6 Sep 2003 - John Kent
+-- Inverted SysClk
+-- Initial release to Open Cores
+--
+-- Version 1.1 - 17 Jan 2004 - John Kent
+-- Updated miniUart.
+--
+-- Version 1.2 - 25 Jan 2004 - John Kent
+-- removed signals "test_alu" and "test_cc"
+-- Trap hardware re-instated.
+--
+-- Version 1.3 - 11 Feb 2004 - John Kent
+-- Designed forked off to produce System09_VDU
+-- Added VDU component
+-- VDU runs at 25MHz and divides the clock by 2 for the CPU
+-- UART Runs at 57.6 Kbps
+--
+-- Version 1.4 - 21 Nov 2004 - John Kent
+-- Changes to make compatible with Spartan3 starter kit version
+-- Designed to run with a 50MHz clock input.
+-- the VDU divides 50 MHz to generate a
+-- 25 MHz VDU Pixel Clock and a 12.5 MHz CPU clock
+-- Changed Monitor ROM signals to make it look like
+-- a standard 2K memory block
+-- Re-assigned I/O port assignments so it is possible to run KBUG9
+-- $E000 - ACIA
+-- $E010 - Keyboard
+-- $E020 - VDU
+-- $E030 - Compact Flash
+-- $E040 - Timer
+-- $E050 - Bus trap
+-- $E060 - Parallel I/O
+--
+-- Version 1.5 - 3rd February 2007 - John Kent
+-- Changed VDU8 to use external clock divider
+-- renamed miniUART to ACIA_6850
+-- Memory decoding of ROM & IO now uses DAT
+--
+-- Version 1.6 - 7th Februaury 2007 - John Kent
+-- Made ACIA Clock generator an external component
+-- Added Generics to VDU and Keyboard
+-- Changed decoding
+--
+-- Version 1.7 - 20th May 2007 - John Kent
+-- Added 4 wait states to CF access
+-- Removed DAT memory map control of ROM & IO
+-- to allow for full use of RAM as a RAM disk.
+-- Mapped in all 16 bits of the CF data bus.
+--
+--===========================================================================
+--
+library ieee;
+ use ieee.std_logic_1164.all;
+ use IEEE.STD_LOGIC_ARITH.ALL;
+ use IEEE.STD_LOGIC_UNSIGNED.ALL;
+ use ieee.numeric_std.all;
+library unisim;
+ use unisim.vcomponents.all;
+
+entity System09 is
+ port(
+ SysClk : in Std_Logic; -- System Clock input
+ Reset_n : in Std_logic; -- Master Reset input (active low)
+ LED : out std_logic; -- Diagnostic LED Flasher
+
+ -- Memory Interface signals
+ -- B5-SRAM
+ ram0_csn : out Std_Logic;
+ ram0_wrln : out Std_Logic;
+ ram0_wrun : out Std_Logic;
+ ram0_addr : out Std_Logic_Vector(16 downto 0);
+ ram0_data : inout Std_Logic_Vector(15 downto 0);
+
+ -- Memory Interface signals
+ -- B3-SRAM
+ ram1_csn : out Std_Logic;
+ ram1_wrln : out Std_Logic;
+ ram1_wrun : out Std_Logic;
+ ram1_addr : out Std_Logic_Vector(16 downto 0);
+ ram1_data : inout Std_Logic_Vector(15 downto 0);
+
+ -- B5 Peripheral IO Board
+
+ -- PS/2 Keyboard
+ kb0_clock : inout Std_logic;
+ kb0_data : inout Std_Logic;
+
+ -- PS/2 Mouse interface
+-- mouse0_clock : in Std_Logic;
+-- mouse0_data : in Std_Logic;
+
+ -- Uart Interface
+ uart0_rxd : in Std_Logic;
+ uart0_txd : out Std_Logic;
+ uart0_rts_n : out Std_Logic;
+ uart0_cts_n : in Std_Logic;
+
+ -- CRTC output signals
+ vga0_vs : out Std_Logic;
+ vga0_hs : out Std_Logic;
+ vga0_blue : out std_logic_vector(1 downto 0);
+ vga0_green : out std_logic_vector(1 downto 0);
+ vga0_red : out std_logic_vector(1 downto 0);
+
+ -- Buzzer
+-- buzzer0 : out std_logic;
+
+ -- B3 Peripheral Connect Board
+
+ -- PS/2 Keyboard
+-- kb1_clock : inout Std_logic;
+-- kb1_data : inout Std_Logic;
+
+ -- PS/2 Mouse interface
+-- mouse0_clock : in Std_Logic;
+-- mouse0_data : in Std_Logic;
+
+ -- Uart Interface
+ uart1_rxd : in Std_Logic;
+ uart1_txd : out Std_Logic;
+ uart1_rts_n : out Std_Logic;
+ uart1_cts_n : in Std_Logic;
+
+ -- CRTC output signals
+-- vga1_vs : out Std_Logic;
+-- vga1_hs : out Std_Logic;
+-- vga1_blue : out std_logic_vector(1 downto 0);
+-- vga1_green : out std_logic_vector(1 downto 0);
+-- vga1_red : out std_logic_vector(1 downto 0);
+
+ -- Buzzer
+-- buzzer1 : out std_logic;
+
+ -- Compact Flash
+ cf_rst_n : out std_logic;
+ cf_cs0_n : out std_logic;
+ cf_cs1_n : out std_logic;
+ cf_rd_n : out std_logic;
+ cf_wr_n : out std_logic;
+ cf_a : out std_logic_vector(2 downto 0);
+ cf_d : inout std_logic_vector(15 downto 0)
+ );
+end System09;
+
+-------------------------------------------------------------------------------
+-- Architecture for System09
+-------------------------------------------------------------------------------
+architecture rtl of System09 is
+ -----------------------------------------------------------------------------
+ -- constants
+ -----------------------------------------------------------------------------
+ constant SYS_CLK_FREQ : integer := 50000000; -- FPGA System Clock
+ constant VGA_CLK_FREQ : integer := 25000000; -- VGA Pixel Clock
+ constant CPU_CLK_FREQ : integer := 12500000; -- CPU Clock
+ constant BAUD0_RATE : integer := 57600; -- Baud Rate
+ constant BAUD1_RATE : integer := 57600; -- Baud Rate
+ constant ACIA0_CLK_FREQ : integer := BAUD0_RATE * 16;
+ constant ACIA1_CLK_FREQ : integer := BAUD1_RATE * 16;
+
+ type hold_state_type is ( hold_release_state, hold_request_state );
+
+ -----------------------------------------------------------------------------
+ -- Signals
+ -----------------------------------------------------------------------------
+ -- Monitor ROM
+ signal rom_data_out : Std_Logic_Vector(7 downto 0);
+ signal rom_cs : std_logic;
+
+ -- UART Interface signals
+ signal uart0_data_out : Std_Logic_Vector(7 downto 0);
+ signal uart0_cs : Std_Logic;
+ signal uart0_irq : Std_Logic;
+ signal uart0_clk : Std_Logic;
+ signal uart0_dcd_n : Std_Logic;
+
+ -- UART Interface signals
+ signal uart1_data_out : Std_Logic_Vector(7 downto 0);
+ signal uart1_cs : Std_Logic;
+ signal uart1_irq : Std_Logic;
+ signal uart1_clk : Std_Logic;
+ signal uart1_dcd_n : Std_Logic;
+
+ -- timer
+ signal timer_data_out : std_logic_vector(7 downto 0);
+ signal timer_cs : std_logic;
+ signal timer_irq : std_logic;
+
+ -- trap
+ signal trap_cs : std_logic;
+ signal trap_data_out : std_logic_vector(7 downto 0);
+ signal trap_irq : std_logic;
+
+ -- compact flash port
+ signal cf_data_out : std_logic_vector(7 downto 0);
+ signal cf_cs : std_logic;
+ signal cf_rd : std_logic;
+ signal cf_wr : std_logic;
+ signal cf_hold : std_logic;
+ signal cf_release : std_logic;
+ signal cf_count : std_logic_vector(3 downto 0);
+ signal cf_hold_state : hold_state_type;
+
+ -- keyboard port
+ signal keyboard_data_out : std_logic_vector(7 downto 0);
+ signal keyboard_cs : std_logic;
+ signal keyboard_irq : std_logic;
+
+ -- B5 RAM
+ signal ram0_cs : std_logic; -- memory chip select
+ signal ram0_wrl : std_logic; -- memory write lower
+ signal ram0_wru : std_logic; -- memory write upper
+ signal ram0_data_out : std_logic_vector(7 downto 0);
+
+ -- B3 RAM
+ signal ram1_cs : std_logic; -- memory chip select
+ signal ram1_wrl : std_logic; -- memory write lower
+ signal ram1_wru : std_logic; -- memory write upper
+ signal ram1_data_out : std_logic_vector(7 downto 0);
+
+ -- CPU Interface signals
+ signal cpu_reset : Std_Logic;
+ signal cpu_clk : Std_Logic;
+ signal cpu_rw : std_logic;
+ signal cpu_vma : std_logic;
+ signal cpu_halt : std_logic;
+ signal cpu_hold : std_logic;
+ signal cpu_firq : std_logic;
+ signal cpu_irq : std_logic;
+ signal cpu_nmi : std_logic;
+ signal cpu_addr : std_logic_vector(15 downto 0);
+ signal cpu_data_in : std_logic_vector(7 downto 0);
+ signal cpu_data_out : std_logic_vector(7 downto 0);
+
+ -- Dynamic address translation
+ signal dat_cs : std_logic;
+ signal dat_addr : std_logic_vector(7 downto 0);
+
+ -- Video Display Unit
+ signal vga_clk : std_logic;
+ signal vdu_cs : std_logic;
+ signal vdu_data_out : std_logic_vector(7 downto 0);
+ signal vga_red : std_logic;
+ signal vga_green : std_logic;
+ signal vga_blue : std_logic;
+
+ -- Flashing Led test signals
+ signal countL : std_logic_vector(23 downto 0);
+ signal clock_div : std_logic_vector(1 downto 0);
+
+-----------------------------------------------------------------
+--
+-- CPU09 CPU core
+--
+-----------------------------------------------------------------
+
+component cpu09
+ port (
+ clk: in std_logic;
+ rst: in std_logic;
+ rw: out std_logic; -- Asynchronous memory interface
+ vma: out std_logic;
+ address: out std_logic_vector(15 downto 0);
+ data_in: in std_logic_vector(7 downto 0);
+ data_out: out std_logic_vector(7 downto 0);
+ halt: in std_logic;
+ hold: in std_logic;
+ irq: in std_logic;
+ nmi: in std_logic;
+ firq: in std_logic
+ );
+end component;
+
+
+----------------------------------------
+--
+-- SBUG Block RAM Monitor ROM
+--
+----------------------------------------
+component mon_rom
+ port (
+ clk : in std_logic;
+ rst : in std_logic;
+ cs : in std_logic;
+ rw : in std_logic;
+ addr : in std_logic_vector (10 downto 0);
+ wdata : in std_logic_vector (7 downto 0);
+ rdata : out std_logic_vector (7 downto 0)
+ );
+end component;
+
+
+----------------------------------------
+--
+-- Dynamic Address Translation Registers
+--
+----------------------------------------
+component dat_ram
+ port (
+ clk: in std_logic;
+ rst: in std_logic;
+ cs: in std_logic;
+ rw: in std_logic;
+ addr_lo: in std_logic_vector(3 downto 0);
+ addr_hi: in std_logic_vector(3 downto 0);
+ data_in: in std_logic_vector(7 downto 0);
+ data_out: out std_logic_vector(7 downto 0)
+ );
+end component;
+
+-----------------------------------------------------------------
+--
+-- 6850 ACIA/UART
+--
+-----------------------------------------------------------------
+
+component ACIA_6850
+ port (
+ clk : in Std_Logic; -- System Clock
+ rst : in Std_Logic; -- Reset input (active high)
+ cs : in Std_Logic; -- miniUART Chip Select
+ rw : in Std_Logic; -- Read / Not Write
+ irq : out Std_Logic; -- Interrupt
+ Addr : in Std_Logic; -- Register Select
+ DataIn : in Std_Logic_Vector(7 downto 0); -- Data Bus In
+ DataOut : out Std_Logic_Vector(7 downto 0); -- Data Bus Out
+ RxC : in Std_Logic; -- Receive Baud Clock
+ TxC : in Std_Logic; -- Transmit Baud Clock
+ RxD : in Std_Logic; -- Receive Data
+ TxD : out Std_Logic; -- Transmit Data
+ DCD_n : in Std_Logic; -- Data Carrier Detect
+ CTS_n : in Std_Logic; -- Clear To Send
+ RTS_n : out Std_Logic ); -- Request To send
+end component;
+
+-----------------------------------------------------------------
+--
+-- ACIA Clock divider
+--
+-----------------------------------------------------------------
+
+component ACIA_Clock
+ generic (
+ SYS_CLK_FREQ : integer := SYS_CLK_FREQ;
+ ACIA_CLK_FREQ : integer
+ );
+ port (
+ clk : in Std_Logic; -- System Clock Input
+ ACIA_clk : out Std_logic -- ACIA Clock output
+ );
+end component;
+
+----------------------------------------
+--
+-- Timer module
+--
+----------------------------------------
+
+component timer
+ port (
+ clk : in std_logic;
+ rst : in std_logic;
+ cs : in std_logic;
+ rw : in std_logic;
+ addr : in std_logic;
+ data_in : in std_logic_vector(7 downto 0);
+ data_out : out std_logic_vector(7 downto 0);
+ irq : out std_logic
+ );
+end component;
+
+------------------------------------------------------------
+--
+-- Bus Trap logic
+--
+------------------------------------------------------------
+
+component trap
+ port (
+ clk : in std_logic;
+ rst : in std_logic;
+ cs : in std_logic;
+ rw : in std_logic;
+ vma : in std_logic;
+ addr : in std_logic_vector(15 downto 0);
+ data_in : in std_logic_vector(7 downto 0);
+ data_out : out std_logic_vector(7 downto 0);
+ irq : out std_logic
+ );
+end component;
+
+----------------------------------------
+--
+-- PS/2 Keyboard
+--
+----------------------------------------
+
+component keyboard
+ generic(
+ KBD_CLK_FREQ : integer := CPU_CLK_FREQ
+ );
+ port(
+ clk : in std_logic;
+ rst : in std_logic;
+ cs : in std_logic;
+ rw : in std_logic;
+ addr : in std_logic;
+ data_in : in std_logic_vector(7 downto 0);
+ data_out : out std_logic_vector(7 downto 0);
+ irq : out std_logic;
+ kbd_clk : inout std_logic;
+ kbd_data : inout std_logic
+ );
+end component;
+
+----------------------------------------
+--
+-- Video Display Unit.
+--
+----------------------------------------
+component vdu8
+ generic(
+ VGA_CLK_FREQ : integer := VGA_CLK_FREQ; -- 25MHz
+ VGA_HOR_CHARS : integer := 80; -- CHARACTERS 25.6us
+ VGA_HOR_CHAR_PIXELS : integer := 8; -- PIXELS 0.32us
+ VGA_HOR_FRONT_PORCH : integer := 16; -- PIXELS 0.64us (0.94us)
+ VGA_HOR_SYNC : integer := 96; -- PIXELS 3.84us (3.77us)
+ VGA_HOR_BACK_PORCH : integer := 48; -- PIXELS 1.92us (1.89us)
+ VGA_VER_CHARS : integer := 25; -- CHARACTERS 12.8ms
+ VGA_VER_CHAR_LINES : integer := 16; -- LINES 0.512ms
+ VGA_VER_FRONT_PORCH : integer := 10; -- LINES 0.320ms
+ VGA_VER_SYNC : integer := 2; -- LINES 0.064ms
+ VGA_VER_BACK_PORCH : integer := 34 -- LINES 1.088ms
+ );
+ port(
+ -- control register interface
+ vdu_clk : in std_logic; -- CPU Clock - 12.5MHz
+ vdu_rst : in std_logic;
+ vdu_cs : in std_logic;
+ vdu_rw : in std_logic;
+ vdu_addr : in std_logic_vector(2 downto 0);
+ vdu_data_in : in std_logic_vector(7 downto 0);
+ vdu_data_out : out std_logic_vector(7 downto 0);
+
+ -- vga port connections
+ vga_clk : in std_logic; -- VGA Pixel Clock - 25 MHz
+ vga_red_o : out std_logic;
+ vga_green_o : out std_logic;
+ vga_blue_o : out std_logic;
+ vga_hsync_o : out std_logic;
+ vga_vsync_o : out std_logic
+ );
+end component;
+
+
+component BUFG
+ port (
+ i: in std_logic;
+ o: out std_logic
+ );
+end component;
+
+begin
+ -----------------------------------------------------------------------------
+ -- Instantiation of internal components
+ -----------------------------------------------------------------------------
+
+----------------------------------------
+--
+-- CPU09 CPU Core
+--
+----------------------------------------
+my_cpu : cpu09 port map (
+ clk => cpu_clk,
+ rst => cpu_reset,
+ rw => cpu_rw,
+ vma => cpu_vma,
+ address => cpu_addr(15 downto 0),
+ data_in => cpu_data_in,
+ data_out => cpu_data_out,
+ halt => cpu_halt,
+ hold => cpu_hold,
+ irq => cpu_irq,
+ nmi => cpu_nmi,
+ firq => cpu_firq
+ );
+
+----------------------------------------
+--
+-- SBUG / KBUG / SYS09BUG Monitor ROM
+--
+----------------------------------------
+my_rom : mon_rom port map (
+ clk => cpu_clk,
+ rst => cpu_reset,
+ cs => rom_cs,
+ rw => '1',
+ addr => cpu_addr(10 downto 0),
+ wdata => cpu_data_out,
+ rdata => rom_data_out
+ );
+
+----------------------------------------
+--
+-- Dynamic Address Translation Registers
+--
+----------------------------------------
+my_dat : dat_ram port map (
+ clk => cpu_clk,
+ rst => cpu_reset,
+ cs => dat_cs,
+ rw => cpu_rw,
+ addr_hi => cpu_addr(15 downto 12),
+ addr_lo => cpu_addr(3 downto 0),
+ data_in => cpu_data_out,
+ data_out => dat_addr(7 downto 0)
+ );
+
+----------------------------------------
+--
+-- ACIA/UART Serial interface
+--
+----------------------------------------
+my_ACIA0 : ACIA_6850 port map (
+ clk => cpu_clk,
+ rst => cpu_reset,
+ cs => uart0_cs,
+ rw => cpu_rw,
+ irq => uart0_irq,
+ Addr => cpu_addr(0),
+ Datain => cpu_data_out,
+ DataOut => uart0_data_out,
+ RxC => uart0_clk,
+ TxC => uart0_clk,
+ RxD => uart0_rxd,
+ TxD => uart0_txd,
+ DCD_n => uart0_dcd_n,
+ CTS_n => uart0_cts_n,
+ RTS_n => uart0_rts_n
+ );
+
+my_ACIA1 : ACIA_6850 port map (
+ clk => cpu_clk,
+ rst => cpu_reset,
+ cs => uart1_cs,
+ rw => cpu_rw,
+ irq => uart1_irq,
+ Addr => cpu_addr(0),
+ Datain => cpu_data_out,
+ DataOut => uart1_data_out,
+ RxC => uart1_clk,
+ TxC => uart1_clk,
+ RxD => uart1_rxd,
+ TxD => uart1_txd,
+ DCD_n => uart1_dcd_n,
+ CTS_n => uart1_cts_n,
+ RTS_n => uart1_rts_n
+ );
+
+----------------------------------------
+--
+-- ACIA Clock
+--
+----------------------------------------
+my_ACIA0_Clock : ACIA_Clock
+ generic map(
+ SYS_CLK_FREQ => SYS_CLK_FREQ,
+ ACIA_CLK_FREQ => ACIA0_CLK_FREQ
+ )
+ port map(
+ clk => SysClk,
+ acia_clk => uart0_clk
+ );
+
+my_ACIA1_Clock : ACIA_Clock
+ generic map(
+ SYS_CLK_FREQ => SYS_CLK_FREQ,
+ ACIA_CLK_FREQ => ACIA1_CLK_FREQ
+ )
+ port map(
+ clk => SysClk,
+ acia_clk => uart1_clk
+ );
+
+
+----------------------------------------
+--
+-- PS/2 Keyboard Interface
+--
+----------------------------------------
+my_keyboard : keyboard
+ generic map (
+ KBD_CLK_FREQ => CPU_CLK_FREQ
+ )
+ port map(
+ clk => cpu_clk,
+ rst => cpu_reset,
+ cs => keyboard_cs,
+ rw => cpu_rw,
+ addr => cpu_addr(0),
+ data_in => cpu_data_out(7 downto 0),
+ data_out => keyboard_data_out(7 downto 0),
+ irq => keyboard_irq,
+ kbd_clk => kb0_clock,
+ kbd_data => kb0_data
+ );
+
+----------------------------------------
+--
+-- Video Display Unit instantiation
+--
+----------------------------------------
+my_vdu : vdu8
+ generic map(
+ VDU_CLK_FREQ => CPU_CLK_FREQ, -- HZ
+ VGA_CLK_FREQ => VGA_CLK_FREQ, -- HZ
+ VGA_HOR_CHARS => 80, -- CHARACTERS
+ VGA_VER_CHARS => 25, -- CHARACTERS
+ VGA_PIX_PER_CHAR => 8, -- PIXELS
+ VGA_LIN_PER_CHAR => 16, -- LINES
+ VGA_HOR_BACK_PORCH => 40, -- PIXELS
+ VGA_HOR_SYNC => 96, -- PIXELS
+ VGA_HOR_FRONT_PORCH => 24, -- PIXELS
+ VGA_VER_BACK_PORCH => 13, -- LINES
+ VGA_VER_SYNC => 1, -- LINES
+ VGA_VER_FRONT_PORCH => 36 -- LINES
+ )
+ port map(
+
+ -- Control Registers
+ vdu_clk => cpu_clk, -- 12.5 MHz System Clock in
+ vdu_rst => cpu_reset,
+ vdu_cs => vdu_cs,
+ vdu_rw => cpu_rw,
+ vdu_addr => cpu_addr(2 downto 0),
+ vdu_data_in => cpu_data_out,
+ vdu_data_out => vdu_data_out,
+
+ -- vga port connections
+ vga_clk => vga_clk, -- 25 MHz VDU pixel clock
+ vga_red_o => vga_red,
+ vga_green_o => vga_green,
+ vga_blue_o => vga_blue,
+ vga_hsync_o => vga0_hs,
+ vga_vsync_o => vga0_vs
+ );
+
+----------------------------------------
+--
+-- Timer Module
+--
+----------------------------------------
+my_timer : timer port map (
+ clk => cpu_clk,
+ rst => cpu_reset,
+ cs => timer_cs,
+ rw => cpu_rw,
+ addr => cpu_addr(0),
+ data_in => cpu_data_out,
+ data_out => timer_data_out,
+ irq => timer_irq
+ );
+
+----------------------------------------
+--
+-- Bus Trap Interrupt logic
+--
+----------------------------------------
+my_trap : trap port map (
+ clk => cpu_clk,
+ rst => cpu_reset,
+ cs => trap_cs,
+ rw => cpu_rw,
+ vma => cpu_vma,
+ addr => cpu_addr,
+ data_in => cpu_data_out,
+ data_out => trap_data_out,
+ irq => trap_irq
+ );
+
+
+--
+-- 12.5 MHz CPU clock
+--
+cpu_clk_buffer : BUFG port map(
+ i => clock_div(1),
+ o => cpu_clk
+ );
+
+--
+-- 25 MHz VGA Pixel clock
+--
+vga_clk_buffer : BUFG port map(
+ i => clock_div(0),
+ o => vga_clk
+ );
+
+----------------------------------------------------------------------
+--
+-- Process to decode memory map
+--
+----------------------------------------------------------------------
+
+mem_decode: process( cpu_clk, Reset_n, dat_addr,
+ cpu_addr, cpu_rw, cpu_vma,
+ rom_data_out,
+ ram0_data_out, ram1_data_out,
+ uart0_data_out, uart1_data_out,
+ keyboard_data_out,
+ vdu_data_out,
+ cf_data_out,
+ timer_data_out,
+ trap_data_out )
+variable decode_addr : std_logic_vector(4 downto 0);
+begin
+ decode_addr := dat_addr(3 downto 0) & cpu_addr(11);
+-- decode_addr := cpu_addr(15 downto 11);
+
+ cpu_data_in <= (others=>'0');
+ rom_cs <= '0';
+ dat_cs <= '0';
+ ram0_cs <= '0';
+ ram1_cs <= '0';
+ uart0_cs <= '0';
+ uart1_cs <= '0';
+ keyboard_cs <= '0';
+ vdu_cs <= '0';
+ cf_cs <= '0';
+ timer_cs <= '0';
+ trap_cs <= '0';
+
+ if cpu_addr( 15 downto 8 ) = "11111111" then
+ cpu_data_in <= rom_data_out;
+ rom_cs <= cpu_vma; -- read ROM
+ dat_cs <= cpu_vma; -- write DAT
+ else
+ case decode_addr is
+ --
+ -- SBUG/KBUG/SYS09BUG Monitor ROM $F800 - $FFFF
+ --
+ when "11111" => -- $F800 - $FFFF
+ cpu_data_in <= rom_data_out;
+ rom_cs <= cpu_vma; -- read ROM
+
+ --
+ -- IO Devices $E000 - $E7FF
+ --
+ when "11100" => -- $E000 - $E7FF
+ case cpu_addr(7 downto 4) is
+ --
+ -- UART / ACIA $E000
+ --
+ when "0000" => -- $E000
+ cpu_data_in <= uart0_data_out;
+ uart0_cs <= cpu_vma;
+
+ --
+ -- WD1771 FDC sites at $E010-$E01F
+ --
+
+ --
+ -- Keyboard port $E020 - $E02F
+ --
+ when "0010" => -- $E020
+ cpu_data_in <= keyboard_data_out;
+ keyboard_cs <= cpu_vma;
+
+ --
+ -- VDU port $E030 - $E03F
+ --
+ when "0011" => -- $E030
+ cpu_data_in <= vdu_data_out;
+ vdu_cs <= cpu_vma;
+
+ --
+ -- Compact Flash $E040 - $E04F
+ --
+ when "0100" => -- $E040
+ cpu_data_in <= cf_data_out;
+ cf_cs <= cpu_vma;
+
+ --
+ -- Timer $E050 - $E05F
+ --
+ when "0101" => -- $E050
+ cpu_data_in <= timer_data_out;
+ timer_cs <= cpu_vma;
+
+ --
+ -- Bus Trap Logic $E060 - $E06F
+ --
+ when "0110" => -- $E060
+ cpu_data_in <= trap_data_out;
+ trap_cs <= cpu_vma;
+
+ --
+ -- UART1 port $E070 - $E07F
+ --
+ when "0111" => -- $E070
+ cpu_data_in <= uart1_data_out;
+ uart1_cs <= cpu_vma;
+
+ when others => -- $E080 to $E7FF
+ null;
+
+ end case;
+ --
+ -- Everything else is RAM
+ --
+ when others =>
+ case dat_addr(7 downto 6) is
+ when "00" =>
+ cpu_data_in <= ram0_data_out;
+ ram0_cs <= cpu_vma;
+ when "01" =>
+ cpu_data_in <= ram1_data_out;
+ ram1_cs <= cpu_vma;
+ when others =>
+ null;
+ end case;
+
+ end case;
+ end if;
+end process;
+
+
+--
+-- B5-SRAM Control
+-- Processes to read and write memory based on bus signals
+--
+ram0_process: process( cpu_clk, Reset_n,
+ cpu_addr, cpu_rw, cpu_vma, cpu_data_out,
+ dat_addr,
+ ram0_cs, ram0_wrl, ram0_wru, ram0_data_out )
+begin
+ ram0_csn <= not( ram0_cs and Reset_n );
+ ram0_wrl <= (not cpu_addr(0)) and (not cpu_rw) and cpu_clk;
+ ram0_wrln <= not (ram0_wrl);
+ ram0_wru <= cpu_addr(0) and (not cpu_rw) and cpu_clk;
+ ram0_wrun <= not (ram0_wru);
+ ram0_addr(16 downto 11) <= dat_addr(5 downto 0);
+ ram0_addr(10 downto 0) <= cpu_addr(11 downto 1);
+
+ if ram0_wrl = '1' then
+ ram0_data(7 downto 0) <= cpu_data_out;
+ else
+ ram0_data(7 downto 0) <= (others=>'Z');
+ end if;
+
+ if ram0_wru = '1' then
+ ram0_data(15 downto 8) <= cpu_data_out;
+ else
+ ram0_data(15 downto 8) <= (others=>'Z');
+ end if;
+
+ if cpu_addr(0) = '1' then
+ ram0_data_out <= ram0_data(15 downto 8);
+ else
+ ram0_data_out <= ram0_data(7 downto 0);
+ end if;
+end process;
+
+--
+-- B3-SRAM Control
+-- Processes to read and write memory based on bus signals
+--
+ram1_process: process( cpu_clk, Reset_n,
+ cpu_addr, cpu_rw, cpu_vma, cpu_data_out,
+ dat_addr,
+ ram1_cs, ram1_wrl, ram1_wru, ram1_data_out )
+begin
+ ram1_csn <= not( ram1_cs and Reset_n );
+ ram1_wrl <= (not cpu_addr(0)) and (not cpu_rw) and cpu_clk;
+ ram1_wrln <= not (ram1_wrl);
+ ram1_wru <= cpu_addr(0) and (not cpu_rw) and cpu_clk;
+ ram1_wrun <= not (ram1_wru);
+ ram1_addr(16 downto 11) <= dat_addr(5 downto 0);
+ ram1_addr(10 downto 0) <= cpu_addr(11 downto 1);
+
+ if ram1_wrl = '1' then
+ ram1_data(7 downto 0) <= cpu_data_out;
+ else
+ ram1_data(7 downto 0) <= (others=>'Z');
+ end if;
+
+ if ram1_wru = '1' then
+ ram1_data(15 downto 8) <= cpu_data_out;
+ else
+ ram1_data(15 downto 8) <= (others=>'Z');
+ end if;
+
+ if cpu_addr(0) = '1' then
+ ram1_data_out <= ram1_data(15 downto 8);
+ else
+ ram1_data_out <= ram1_data(7 downto 0);
+ end if;
+end process;
+
+--
+-- Compact Flash Control
+--
+compact_flash: process( Reset_n,
+ cpu_addr, cpu_rw, cpu_vma, cpu_data_out,
+ cf_cs, cf_rd, cf_wr, cf_d )
+begin
+ cf_rst_n <= Reset_n;
+ cf_cs0_n <= not( cf_cs ) or cpu_addr(3);
+ cf_cs1_n <= not( cf_cs and cpu_addr(3));
+ cf_wr <= cf_cs and (not cpu_rw);
+ cf_rd <= cf_cs and cpu_rw;
+ cf_wr_n <= not cf_wr;
+ cf_rd_n <= not cf_rd;
+ cf_a <= cpu_addr(2 downto 0);
+ if cf_wr = '1' then
+ cf_d(7 downto 0) <= cpu_data_out;
+ cf_d(15 downto 8) <= (others => '0');
+ else
+ cf_d(7 downto 0) <= (others => 'Z');
+ cf_d(15 downto 8) <= (others => 'Z');
+ end if;
+ cf_data_out <= cf_d(7 downto 0);
+end process;
+
+--
+-- Hold CF access for a few cycles
+--
+cf_hold_proc: process( cpu_clk, Reset_n )
+begin
+ if Reset_n = '0' then
+ cf_release <= '0';
+ cf_count <= "0000";
+ cf_hold_state <= hold_release_state;
+ elsif cpu_clk'event and cpu_clk='0' then
+ case cf_hold_state is
+ when hold_release_state =>
+ cf_release <= '0';
+ if cf_cs = '1' then
+ cf_count <= "0011";
+ cf_hold_state <= hold_request_state;
+ end if;
+
+ when hold_request_state =>
+ cf_count <= cf_count - "0001";
+ if cf_count = "0000" then
+ cf_release <= '1';
+ cf_hold_state <= hold_release_state;
+ end if;
+ when others =>
+ null;
+ end case;
+ end if;
+end process;
+
+--
+-- Interrupts and other bus control signals
+--
+interrupts : process( Reset_n,
+ cf_cs, cf_hold, cf_release,
+ uart0_irq, uart1_irq,
+ trap_irq, timer_irq, keyboard_irq
+ )
+begin
+ cf_hold <= cf_cs and (not cf_release);
+ cpu_reset <= not Reset_n; -- CPU reset is active high
+ cpu_irq <= uart0_irq or uart1_irq or keyboard_irq;
+ cpu_nmi <= trap_irq;
+ cpu_firq <= timer_irq;
+ cpu_halt <= '0';
+ cpu_hold <= cf_hold;
+end process;
+
+
+--
+-- flash led to indicate code is working
+--
+my_LED_Flasher: process (cpu_clk, CountL )
+begin
+ if(cpu_clk'event and cpu_clk = '0') then
+ countL <= countL + 1;
+ end if;
+ LED <= countL(23);
+end process;
+
+--
+-- Clock divider
+--
+my_clock_divider: process( SysClk )
+begin
+ if SysClk'event and SysClk='0' then
+ clock_div <= clock_div + "01";
+ end if;
+end process;
+--
+-- Assign VDU VGA colour output
+-- only 8 colours are handled.
+--
+my_vga_out: process( vga_red, vga_green, vga_blue )
+begin
+ vga0_red <= vga_red & vga_red;
+ vga0_green <= vga_green & vga_green;
+ vga0_blue <= vga_blue & vga_blue;
+ uart0_dcd_n <= '0';
+ uart1_dcd_n <= '0';
+end process;
+
+end rtl; --===================== End of architecture =======================--
+
Index: System09/trunk/rtl/System09_BurchED_B5-X300_2/transcript
===================================================================
--- System09/trunk/rtl/System09_BurchED_B5-X300_2/transcript (nonexistent)
+++ System09/trunk/rtl/System09_BurchED_B5-X300_2/transcript (revision 104)
@@ -0,0 +1,46 @@
+# Reading G:/Modeltech_xe_starter/tcl/vsim/pref.tcl
+# do acia_6850_testbench.fdo
+# ** Warning: (vlib-34) Library already exists at "work".
+# Model Technology ModelSim XE III vcom 6.0a Compiler 2004.11 Nov 10 2004
+# -- Loading package standard
+# -- Loading package std_logic_1164
+# -- Loading package std_logic_arith
+# -- Loading package std_logic_unsigned
+# -- Compiling entity acia_rx
+# -- Compiling architecture rtl of acia_rx
+# Model Technology ModelSim XE III vcom 6.0a Compiler 2004.11 Nov 10 2004
+# -- Loading package standard
+# -- Loading package std_logic_1164
+# -- Loading package numeric_std
+# -- Loading package std_logic_arith
+# -- Loading package std_logic_unsigned
+# -- Compiling entity acia_tx
+# -- Compiling architecture rtl of acia_tx
+# Model Technology ModelSim XE III vcom 6.0a Compiler 2004.11 Nov 10 2004
+# -- Loading package standard
+# -- Loading package std_logic_1164
+# -- Loading package numeric_std
+# -- Compiling entity acia_6850
+# -- Compiling architecture rtl of acia_6850
+# Model Technology ModelSim XE III vcom 6.0a Compiler 2004.11 Nov 10 2004
+# -- Loading package standard
+# -- Loading package std_logic_1164
+# -- Loading package std_logic_arith
+# -- Loading package std_logic_unsigned
+# -- Loading package numeric_std
+# -- Compiling entity acia_6850_testbench
+# -- Compiling architecture behavior of acia_6850_testbench
+# vsim -lib work -t 1ps acia_6850_testbench
+# Loading G:\Modeltech_xe_starter\win32xoem/../std.standard
+# Loading G:\Modeltech_xe_starter\win32xoem/../ieee.std_logic_1164(body)
+# Loading G:\Modeltech_xe_starter\win32xoem/../ieee.std_logic_arith(body)
+# Loading G:\Modeltech_xe_starter\win32xoem/../ieee.std_logic_unsigned(body)
+# Loading G:\Modeltech_xe_starter\win32xoem/../ieee.numeric_std(body)
+# Loading work.acia_6850_testbench(behavior)
+# Loading work.acia_6850(rtl)
+# Loading work.acia_rx(rtl)
+# Loading work.acia_tx(rtl)
+# .main_pane.mdi.interior.cs.vm.paneset.cli_0.wf.clip.cs
+# .main_pane.workspace
+# .main_pane.signals.interior.cs
+run -all
Index: System09/trunk/rtl/System09_BurchED_B5-X300_2/System09_BurchED_B5-X300.ise_ISE_Backup
===================================================================
Cannot display: file marked as a binary type.
svn:mime-type = application/octet-stream
Index: System09/trunk/rtl/System09_BurchED_B5-X300_2/System09_BurchED_B5-X300.ise_ISE_Backup
===================================================================
--- System09/trunk/rtl/System09_BurchED_B5-X300_2/System09_BurchED_B5-X300.ise_ISE_Backup (nonexistent)
+++ System09/trunk/rtl/System09_BurchED_B5-X300_2/System09_BurchED_B5-X300.ise_ISE_Backup (revision 104)
System09/trunk/rtl/System09_BurchED_B5-X300_2/System09_BurchED_B5-X300.ise_ISE_Backup
Property changes :
Added: svn:mime-type
## -0,0 +1 ##
+application/octet-stream
\ No newline at end of property
Index: System09/trunk/rtl/System09_BurchED_B5-X300_2/__projnav/sumrpt_tcl.rsp
===================================================================
--- System09/trunk/rtl/System09_BurchED_B5-X300_2/__projnav/sumrpt_tcl.rsp (nonexistent)
+++ System09/trunk/rtl/System09_BurchED_B5-X300_2/__projnav/sumrpt_tcl.rsp (revision 104)
@@ -0,0 +1 @@
+set ADucfFile {System09_BurchED_B5-X300.ucf}
Index: System09/trunk/rtl/System09_BurchED_B5-X300_2/__projnav/runXst_tcl.rsp
===================================================================
--- System09/trunk/rtl/System09_BurchED_B5-X300_2/__projnav/runXst_tcl.rsp (nonexistent)
+++ System09/trunk/rtl/System09_BurchED_B5-X300_2/__projnav/runXst_tcl.rsp (revision 104)
@@ -0,0 +1 @@
+set allSynthModules {cpu09.MOD mon_rom.MOD dat_ram.MOD acia_rx.MOD acia_tx.MOD acia_6850.MOD bit_funcs.MOD acia_clock.MOD keymap_rom.MOD ps2_keyboard_interface.MOD keyboard.MOD char_rom.MOD ram_2k.MOD vdu8.MOD timer.MOD trap.MOD system09.MOD}