OpenCores
URL https://opencores.org/ocsvn/System09/System09/trunk

Subversion Repositories System09

Compare Revisions

  • This comparison shows the changes necessary to convert path
    /
    from Rev 116 to Rev 117
    Reverse comparison

Rev 116 → Rev 117

/System09/trunk/rtl/System09_Terasic_DE1/System09_Terasic_DE1.vhd
0,0 → 1,1120
--=============================================================================--
-- --
-- System09 - Synthesizable System On a Chip - VHDL FPGA core top level file. --
-- --
--=============================================================================--
--
--
-- File name : System09_Terasic_DE1.vhd
--
-- Entity name : System09
--
-- Purpose : Top level file for 6809 compatible system on a chip
-- Designed with Alera EP2C20 Cyclone 2 FPGA.
-- Implemented with Terasic DE1 FPGA board,
--
-- Dependencies : ieee.Std_Logic_1164
-- ieee.std_logic_unsigned
-- ieee.std_logic_arith
-- ieee.numeric_std
--
-- Uses : cpu09 (..\VHDL\cpu09.vhd) CPU core
-- dat_ram (..\VHDL\datram.vhd) Dynamic Address Translation
-- mon_rom (..\Cyclone2\mon_rom.vhd) Monitor ROM
-- acia6850 (..\VHDL\acia6850.vhd) ACIA (UART)
-- ACIA_Clock (..\VHDL\ACIA_Clock.vhd) ACIA Baud Rate Clock Divider
-- keyboard (..\VHDL\keyboard.vhd) PS/2 Keyboard register interface
-- ps2_keyboard (..\VHDL\ps2_keyboard.vhd) PS/2 Keyboard interface logic
-- keymap_rom (..\Cyclone2\keymap_rom.vhd) PS/2 Keyboard key code look up table
-- trap (..\VHDL\trap.vhd) Hardware breakpointy trap
-- timer (..\VHDL\timer.vhd) Interrupt timer
-- vdu8 (..\VHDL\vdu8.vhd) Video Display Unit
-- (..\Cyclone2\char_rom.vhd) Character Generator ROM (B16_RAM)
-- (..\Cyclone2\ram_2k.vhd) Text & Attribute RAM Buffer
-- sprom (..\Cyclone2\sprom.vhd) Single port altsyncrom
-- spram (..\Cyclone2\spram.vhd) Single port altsyncram
-- bit_funcs (..\VHDL\bit_funcs.vhd) Bit manipulation Functions package
--
-- Author : John E. Kent
-- dilbert57@opencores.org
--
-- Memory Map :
--
-- $0000 - $DFFF System RAM (512K Mapped via DAT)
-- $E000 - ACIA (SWTPc)
-- $E010 - Reserved for SWTPc FD-01 FD1771 FDC
-- $E020 - Keyboard
-- $E030 - VDU
-- $E040 - Reserved for SWTPc MP-T (was Compact Flash)
-- $E050 - Timer
-- $E060 - Trap (Hardware Breakpoint)
-- $E070 - Reserved for Trace Buffer
-- $E080 - Reserved for SWTPc MP-ID 6821 PIA (?)
-- $E090 - Reserved for SWTPc MP-ID 6840 PTM (?)
-- $E0A0 - Switches in / LEDS out
-- $E0B0 - 7 Segment hex display
-- $E0C0 - Reserved
-- $E0D0 - Reserved
-- $E0E0 - Reserved
-- $E0F0 - Reserved
-- $E100 - $E13F Reserved IDE / Compact Flash Card
-- $E140 - $E17F Reserved for Ethernet MAC (XESS)
-- $E180 - $E1BF Reserved for Expansion Slot 0 (XESS)
-- $E1C0 - $E1FF Reserved for Expansion Slot 1 (XESS)
-- $E200 - $EFFF Reserved for Future I/O
-- $F000 - $F7FF RAM for Sys09bug monitor extensions
-- $F800 - $FFFF Sys09bug ROM (Read only)
-- $FFF0 - $FFFF DAT - Dynamic Address Translation (Write Only)
--
--
-- Copyright (C) 2003 - 2010 John Kent
--
-- This program is free software: you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation, either version 3 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program. If not, see <http://www.gnu.org/licenses/>.
--
--===========================================================================--
--
-- Revision History:
--
--===========================================================================--
--
-- Version 0.1 - 20 March 2003
-- Version 0.2 - 30 March 2003
-- Version 0.3 - 29 April 2003
-- Version 0.4 - 29 June 2003
--
-- Version 0.5 - 19 July 2003
-- prints out "Hello World"
--
-- Version 0.6 - 5 September 2003
-- Runs SBUG
--
-- Version 1.0- 6 Sep 2003 - John Kent
-- Inverted sys_clk
-- Initial release to Open Cores
--
-- Version 1.1 - 17 Jan 2004 - John Kent
-- Updated miniUart.
--
-- Version 1.2 - 25 Jan 2004 - John Kent
-- removed signals "test_alu" and "test_cc"
-- Trap hardware re-instated.
--
-- Version 1.3 - 11 Feb 2004 - John Kent
-- Designed forked off to produce System09_VDU
-- Added VDU component
-- VDU runs at 25MHz and divides the clock by 2 for the CPU
-- UART Runs at 57.6 Kbps
--
-- Version 2.0 - 2 September 2004 - John Kent
-- ported to Digilent Xilinx Spartan3 starter board
-- removed Compaact Flash and Trap Logic.
-- Replaced SBUG with KBug9s
--
-- Version 2.1 - 21 November 2006 - John Kent
-- Replaced KBug9s with Sys09bug 1.0
-- Inverted bottom nybble of DAT register outputs
-- Changed ROM & I/O decoding to be compatible with SWTPc
-- Upped the serial baud rate to 115.2 KBd
-- added multiple global clock buffers
-- (Uart would not operate correctly)
--
-- Version 2.2 - 22 December 2006 - John Kent
-- Increased CPU clock from 12.5MHz to 25 MHz.
-- Removed some of the global clock buffers
-- Added LED output register
-- Changed address decoding to 4K Blocks
--
-- Version 2.3 - 1 June 2007 - John Kent
-- Updated VDU & ACIA
-- Changed decoding for Sys09Bug
--
-- Version 2.4 - 31 January 2008 - John Kent
-- ACIA does not appear to work.
-- Made RAM OE and WE strobes synchonous to sys_clk
--
-- Version 2.5 - 23rd Feburary 2009 - John Kent
-- Implemented recommendation to remove vga_clk clock buffer
--
-- Version 2.6 - 5th september 2010 - John Kent
-- Renamed ACIA_6850 to acia6850
-- Updated generics on VDU8
-- Shortened the "keyboard" label
-- Fixed up address label on CPU09
-- Removed Flex RAM
-- Map RAM at $F000 - $F7FF
--
-- Vesrion 2.7 - 22nd October 2010 - John Kent
-- Ported from Digilent XC3S200 Starter to
-- Terasic EP2C20 DE1 board.
--
--===========================================================================--
library ieee;
use ieee.std_logic_1164.all;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
use ieee.numeric_std.all;
 
entity System09_Terasic_DE1 is
port(
-- clocks
clock_24 : in std_logic_vector(1 downto 0);
clock_27 : in std_logic;
clock_50 : in std_logic; -- System Clock input
ext_clock : in std_logic;
-- push button keys
key : in std_logic_vector(3 downto 0); -- RST, NMI
 
-- SRAM interface signals
 
sram_ce_n : out std_logic;
sram_we_n : out std_logic;
sram_oe_n : out std_logic;
sram_ub_n : out std_logic;
sram_lb_n : out std_logic;
sram_addr : out std_logic_vector(17 downto 0);
sram_dq : inout std_logic_vector(15 downto 0);
 
-- PS/2 Keyboard
ps2_clk : inout Std_logic;
ps2_dat : inout Std_Logic;
 
-- ACIA/UART Interface
uart_rxd : in Std_Logic;
uart_txd : out Std_Logic;
 
-- CRTC output signals
vga_r : out std_logic_vector(3 downto 0);
vga_g : out std_logic_vector(3 downto 0);
vga_b : out std_logic_vector(3 downto 0);
vga_hs : out Std_Logic;
vga_vs : out Std_Logic;
 
-- LEDS & Switches
ledg : out std_logic_vector(7 downto 0);
ledr : out std_logic_vector(9 downto 0);
sw : in std_logic_vector(9 downto 0);
 
-- hexadecimal display
hex0 : out std_logic_vector(6 downto 0);
hex1 : out std_logic_vector(6 downto 0);
hex2 : out std_logic_vector(6 downto 0);
hex3 : out std_logic_vector(6 downto 0);
-- gnereal purpose I/O
gpio_0 : in std_logic_vector(35 downto 0);
gpio_1 : in std_logic_vector(35 downto 0);
-- i2c interface
i2c_sclk : in std_logic;
i2c_sdat : in std_logic;
-- audio codec
aud_adcdat : in std_logic;
aud_adclrck : in std_logic;
aud_bclk : in std_logic;
aud_dacdat : in std_logic;
aud_daclrck : in std_logic;
aud_xck : in std_logic;
-- dram
dram_addr : out std_logic_vector(11 downto 0);
dram_dq : in std_logic_vector(15 downto 0);
dram_cs_n : out std_logic;
dram_ba_0 : in std_logic;
dram_ba_1 : in std_logic;
dram_ldqm : in std_logic;
dram_udqm : in std_logic;
dram_ras_n : out std_logic;
dram_cas_n : out std_logic;
dram_we_n : out std_logic;
dram_cke : in std_logic;
dram_clk : in std_logic;
-- Flash memory
fl_addr : out std_logic_vector(21 downto 0);
fl_dq : in std_logic_vector(7 downto 0);
fl_rst_n : in std_logic;
fl_oe_n : out std_logic;
fl_we_n : out std_logic;
-- JTAG
tck : in std_logic;
tcs : in std_logic;
tdi : in std_logic;
tdo : in std_logic
);
end System09_Terasic_DE1;
 
-------------------------------------------------------------------------------
-- Architecture for System09
-------------------------------------------------------------------------------
architecture my_computer of System09_Terasic_DE1 is
-----------------------------------------------------------------------------
-- constants
-----------------------------------------------------------------------------
constant SYS_CLK_FREQ : integer := 50000000; -- FPGA System Clock
constant VGA_CLK_FREQ : integer := 25000000; -- VGA Pixel Clock
constant CPU_CLK_FREQ : integer := 25000000; -- CPU Clock
constant BAUD_Rate : integer := 57600; -- Baud Rate
constant ACIA_CLK_FREQ : integer := BAUD_Rate * 16;
 
type hold_state_type is ( hold_release_state, hold_request_state );
 
-----------------------------------------------------------------------------
-- Signals
-----------------------------------------------------------------------------
 
signal sys_clk : std_logic;
signal vga_clk : std_logic;
signal pll_locked : std_logic;
-- CPU Interface signals
signal cpu_clk : std_logic;
signal cpu_rst : std_logic;
signal cpu_rw : std_logic;
signal cpu_vma : std_logic;
signal cpu_halt : std_logic;
signal cpu_hold : std_logic;
signal cpu_firq : std_logic;
signal cpu_irq : std_logic;
signal cpu_nmi : std_logic;
signal cpu_addr : std_logic_vector(15 downto 0);
signal cpu_data_in : std_logic_vector(7 downto 0);
signal cpu_data_out : std_logic_vector(7 downto 0);
 
-- Dynamic Address Translation
signal dat_cs : std_logic;
signal dat_addr : std_logic_vector(7 downto 0);
 
-- BOOT ROM
signal rom_cs : Std_logic;
signal rom_data_out : Std_Logic_Vector(7 downto 0);
 
-- ACIA Interface signals
signal acia_clk : std_logic;
signal acia_cs : Std_Logic;
signal acia_data_out : Std_Logic_Vector(7 downto 0);
signal acia_irq : Std_Logic;
signal acia_rxd : Std_Logic;
signal acia_txd : Std_Logic;
signal acia_dcd_n : Std_Logic;
-- signal acia_rts_n : Std_Logic;
signal acia_cts_n : Std_Logic;
 
-- keyboard port
signal kbd_data_out : std_logic_vector(7 downto 0);
signal kbd_cs : std_logic;
signal kbd_irq : std_logic;
-- LEDs
signal leds_data_out : std_logic_vector(7 downto 0);
signal leds_cs : std_logic;
 
-- Video Display Unit
signal vdu_cs : std_logic;
signal vdu_data_out : std_logic_vector(7 downto 0);
signal vga_red : std_logic;
signal vga_green : std_logic;
signal vga_blue : std_logic;
 
-- LEDs
signal led_cs : std_logic;
signal led_data_out : std_logic_vector(7 downto 0);
 
-- 7 Segment Display
signal hex_cs : std_logic;
signal hex_data_out : std_logic_vector(7 downto 0);
signal hex0_reg : std_logic_vector(7 downto 0);
signal hex1_reg : std_logic_vector(7 downto 0);
signal hex2_reg : std_logic_vector(7 downto 0);
signal hex3_reg : std_logic_vector(7 downto 0);
-- interrupt timer
signal tmr_data_out : std_logic_vector(7 downto 0);
signal tmr_cs : std_logic;
signal tmr_irq : std_logic;
 
-- hardware break point (trap)
signal hbp_data_out : std_logic_vector(7 downto 0);
signal hbp_cs : std_logic;
signal hbp_irq : std_logic;
 
-- RAM
signal sram_cs : std_logic; -- memory chip select
signal sram_data_out : std_logic_vector(7 downto 0);
signal sram_ce : std_logic;
signal sram_ub : std_logic;
signal sram_lb : std_logic;
signal sram_we : std_logic;
signal sram_oe : std_logic;
 
-- System Clock Prescaler
signal clk_count : std_logic;
 
-----------------------------------------------------------------
--
-- CPU09 CPU core
--
-----------------------------------------------------------------
 
component cpu09
port (
clk : in std_logic;
rst : in std_logic;
vma : out std_logic;
addr : out std_logic_vector(15 downto 0);
rw : out std_logic;
data_in : in std_logic_vector(7 downto 0);
data_out : out std_logic_vector(7 downto 0);
halt : in std_logic;
hold : in std_logic;
irq : in std_logic;
nmi : in std_logic;
firq : in std_logic
);
end component;
 
----------------------------------------
--
-- Dynamic Address Translation Registers
--
----------------------------------------
component dat_ram
port (
clk : in std_logic;
rst : in std_logic;
cs : in std_logic;
rw : in std_logic;
addr_lo : in std_logic_vector(3 downto 0);
addr_hi : in std_logic_vector(3 downto 0);
data_in : in std_logic_vector(7 downto 0);
data_out : out std_logic_vector(7 downto 0)
);
end component;
 
----------------------------------------
--
-- 4KByte Block RAM Monitor ROM
--
----------------------------------------
component mon_rom
Port (
clk : in std_logic;
rst : in std_logic;
cs : in std_logic;
rw : in std_logic;
addr : in std_logic_vector (10 downto 0);
data_in : in std_logic_vector (7 downto 0);
data_out : out std_logic_vector (7 downto 0)
);
end component;
 
-----------------------------------------------------------------
--
-- 6850 ACIA
--
-----------------------------------------------------------------
 
component acia6850
port (
clk : in Std_Logic; -- System Clock
rst : in Std_Logic; -- Reset input (active high)
cs : in Std_Logic; -- ACIA Chip Select
rw : in Std_Logic; -- Read / Not Write
addr : in Std_Logic; -- Register Select
data_in : in Std_Logic_Vector(7 downto 0); -- Data Bus In
data_out : out Std_Logic_Vector(7 downto 0); -- Data Bus Out
irq : out Std_Logic; -- Interrupt
RxC : in Std_Logic; -- Receive Baud Clock
TxC : in Std_Logic; -- Transmit Baud Clock
RxD : in Std_Logic; -- Receive Data
TxD : out Std_Logic; -- Transmit Data
DCD_n : in Std_Logic; -- Data Carrier Detect
CTS_n : in Std_Logic; -- Clear To Send
RTS_n : out Std_Logic -- Request To send
);
end component;
 
-----------------------------------------------------------------
--
-- ACIA Clock divider
--
-----------------------------------------------------------------
 
component ACIA_Clock
generic (
SYS_CLK_FREQ : integer := SYS_CLK_FREQ;
ACIA_CLK_FREQ : integer := ACIA_CLK_FREQ
);
port (
clk : in Std_Logic; -- System Clock Input
acia_clk : out Std_logic -- ACIA Clock output
);
end component;
 
----------------------------------------
--
-- PS/2 Keyboard
--
----------------------------------------
 
component keyboard
generic(
KBD_CLK_FREQ : integer := CPU_CLK_FREQ
);
port(
clk : in std_logic;
rst : in std_logic;
cs : in std_logic;
addr : in std_logic;
rw : in std_logic;
data_in : in std_logic_vector(7 downto 0);
data_out : out std_logic_vector(7 downto 0);
irq : out std_logic;
kbd_clk : inout std_logic;
kbd_data : inout std_logic
);
end component;
 
----------------------------------------
--
-- Video Display Unit.
--
----------------------------------------
component vdu8
generic(
VGA_CLK_FREQ : integer := VGA_CLK_FREQ; -- HZ
VGA_HOR_CHARS : integer := 80; -- CHARACTERS 25.6us
VGA_HOR_CHAR_PIXELS : integer := 8; -- PIXELS 0.32us
VGA_HOR_FRONT_PORCH : integer := 16; -- PIXELS 0.64us
VGA_HOR_SYNC : integer := 96; -- PIXELS 3.84us
VGA_HOR_BACK_PORCH : integer := 48; -- PIXELS 1.92us
VGA_VER_CHARS : integer := 25; -- CHARACTERS 12.8ms
VGA_VER_CHAR_LINES : integer := 16; -- LINES 0.512ms
VGA_VER_FRONT_PORCH : integer := 10; -- LINES 0.320ms
VGA_VER_SYNC : integer := 2; -- LINES 0.064ms
VGA_VER_BACK_PORCH : integer := 34 -- LINES 1.088ms
);
port(
-- control register interface
vdu_clk : in std_logic; -- CPU Clock - 12.5MHz
vdu_rst : in std_logic;
vdu_cs : in std_logic;
vdu_rw : in std_logic;
vdu_addr : in std_logic_vector(2 downto 0);
vdu_data_in : in std_logic_vector(7 downto 0);
vdu_data_out : out std_logic_vector(7 downto 0);
 
-- vga port connections
vga_clk : in std_logic; -- VGA Pixel Clock - 25 MHz
vga_red_o : out std_logic;
vga_green_o : out std_logic;
vga_blue_o : out std_logic;
vga_hsync_o : out std_logic;
vga_vsync_o : out std_logic
);
end component;
 
----------------------------------------
--
-- Interrupt timer
--
----------------------------------------
 
component timer is
port (
clk : in std_logic;
rst : in std_logic;
cs : in std_logic;
addr : in std_logic;
rw : in std_logic;
data_in : in std_logic_vector(7 downto 0);
data_out : out std_logic_vector(7 downto 0);
irq : out std_logic
);
end component;
 
----------------------------------------
--
-- hardware break point (bus trap)
--
----------------------------------------
 
component trap is
port (
clk : in std_logic;
rst : in std_logic;
cs : in std_logic;
rw : in std_logic;
vma : in std_logic;
addr : in std_logic_vector(15 downto 0);
data_in : in std_logic_vector(7 downto 0);
data_out : out std_logic_vector(7 downto 0);
irq : out std_logic
);
end component;
 
 
component pll IS
PORT
(
areset : IN STD_LOGIC := '0';
inclk0 : IN STD_LOGIC := '0';
c0 : OUT STD_LOGIC ;
c1 : OUT STD_LOGIC ;
c2 : OUT STD_LOGIC ;
locked : OUT STD_LOGIC
);
END component;
 
begin
-----------------------------------------------------------------------------
-- Instantiation of internal components
-----------------------------------------------------------------------------
 
my_cpu : cpu09 port map (
clk => cpu_clk,
rst => cpu_rst,
vma => cpu_vma,
addr => cpu_addr(15 downto 0),
rw => cpu_rw,
data_in => cpu_data_in,
data_out => cpu_data_out,
halt => cpu_halt,
hold => cpu_hold,
irq => cpu_irq,
nmi => cpu_nmi,
firq => cpu_firq
);
 
my_dat : dat_ram port map (
clk => cpu_clk,
rst => cpu_rst,
cs => dat_cs,
addr_hi => cpu_addr(15 downto 12),
addr_lo => cpu_addr(3 downto 0),
rw => cpu_rw,
data_in => cpu_data_out,
data_out => dat_addr(7 downto 0)
);
 
my_rom : mon_rom port map (
clk => cpu_clk,
rst => cpu_rst,
cs => rom_cs,
rw => '1',
addr => cpu_addr(10 downto 0),
data_in => cpu_data_out,
data_out => rom_data_out
);
 
my_acia : acia6850 port map (
clk => cpu_clk,
rst => cpu_rst,
cs => acia_cs,
addr => cpu_addr(0),
rw => cpu_rw,
data_in => cpu_data_out,
data_out => acia_data_out,
irq => acia_irq,
RxC => acia_clk,
TxC => acia_clk,
RxD => acia_rxd,
TxD => acia_txd,
DCD_n => acia_dcd_n,
CTS_n => acia_cts_n,
RTS_n => open
);
 
 
----------------------------------------
--
-- ACIA Clock
--
----------------------------------------
my_ACIA_Clock : ACIA_Clock
generic map(
SYS_CLK_FREQ => SYS_CLK_FREQ,
ACIA_CLK_FREQ => ACIA_CLK_FREQ
)
port map(
clk => sys_clk,
acia_clk => acia_clk
);
 
 
----------------------------------------
--
-- PS/2 Keyboard Interface
--
----------------------------------------
my_keyboard : keyboard
generic map (
KBD_CLK_FREQ => CPU_CLK_FREQ
)
port map(
clk => cpu_clk,
rst => cpu_rst,
cs => kbd_cs,
addr => cpu_addr(0),
rw => cpu_rw,
data_in => cpu_data_out(7 downto 0),
data_out => kbd_data_out(7 downto 0),
irq => kbd_irq,
kbd_clk => ps2_clk,
kbd_data => ps2_dat
);
 
----------------------------------------
--
-- Video Display Unit instantiation
--
----------------------------------------
my_vdu : vdu8
generic map(
VGA_CLK_FREQ => VGA_CLK_FREQ, -- 25MHZ
VGA_HOR_CHARS => 80, -- CHARACTERS 25.6us
VGA_HOR_CHAR_PIXELS => 8, -- PIXELS 0.32us
VGA_HOR_FRONT_PORCH => 16, -- PIXELS 0.64us
VGA_HOR_SYNC => 96, -- PIXELS 3.84us
VGA_HOR_BACK_PORCH => 48, -- PIXELS 1.92us
VGA_VER_CHARS => 25, -- CHARACTERS 12.8ms
VGA_VER_CHAR_LINES => 16, -- LINES 0.512ms
VGA_VER_FRONT_PORCH => 10, -- LINES 0.320ms
VGA_VER_SYNC => 2, -- LINES 0.064ms
VGA_VER_BACK_PORCH => 34 -- LINES 1.088ms
)
port map(
 
-- Control Registers
vdu_clk => cpu_clk, -- 12.5 MHz System Clock in
vdu_rst => cpu_rst,
vdu_cs => vdu_cs,
vdu_addr => cpu_addr(2 downto 0),
vdu_rw => cpu_rw,
vdu_data_in => cpu_data_out,
vdu_data_out => vdu_data_out,
 
-- vga port connections
vga_clk => vga_clk, -- 25 MHz pixel clock
vga_red_o => vga_red,
vga_green_o => vga_green,
vga_blue_o => vga_blue,
vga_hsync_o => vga_hs,
vga_vsync_o => vga_vs
);
 
----------------------------------------
--
-- Interrupt timer
--
----------------------------------------
 
my_timer : timer
port map (
clk => cpu_clk,
rst => cpu_rst,
cs => tmr_cs,
addr => cpu_addr(0),
rw => cpu_rw,
data_in => cpu_data_out,
data_out => tmr_data_out,
irq => tmr_irq
);
 
----------------------------------------
--
-- hardware break point (bus trap)
--
----------------------------------------
 
my_hw_bp : trap
port map (
clk => cpu_clk,
rst => cpu_rst,
cs => hbp_cs,
rw => cpu_rw,
vma => cpu_vma,
addr => cpu_addr,
data_in => cpu_data_out,
data_out => hbp_data_out,
irq => hbp_irq
);
 
----------------------------------------
--
-- Phase Locked Loop Clock divider
--
 
my_pll : pll
PORT MAP
(
areset => '0',
inclk0 => clock_50,
c0 => sys_clk,
c1 => cpu_clk,
c2 => vga_clk,
locked => pll_locked
);
----------------------------------------------------------------------
--
-- Process to decode memory map
--
----------------------------------------------------------------------
 
mem_decode: process( cpu_addr, cpu_rw, cpu_vma,
dat_cs, dat_addr,
rom_data_out,
acia_data_out,
kbd_data_out,
vdu_data_out,
hex_data_out,
led_data_out,
tmr_data_out,
hbp_data_out,
sram_data_out
)
begin
cpu_data_in <= (others=>'0');
dat_cs <= '0';
rom_cs <= '0';
acia_cs <= '0';
kbd_cs <= '0';
vdu_cs <= '0';
hex_cs <= '0';
led_cs <= '0';
sram_cs <= '0';
tmr_cs <= '0';
hbp_cs <= '0';
-- pb_cs <= '0';
-- ide_cs <= '0';
-- ether_cs <= '0';
-- slot1_cs <= '0';
-- slot2_cs <= '0';
 
if cpu_addr( 15 downto 8 ) = "11111111" then
cpu_data_in <= rom_data_out;
dat_cs <= cpu_vma; -- write DAT
rom_cs <= cpu_vma; -- read ROM
--
-- Sys09Bug Monitor ROM $F000 - $FFFF
--
elsif dat_addr(3 downto 0) = "1111" then -- $XF000 - $XFFFF
if cpu_addr(11) = '1' then
--
-- Monitor ROM $F800 - $FFFF
--
cpu_data_in <= rom_data_out;
rom_cs <= cpu_vma; -- read ROM
else
--
-- SRAM $F000 - $F7FF
--
cpu_data_in <= sram_data_out;
sram_cs <= cpu_vma;
end if;
--
-- IO Devices $E000 - $EFFF
--
elsif dat_addr(3 downto 0) = "1110" then -- $XE000 - $XEFFF
case cpu_addr(11 downto 8) is
--
-- SWTPC peripherals from $E000 to $E0FF
--
when "0000" =>
case cpu_addr(7 downto 4) is
--
-- ACIA ($E000 - $E00F)
--
when "0000" =>
cpu_data_in <= acia_data_out;
acia_cs <= cpu_vma;
 
--
-- Reserved - FD1771 FDC ($E010 - $E01F) (SWTPC)
--
 
--
-- Keyboard port ($E020 - $E02F)
--
when "0010" =>
cpu_data_in <= kbd_data_out;
kbd_cs <= cpu_vma;
 
--
-- VDU port ($E030 - $E03F)
--
when "0011" =>
cpu_data_in <= vdu_data_out;
vdu_cs <= cpu_vma;
 
--
-- Reserved - SWTPc MP-T ($E040 - $E04F)
--
 
--
-- Reserved - Timer ($E050 - $E05F) (B5-X300)
--
when "0101" =>
cpu_data_in <= tmr_data_out;
tmr_cs <= cpu_vma;
--
-- Reserved - hardware break point (Bus Trap) ($E060 - $E06F)
--
when "0110" =>
cpu_data_in <= hbp_data_out;
hbp_cs <= cpu_vma;
--
-- Reserved - I/O port ($E070 - $E07F) (B5-X300)
--
 
--
-- Reserved - PTM 6840 ($E080 - $E08F) (SWTPC)
--
 
--
-- Reserved - PIA Timer ($E090 - $E09F) (SWTPC)
--
 
--
-- Read Switched port ($E0A0 - $E0AF)
-- Write LEDS
--
when "1010" =>
cpu_data_in <= led_data_out;
led_cs <= cpu_vma;
 
--
-- 7 segment display port ($E0B0 - $E0BF)
--
when "1011" =>
cpu_data_in <= hex_data_out;
hex_cs <= cpu_vma;
 
 
when others => -- $EXC0 to $EXFF
null;
end case;
--
-- $E100 to $EFFF reserved for future use
--
when others =>
null;
end case;
--
-- Everything else is RAM
--
else
cpu_data_in <= sram_data_out;
sram_cs <= cpu_vma;
end if;
end process;
 
 
--
-- 1M byte SRAM Control
-- Processes to read and write memory based on bus signals
--
sram_process: process( sys_clk, cpu_rst,
cpu_addr, cpu_rw, cpu_vma, cpu_data_out,
dat_addr, sram_cs,
sram_ce, sram_ub, sram_lb, sram_dq,
sram_we, sram_oe )
begin
--
-- Clock Hold on rising edge
--
if( sys_clk'event and sys_clk='1' ) then
--
-- sram_hold signal helps
--
if( cpu_rst = '1' ) then
sram_we <= '0';
sram_oe <= '0';
else
if (sram_cs = '1') and (sram_we = '0') and (sram_oe = '0') then
sram_we <= not cpu_rw;
sram_oe <= cpu_rw;
else
sram_we <= '0';
sram_oe <= '0';
end if;
end if;
end if;
 
sram_we_n <= not sram_we;
sram_oe_n <= not sram_oe;
 
sram_ce <= sram_cs;
sram_ub <= not cpu_addr(0);
sram_lb <= cpu_addr(0);
sram_ce_n <= not sram_ce;
sram_ub_n <= not sram_ub;
sram_lb_n <= not sram_lb;
 
sram_addr(17 downto 11) <= dat_addr(6 downto 0);
sram_addr(10 downto 0) <= cpu_addr(11 downto 1);
 
if sram_we = '1' and sram_ce = '1' and sram_lb = '1' then
sram_dq(7 downto 0) <= cpu_data_out;
else
sram_dq(7 downto 0) <= "ZZZZZZZZ";
end if;
 
if sram_we = '1' and sram_ce = '1' and sram_ub = '1' then
sram_dq(15 downto 8) <= cpu_data_out;
else
sram_dq(15 downto 8) <= "ZZZZZZZZ";
end if;
 
if cpu_addr(0) = '0' then
sram_data_out <= sram_dq(15 downto 8);
else
sram_data_out <= sram_dq(7 downto 0);
end if;
end process;
 
--
-- LEDS output register
--
led_output : process( cpu_clk, cpu_rst, led_cs, cpu_rw, cpu_addr, cpu_data_out, sw )
begin
if cpu_clk'event and cpu_clk='0' then
if cpu_rst = '1' then
ledr <= (others=>'0');
ledg <= (others=>'0');
else
if led_cs = '1' and cpu_rw = '0' then
if cpu_addr(0) = '0' then
ledr(7 downto 0) <= cpu_data_out;
else
ledg(7 downto 0) <= cpu_data_out;
end if;
end if;
end if;
end if;
led_data_out <= sw(7 downto 0);
end process;
 
--
-- 7 segment HEX display output register
--
hex_output : process( cpu_clk, cpu_rst, hex_cs, cpu_rw, cpu_addr, cpu_data_out,
hex0_reg, hex1_reg, hex2_reg, hex3_reg )
begin
if cpu_clk'event and cpu_clk='0' then
if cpu_rst = '1' then
hex0_reg <= (others=>'0');
hex1_reg <= (others=>'0');
hex2_reg <= (others=>'0');
hex3_reg <= (others=>'0');
else
if hex_cs = '1' and cpu_rw = '0' then
case cpu_addr(1 downto 0) is
when "00" =>
hex0_reg <= cpu_data_out;
when "01" =>
hex1_reg <= cpu_data_out;
when "10" =>
hex2_reg <= cpu_data_out;
when "11" =>
hex3_reg <= cpu_data_out;
end case;
end if;
end if;
end if;
 
case cpu_addr(1 downto 0) is
when "00" =>
hex_data_out <= hex0_reg;
when "01" =>
hex_data_out <= hex1_reg;
when "10" =>
hex_data_out <= hex2_reg;
when "11" =>
hex_data_out <= hex3_reg;
end case;
 
hex0 <= not hex0_reg(6 downto 0);
hex1 <= not hex1_reg(6 downto 0);
hex2 <= not hex2_reg(6 downto 0);
hex3 <= not hex3_reg(6 downto 0);
end process;
 
--
-- Interrupts and other bus control signals
--
interrupts : process( key, pll_locked,
acia_irq, kbd_irq, hbp_irq, tmr_irq )
begin
cpu_rst <= not key(0); -- CPU reset is active high
cpu_firq <= kbd_irq;
cpu_nmi <= (not key(1)) or hbp_irq;
cpu_irq <= acia_irq or tmr_irq;
cpu_halt <= '0';
cpu_hold <= '0';
end process;
 
--
-- ACIA pin assignments
--
acia_assignments : process( uart_rxd, acia_txd )
begin
acia_dcd_n <= '0';
acia_cts_n <= '0';
acia_rxd <= uart_rxd;
uart_txd <= acia_txd;
end process;
 
--
-- assign vga colour bits to single bit RGB output of VDU
--
vga_assignments : process( vga_red, vga_green, vga_blue )
begin
vga_r <= (others=>vga_red);
vga_g <= (others=>vga_green);
vga_b <= (others=>vga_blue);
end process;
 
--
-- assign dram signals
--
dram_assign : process( all )
begin
dram_addr <= (others=>'0');
dram_cs_n <= '1';
dram_ras_n <= '1';
dram_cas_n <= '1';
dram_we_n <= '1';
end process;
 
--
-- assign flash memory signals
--
flash_assign : process( all )
begin
fl_addr <= (others=>'0');
fl_oe_n <= '1';
fl_we_n <= '1';
end process;
 
end my_computer; --===================== End of architecture =======================--
 
/System09/trunk/rtl/System09_Terasic_DE1/system09.pof Cannot display: file marked as a binary type. svn:mime-type = application/octet-stream
System09/trunk/rtl/System09_Terasic_DE1/system09.pof Property changes : Added: svn:mime-type ## -0,0 +1 ## +application/octet-stream \ No newline at end of property Index: System09/trunk/rtl/System09_Terasic_DE1/system09.pin =================================================================== --- System09/trunk/rtl/System09_Terasic_DE1/system09.pin (nonexistent) +++ System09/trunk/rtl/System09_Terasic_DE1/system09.pin (revision 117) @@ -0,0 +1,557 @@ + -- Copyright (C) 1991-2010 Altera Corporation + -- Your use of Altera Corporation's design tools, logic functions + -- and other software and tools, and its AMPP partner logic + -- functions, and any output files from any of the foregoing + -- (including device programming or simulation files), and any + -- associated documentation or information are expressly subject + -- to the terms and conditions of the Altera Program License + -- Subscription Agreement, Altera MegaCore Function License + -- Agreement, or other applicable license agreement, including, + -- without limitation, that your use is for the sole purpose of + -- programming logic devices manufactured by Altera and sold by + -- Altera or its authorized distributors. Please refer to the + -- applicable agreement for further details. + -- + -- This is a Quartus II output file. It is for reporting purposes only, and is + -- not intended for use as a Quartus II input file. This file cannot be used + -- to make Quartus II pin assignments - for instructions on how to make pin + -- assignments, please see Quartus II help. + --------------------------------------------------------------------------------- + + + + --------------------------------------------------------------------------------- + -- NC : No Connect. This pin has no internal connection to the device. + -- DNU : Do Not Use. This pin MUST NOT be connected. + -- VCCINT : Dedicated power pin, which MUST be connected to VCC (1.2V). + -- VCCIO : Dedicated power pin, which MUST be connected to VCC + -- of its bank. + -- Bank 1: 3.3V + -- Bank 2: 3.3V + -- Bank 3: 3.3V + -- Bank 4: 3.3V + -- Bank 5: 3.3V + -- Bank 6: 3.3V + -- Bank 7: 3.3V + -- Bank 8: 3.3V + -- GND : Dedicated ground pin. Dedicated GND pins MUST be connected to GND. + -- It can also be used to report unused dedicated pins. The connection + -- on the board for unused dedicated pins depends on whether this will + -- be used in a future design. One example is device migration. When + -- using device migration, refer to the device pin-tables. If it is a + -- GND pin in the pin table or if it will not be used in a future design + -- for another purpose the it MUST be connected to GND. If it is an unused + -- dedicated pin, then it can be connected to a valid signal on the board + -- (low, high, or toggling) if that signal is required for a different + -- revision of the design. + -- GND+ : Unused input pin. It can also be used to report unused dual-purpose pins. + -- This pin should be connected to GND. It may also be connected to a + -- valid signal on the board (low, high, or toggling) if that signal + -- is required for a different revision of the design. + -- GND* : Unused I/O pin. For transceiver I/O banks, connect each pin marked GND* + -- either individually through a 10k Ohm resistor to GND or tie all pins + -- together and connect through a single 10k Ohm resistor to GND. + -- For non-transceiver I/O banks, connect each pin marked GND* directly to GND + -- or leave it unconnected. + -- RESERVED : Unused I/O pin, which MUST be left unconnected. + -- RESERVED_INPUT : Pin is tri-stated and should be connected to the board. + -- RESERVED_INPUT_WITH_WEAK_PULLUP : Pin is tri-stated with internal weak pull-up resistor. + -- RESERVED_INPUT_WITH_BUS_HOLD : Pin is tri-stated with bus-hold circuitry. + -- RESERVED_OUTPUT_DRIVEN_HIGH : Pin is output driven high. + --------------------------------------------------------------------------------- + + + + --------------------------------------------------------------------------------- + -- Pin directions (input, output or bidir) are based on device operating in user mode. + --------------------------------------------------------------------------------- + +Quartus II Version 9.1 Build 304 01/25/2010 Service Pack 1 SJ Web Edition +CHIP "system09" ASSIGNED TO AN: EP2C20F484C7 + +Pin Name/Usage : Location : Dir. : I/O Standard : Voltage : I/O Bank : User Assignment +------------------------------------------------------------------------------------------------------------- +GND : A1 : gnd : : : : +VCCIO3 : A2 : power : : 3.3V : 3 : +i2c_sclk : A3 : input : 3.3-V LVTTL : : 3 : Y +aud_bclk : A4 : input : 3.3-V LVTTL : : 3 : Y +aud_daclrck : A5 : input : 3.3-V LVTTL : : 3 : Y +aud_adclrck : A6 : input : 3.3-V LVTTL : : 3 : Y +vga_r[2] : A7 : output : 3.3-V LVTTL : : 3 : Y +vga_g[3] : A8 : output : 3.3-V LVTTL : : 3 : Y +vga_b[0] : A9 : output : 3.3-V LVTTL : : 3 : Y +vga_b[2] : A10 : output : 3.3-V LVTTL : : 3 : Y +vga_hs : A11 : output : 3.3-V LVTTL : : 3 : Y +clock_24[1] : A12 : input : 3.3-V LVTTL : : 4 : Y +gpio_0[0] : A13 : input : 3.3-V LVTTL : : 4 : Y +gpio_0[2] : A14 : input : 3.3-V LVTTL : : 4 : Y +gpio_0[4] : A15 : input : 3.3-V LVTTL : : 4 : Y +gpio_0[6] : A16 : input : 3.3-V LVTTL : : 4 : Y +gpio_0[8] : A17 : input : 3.3-V LVTTL : : 4 : Y +gpio_0[10] : A18 : input : 3.3-V LVTTL : : 4 : Y +gpio_0[12] : A19 : input : 3.3-V LVTTL : : 4 : Y +gpio_0[14] : A20 : input : 3.3-V LVTTL : : 4 : Y +VCCIO4 : A21 : power : : 3.3V : 4 : +GND : A22 : gnd : : : : +VCCIO1 : AA1 : power : : 3.3V : 1 : +GND : AA2 : gnd : : : : +sram_addr[0] : AA3 : output : 3.3-V LVTTL : : 8 : Y +sram_addr[2] : AA4 : output : 3.3-V LVTTL : : 8 : Y +sram_addr[4] : AA5 : output : 3.3-V LVTTL : : 8 : Y +sram_dq[0] : AA6 : bidir : 3.3-V LVTTL : : 8 : Y +sram_dq[2] : AA7 : bidir : 3.3-V LVTTL : : 8 : Y +sram_dq[4] : AA8 : bidir : 3.3-V LVTTL : : 8 : Y +sram_dq[6] : AA9 : bidir : 3.3-V LVTTL : : 8 : Y +sram_we_n : AA10 : output : 3.3-V LVTTL : : 8 : Y +sram_addr[6] : AA11 : output : 3.3-V LVTTL : : 8 : Y +fl_addr[15] : AA12 : output : 3.3-V LVTTL : : 7 : Y +fl_addr[13] : AA13 : output : 3.3-V LVTTL : : 7 : Y +fl_addr[1] : AA14 : output : 3.3-V LVTTL : : 7 : Y +fl_oe_n : AA15 : output : 3.3-V LVTTL : : 7 : Y +fl_dq[1] : AA16 : input : 3.3-V LVTTL : : 7 : Y +fl_dq[3] : AA17 : input : 3.3-V LVTTL : : 7 : Y +fl_dq[5] : AA18 : input : 3.3-V LVTTL : : 7 : Y +fl_dq[7] : AA19 : input : 3.3-V LVTTL : : 7 : Y +fl_addr[17] : AA20 : output : 3.3-V LVTTL : : 7 : Y +GND : AA21 : gnd : : : : +VCCIO6 : AA22 : power : : 3.3V : 6 : +GND : AB1 : gnd : : : : +VCCIO8 : AB2 : power : : 3.3V : 8 : +sram_addr[1] : AB3 : output : 3.3-V LVTTL : : 8 : Y +sram_addr[3] : AB4 : output : 3.3-V LVTTL : : 8 : Y +sram_ce_n : AB5 : output : 3.3-V LVTTL : : 8 : Y +sram_dq[1] : AB6 : bidir : 3.3-V LVTTL : : 8 : Y +sram_dq[3] : AB7 : bidir : 3.3-V LVTTL : : 8 : Y +sram_dq[5] : AB8 : bidir : 3.3-V LVTTL : : 8 : Y +sram_dq[7] : AB9 : bidir : 3.3-V LVTTL : : 8 : Y +sram_addr[5] : AB10 : output : 3.3-V LVTTL : : 8 : Y +sram_addr[7] : AB11 : output : 3.3-V LVTTL : : 8 : Y +fl_addr[16] : AB12 : output : 3.3-V LVTTL : : 7 : Y +fl_addr[14] : AB13 : output : 3.3-V LVTTL : : 7 : Y +fl_addr[12] : AB14 : output : 3.3-V LVTTL : : 7 : Y +RESERVED_INPUT : AB15 : : : : 7 : +fl_dq[0] : AB16 : input : 3.3-V LVTTL : : 7 : Y +fl_dq[2] : AB17 : input : 3.3-V LVTTL : : 7 : Y +fl_dq[4] : AB18 : input : 3.3-V LVTTL : : 7 : Y +fl_dq[6] : AB19 : input : 3.3-V LVTTL : : 7 : Y +fl_addr[0] : AB20 : output : 3.3-V LVTTL : : 7 : Y +VCCIO7 : AB21 : power : : 3.3V : 7 : +GND : AB22 : gnd : : : : +VCCIO2 : B1 : power : : 3.3V : 2 : +GND : B2 : gnd : : : : +i2c_sdat : B3 : input : 3.3-V LVTTL : : 3 : Y +aud_xck : B4 : input : 3.3-V LVTTL : : 3 : Y +aud_dacdat : B5 : input : 3.3-V LVTTL : : 3 : Y +aud_adcdat : B6 : input : 3.3-V LVTTL : : 3 : Y +vga_r[3] : B7 : output : 3.3-V LVTTL : : 3 : Y +vga_g[0] : B8 : output : 3.3-V LVTTL : : 3 : Y +vga_g[2] : B9 : output : 3.3-V LVTTL : : 3 : Y +vga_b[3] : B10 : output : 3.3-V LVTTL : : 3 : Y +vga_vs : B11 : output : 3.3-V LVTTL : : 3 : Y +clock_24[0] : B12 : input : 3.3-V LVTTL : : 4 : Y +gpio_0[1] : B13 : input : 3.3-V LVTTL : : 4 : Y +gpio_0[3] : B14 : input : 3.3-V LVTTL : : 4 : Y +gpio_0[5] : B15 : input : 3.3-V LVTTL : : 4 : Y +gpio_0[7] : B16 : input : 3.3-V LVTTL : : 4 : Y +gpio_0[9] : B17 : input : 3.3-V LVTTL : : 4 : Y +gpio_0[11] : B18 : input : 3.3-V LVTTL : : 4 : Y +gpio_0[13] : B19 : input : 3.3-V LVTTL : : 4 : Y +gpio_0[15] : B20 : input : 3.3-V LVTTL : : 4 : Y +GND : B21 : gnd : : : : +VCCIO5 : B22 : power : : 3.3V : 5 : +hex2[3] : C1 : output : 3.3-V LVTTL : : 2 : Y +hex2[2] : C2 : output : 3.3-V LVTTL : : 2 : Y +~nCSO~ / RESERVED_INPUT_WITH_WEAK_PULLUP : C3 : input : 3.3-V LVTTL : : 2 : N +~ASDO~ / RESERVED_INPUT_WITH_WEAK_PULLUP : C4 : input : 3.3-V LVTTL : : 2 : N +GND : C5 : gnd : : : : +VCCIO3 : C6 : power : : 3.3V : 3 : +tck : C7 : input : 3.3-V LVTTL : : 3 : Y +GND : C8 : gnd : : : : +vga_r[1] : C9 : output : 3.3-V LVTTL : : 3 : Y +vga_g[1] : C10 : output : 3.3-V LVTTL : : 3 : Y +VCCIO3 : C11 : power : : 3.3V : 3 : +VCCIO4 : C12 : power : : 3.3V : 4 : +RESERVED_INPUT : C13 : : : : 4 : +gpio_1[10] : C14 : input : 3.3-V LVTTL : : 4 : Y +GND : C15 : gnd : : : : +RESERVED_INPUT : C16 : : : : 4 : +gpio_1[14] : C17 : input : 3.3-V LVTTL : : 4 : Y +gpio_1[15] : C18 : input : 3.3-V LVTTL : : 4 : Y +gpio_1[16] : C19 : input : 3.3-V LVTTL : : 5 : Y +gpio_1[17] : C20 : input : 3.3-V LVTTL : : 5 : Y +gpio_0[16] : C21 : input : 3.3-V LVTTL : : 5 : Y +gpio_0[17] : C22 : input : 3.3-V LVTTL : : 5 : Y +hex1[6] : D1 : output : 3.3-V LVTTL : : 2 : Y +hex1[5] : D2 : output : 3.3-V LVTTL : : 2 : Y +hex2[6] : D3 : output : 3.3-V LVTTL : : 2 : Y +hex3[6] : D4 : output : 3.3-V LVTTL : : 2 : Y +hex3[1] : D5 : output : 3.3-V LVTTL : : 2 : Y +hex3[2] : D6 : output : 3.3-V LVTTL : : 2 : Y +tdo : D7 : input : 3.3-V LVTTL : : 3 : Y +tcs : D8 : input : 3.3-V LVTTL : : 3 : Y +vga_r[0] : D9 : output : 3.3-V LVTTL : : 3 : Y +GND : D10 : gnd : : : : +vga_b[1] : D11 : output : 3.3-V LVTTL : : 3 : Y +clock_27 : D12 : input : 3.3-V LVTTL : : 3 : Y +GND : D13 : gnd : : : : +gpio_1[11] : D14 : input : 3.3-V LVTTL : : 4 : Y +gpio_1[12] : D15 : input : 3.3-V LVTTL : : 4 : Y +gpio_1[13] : D16 : input : 3.3-V LVTTL : : 4 : Y +VCCIO4 : D17 : power : : 3.3V : 4 : +GND : D18 : gnd : : : : +gpio_1[18] : D19 : input : 3.3-V LVTTL : : 5 : Y +gpio_1[19] : D20 : input : 3.3-V LVTTL : : 5 : Y +gpio_0[18] : D21 : input : 3.3-V LVTTL : : 5 : Y +gpio_0[19] : D22 : input : 3.3-V LVTTL : : 5 : Y +hex1[0] : E1 : output : 3.3-V LVTTL : : 2 : Y +hex0[6] : E2 : output : 3.3-V LVTTL : : 2 : Y +hex2[4] : E3 : output : 3.3-V LVTTL : : 2 : Y +hex2[5] : E4 : output : 3.3-V LVTTL : : 2 : Y +VCCD_PLL3 : E5 : power : : 1.2V : : +VCCA_PLL3 : E6 : power : : 1.2V : : +RESERVED_INPUT : E7 : : : : 3 : +tdi : E8 : input : 3.3-V LVTTL : : 3 : Y +RESERVED_INPUT : E9 : : : : 3 : +VCCIO3 : E10 : power : : 3.3V : 3 : +RESERVED_INPUT : E11 : : : : 3 : +GND+ : E12 : : : : 3 : +VCCIO4 : E13 : power : : 3.3V : 4 : +gpio_1[4] : E14 : input : 3.3-V LVTTL : : 4 : Y +gpio_1[5] : E15 : input : 3.3-V LVTTL : : 4 : Y +GNDA_PLL2 : E16 : gnd : : : : +GND_PLL2 : E17 : gnd : : : : +gpio_1[23] : E18 : input : 3.3-V LVTTL : : 5 : Y +gpio_1[22] : E19 : input : 3.3-V LVTTL : : 5 : Y +gpio_1[20] : E20 : input : 3.3-V LVTTL : : 5 : Y +gpio_0[20] : E21 : input : 3.3-V LVTTL : : 5 : Y +gpio_0[21] : E22 : input : 3.3-V LVTTL : : 5 : Y +hex0[5] : F1 : output : 3.3-V LVTTL : : 2 : Y +hex0[4] : F2 : output : 3.3-V LVTTL : : 2 : Y +hex3[5] : F3 : output : 3.3-V LVTTL : : 2 : Y +hex3[0] : F4 : output : 3.3-V LVTTL : : 2 : Y +GND_PLL3 : F5 : gnd : : : : +GND_PLL3 : F6 : gnd : : : : +GNDA_PLL3 : F7 : gnd : : : : +RESERVED_INPUT : F8 : : : : 3 : +RESERVED_INPUT : F9 : : : : 3 : +RESERVED_INPUT : F10 : : : : 3 : +RESERVED_INPUT : F11 : : : : 3 : +gpio_1[8] : F12 : input : 3.3-V LVTTL : : 4 : Y +gpio_1[9] : F13 : input : 3.3-V LVTTL : : 4 : Y +uart_rxd : F14 : input : 3.3-V LVTTL : : 4 : Y +gpio_1[6] : F15 : input : 3.3-V LVTTL : : 4 : Y +VCCA_PLL2 : F16 : power : : 1.2V : : +VCCD_PLL2 : F17 : power : : 1.2V : : +GND_PLL2 : F18 : gnd : : : : +GND : F19 : gnd : : : : +gpio_1[21] : F20 : input : 3.3-V LVTTL : : 5 : Y +gpio_0[22] : F21 : input : 3.3-V LVTTL : : 5 : Y +gpio_0[23] : F22 : input : 3.3-V LVTTL : : 5 : Y +NC : G1 : : : : : +NC : G2 : : : : : +hex1[4] : G3 : output : 3.3-V LVTTL : : 2 : Y +GND : G4 : gnd : : : : +hex2[0] : G5 : output : 3.3-V LVTTL : : 2 : Y +hex2[1] : G6 : output : 3.3-V LVTTL : : 2 : Y +RESERVED_INPUT : G7 : : : : 3 : +RESERVED_INPUT : G8 : : : : 3 : +VCCIO3 : G9 : power : : 3.3V : 3 : +GND : G10 : gnd : : : : +RESERVED_INPUT : G11 : : : : 3 : +uart_txd : G12 : output : 3.3-V LVTTL : : 4 : Y +GND : G13 : gnd : : : : +VCCIO4 : G14 : power : : 3.3V : 4 : +gpio_1[3] : G15 : input : 3.3-V LVTTL : : 4 : Y +gpio_1[7] : G16 : input : 3.3-V LVTTL : : 4 : Y +gpio_1[26] : G17 : input : 3.3-V LVTTL : : 5 : Y +gpio_1[25] : G18 : input : 3.3-V LVTTL : : 5 : Y +VCCIO5 : G19 : power : : 3.3V : 5 : +gpio_1[24] : G20 : input : 3.3-V LVTTL : : 5 : Y +gpio_0[24] : G21 : input : 3.3-V LVTTL : : 5 : Y +gpio_0[25] : G22 : input : 3.3-V LVTTL : : 5 : Y +hex0[3] : H1 : output : 3.3-V LVTTL : : 2 : Y +hex0[2] : H2 : output : 3.3-V LVTTL : : 2 : Y +RESERVED_INPUT : H3 : : : : 2 : +hex1[3] : H4 : output : 3.3-V LVTTL : : 2 : Y +hex1[2] : H5 : output : 3.3-V LVTTL : : 2 : Y +hex1[1] : H6 : output : 3.3-V LVTTL : : 2 : Y +RESERVED_INPUT : H7 : : : : 3 : +RESERVED_INPUT : H8 : : : : 3 : +RESERVED_INPUT : H9 : : : : 3 : +RESERVED_INPUT : H10 : : : : 3 : +RESERVED_INPUT : H11 : : : : 3 : +gpio_1[0] : H12 : input : 3.3-V LVTTL : : 4 : Y +gpio_1[1] : H13 : input : 3.3-V LVTTL : : 4 : Y +gpio_1[2] : H14 : input : 3.3-V LVTTL : : 4 : Y +ps2_clk : H15 : bidir : 3.3-V LVTTL : : 4 : Y +RESERVED_INPUT : H16 : : : : 5 : +gpio_1[27] : H17 : input : 3.3-V LVTTL : : 5 : Y +gpio_1[29] : H18 : input : 3.3-V LVTTL : : 5 : Y +RESERVED_INPUT : H19 : : : : 5 : +GND : H20 : gnd : : : : +NC : H21 : : : : : +NC : H22 : : : : : +hex0[1] : J1 : output : 3.3-V LVTTL : : 2 : Y +hex0[0] : J2 : output : 3.3-V LVTTL : : 2 : Y +NC : J3 : : : : : +hex3[3] : J4 : output : 3.3-V LVTTL : : 2 : Y +NC : J5 : : : : : +NC : J6 : : : : : +VCCIO2 : J7 : power : : 3.3V : 2 : +NC : J8 : : : : : +NC : J9 : : : : : +VCCINT : J10 : power : : 1.2V : : +VCCINT : J11 : power : : 1.2V : : +VCCINT : J12 : power : : 1.2V : : +VCCINT : J13 : power : : 1.2V : : +ps2_dat : J14 : bidir : 3.3-V LVTTL : : 4 : Y +gpio_1[28] : J15 : input : 3.3-V LVTTL : : 5 : Y +VCCIO5 : J16 : power : : 3.3V : 5 : +RESERVED_INPUT : J17 : : : : 5 : +gpio_0[32] : J18 : input : 3.3-V LVTTL : : 5 : Y +gpio_0[30] : J19 : input : 3.3-V LVTTL : : 5 : Y +gpio_0[31] : J20 : input : 3.3-V LVTTL : : 5 : Y +gpio_0[26] : J21 : input : 3.3-V LVTTL : : 5 : Y +gpio_0[27] : J22 : input : 3.3-V LVTTL : : 5 : Y +nCE : K1 : : : : 2 : +TCK : K2 : input : : : 2 : +GND : K3 : gnd : : : : +DATA0 : K4 : input : : : 2 : +TDI : K5 : input : : : 2 : +TMS : K6 : input : : : 2 : +GND : K7 : gnd : : : : +NC : K8 : : : : : +VCCINT : K9 : power : : 1.2V : : +GND : K10 : gnd : : : : +GND : K11 : gnd : : : : +GND : K12 : gnd : : : : +GND : K13 : gnd : : : : +VCCINT : K14 : power : : 1.2V : : +NC : K15 : : : : : +GND : K16 : gnd : : : : +NC : K17 : : : : : +NC : K18 : : : : : +GND : K19 : gnd : : : : +gpio_0[33] : K20 : input : 3.3-V LVTTL : : 5 : Y +gpio_0[28] : K21 : input : 3.3-V LVTTL : : 5 : Y +gpio_0[29] : K22 : input : 3.3-V LVTTL : : 5 : Y +clock_50 : L1 : input : 3.3-V LVTTL : : 2 : Y +sw[9] : L2 : input : 3.3-V LVTTL : : 2 : Y +VCCIO2 : L3 : power : : 3.3V : 2 : +nCONFIG : L4 : : : : 2 : +TDO : L5 : output : : : 2 : +DCLK : L6 : : : : 2 : +NC : L7 : : : : : +hex3[4] : L8 : output : 3.3-V LVTTL : : 2 : Y +VCCINT : L9 : power : : 1.2V : : +GND : L10 : gnd : : : : +GND : L11 : gnd : : : : +GND : L12 : gnd : : : : +GND : L13 : gnd : : : : +VCCINT : L14 : power : : 1.2V : : +NC : L15 : : : : : +NC : L16 : : : : : +NC : L17 : : : : : +gpio_0[35] : L18 : input : 3.3-V LVTTL : : 5 : Y +gpio_0[34] : L19 : input : 3.3-V LVTTL : : 5 : Y +VCCIO5 : L20 : power : : 3.3V : 5 : +sw[1] : L21 : input : 3.3-V LVTTL : : 5 : Y +sw[0] : L22 : input : 3.3-V LVTTL : : 5 : Y +sw[8] : M1 : input : 3.3-V LVTTL : : 1 : Y +sw[7] : M2 : input : 3.3-V LVTTL : : 1 : Y +VCCIO1 : M3 : power : : 3.3V : 1 : +GND : M4 : gnd : : : : +dram_udqm : M5 : input : 3.3-V LVTTL : : 1 : Y +RESERVED_INPUT : M6 : : : : 1 : +NC : M7 : : : : : +NC : M8 : : : : : +VCCINT : M9 : power : : 1.2V : : +GND : M10 : gnd : : : : +GND : M11 : gnd : : : : +GND : M12 : gnd : : : : +GND : M13 : gnd : : : : +VCCINT : M14 : power : : 1.2V : : +NC : M15 : : : : : +NC : M16 : : : : : +MSEL0 : M17 : : : : 6 : +RESERVED_INPUT : M18 : : : : 6 : +RESERVED_INPUT : M19 : : : : 6 : +VCCIO6 : M20 : power : : 3.3V : 6 : +ext_clock : M21 : input : 3.3-V LVTTL : : 6 : Y +sw[2] : M22 : input : 3.3-V LVTTL : : 6 : Y +dram_dq[8] : N1 : input : 3.3-V LVTTL : : 1 : Y +dram_dq[9] : N2 : input : 3.3-V LVTTL : : 1 : Y +dram_cke : N3 : input : 3.3-V LVTTL : : 1 : Y +dram_addr[9] : N4 : output : 3.3-V LVTTL : : 1 : Y +NC : N5 : : : : : +dram_addr[11] : N6 : output : 3.3-V LVTTL : : 1 : Y +GND : N7 : gnd : : : : +NC : N8 : : : : : +VCCINT : N9 : power : : 1.2V : : +GND : N10 : gnd : : : : +GND : N11 : gnd : : : : +GND : N12 : gnd : : : : +GND : N13 : gnd : : : : +VCCINT : N14 : power : : 1.2V : : +gpio_1[33] : N15 : input : 3.3-V LVTTL : : 6 : Y +GND : N16 : gnd : : : : +MSEL1 : N17 : : : : 6 : +CONF_DONE : N18 : : : : 6 : +GND : N19 : gnd : : : : +nSTATUS : N20 : : : : 6 : +gpio_1[31] : N21 : input : 3.3-V LVTTL : : 6 : Y +gpio_1[30] : N22 : input : 3.3-V LVTTL : : 6 : Y +dram_dq[10] : P1 : input : 3.3-V LVTTL : : 1 : Y +dram_dq[11] : P2 : input : 3.3-V LVTTL : : 1 : Y +dram_addr[8] : P3 : output : 3.3-V LVTTL : : 1 : Y +NC : P4 : : : : : +dram_addr[7] : P5 : output : 3.3-V LVTTL : : 1 : Y +dram_addr[6] : P6 : output : 3.3-V LVTTL : : 1 : Y +VCCIO1 : P7 : power : : 3.3V : 1 : +RESERVED_INPUT : P8 : : : : 8 : +RESERVED_INPUT : P9 : : : : 8 : +VCCINT : P10 : power : : 1.2V : : +VCCINT : P11 : power : : 1.2V : : +VCCINT : P12 : power : : 1.2V : : +VCCINT : P13 : power : : 1.2V : : +NC : P14 : : : : : +gpio_1[32] : P15 : input : 3.3-V LVTTL : : 6 : Y +VCCIO6 : P16 : power : : 3.3V : 6 : +gpio_1[34] : P17 : input : 3.3-V LVTTL : : 6 : Y +gpio_1[35] : P18 : input : 3.3-V LVTTL : : 6 : Y +NC : P19 : : : : : +NC : P20 : : : : : +NC : P21 : : : : : +NC : P22 : : : : : +dram_dq[12] : R1 : input : 3.3-V LVTTL : : 1 : Y +dram_dq[13] : R2 : input : 3.3-V LVTTL : : 1 : Y +GND : R3 : gnd : : : : +NC : R4 : : : : : +dram_addr[5] : R5 : output : 3.3-V LVTTL : : 1 : Y +dram_addr[4] : R6 : output : 3.3-V LVTTL : : 1 : Y +dram_ldqm : R7 : input : 3.3-V LVTTL : : 1 : Y +dram_we_n : R8 : output : 3.3-V LVTTL : : 1 : Y +sram_dq[12] : R9 : bidir : 3.3-V LVTTL : : 8 : Y +sram_addr[14] : R10 : output : 3.3-V LVTTL : : 8 : Y +sram_addr[10] : R11 : output : 3.3-V LVTTL : : 8 : Y +fl_addr[10] : R12 : output : 3.3-V LVTTL : : 7 : Y +fl_addr[21] : R13 : output : 3.3-V LVTTL : : 7 : Y +fl_addr[8] : R14 : output : 3.3-V LVTTL : : 7 : Y +fl_addr[3] : R15 : output : 3.3-V LVTTL : : 7 : Y +RESERVED_INPUT : R16 : : : : 7 : +ledr[9] : R17 : output : 3.3-V LVTTL : : 6 : Y +ledr[8] : R18 : output : 3.3-V LVTTL : : 6 : Y +ledr[1] : R19 : output : 3.3-V LVTTL : : 6 : Y +ledr[0] : R20 : output : 3.3-V LVTTL : : 6 : Y +key[1] : R21 : input : 3.3-V LVTTL : : 6 : Y +key[0] : R22 : input : 3.3-V LVTTL : : 6 : Y +dram_dq[14] : T1 : input : 3.3-V LVTTL : : 1 : Y +dram_dq[15] : T2 : input : 3.3-V LVTTL : : 1 : Y +dram_cas_n : T3 : output : 3.3-V LVTTL : : 1 : Y +VCCIO1 : T4 : power : : 3.3V : 1 : +dram_ras_n : T5 : output : 3.3-V LVTTL : : 1 : Y +dram_cs_n : T6 : output : 3.3-V LVTTL : : 1 : Y +sram_addr[15] : T7 : output : 3.3-V LVTTL : : 8 : Y +sram_oe_n : T8 : output : 3.3-V LVTTL : : 8 : Y +VCCIO8 : T9 : power : : 3.3V : 8 : +GND : T10 : gnd : : : : +sram_addr[11] : T11 : output : 3.3-V LVTTL : : 8 : Y +fl_addr[11] : T12 : output : 3.3-V LVTTL : : 7 : Y +GND : T13 : gnd : : : : +VCCIO7 : T14 : power : : 3.3V : 7 : +fl_addr[4] : T15 : output : 3.3-V LVTTL : : 7 : Y +RESERVED_INPUT : T16 : : : : 7 : +GND_PLL4 : T17 : gnd : : : : +ledr[4] : T18 : output : 3.3-V LVTTL : : 6 : Y +VCCIO6 : T19 : power : : 3.3V : 6 : +GND : T20 : gnd : : : : +key[3] : T21 : input : 3.3-V LVTTL : : 6 : Y +key[2] : T22 : input : 3.3-V LVTTL : : 6 : Y +dram_dq[0] : U1 : input : 3.3-V LVTTL : : 1 : Y +dram_dq[1] : U2 : input : 3.3-V LVTTL : : 1 : Y +dram_ba_0 : U3 : input : 3.3-V LVTTL : : 1 : Y +dram_clk : U4 : input : 3.3-V LVTTL : : 1 : Y +GND_PLL1 : U5 : gnd : : : : +VCCD_PLL1 : U6 : power : : 1.2V : : +VCCA_PLL1 : U7 : power : : 1.2V : : +sram_dq[15] : U8 : bidir : 3.3-V LVTTL : : 8 : Y +sram_dq[11] : U9 : bidir : 3.3-V LVTTL : : 8 : Y +sram_addr[13] : U10 : output : 3.3-V LVTTL : : 8 : Y +sw[6] : U11 : input : 3.3-V LVTTL : : 8 : Y +sw[5] : U12 : input : 3.3-V LVTTL : : 8 : Y +fl_addr[20] : U13 : output : 3.3-V LVTTL : : 7 : Y +fl_addr[18] : U14 : output : 3.3-V LVTTL : : 7 : Y +fl_addr[5] : U15 : output : 3.3-V LVTTL : : 7 : Y +VCCA_PLL4 : U16 : power : : 1.2V : : +VCCD_PLL4 : U17 : power : : 1.2V : : +ledr[7] : U18 : output : 3.3-V LVTTL : : 6 : Y +ledr[2] : U19 : output : 3.3-V LVTTL : : 6 : Y +RESERVED_INPUT : U20 : : : : 6 : +ledg[1] : U21 : output : 3.3-V LVTTL : : 6 : Y +ledg[0] : U22 : output : 3.3-V LVTTL : : 6 : Y +dram_dq[2] : V1 : input : 3.3-V LVTTL : : 1 : Y +dram_dq[3] : V2 : input : 3.3-V LVTTL : : 1 : Y +GND : V3 : gnd : : : : +dram_ba_1 : V4 : input : 3.3-V LVTTL : : 1 : Y +GND_PLL1 : V5 : gnd : : : : +GND : V6 : gnd : : : : +GNDA_PLL1 : V7 : gnd : : : : +sram_dq[14] : V8 : bidir : 3.3-V LVTTL : : 8 : Y +sram_dq[10] : V9 : bidir : 3.3-V LVTTL : : 8 : Y +VCCIO8 : V10 : power : : 3.3V : 8 : +sram_addr[8] : V11 : output : 3.3-V LVTTL : : 8 : Y +sw[3] : V12 : input : 3.3-V LVTTL : : 7 : Y +VCCIO7 : V13 : power : : 3.3V : 7 : +fl_addr[19] : V14 : output : 3.3-V LVTTL : : 7 : Y +fl_addr[6] : V15 : output : 3.3-V LVTTL : : 7 : Y +GNDA_PLL4 : V16 : gnd : : : : +GND : V17 : gnd : : : : +GND_PLL4 : V18 : gnd : : : : +ledr[5] : V19 : output : 3.3-V LVTTL : : 6 : Y +RESERVED_INPUT : V20 : : : : 6 : +ledg[3] : V21 : output : 3.3-V LVTTL : : 6 : Y +ledg[2] : V22 : output : 3.3-V LVTTL : : 6 : Y +dram_dq[4] : W1 : input : 3.3-V LVTTL : : 1 : Y +dram_dq[5] : W2 : input : 3.3-V LVTTL : : 1 : Y +dram_addr[10] : W3 : output : 3.3-V LVTTL : : 1 : Y +dram_addr[0] : W4 : output : 3.3-V LVTTL : : 1 : Y +dram_addr[1] : W5 : output : 3.3-V LVTTL : : 1 : Y +VCCIO8 : W6 : power : : 3.3V : 8 : +sram_ub_n : W7 : output : 3.3-V LVTTL : : 8 : Y +sram_dq[13] : W8 : bidir : 3.3-V LVTTL : : 8 : Y +sram_dq[9] : W9 : bidir : 3.3-V LVTTL : : 8 : Y +GND : W10 : gnd : : : : +sram_addr[9] : W11 : output : 3.3-V LVTTL : : 8 : Y +sw[4] : W12 : input : 3.3-V LVTTL : : 7 : Y +GND : W13 : gnd : : : : +fl_rst_n : W14 : input : 3.3-V LVTTL : : 7 : Y +fl_addr[7] : W15 : output : 3.3-V LVTTL : : 7 : Y +RESERVED_INPUT : W16 : : : : 7 : +VCCIO7 : W17 : power : : 3.3V : 7 : +NC : W18 : : : : : +GND : W19 : gnd : : : : +RESERVED_INPUT : W20 : : : : 6 : +ledg[5] : W21 : output : 3.3-V LVTTL : : 6 : Y +ledg[4] : W22 : output : 3.3-V LVTTL : : 6 : Y +dram_dq[6] : Y1 : input : 3.3-V LVTTL : : 1 : Y +dram_dq[7] : Y2 : input : 3.3-V LVTTL : : 1 : Y +dram_addr[2] : Y3 : output : 3.3-V LVTTL : : 1 : Y +dram_addr[3] : Y4 : output : 3.3-V LVTTL : : 1 : Y +sram_addr[17] : Y5 : output : 3.3-V LVTTL : : 8 : Y +sram_addr[16] : Y6 : output : 3.3-V LVTTL : : 8 : Y +sram_lb_n : Y7 : output : 3.3-V LVTTL : : 8 : Y +GND : Y8 : gnd : : : : +sram_dq[8] : Y9 : bidir : 3.3-V LVTTL : : 8 : Y +sram_addr[12] : Y10 : output : 3.3-V LVTTL : : 8 : Y +VCCIO8 : Y11 : power : : 3.3V : 8 : +VCCIO7 : Y12 : power : : 3.3V : 7 : +fl_addr[9] : Y13 : output : 3.3-V LVTTL : : 7 : Y +fl_we_n : Y14 : output : 3.3-V LVTTL : : 7 : Y +GND : Y15 : gnd : : : : +fl_addr[2] : Y16 : output : 3.3-V LVTTL : : 7 : Y +RESERVED_INPUT : Y17 : : : : 7 : +ledr[6] : Y18 : output : 3.3-V LVTTL : : 6 : Y +ledr[3] : Y19 : output : 3.3-V LVTTL : : 6 : Y +RESERVED_INPUT : Y20 : : : : 6 : +ledg[7] : Y21 : output : 3.3-V LVTTL : : 6 : Y +ledg[6] : Y22 : output : 3.3-V LVTTL : : 6 : Y Index: System09/trunk/rtl/System09_Terasic_DE1/system09.qpf =================================================================== --- System09/trunk/rtl/System09_Terasic_DE1/system09.qpf (nonexistent) +++ System09/trunk/rtl/System09_Terasic_DE1/system09.qpf (revision 117) @@ -0,0 +1,23 @@ +# Copyright (C) 1991-2005 Altera Corporation +# Your use of Altera Corporation's design tools, logic functions +# and other software and tools, and its AMPP partner logic +# functions, and any output files any of the foregoing +# (including device programming or simulation files), and any +# associated documentation or information are expressly subject +# to the terms and conditions of the Altera Program License +# Subscription Agreement, Altera MegaCore Function License +# Agreement, or other applicable license agreement, including, +# without limitation, that your use is for the sole purpose of +# programming logic devices manufactured by Altera and sold by +# Altera or its authorized distributors. Please refer to the +# applicable agreement for further details. + + + +QUARTUS_VERSION = "5.0" +DATE = "19:21:54 August 25, 2005" + + +# Revisions + +PROJECT_REVISION = "system09" Index: System09/trunk/rtl/System09_Terasic_DE1/system09.sof =================================================================== Cannot display: file marked as a binary type. svn:mime-type = application/octet-stream Index: System09/trunk/rtl/System09_Terasic_DE1/system09.sof =================================================================== --- System09/trunk/rtl/System09_Terasic_DE1/system09.sof (nonexistent) +++ System09/trunk/rtl/System09_Terasic_DE1/system09.sof (revision 117)
System09/trunk/rtl/System09_Terasic_DE1/system09.sof Property changes : Added: svn:mime-type ## -0,0 +1 ## +application/octet-stream \ No newline at end of property Index: System09/trunk/rtl/System09_Terasic_DE1/system09.qsf =================================================================== --- System09/trunk/rtl/System09_Terasic_DE1/system09.qsf (nonexistent) +++ System09/trunk/rtl/System09_Terasic_DE1/system09.qsf (revision 117) @@ -0,0 +1,544 @@ +# copyright (c) 1991-2005 altera corporation +# your use of altera corporation's design tools, logic functions +# and other software and tools, and its ampp partner logic +# functions, and any output files any of the foregoing +# (including device programming or simulation files), and any +# associated documentation or information are expressly subject +# to the terms and conditions of the altera program license +# subscription agreement, altera megacore function license +# agreement, or other applicable license agreement, including, +# without limitation, that your use is for the sole purpose of +# programming logic devices manufactured by altera and sold by +# altera or its authorized distributors. please refer to the +# applicable agreement for further details. + + +# the default values for assignments are stored in the file +# system09_assignment_defaults.qdf +# if this file doesn't exist, and for assignments not listed, see file +# assignment_defaults.qdf + +# altera recommends that you do not modify this file. this +# file is updated automatically by the quartus ii software +# and any changes you make may be lost or overwritten. + + +# project-wide assignments +# ======================== +set_global_assignment -name LAST_QUARTUS_VERSION "9.1 SP1" + +# pin & location assignments +# ========================== + +# analysis & synthesis assignments +# ================================ +set_global_assignment -name FAMILY "cyclone ii" +set_global_assignment -name TOP_LEVEL_ENTITY System09_Terasic_DE1 + +# fitter assignments +# ================== +set_global_assignment -name DEVICE ep2c20f484c7 +set_global_assignment -name CYCLONEII_RESERVE_NCEO_AFTER_CONFIGURATION "USE AS REGULAR IO" +set_global_assignment -name RESERVE_ALL_UNUSED_PINS "AS INPUT TRI-STATED" +set_global_assignment -name RESERVE_ASDO_AFTER_CONFIGURATION "AS INPUT TRI-STATED" + +# assembler assignments +# ===================== +set_global_assignment -name RESERVE_ALL_UNUSED_PINS_NO_OUTPUT_GND "AS OUTPUT DRIVING AN UNSPECIFIED SIGNAL" + +set_global_assignment -name SEED 1 +set_instance_assignment -name IO_STANDARD LVTTL -to aud_adcdat +set_instance_assignment -name IO_STANDARD LVTTL -to aud_adclrck +set_instance_assignment -name IO_STANDARD LVTTL -to aud_bclk +set_instance_assignment -name IO_STANDARD LVTTL -to aud_dacdat +set_instance_assignment -name IO_STANDARD LVTTL -to aud_daclrck +set_instance_assignment -name IO_STANDARD LVTTL -to aud_xck +set_instance_assignment -name IO_STANDARD LVTTL -to clock_24[0] +set_instance_assignment -name IO_STANDARD LVTTL -to clock_24[1] +# set_instance_assignment -name io_standard lvttl -to clock_27[1] +set_instance_assignment -name IO_STANDARD LVTTL -to clock_50 +set_instance_assignment -name IO_STANDARD LVTTL -to ext_clock +set_instance_assignment -name IO_STANDARD LVTTL -to gpio_0[0] +set_instance_assignment -name IO_STANDARD LVTTL -to gpio_0[10] +set_instance_assignment -name IO_STANDARD LVTTL -to gpio_0[11] +set_instance_assignment -name IO_STANDARD LVTTL -to gpio_0[12] +set_instance_assignment -name IO_STANDARD LVTTL -to gpio_0[13] +set_instance_assignment -name IO_STANDARD LVTTL -to gpio_0[14] +set_instance_assignment -name IO_STANDARD LVTTL -to gpio_0[15] +set_instance_assignment -name IO_STANDARD LVTTL -to gpio_0[16] +set_instance_assignment -name IO_STANDARD LVTTL -to gpio_0[17] +set_instance_assignment -name IO_STANDARD LVTTL -to gpio_0[18] +set_instance_assignment -name IO_STANDARD LVTTL -to gpio_0[19] +set_instance_assignment -name IO_STANDARD LVTTL -to gpio_0[1] +set_instance_assignment -name IO_STANDARD LVTTL -to gpio_0[20] +set_instance_assignment -name IO_STANDARD LVTTL -to gpio_0[21] +set_instance_assignment -name IO_STANDARD LVTTL -to gpio_0[22] +set_instance_assignment -name IO_STANDARD LVTTL -to gpio_0[23] +set_instance_assignment -name IO_STANDARD LVTTL -to gpio_0[24] +set_instance_assignment -name IO_STANDARD LVTTL -to gpio_0[25] +set_instance_assignment -name IO_STANDARD LVTTL -to gpio_0[26] +set_instance_assignment -name IO_STANDARD LVTTL -to gpio_0[27] +set_instance_assignment -name IO_STANDARD LVTTL -to gpio_0[28] +set_instance_assignment -name IO_STANDARD LVTTL -to gpio_0[29] +set_instance_assignment -name IO_STANDARD LVTTL -to gpio_0[2] +set_instance_assignment -name IO_STANDARD LVTTL -to gpio_0[30] +set_instance_assignment -name IO_STANDARD LVTTL -to gpio_0[31] +set_instance_assignment -name IO_STANDARD LVTTL -to gpio_0[32] +set_instance_assignment -name IO_STANDARD LVTTL -to gpio_0[33] +set_instance_assignment -name IO_STANDARD LVTTL -to gpio_0[34] +set_instance_assignment -name IO_STANDARD LVTTL -to gpio_0[35] +set_instance_assignment -name IO_STANDARD LVTTL -to gpio_0[3] +set_instance_assignment -name IO_STANDARD LVTTL -to gpio_0[4] +set_instance_assignment -name IO_STANDARD LVTTL -to gpio_0[5] +set_instance_assignment -name IO_STANDARD LVTTL -to gpio_0[6] +set_instance_assignment -name IO_STANDARD LVTTL -to gpio_0[7] +set_instance_assignment -name IO_STANDARD LVTTL -to gpio_0[8] +set_instance_assignment -name IO_STANDARD LVTTL -to gpio_0[9] +set_instance_assignment -name IO_STANDARD LVTTL -to gpio_1[0] +set_instance_assignment -name IO_STANDARD LVTTL -to gpio_1[10] +set_instance_assignment -name IO_STANDARD LVTTL -to gpio_1[11] +set_instance_assignment -name IO_STANDARD LVTTL -to gpio_1[12] +set_instance_assignment -name IO_STANDARD LVTTL -to gpio_1[13] +set_instance_assignment -name IO_STANDARD LVTTL -to gpio_1[14] +set_instance_assignment -name IO_STANDARD LVTTL -to gpio_1[15] +set_instance_assignment -name IO_STANDARD LVTTL -to gpio_1[16] +set_instance_assignment -name IO_STANDARD LVTTL -to gpio_1[17] +set_instance_assignment -name IO_STANDARD LVTTL -to gpio_1[18] +set_instance_assignment -name IO_STANDARD LVTTL -to gpio_1[19] +set_instance_assignment -name IO_STANDARD LVTTL -to gpio_1[1] +set_instance_assignment -name IO_STANDARD LVTTL -to gpio_1[20] +set_instance_assignment -name IO_STANDARD LVTTL -to gpio_1[21] +set_instance_assignment -name IO_STANDARD LVTTL -to gpio_1[22] +set_instance_assignment -name IO_STANDARD LVTTL -to gpio_1[23] +set_instance_assignment -name IO_STANDARD LVTTL -to gpio_1[24] +set_instance_assignment -name IO_STANDARD LVTTL -to gpio_1[25] +set_instance_assignment -name IO_STANDARD LVTTL -to gpio_1[26] +set_instance_assignment -name IO_STANDARD LVTTL -to gpio_1[27] +set_instance_assignment -name IO_STANDARD LVTTL -to gpio_1[28] +set_instance_assignment -name IO_STANDARD LVTTL -to gpio_1[29] +set_instance_assignment -name IO_STANDARD LVTTL -to gpio_1[2] +set_instance_assignment -name IO_STANDARD LVTTL -to gpio_1[30] +set_instance_assignment -name IO_STANDARD LVTTL -to gpio_1[31] +set_instance_assignment -name IO_STANDARD LVTTL -to gpio_1[32] +set_instance_assignment -name IO_STANDARD LVTTL -to gpio_1[33] +set_instance_assignment -name IO_STANDARD LVTTL -to gpio_1[34] +set_instance_assignment -name IO_STANDARD LVTTL -to gpio_1[35] +set_instance_assignment -name IO_STANDARD LVTTL -to gpio_1[3] +set_instance_assignment -name IO_STANDARD LVTTL -to gpio_1[4] +set_instance_assignment -name IO_STANDARD LVTTL -to gpio_1[5] +set_instance_assignment -name IO_STANDARD LVTTL -to gpio_1[6] +set_instance_assignment -name IO_STANDARD LVTTL -to gpio_1[7] +set_instance_assignment -name IO_STANDARD LVTTL -to gpio_1[8] +set_instance_assignment -name IO_STANDARD LVTTL -to gpio_1[9] +set_instance_assignment -name IO_STANDARD LVTTL -to hex0[0] +set_instance_assignment -name IO_STANDARD LVTTL -to hex0[1] +set_instance_assignment -name IO_STANDARD LVTTL -to hex0[2] +set_instance_assignment -name IO_STANDARD LVTTL -to hex0[3] +set_instance_assignment -name IO_STANDARD LVTTL -to hex0[4] +set_instance_assignment -name IO_STANDARD LVTTL -to hex0[5] +set_instance_assignment -name IO_STANDARD LVTTL -to hex0[6] +set_instance_assignment -name IO_STANDARD LVTTL -to hex1[0] +set_instance_assignment -name IO_STANDARD LVTTL -to hex1[1] +set_instance_assignment -name IO_STANDARD LVTTL -to hex1[2] +set_instance_assignment -name IO_STANDARD LVTTL -to hex1[3] +set_instance_assignment -name IO_STANDARD LVTTL -to hex1[4] +set_instance_assignment -name IO_STANDARD LVTTL -to hex1[5] +set_instance_assignment -name IO_STANDARD LVTTL -to hex1[6] +set_instance_assignment -name IO_STANDARD LVTTL -to hex2[0] +set_instance_assignment -name IO_STANDARD LVTTL -to hex2[1] +set_instance_assignment -name IO_STANDARD LVTTL -to hex2[2] +set_instance_assignment -name IO_STANDARD LVTTL -to hex2[3] +set_instance_assignment -name IO_STANDARD LVTTL -to hex2[4] +set_instance_assignment -name IO_STANDARD LVTTL -to hex2[5] +set_instance_assignment -name IO_STANDARD LVTTL -to hex2[6] +set_instance_assignment -name IO_STANDARD LVTTL -to hex3[0] +set_instance_assignment -name IO_STANDARD LVTTL -to hex3[1] +set_instance_assignment -name IO_STANDARD LVTTL -to hex3[2] +set_instance_assignment -name IO_STANDARD LVTTL -to hex3[3] +set_instance_assignment -name IO_STANDARD LVTTL -to hex3[4] +set_instance_assignment -name IO_STANDARD LVTTL -to hex3[5] +set_instance_assignment -name IO_STANDARD LVTTL -to hex3[6] +set_instance_assignment -name IO_STANDARD LVTTL -to i2c_sclk +set_instance_assignment -name IO_STANDARD LVTTL -to i2c_sdat +set_instance_assignment -name IO_STANDARD LVTTL -to key[0] +set_instance_assignment -name IO_STANDARD LVTTL -to key[1] +set_instance_assignment -name IO_STANDARD LVTTL -to key[2] +set_instance_assignment -name IO_STANDARD LVTTL -to key[3] +set_instance_assignment -name IO_STANDARD LVTTL -to ledg[0] +set_instance_assignment -name IO_STANDARD LVTTL -to ledg[1] +set_instance_assignment -name IO_STANDARD LVTTL -to ledg[2] +set_instance_assignment -name IO_STANDARD LVTTL -to ledg[3] +set_instance_assignment -name IO_STANDARD LVTTL -to ledg[4] +set_instance_assignment -name IO_STANDARD LVTTL -to ledg[5] +set_instance_assignment -name IO_STANDARD LVTTL -to ledg[6] +set_instance_assignment -name IO_STANDARD LVTTL -to ledg[7] +set_instance_assignment -name IO_STANDARD LVTTL -to ledr[0] +set_instance_assignment -name IO_STANDARD LVTTL -to ledr[1] +set_instance_assignment -name IO_STANDARD LVTTL -to ledr[2] +set_instance_assignment -name IO_STANDARD LVTTL -to ledr[3] +set_instance_assignment -name IO_STANDARD LVTTL -to ledr[4] +set_instance_assignment -name IO_STANDARD LVTTL -to ledr[5] +set_instance_assignment -name IO_STANDARD LVTTL -to ledr[6] +set_instance_assignment -name IO_STANDARD LVTTL -to ledr[7] +set_instance_assignment -name IO_STANDARD LVTTL -to ledr[8] +set_instance_assignment -name IO_STANDARD LVTTL -to ledr[9] +set_instance_assignment -name IO_STANDARD LVTTL -to ps2_clk +set_instance_assignment -name IO_STANDARD LVTTL -to ps2_dat +set_instance_assignment -name IO_STANDARD LVTTL -to sw[0] +set_instance_assignment -name IO_STANDARD LVTTL -to sw[1] +set_instance_assignment -name IO_STANDARD LVTTL -to sw[2] +set_instance_assignment -name IO_STANDARD LVTTL -to sw[3] +set_instance_assignment -name IO_STANDARD LVTTL -to sw[4] +set_instance_assignment -name IO_STANDARD LVTTL -to sw[5] +set_instance_assignment -name IO_STANDARD LVTTL -to sw[6] +set_instance_assignment -name IO_STANDARD LVTTL -to sw[7] +set_instance_assignment -name IO_STANDARD LVTTL -to sw[8] +set_instance_assignment -name IO_STANDARD LVTTL -to sw[9] +set_instance_assignment -name IO_STANDARD LVTTL -to tck +set_instance_assignment -name IO_STANDARD LVTTL -to tcs +set_instance_assignment -name IO_STANDARD LVTTL -to tdi +set_instance_assignment -name IO_STANDARD LVTTL -to tdo +set_instance_assignment -name IO_STANDARD LVTTL -to uart_rxd +set_instance_assignment -name IO_STANDARD LVTTL -to uart_txd +set_instance_assignment -name IO_STANDARD LVTTL -to vga_b[0] +set_instance_assignment -name IO_STANDARD LVTTL -to vga_b[1] +set_instance_assignment -name IO_STANDARD LVTTL -to vga_b[2] +set_instance_assignment -name IO_STANDARD LVTTL -to vga_b[3] +set_instance_assignment -name IO_STANDARD LVTTL -to vga_g[0] +set_instance_assignment -name IO_STANDARD LVTTL -to vga_g[1] +set_instance_assignment -name IO_STANDARD LVTTL -to vga_g[2] +set_instance_assignment -name IO_STANDARD LVTTL -to vga_g[3] +set_instance_assignment -name IO_STANDARD LVTTL -to vga_hs +set_instance_assignment -name IO_STANDARD LVTTL -to vga_r[0] +set_instance_assignment -name IO_STANDARD LVTTL -to vga_r[1] +set_instance_assignment -name IO_STANDARD LVTTL -to vga_r[2] +set_instance_assignment -name IO_STANDARD LVTTL -to vga_r[3] +set_instance_assignment -name IO_STANDARD LVTTL -to vga_vs +set_location_assignment PIN_B6 -to aud_adcdat +set_location_assignment PIN_A6 -to aud_adclrck +set_location_assignment PIN_A4 -to aud_bclk +set_location_assignment PIN_B5 -to aud_dacdat +set_location_assignment PIN_A5 -to aud_daclrck +set_location_assignment PIN_B4 -to aud_xck +set_location_assignment PIN_B12 -to clock_24[0] +set_location_assignment PIN_A12 -to clock_24[1] +set_location_assignment PIN_D12 -to clock_27 +# set_location_assignment pin_e12 -to clock_27[1] +set_location_assignment PIN_L1 -to clock_50 +set_location_assignment PIN_W4 -to dram_addr[0] +set_location_assignment PIN_W3 -to dram_addr[10] +set_location_assignment PIN_N6 -to dram_addr[11] +set_location_assignment PIN_W5 -to dram_addr[1] +set_location_assignment PIN_Y3 -to dram_addr[2] +set_location_assignment PIN_Y4 -to dram_addr[3] +set_location_assignment PIN_R6 -to dram_addr[4] +set_location_assignment PIN_R5 -to dram_addr[5] +set_location_assignment PIN_P6 -to dram_addr[6] +set_location_assignment PIN_P5 -to dram_addr[7] +set_location_assignment PIN_P3 -to dram_addr[8] +set_location_assignment PIN_N4 -to dram_addr[9] +set_location_assignment PIN_U3 -to dram_ba_0 +set_location_assignment PIN_V4 -to dram_ba_1 +set_location_assignment PIN_T3 -to dram_cas_n +set_location_assignment PIN_N3 -to dram_cke +set_location_assignment PIN_U4 -to dram_clk +set_location_assignment PIN_T6 -to dram_cs_n +set_location_assignment PIN_U1 -to dram_dq[0] +set_location_assignment PIN_P1 -to dram_dq[10] +set_location_assignment PIN_P2 -to dram_dq[11] +set_location_assignment PIN_R1 -to dram_dq[12] +set_location_assignment PIN_R2 -to dram_dq[13] +set_location_assignment PIN_T1 -to dram_dq[14] +set_location_assignment PIN_T2 -to dram_dq[15] +set_location_assignment PIN_U2 -to dram_dq[1] +set_location_assignment PIN_V1 -to dram_dq[2] +set_location_assignment PIN_V2 -to dram_dq[3] +set_location_assignment PIN_W1 -to dram_dq[4] +set_location_assignment PIN_W2 -to dram_dq[5] +set_location_assignment PIN_Y1 -to dram_dq[6] +set_location_assignment PIN_Y2 -to dram_dq[7] +set_location_assignment PIN_N1 -to dram_dq[8] +set_location_assignment PIN_N2 -to dram_dq[9] +set_location_assignment PIN_R7 -to dram_ldqm +set_location_assignment PIN_T5 -to dram_ras_n +set_location_assignment PIN_M5 -to dram_udqm +set_location_assignment PIN_R8 -to dram_we_n +set_location_assignment PIN_M21 -to ext_clock +set_location_assignment PIN_AB20 -to fl_addr[0] +set_location_assignment PIN_R12 -to fl_addr[10] +set_location_assignment PIN_T12 -to fl_addr[11] +set_location_assignment PIN_AB14 -to fl_addr[12] +set_location_assignment PIN_AA13 -to fl_addr[13] +set_location_assignment PIN_AB13 -to fl_addr[14] +set_location_assignment PIN_AA12 -to fl_addr[15] +set_location_assignment PIN_AB12 -to fl_addr[16] +set_location_assignment PIN_AA20 -to fl_addr[17] +set_location_assignment PIN_U14 -to fl_addr[18] +set_location_assignment PIN_V14 -to fl_addr[19] +set_location_assignment PIN_AA14 -to fl_addr[1] +set_location_assignment PIN_U13 -to fl_addr[20] +set_location_assignment PIN_R13 -to fl_addr[21] +set_location_assignment PIN_Y16 -to fl_addr[2] +set_location_assignment PIN_R15 -to fl_addr[3] +set_location_assignment PIN_T15 -to fl_addr[4] +set_location_assignment PIN_U15 -to fl_addr[5] +set_location_assignment PIN_V15 -to fl_addr[6] +set_location_assignment PIN_W15 -to fl_addr[7] +set_location_assignment PIN_R14 -to fl_addr[8] +set_location_assignment PIN_Y13 -to fl_addr[9] +set_location_assignment PIN_AB16 -to fl_dq[0] +set_location_assignment PIN_AA16 -to fl_dq[1] +set_location_assignment PIN_AB17 -to fl_dq[2] +set_location_assignment PIN_AA17 -to fl_dq[3] +set_location_assignment PIN_AB18 -to fl_dq[4] +set_location_assignment PIN_AA18 -to fl_dq[5] +set_location_assignment PIN_AB19 -to fl_dq[6] +set_location_assignment PIN_AA19 -to fl_dq[7] +set_location_assignment PIN_AA15 -to fl_oe_n +set_location_assignment PIN_W14 -to fl_rst_n +set_location_assignment PIN_Y14 -to fl_we_n +set_location_assignment PIN_A13 -to gpio_0[0] +set_location_assignment PIN_A18 -to gpio_0[10] +set_location_assignment PIN_B18 -to gpio_0[11] +set_location_assignment PIN_A19 -to gpio_0[12] +set_location_assignment PIN_B19 -to gpio_0[13] +set_location_assignment PIN_A20 -to gpio_0[14] +set_location_assignment PIN_B20 -to gpio_0[15] +set_location_assignment PIN_C21 -to gpio_0[16] +set_location_assignment PIN_C22 -to gpio_0[17] +set_location_assignment PIN_D21 -to gpio_0[18] +set_location_assignment PIN_D22 -to gpio_0[19] +set_location_assignment PIN_B13 -to gpio_0[1] +set_location_assignment PIN_E21 -to gpio_0[20] +set_location_assignment PIN_E22 -to gpio_0[21] +set_location_assignment PIN_F21 -to gpio_0[22] +set_location_assignment PIN_F22 -to gpio_0[23] +set_location_assignment PIN_G21 -to gpio_0[24] +set_location_assignment PIN_G22 -to gpio_0[25] +set_location_assignment PIN_J21 -to gpio_0[26] +set_location_assignment PIN_J22 -to gpio_0[27] +set_location_assignment PIN_K21 -to gpio_0[28] +set_location_assignment PIN_K22 -to gpio_0[29] +set_location_assignment PIN_A14 -to gpio_0[2] +set_location_assignment PIN_J19 -to gpio_0[30] +set_location_assignment PIN_J20 -to gpio_0[31] +set_location_assignment PIN_J18 -to gpio_0[32] +set_location_assignment PIN_K20 -to gpio_0[33] +set_location_assignment PIN_L19 -to gpio_0[34] +set_location_assignment PIN_L18 -to gpio_0[35] +set_location_assignment PIN_B14 -to gpio_0[3] +set_location_assignment PIN_A15 -to gpio_0[4] +set_location_assignment PIN_B15 -to gpio_0[5] +set_location_assignment PIN_A16 -to gpio_0[6] +set_location_assignment PIN_B16 -to gpio_0[7] +set_location_assignment PIN_A17 -to gpio_0[8] +set_location_assignment PIN_B17 -to gpio_0[9] +set_location_assignment PIN_H12 -to gpio_1[0] +set_location_assignment PIN_C14 -to gpio_1[10] +set_location_assignment PIN_D14 -to gpio_1[11] +set_location_assignment PIN_D15 -to gpio_1[12] +set_location_assignment PIN_D16 -to gpio_1[13] +set_location_assignment PIN_C17 -to gpio_1[14] +set_location_assignment PIN_C18 -to gpio_1[15] +set_location_assignment PIN_C19 -to gpio_1[16] +set_location_assignment PIN_C20 -to gpio_1[17] +set_location_assignment PIN_D19 -to gpio_1[18] +set_location_assignment PIN_D20 -to gpio_1[19] +set_location_assignment PIN_H13 -to gpio_1[1] +set_location_assignment PIN_E20 -to gpio_1[20] +set_location_assignment PIN_F20 -to gpio_1[21] +set_location_assignment PIN_E19 -to gpio_1[22] +set_location_assignment PIN_E18 -to gpio_1[23] +set_location_assignment PIN_G20 -to gpio_1[24] +set_location_assignment PIN_G18 -to gpio_1[25] +set_location_assignment PIN_G17 -to gpio_1[26] +set_location_assignment PIN_H17 -to gpio_1[27] +set_location_assignment PIN_J15 -to gpio_1[28] +set_location_assignment PIN_H18 -to gpio_1[29] +set_location_assignment PIN_H14 -to gpio_1[2] +set_location_assignment PIN_N22 -to gpio_1[30] +set_location_assignment PIN_N21 -to gpio_1[31] +set_location_assignment PIN_P15 -to gpio_1[32] +set_location_assignment PIN_N15 -to gpio_1[33] +set_location_assignment PIN_P17 -to gpio_1[34] +set_location_assignment PIN_P18 -to gpio_1[35] +set_location_assignment PIN_G15 -to gpio_1[3] +set_location_assignment PIN_E14 -to gpio_1[4] +set_location_assignment PIN_E15 -to gpio_1[5] +set_location_assignment PIN_F15 -to gpio_1[6] +set_location_assignment PIN_G16 -to gpio_1[7] +set_location_assignment PIN_F12 -to gpio_1[8] +set_location_assignment PIN_F13 -to gpio_1[9] +set_location_assignment PIN_J2 -to hex0[0] +set_location_assignment PIN_J1 -to hex0[1] +set_location_assignment PIN_H2 -to hex0[2] +set_location_assignment PIN_H1 -to hex0[3] +set_location_assignment PIN_F2 -to hex0[4] +set_location_assignment PIN_F1 -to hex0[5] +set_location_assignment PIN_E2 -to hex0[6] +set_location_assignment PIN_E1 -to hex1[0] +set_location_assignment PIN_H6 -to hex1[1] +set_location_assignment PIN_H5 -to hex1[2] +set_location_assignment PIN_H4 -to hex1[3] +set_location_assignment PIN_G3 -to hex1[4] +set_location_assignment PIN_D2 -to hex1[5] +set_location_assignment PIN_D1 -to hex1[6] +set_location_assignment PIN_G5 -to hex2[0] +set_location_assignment PIN_G6 -to hex2[1] +set_location_assignment PIN_C2 -to hex2[2] +set_location_assignment PIN_C1 -to hex2[3] +set_location_assignment PIN_E3 -to hex2[4] +set_location_assignment PIN_E4 -to hex2[5] +set_location_assignment PIN_D3 -to hex2[6] +set_location_assignment PIN_F4 -to hex3[0] +set_location_assignment PIN_D5 -to hex3[1] +set_location_assignment PIN_D6 -to hex3[2] +set_location_assignment PIN_J4 -to hex3[3] +set_location_assignment PIN_L8 -to hex3[4] +set_location_assignment PIN_F3 -to hex3[5] +set_location_assignment PIN_D4 -to hex3[6] +set_location_assignment PIN_A3 -to i2c_sclk +set_location_assignment PIN_B3 -to i2c_sdat +set_location_assignment PIN_R22 -to key[0] +set_location_assignment PIN_R21 -to key[1] +set_location_assignment PIN_T22 -to key[2] +set_location_assignment PIN_T21 -to key[3] +set_location_assignment PIN_U22 -to ledg[0] +set_location_assignment PIN_U21 -to ledg[1] +set_location_assignment PIN_V22 -to ledg[2] +set_location_assignment PIN_V21 -to ledg[3] +set_location_assignment PIN_W22 -to ledg[4] +set_location_assignment PIN_W21 -to ledg[5] +set_location_assignment PIN_Y22 -to ledg[6] +set_location_assignment PIN_Y21 -to ledg[7] +set_location_assignment PIN_R20 -to ledr[0] +set_location_assignment PIN_R19 -to ledr[1] +set_location_assignment PIN_U19 -to ledr[2] +set_location_assignment PIN_Y19 -to ledr[3] +set_location_assignment PIN_T18 -to ledr[4] +set_location_assignment PIN_V19 -to ledr[5] +set_location_assignment PIN_Y18 -to ledr[6] +set_location_assignment PIN_U18 -to ledr[7] +set_location_assignment PIN_R18 -to ledr[8] +set_location_assignment PIN_R17 -to ledr[9] +set_location_assignment PIN_H15 -to ps2_clk +set_location_assignment PIN_J14 -to ps2_dat +set_location_assignment PIN_AA3 -to sram_addr[0] +set_location_assignment PIN_R11 -to sram_addr[10] +set_location_assignment PIN_T11 -to sram_addr[11] +set_location_assignment PIN_Y10 -to sram_addr[12] +set_location_assignment PIN_U10 -to sram_addr[13] +set_location_assignment PIN_R10 -to sram_addr[14] +set_location_assignment PIN_T7 -to sram_addr[15] +set_location_assignment PIN_Y6 -to sram_addr[16] +set_location_assignment PIN_Y5 -to sram_addr[17] +set_location_assignment PIN_AB3 -to sram_addr[1] +set_location_assignment PIN_AA4 -to sram_addr[2] +set_location_assignment PIN_AB4 -to sram_addr[3] +set_location_assignment PIN_AA5 -to sram_addr[4] +set_location_assignment PIN_AB10 -to sram_addr[5] +set_location_assignment PIN_AA11 -to sram_addr[6] +set_location_assignment PIN_AB11 -to sram_addr[7] +set_location_assignment PIN_V11 -to sram_addr[8] +set_location_assignment PIN_W11 -to sram_addr[9] +set_location_assignment PIN_AB5 -to sram_ce_n +set_location_assignment PIN_AA6 -to sram_dq[0] +set_location_assignment PIN_V9 -to sram_dq[10] +set_location_assignment PIN_U9 -to sram_dq[11] +set_location_assignment PIN_R9 -to sram_dq[12] +set_location_assignment PIN_W8 -to sram_dq[13] +set_location_assignment PIN_V8 -to sram_dq[14] +set_location_assignment PIN_U8 -to sram_dq[15] +set_location_assignment PIN_AB6 -to sram_dq[1] +set_location_assignment PIN_AA7 -to sram_dq[2] +set_location_assignment PIN_AB7 -to sram_dq[3] +set_location_assignment PIN_AA8 -to sram_dq[4] +set_location_assignment PIN_AB8 -to sram_dq[5] +set_location_assignment PIN_AA9 -to sram_dq[6] +set_location_assignment PIN_AB9 -to sram_dq[7] +set_location_assignment PIN_Y9 -to sram_dq[8] +set_location_assignment PIN_W9 -to sram_dq[9] +set_location_assignment PIN_Y7 -to sram_lb_n +set_location_assignment PIN_T8 -to sram_oe_n +set_location_assignment PIN_W7 -to sram_ub_n +set_location_assignment PIN_AA10 -to sram_we_n +set_location_assignment PIN_L22 -to sw[0] +set_location_assignment PIN_L21 -to sw[1] +set_location_assignment PIN_M22 -to sw[2] +set_location_assignment PIN_V12 -to sw[3] +set_location_assignment PIN_W12 -to sw[4] +set_location_assignment PIN_U12 -to sw[5] +set_location_assignment PIN_U11 -to sw[6] +set_location_assignment PIN_M2 -to sw[7] +set_location_assignment PIN_M1 -to sw[8] +set_location_assignment PIN_L2 -to sw[9] +set_location_assignment PIN_C7 -to tck +set_location_assignment PIN_D8 -to tcs +set_location_assignment PIN_E8 -to tdi +set_location_assignment PIN_D7 -to tdo +set_location_assignment PIN_F14 -to uart_rxd +set_location_assignment PIN_G12 -to uart_txd +set_location_assignment PIN_A9 -to vga_b[0] +set_location_assignment PIN_D11 -to vga_b[1] +set_location_assignment PIN_A10 -to vga_b[2] +set_location_assignment PIN_B10 -to vga_b[3] +set_location_assignment PIN_B8 -to vga_g[0] +set_location_assignment PIN_C10 -to vga_g[1] +set_location_assignment PIN_B9 -to vga_g[2] +set_location_assignment PIN_A8 -to vga_g[3] +set_location_assignment PIN_A11 -to vga_hs +set_location_assignment PIN_D9 -to vga_r[0] +set_location_assignment PIN_C9 -to vga_r[1] +set_location_assignment PIN_A7 -to vga_r[2] +set_location_assignment PIN_B7 -to vga_r[3] +set_location_assignment PIN_B11 -to vga_vs + +set_global_assignment -name MISC_FILE "C:/VHDL/System09_sandbox_JK/rtl/System09_Terasic_DE1/system09.dpf" +set_global_assignment -name PARTITION_NETLIST_TYPE SOURCE -section_id Top +set_global_assignment -name PARTITION_COLOR 2147039 -section_id Top +set_global_assignment -name LL_ROOT_REGION ON -section_id "Root Region" +set_global_assignment -name LL_MEMBER_STATE LOCKED -section_id "Root Region" +set_global_assignment -name FITTER_EFFORT "STANDARD FIT" +set_global_assignment -name FITTER_AGGRESSIVE_ROUTABILITY_OPTIMIZATION ALWAYS +set_global_assignment -name OPTIMIZE_TIMING OFF +set_global_assignment -name AUTO_RAM_RECOGNITION ON +set_global_assignment -name AUTO_SHIFT_REGISTER_RECOGNITION ALWAYS +set_global_assignment -name OPTIMIZATION_TECHNIQUE AREA +set_global_assignment -name STRATIXII_OPTIMIZATION_TECHNIQUE AREA +set_global_assignment -name CYCLONE_OPTIMIZATION_TECHNIQUE AREA +set_global_assignment -name CYCLONEII_OPTIMIZATION_TECHNIQUE AREA +set_global_assignment -name STRATIX_OPTIMIZATION_TECHNIQUE AREA +set_global_assignment -name MAXII_OPTIMIZATION_TECHNIQUE AREA +set_global_assignment -name MAX7000_OPTIMIZATION_TECHNIQUE AREA +set_global_assignment -name ADV_NETLIST_OPT_SYNTH_WYSIWYG_REMAP ON +set_global_assignment -name REMOVE_REDUNDANT_LOGIC_CELLS ON +set_global_assignment -name MUX_RESTRUCTURE ON +set_global_assignment -name ALLOW_ANY_ROM_SIZE_FOR_RECOGNITION ON +set_global_assignment -name ALLOW_ANY_RAM_SIZE_FOR_RECOGNITION ON +set_global_assignment -name ALLOW_ANY_SHIFT_REGISTER_SIZE_FOR_RECOGNITION ON +set_global_assignment -name PHYSICAL_SYNTHESIS_COMBO_LOGIC_FOR_AREA ON +set_global_assignment -name PHYSICAL_SYNTHESIS_MAP_LOGIC_TO_MEMORY_FOR_AREA ON +set_global_assignment -name DO_MIN_ANALYSIS ON +set_global_assignment -name FMAX_REQUIREMENT "50 MHz" +set_global_assignment -name MIF_FILE ../Cyclone2/keymap_rom.mif +set_global_assignment -name HEX_FILE "../Cyclone2/sys09bug_de2-70.hex" +set_global_assignment -name MIF_FILE ../Cyclone2/char_rom.mif +set_global_assignment -name VHDL_FILE ../VHDL/trap.vhd +set_global_assignment -name VHDL_FILE System09_Terasic_DE1.vhd +set_global_assignment -name VHDL_FILE ../VHDL/ps2_keyboard.vhd +set_global_assignment -name VHDL_FILE ../VHDL/acia6850.vhd +set_global_assignment -name VHDL_FILE ../VHDL/timer.vhd +set_global_assignment -name VHDL_FILE ../VHDL/vdu8.vhd +set_global_assignment -name VHDL_FILE ../VHDL/keyboard.vhd +set_global_assignment -name VHDL_FILE ../VHDL/datram.vhd +set_global_assignment -name VHDL_FILE ../VHDL/cpu09.vhd +set_global_assignment -name VHDL_FILE ../VHDL/bit_funcs.vhd +set_global_assignment -name VHDL_FILE ../VHDL/ACIA_Clock.vhd +set_global_assignment -name VHDL_FILE ../Cyclone2/sprom.vhd +set_global_assignment -name VHDL_FILE ../Cyclone2/spram.vhd +set_global_assignment -name VHDL_FILE ../Cyclone2/mon_rom.vhd +set_global_assignment -name VHDL_FILE ../Cyclone2/char_rom.vhd +set_global_assignment -name VHDL_FILE ../Cyclone2/keymap_rom.vhd +set_global_assignment -name VHDL_FILE ../Cyclone2/ram_2k.vhd +set_global_assignment -name QIP_FILE ../Cyclone2/pll.qip +set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top \ No newline at end of file Index: System09/trunk/rtl/System09_Terasic_DE1/system09_assignment_defaults.qdf =================================================================== --- System09/trunk/rtl/System09_Terasic_DE1/system09_assignment_defaults.qdf (nonexistent) +++ System09/trunk/rtl/System09_Terasic_DE1/system09_assignment_defaults.qdf (revision 117) @@ -0,0 +1,642 @@ +# -------------------------------------------------------------------------- # +# +# Copyright (C) 1991-2009 Altera Corporation +# Your use of Altera Corporation's design tools, logic functions +# and other software and tools, and its AMPP partner logic +# functions, and any output files from any of the foregoing +# (including device programming or simulation files), and any +# associated documentation or information are expressly subject +# to the terms and conditions of the Altera Program License +# Subscription Agreement, Altera MegaCore Function License +# Agreement, or other applicable license agreement, including, +# without limitation, that your use is for the sole purpose of +# programming logic devices manufactured by Altera and sold by +# Altera or its authorized distributors. Please refer to the +# applicable agreement for further details. +# +# -------------------------------------------------------------------------- # +# +# Quartus II +# Version 9.0 Build 235 06/17/2009 Service Pack 2 SJ Full Version +# Date created = 17:10:05 March 10, 2010 +# +# -------------------------------------------------------------------------- # +# +# Note: +# +# 1) Do not modify this file. This file was generated +# automatically by the Quartus II software and is used +# to preserve global assignments across Quartus II versions. +# +# -------------------------------------------------------------------------- # + +set_global_assignment -name PROJECT_SHOW_ENTITY_NAME On +set_global_assignment -name PROJECT_USE_SIMPLIFIED_NAMES Off +set_global_assignment -name ENABLE_REDUCED_MEMORY_MODE Off +set_global_assignment -name VER_COMPATIBLE_DB_DIR export_db +set_global_assignment -name AUTO_EXPORT_VER_COMPATIBLE_DB Off +set_global_assignment -name SMART_RECOMPILE Off +set_global_assignment -name FLOW_DISABLE_ASSEMBLER Off +set_global_assignment -name FLOW_ENABLE_HC_COMPARE Off +set_global_assignment -name HC_OUTPUT_DIR hc_output +set_global_assignment -name SAVE_MIGRATION_INFO_DURING_COMPILATION Off +set_global_assignment -name FLOW_ENABLE_IO_ASSIGNMENT_ANALYSIS Off +set_global_assignment -name RUN_FULL_COMPILE_ON_DEVICE_CHANGE On +set_global_assignment -name FLOW_ENABLE_RTL_VIEWER Off +set_global_assignment -name READ_OR_WRITE_IN_BYTE_ADDRESS "Use global settings" +set_global_assignment -name FLOW_HARDCOPY_DESIGN_READINESS_CHECK On +set_global_assignment -name DEFAULT_HOLD_MULTICYCLE "Same as Multicycle" +set_global_assignment -name CUT_OFF_PATHS_BETWEEN_CLOCK_DOMAINS On +set_global_assignment -name CUT_OFF_READ_DURING_WRITE_PATHS On +set_global_assignment -name CUT_OFF_IO_PIN_FEEDBACK On +set_global_assignment -name DO_COMBINED_ANALYSIS Off +set_global_assignment -name IGNORE_CLOCK_SETTINGS Off +set_global_assignment -name ANALYZE_LATCHES_AS_SYNCHRONOUS_ELEMENTS On +set_global_assignment -name ENABLE_RECOVERY_REMOVAL_ANALYSIS Off +set_global_assignment -name ENABLE_CLOCK_LATENCY Off +set_global_assignment -name USE_TIMEQUEST_TIMING_ANALYZER Off -family ACEX1K +set_global_assignment -name USE_TIMEQUEST_TIMING_ANALYZER Off -family MAX7000B +set_global_assignment -name USE_TIMEQUEST_TIMING_ANALYZER Off -family "HardCopy II" +set_global_assignment -name USE_TIMEQUEST_TIMING_ANALYZER Off -family FLEX10KA +set_global_assignment -name USE_TIMEQUEST_TIMING_ANALYZER On -family "Stratix IV" +set_global_assignment -name USE_TIMEQUEST_TIMING_ANALYZER On -family "Cyclone III" +set_global_assignment -name USE_TIMEQUEST_TIMING_ANALYZER Off -family "HardCopy Stratix" +set_global_assignment -name USE_TIMEQUEST_TIMING_ANALYZER Off -family APEX20KE +set_global_assignment -name USE_TIMEQUEST_TIMING_ANALYZER Off -family MAX7000AE +set_global_assignment -name USE_TIMEQUEST_TIMING_ANALYZER Off -family Cyclone +set_global_assignment -name USE_TIMEQUEST_TIMING_ANALYZER Off -family "Stratix II GX" +set_global_assignment -name USE_TIMEQUEST_TIMING_ANALYZER Off -family FLEX10K +set_global_assignment -name USE_TIMEQUEST_TIMING_ANALYZER Off -family "MAX II" +set_global_assignment -name USE_TIMEQUEST_TIMING_ANALYZER Off -family APEX20KC +set_global_assignment -name USE_TIMEQUEST_TIMING_ANALYZER On -family "Arria II GX" +set_global_assignment -name USE_TIMEQUEST_TIMING_ANALYZER Off -family "Stratix GX" +set_global_assignment -name USE_TIMEQUEST_TIMING_ANALYZER On -family "HardCopy III" +set_global_assignment -name USE_TIMEQUEST_TIMING_ANALYZER Off -family MAX7000S +set_global_assignment -name USE_TIMEQUEST_TIMING_ANALYZER Off -family FLEX6000 +set_global_assignment -name USE_TIMEQUEST_TIMING_ANALYZER Off -family "APEX II" +set_global_assignment -name USE_TIMEQUEST_TIMING_ANALYZER Off -family FLEX10KE +set_global_assignment -name USE_TIMEQUEST_TIMING_ANALYZER Off -family "Cyclone II" +set_global_assignment -name USE_TIMEQUEST_TIMING_ANALYZER On -family "HardCopy IV" +set_global_assignment -name USE_TIMEQUEST_TIMING_ANALYZER On -family "Cyclone III LS" +set_global_assignment -name USE_TIMEQUEST_TIMING_ANALYZER On -family "Stratix III" +set_global_assignment -name USE_TIMEQUEST_TIMING_ANALYZER On -family "Arria GX" +set_global_assignment -name USE_TIMEQUEST_TIMING_ANALYZER Off -family MAX3000A +set_global_assignment -name USE_TIMEQUEST_TIMING_ANALYZER Off -family "Stratix II" +set_global_assignment -name USE_TIMEQUEST_TIMING_ANALYZER Off -family Stratix +set_global_assignment -name NUMBER_OF_SOURCES_PER_DESTINATION_TO_REPORT 10 +set_global_assignment -name NUMBER_OF_DESTINATION_TO_REPORT 10 +set_global_assignment -name NUMBER_OF_PATHS_TO_REPORT 200 +set_global_assignment -name DO_MIN_ANALYSIS Off +set_global_assignment -name DO_MIN_TIMING Off +set_global_assignment -name REPORT_IO_PATHS_SEPARATELY Off +set_global_assignment -name FLOW_ENABLE_TIMING_CONSTRAINT_CHECK Off +set_global_assignment -name TIMEQUEST_MULTICORNER_ANALYSIS Off -family ACEX1K +set_global_assignment -name TIMEQUEST_MULTICORNER_ANALYSIS Off -family MAX7000B +set_global_assignment -name TIMEQUEST_MULTICORNER_ANALYSIS On -family "HardCopy II" +set_global_assignment -name TIMEQUEST_MULTICORNER_ANALYSIS Off -family FLEX10KA +set_global_assignment -name TIMEQUEST_MULTICORNER_ANALYSIS On -family "Stratix IV" +set_global_assignment -name TIMEQUEST_MULTICORNER_ANALYSIS On -family "Cyclone III" +set_global_assignment -name TIMEQUEST_MULTICORNER_ANALYSIS Off -family "HardCopy Stratix" +set_global_assignment -name TIMEQUEST_MULTICORNER_ANALYSIS Off -family APEX20KE +set_global_assignment -name TIMEQUEST_MULTICORNER_ANALYSIS Off -family MAX7000AE +set_global_assignment -name TIMEQUEST_MULTICORNER_ANALYSIS Off -family Cyclone +set_global_assignment -name TIMEQUEST_MULTICORNER_ANALYSIS On -family "Stratix II GX" +set_global_assignment -name TIMEQUEST_MULTICORNER_ANALYSIS Off -family FLEX10K +set_global_assignment -name TIMEQUEST_MULTICORNER_ANALYSIS Off -family "MAX II" +set_global_assignment -name TIMEQUEST_MULTICORNER_ANALYSIS Off -family APEX20KC +set_global_assignment -name TIMEQUEST_MULTICORNER_ANALYSIS On -family "Arria II GX" +set_global_assignment -name TIMEQUEST_MULTICORNER_ANALYSIS Off -family "Stratix GX" +set_global_assignment -name TIMEQUEST_MULTICORNER_ANALYSIS On -family "HardCopy III" +set_global_assignment -name TIMEQUEST_MULTICORNER_ANALYSIS Off -family MAX7000S +set_global_assignment -name TIMEQUEST_MULTICORNER_ANALYSIS Off -family FLEX6000 +set_global_assignment -name TIMEQUEST_MULTICORNER_ANALYSIS Off -family "APEX II" +set_global_assignment -name TIMEQUEST_MULTICORNER_ANALYSIS Off -family FLEX10KE +set_global_assignment -name TIMEQUEST_MULTICORNER_ANALYSIS On -family "Cyclone II" +set_global_assignment -name TIMEQUEST_MULTICORNER_ANALYSIS On -family "HardCopy IV" +set_global_assignment -name TIMEQUEST_MULTICORNER_ANALYSIS On -family "Cyclone III LS" +set_global_assignment -name TIMEQUEST_MULTICORNER_ANALYSIS On -family "Stratix III" +set_global_assignment -name TIMEQUEST_MULTICORNER_ANALYSIS On -family "Arria GX" +set_global_assignment -name TIMEQUEST_MULTICORNER_ANALYSIS Off -family MAX3000A +set_global_assignment -name TIMEQUEST_MULTICORNER_ANALYSIS On -family "Stratix II" +set_global_assignment -name TIMEQUEST_MULTICORNER_ANALYSIS Off -family Stratix +set_global_assignment -name TIMEQUEST_DO_REPORT_TIMING Off +set_global_assignment -name TIMEQUEST_DO_CCPP_REMOVAL Off -family ACEX1K +set_global_assignment -name TIMEQUEST_DO_CCPP_REMOVAL Off -family MAX7000B +set_global_assignment -name TIMEQUEST_DO_CCPP_REMOVAL Off -family "HardCopy II" +set_global_assignment -name TIMEQUEST_DO_CCPP_REMOVAL Off -family FLEX10KA +set_global_assignment -name TIMEQUEST_DO_CCPP_REMOVAL On -family "Stratix IV" +set_global_assignment -name TIMEQUEST_DO_CCPP_REMOVAL On -family "Cyclone III" +set_global_assignment -name TIMEQUEST_DO_CCPP_REMOVAL Off -family "HardCopy Stratix" +set_global_assignment -name TIMEQUEST_DO_CCPP_REMOVAL Off -family APEX20KE +set_global_assignment -name TIMEQUEST_DO_CCPP_REMOVAL Off -family MAX7000AE +set_global_assignment -name TIMEQUEST_DO_CCPP_REMOVAL Off -family Cyclone +set_global_assignment -name TIMEQUEST_DO_CCPP_REMOVAL Off -family "Stratix II GX" +set_global_assignment -name TIMEQUEST_DO_CCPP_REMOVAL Off -family FLEX10K +set_global_assignment -name TIMEQUEST_DO_CCPP_REMOVAL Off -family "MAX II" +set_global_assignment -name TIMEQUEST_DO_CCPP_REMOVAL Off -family APEX20KC +set_global_assignment -name TIMEQUEST_DO_CCPP_REMOVAL On -family "Arria II GX" +set_global_assignment -name TIMEQUEST_DO_CCPP_REMOVAL Off -family "Stratix GX" +set_global_assignment -name TIMEQUEST_DO_CCPP_REMOVAL On -family "HardCopy III" +set_global_assignment -name TIMEQUEST_DO_CCPP_REMOVAL Off -family MAX7000S +set_global_assignment -name TIMEQUEST_DO_CCPP_REMOVAL Off -family FLEX6000 +set_global_assignment -name TIMEQUEST_DO_CCPP_REMOVAL Off -family "APEX II" +set_global_assignment -name TIMEQUEST_DO_CCPP_REMOVAL Off -family FLEX10KE +set_global_assignment -name TIMEQUEST_DO_CCPP_REMOVAL Off -family "Cyclone II" +set_global_assignment -name TIMEQUEST_DO_CCPP_REMOVAL On -family "HardCopy IV" +set_global_assignment -name TIMEQUEST_DO_CCPP_REMOVAL On -family "Cyclone III LS" +set_global_assignment -name TIMEQUEST_DO_CCPP_REMOVAL On -family "Stratix III" +set_global_assignment -name TIMEQUEST_DO_CCPP_REMOVAL Off -family "Arria GX" +set_global_assignment -name TIMEQUEST_DO_CCPP_REMOVAL Off -family MAX3000A +set_global_assignment -name TIMEQUEST_DO_CCPP_REMOVAL Off -family "Stratix II" +set_global_assignment -name TIMEQUEST_DO_CCPP_REMOVAL Off -family Stratix +set_global_assignment -name MUX_RESTRUCTURE Auto +set_global_assignment -name ENABLE_IP_DEBUG Off +set_global_assignment -name SAVE_DISK_SPACE On +set_global_assignment -name DISABLE_OCP_HW_EVAL Off +set_global_assignment -name DEVICE_FILTER_PACKAGE Any +set_global_assignment -name DEVICE_FILTER_PIN_COUNT Any +set_global_assignment -name DEVICE_FILTER_SPEED_GRADE Any +set_global_assignment -name EDA_DESIGN_ENTRY_SYNTHESIS_TOOL "" +set_global_assignment -name VERILOG_INPUT_VERSION Verilog_2001 +set_global_assignment -name VHDL_INPUT_VERSION VHDL93 +set_global_assignment -name FAMILY "Stratix II" +set_global_assignment -name TRUE_WYSIWYG_FLOW Off +set_global_assignment -name SMART_COMPILE_IGNORES_TDC_FOR_STRATIX_PLL_CHANGES Off +set_global_assignment -name STATE_MACHINE_PROCESSING Auto +set_global_assignment -name SAFE_STATE_MACHINE Off +set_global_assignment -name EXTRACT_VERILOG_STATE_MACHINES On +set_global_assignment -name EXTRACT_VHDL_STATE_MACHINES On +set_global_assignment -name IGNORE_VERILOG_INITIAL_CONSTRUCTS Off +set_global_assignment -name VERILOG_CONSTANT_LOOP_LIMIT 5000 +set_global_assignment -name VERILOG_NON_CONSTANT_LOOP_LIMIT 250 +set_global_assignment -name ADD_PASS_THROUGH_LOGIC_TO_INFERRED_RAMS On +set_global_assignment -name PARALLEL_SYNTHESIS Off +set_global_assignment -name DSP_BLOCK_BALANCING Auto +set_global_assignment -name MAX_BALANCING_DSP_BLOCKS "-1 (Unlimited)" +set_global_assignment -name NOT_GATE_PUSH_BACK On +set_global_assignment -name ALLOW_POWER_UP_DONT_CARE On +set_global_assignment -name REMOVE_REDUNDANT_LOGIC_CELLS Off +set_global_assignment -name REMOVE_DUPLICATE_REGISTERS On +set_global_assignment -name IGNORE_CARRY_BUFFERS Off +set_global_assignment -name IGNORE_CASCADE_BUFFERS Off +set_global_assignment -name IGNORE_GLOBAL_BUFFERS Off +set_global_assignment -name IGNORE_ROW_GLOBAL_BUFFERS Off +set_global_assignment -name IGNORE_LCELL_BUFFERS Off +set_global_assignment -name MAX7000_IGNORE_LCELL_BUFFERS AUTO +set_global_assignment -name IGNORE_SOFT_BUFFERS On +set_global_assignment -name MAX7000_IGNORE_SOFT_BUFFERS Off +set_global_assignment -name LIMIT_AHDL_INTEGERS_TO_32_BITS Off +set_global_assignment -name AUTO_GLOBAL_CLOCK_MAX On +set_global_assignment -name AUTO_GLOBAL_OE_MAX On +set_global_assignment -name MAX_AUTO_GLOBAL_REGISTER_CONTROLS On +set_global_assignment -name AUTO_IMPLEMENT_IN_ROM Off +set_global_assignment -name APEX20K_TECHNOLOGY_MAPPER Lut +set_global_assignment -name OPTIMIZATION_TECHNIQUE Balanced +set_global_assignment -name STRATIXII_OPTIMIZATION_TECHNIQUE Balanced +set_global_assignment -name CYCLONE_OPTIMIZATION_TECHNIQUE Balanced +set_global_assignment -name CYCLONEII_OPTIMIZATION_TECHNIQUE Balanced +set_global_assignment -name STRATIX_OPTIMIZATION_TECHNIQUE Balanced +set_global_assignment -name MAXII_OPTIMIZATION_TECHNIQUE Balanced +set_global_assignment -name MAX7000_OPTIMIZATION_TECHNIQUE Speed +set_global_assignment -name APEX20K_OPTIMIZATION_TECHNIQUE Balanced +set_global_assignment -name MERCURY_OPTIMIZATION_TECHNIQUE Area +set_global_assignment -name FLEX6K_OPTIMIZATION_TECHNIQUE Area +set_global_assignment -name FLEX10K_OPTIMIZATION_TECHNIQUE Area +set_global_assignment -name ALLOW_XOR_GATE_USAGE On +set_global_assignment -name AUTO_LCELL_INSERTION On +set_global_assignment -name CARRY_CHAIN_LENGTH 48 +set_global_assignment -name FLEX6K_CARRY_CHAIN_LENGTH 32 +set_global_assignment -name FLEX10K_CARRY_CHAIN_LENGTH 32 +set_global_assignment -name MERCURY_CARRY_CHAIN_LENGTH 48 +set_global_assignment -name STRATIX_CARRY_CHAIN_LENGTH 70 +set_global_assignment -name STRATIXII_CARRY_CHAIN_LENGTH 70 +set_global_assignment -name CASCADE_CHAIN_LENGTH 2 +set_global_assignment -name PARALLEL_EXPANDER_CHAIN_LENGTH 16 +set_global_assignment -name MAX7000_PARALLEL_EXPANDER_CHAIN_LENGTH 4 +set_global_assignment -name AUTO_CARRY_CHAINS On +set_global_assignment -name AUTO_CASCADE_CHAINS On +set_global_assignment -name AUTO_PARALLEL_EXPANDERS On +set_global_assignment -name AUTO_OPEN_DRAIN_PINS On +set_global_assignment -name ADV_NETLIST_OPT_SYNTH_WYSIWYG_REMAP Off +set_global_assignment -name AUTO_ROM_RECOGNITION On +set_global_assignment -name AUTO_RAM_RECOGNITION On +set_global_assignment -name AUTO_DSP_RECOGNITION On +set_global_assignment -name AUTO_SHIFT_REGISTER_RECOGNITION Auto +set_global_assignment -name AUTO_CLOCK_ENABLE_RECOGNITION On +set_global_assignment -name STRICT_RAM_RECOGNITION Off +set_global_assignment -name ALLOW_SYNCH_CTRL_USAGE On +set_global_assignment -name FORCE_SYNCH_CLEAR Off +set_global_assignment -name AUTO_RAM_BLOCK_BALANCING On +set_global_assignment -name AUTO_RAM_TO_LCELL_CONVERSION Off +set_global_assignment -name AUTO_RESOURCE_SHARING Off +set_global_assignment -name ALLOW_ANY_RAM_SIZE_FOR_RECOGNITION Off +set_global_assignment -name ALLOW_ANY_ROM_SIZE_FOR_RECOGNITION Off +set_global_assignment -name ALLOW_ANY_SHIFT_REGISTER_SIZE_FOR_RECOGNITION Off +set_global_assignment -name MAX7000_FANIN_PER_CELL 100 +set_global_assignment -name USE_LOGICLOCK_CONSTRAINTS_IN_BALANCING On +set_global_assignment -name MAX_RAM_BLOCKS_M512 "-1 (Unlimited)" +set_global_assignment -name MAX_RAM_BLOCKS_M4K "-1 (Unlimited)" +set_global_assignment -name MAX_RAM_BLOCKS_MRAM "-1 (Unlimited)" +set_global_assignment -name IGNORE_TRANSLATE_OFF_AND_SYNTHESIS_OFF Off +set_global_assignment -name STRATIXGX_BYPASS_REMAPPING_OF_FORCE_SIGNAL_DETECT_SIGNAL_THRESHOLD_SELECT Off +set_global_assignment -name SYNTH_TIMING_DRIVEN_SYNTHESIS Off +set_global_assignment -name SHOW_PARAMETER_SETTINGS_TABLES_IN_SYNTHESIS_REPORT On +set_global_assignment -name IGNORE_MAX_FANOUT_ASSIGNMENTS Off +set_global_assignment -name SYNCHRONIZATION_REGISTER_CHAIN_LENGTH 2 +set_global_assignment -name OPTIMIZE_POWER_DURING_SYNTHESIS "Normal compilation" +set_global_assignment -name HDL_MESSAGE_LEVEL Level2 +set_global_assignment -name USE_HIGH_SPEED_ADDER Auto +set_global_assignment -name NUMBER_OF_REMOVED_REGISTERS_REPORTED 100 +set_global_assignment -name NUMBER_OF_INVERTED_REGISTERS_REPORTED 100 +set_global_assignment -name SYNTH_CLOCK_MUX_PROTECTION On +set_global_assignment -name SYNTH_GATED_CLOCK_CONVERSION Off +set_global_assignment -name BLOCK_DESIGN_NAMING Auto +set_global_assignment -name SYNTH_PROTECT_SDC_CONSTRAINT Off +set_global_assignment -name SYNTHESIS_EFFORT Auto +set_global_assignment -name SHIFT_REGISTER_RECOGNITION_ACLR_SIGNAL On +set_global_assignment -name PRE_MAPPING_RESYNTHESIS Off +set_global_assignment -name SYNTH_MESSAGE_LEVEL Medium +set_global_assignment -name ROUTER_TIMING_OPTIMIZATION_LEVEL Normal +set_global_assignment -name PLACEMENT_EFFORT_MULTIPLIER 1.0 +set_global_assignment -name ROUTER_EFFORT_MULTIPLIER 1.0 +set_global_assignment -name FIT_ATTEMPTS_TO_SKIP 0.0 +set_global_assignment -name ECO_ALLOW_ROUTING_CHANGES Off +set_global_assignment -name DEVICE AUTO +set_global_assignment -name BASE_PIN_OUT_FILE_ON_SAMEFRAME_DEVICE Off +set_global_assignment -name ENABLE_JTAG_BST_SUPPORT Off +set_global_assignment -name MAX7000_ENABLE_JTAG_BST_SUPPORT On +set_global_assignment -name RESERVE_NCEO_AFTER_CONFIGURATION "Use as regular IO" +set_global_assignment -name CYCLONEII_RESERVE_NCEO_AFTER_CONFIGURATION "Use as programming pin" +set_global_assignment -name STRATIXIII_UPDATE_MODE Standard +set_global_assignment -name STRATIX_UPDATE_MODE Standard +set_global_assignment -name STRATIXIII_CONFIGURATION_SCHEME "Passive Serial" +set_global_assignment -name CYCLONEIII_CONFIGURATION_SCHEME "Active Serial" +set_global_assignment -name STRATIXII_CONFIGURATION_SCHEME "Passive Serial" +set_global_assignment -name CYCLONEII_CONFIGURATION_SCHEME "Active Serial" +set_global_assignment -name APEX20K_CONFIGURATION_SCHEME "Passive Serial" +set_global_assignment -name STRATIX_CONFIGURATION_SCHEME "Passive Serial" +set_global_assignment -name CYCLONE_CONFIGURATION_SCHEME "Active Serial" +set_global_assignment -name MERCURY_CONFIGURATION_SCHEME "Passive Serial" +set_global_assignment -name FLEX6K_CONFIGURATION_SCHEME "Passive Serial" +set_global_assignment -name FLEX10K_CONFIGURATION_SCHEME "Passive Serial" +set_global_assignment -name APEXII_CONFIGURATION_SCHEME "Passive Serial" +set_global_assignment -name USER_START_UP_CLOCK Off +set_global_assignment -name ENABLE_VREFA_PIN Off +set_global_assignment -name ENABLE_VREFB_PIN Off +set_global_assignment -name ALWAYS_ENABLE_INPUT_BUFFERS Off +set_global_assignment -name ENABLE_ASMI_FOR_FLASH_LOADER Off +set_global_assignment -name ENABLE_DEVICE_WIDE_RESET Off +set_global_assignment -name ENABLE_DEVICE_WIDE_OE Off +set_global_assignment -name RESERVE_ALL_UNUSED_PINS "As output driving ground" +set_global_assignment -name FLEX10K_ENABLE_LOCK_OUTPUT Off +set_global_assignment -name ENABLE_INIT_DONE_OUTPUT Off +set_global_assignment -name RESERVE_NWS_NRS_NCS_CS_AFTER_CONFIGURATION "Use as regular IO" +set_global_assignment -name RESERVE_RDYNBUSY_AFTER_CONFIGURATION "Use as regular IO" +set_global_assignment -name RESERVE_DATA7_THROUGH_DATA1_AFTER_CONFIGURATION "Use as regular IO" +set_global_assignment -name RESERVE_DATA0_AFTER_CONFIGURATION "As input tri-stated" +set_global_assignment -name RESERVE_ASDO_AFTER_CONFIGURATION "Use as regular IO" +set_global_assignment -name RESERVE_DATA1_AFTER_CONFIGURATION "As input tri-stated" +set_global_assignment -name RESERVE_DATA7_THROUGH_DATA2_AFTER_CONFIGURATION "Use as regular IO" +set_global_assignment -name RESERVE_FLASH_NCE_AFTER_CONFIGURATION "As input tri-stated" +set_global_assignment -name RESERVE_OTHER_AP_PINS_AFTER_CONFIGURATION "Use as regular IO" +set_global_assignment -name RESERVE_DCLK_AFTER_CONFIGURATION "Use as programming pin" +set_global_assignment -name CRC_ERROR_CHECKING Off +set_global_assignment -name OPTIMIZE_HOLD_TIMING "IO Paths and Minimum TPD Paths" -family "Stratix GX" +set_global_assignment -name OPTIMIZE_HOLD_TIMING -value "ALL PATHS" -family "HardCopy III" +set_global_assignment -name OPTIMIZE_HOLD_TIMING "IO Paths and Minimum TPD Paths" -family "Cyclone II" +set_global_assignment -name OPTIMIZE_HOLD_TIMING "IO Paths and Minimum TPD Paths" -family "HardCopy II" +set_global_assignment -name OPTIMIZE_HOLD_TIMING -value "ALL PATHS" -family "Stratix IV" +set_global_assignment -name OPTIMIZE_HOLD_TIMING -value "ALL PATHS" -family "HardCopy IV" +set_global_assignment -name OPTIMIZE_HOLD_TIMING -value "ALL PATHS" -family "Cyclone III LS" +set_global_assignment -name OPTIMIZE_HOLD_TIMING -value "ALL PATHS" -family "Cyclone III" +set_global_assignment -name OPTIMIZE_HOLD_TIMING -value "ALL PATHS" -family "Stratix III" +set_global_assignment -name OPTIMIZE_HOLD_TIMING "IO Paths and Minimum TPD Paths" -family "HardCopy Stratix" +set_global_assignment -name OPTIMIZE_HOLD_TIMING -value "ALL PATHS" -family "Arria GX" +set_global_assignment -name OPTIMIZE_HOLD_TIMING "IO Paths and Minimum TPD Paths" -family "Stratix II GX" +set_global_assignment -name OPTIMIZE_HOLD_TIMING "IO Paths and Minimum TPD Paths" -family Cyclone +set_global_assignment -name OPTIMIZE_HOLD_TIMING "IO Paths and Minimum TPD Paths" -family "Stratix II" +set_global_assignment -name OPTIMIZE_HOLD_TIMING "IO Paths and Minimum TPD Paths" -family "MAX II" +set_global_assignment -name OPTIMIZE_HOLD_TIMING "IO Paths and Minimum TPD Paths" -family Stratix +set_global_assignment -name OPTIMIZE_HOLD_TIMING -value "ALL PATHS" -family "Arria II GX" +set_global_assignment -name OPTIMIZE_MULTI_CORNER_TIMING Off +set_global_assignment -name BLOCK_RAM_TO_MLAB_CELL_CONVERSION On +set_global_assignment -name BLOCK_RAM_AND_MLAB_EQUIVALENT_POWER_UP_CONDITIONS Auto +set_global_assignment -name BLOCK_RAM_AND_MLAB_EQUIVALENT_PAUSED_READ_CAPABILITIES Care +set_global_assignment -name PROGRAMMABLE_POWER_TECHNOLOGY_SETTING "Force All Tiles with Failing Timing Paths to High Speed" +set_global_assignment -name PROGRAMMABLE_POWER_MAXIMUM_HIGH_SPEED_FRACTION_OF_USED_LAB_TILES 1.0 +set_global_assignment -name GUARANTEE_MIN_DELAY_CORNER_IO_ZERO_HOLD_TIME On +set_global_assignment -name OPTIMIZE_POWER_DURING_FITTING "Normal compilation" +set_global_assignment -name OPTIMIZE_SSN Off -family "Cyclone III LS" +set_global_assignment -name OPTIMIZE_SSN Off -family "Cyclone III" +set_global_assignment -name OPTIMIZE_SSN Off -family "Stratix III" +set_global_assignment -name OPTIMIZE_SSN Off -family "HardCopy III" +set_global_assignment -name OPTIMIZE_SSN Off -family "HardCopy IV" +set_global_assignment -name OPTIMIZE_TIMING "Normal compilation" +set_global_assignment -name ECO_OPTIMIZE_TIMING Off +set_global_assignment -name ECO_REGENERATE_REPORT Off +set_global_assignment -name OPTIMIZE_IOC_REGISTER_PLACEMENT_FOR_TIMING On +set_global_assignment -name FIT_ONLY_ONE_ATTEMPT Off +set_global_assignment -name FINAL_PLACEMENT_OPTIMIZATION Automatically +set_global_assignment -name FITTER_AGGRESSIVE_ROUTABILITY_OPTIMIZATION Automatically +set_global_assignment -name SEED 1 +set_global_assignment -name SLOW_SLEW_RATE Off +set_global_assignment -name PCI_IO Off +set_global_assignment -name TURBO_BIT On +set_global_assignment -name WEAK_PULL_UP_RESISTOR Off +set_global_assignment -name ENABLE_BUS_HOLD_CIRCUITRY Off +set_global_assignment -name AUTO_GLOBAL_MEMORY_CONTROLS Off +set_global_assignment -name MIGRATION_CONSTRAIN_CORE_RESOURCES On +set_global_assignment -name AUTO_PACKED_REGISTERS_STRATIXII AUTO +set_global_assignment -name AUTO_PACKED_REGISTERS_MAXII AUTO +set_global_assignment -name AUTO_PACKED_REGISTERS_CYCLONE Auto +set_global_assignment -name AUTO_PACKED_REGISTERS Off +set_global_assignment -name AUTO_PACKED_REGISTERS_STRATIX AUTO +set_global_assignment -name NORMAL_LCELL_INSERT On +set_global_assignment -name CARRY_OUT_PINS_LCELL_INSERT On +set_global_assignment -name AUTO_DELAY_CHAINS On +set_global_assignment -name XSTL_INPUT_ALLOW_SE_BUFFER Off +set_global_assignment -name TREAT_BIDIR_AS_OUTPUT Off +set_global_assignment -name AUTO_MERGE_PLLS On +set_global_assignment -name IGNORE_MODE_FOR_MERGE Off +set_global_assignment -name AUTO_TURBO_BIT ON +set_global_assignment -name PHYSICAL_SYNTHESIS_COMBO_LOGIC_FOR_AREA Off +set_global_assignment -name PHYSICAL_SYNTHESIS_COMBO_LOGIC Off +set_global_assignment -name PHYSICAL_SYNTHESIS_LOG_FILE Off +set_global_assignment -name PHYSICAL_SYNTHESIS_REGISTER_DUPLICATION Off +set_global_assignment -name PHYSICAL_SYNTHESIS_MAP_LOGIC_TO_MEMORY_FOR_AREA Off +set_global_assignment -name PHYSICAL_SYNTHESIS_REGISTER_RETIMING Off +set_global_assignment -name PHYSICAL_SYNTHESIS_ASYNCHRONOUS_SIGNAL_PIPELINING Off +set_global_assignment -name IO_PLACEMENT_OPTIMIZATION On +set_global_assignment -name ALLOW_LVTTL_LVCMOS_INPUT_LEVELS_TO_OVERDRIVE_INPUT_BUFFER Off +set_global_assignment -name OVERRIDE_DEFAULT_ELECTROMIGRATION_PARAMETERS Off +set_global_assignment -name FITTER_EFFORT "Auto Fit" +set_global_assignment -name FITTER_AUTO_EFFORT_DESIRED_SLACK_MARGIN 0ns +set_global_assignment -name PHYSICAL_SYNTHESIS_EFFORT Normal +set_global_assignment -name ROUTER_LCELL_INSERTION_AND_LOGIC_DUPLICATION AUTO +set_global_assignment -name ROUTER_REGISTER_DUPLICATION AUTO +set_global_assignment -name STRATIXGX_ALLOW_CLOCK_FANOUT_WITH_ANALOG_RESET Off +set_global_assignment -name AUTO_GLOBAL_CLOCK On +set_global_assignment -name AUTO_GLOBAL_OE On +set_global_assignment -name AUTO_GLOBAL_REGISTER_CONTROLS On +set_global_assignment -name FITTER_EARLY_TIMING_ESTIMATE_MODE Realistic +set_global_assignment -name STRATIXGX_ALLOW_GIGE_UNDER_FULL_DATARATE_RANGE Off +set_global_assignment -name STRATIXGX_ALLOW_RX_CORECLK_FROM_NON_RX_CLKOUT_SOURCE_IN_DOUBLE_DATA_WIDTH_MODE Off +set_global_assignment -name STRATIXGX_ALLOW_GIGE_IN_DOUBLE_DATA_WIDTH_MODE Off +set_global_assignment -name STRATIXGX_ALLOW_PARALLEL_LOOPBACK_IN_DOUBLE_DATA_WIDTH_MODE Off +set_global_assignment -name STRATIXGX_ALLOW_XAUI_IN_SINGLE_DATA_WIDTH_MODE Off +set_global_assignment -name STRATIXGX_ALLOW_XAUI_WITH_CORECLK_SELECTED_AT_RATE_MATCHER Off +set_global_assignment -name STRATIXGX_ALLOW_XAUI_WITH_RX_CORECLK_FROM_NON_TXPLL_SOURCE Off +set_global_assignment -name STRATIXGX_ALLOW_GIGE_WITH_CORECLK_SELECTED_AT_RATE_MATCHER Off +set_global_assignment -name STRATIXGX_ALLOW_GIGE_WITHOUT_8B10B Off +set_global_assignment -name STRATIXGX_ALLOW_GIGE_WITH_RX_CORECLK_FROM_NON_TXPLL_SOURCE Off +set_global_assignment -name STRATIXGX_ALLOW_POST8B10B_LOOPBACK Off +set_global_assignment -name STRATIXGX_ALLOW_REVERSE_PARALLEL_LOOPBACK Off +set_global_assignment -name STRATIXGX_ALLOW_USE_OF_GXB_COUPLED_IOS Off +set_global_assignment -name GENERATE_GXB_RECONFIG_MIF Off +set_global_assignment -name GENERATE_GXB_RECONFIG_MIF_WITH_PLL Off +set_global_assignment -name RESERVE_ALL_UNUSED_PINS_WEAK_PULLUP "As input tri-stated with weak pull-up" +set_global_assignment -name STOP_AFTER_CONGESTION_MAP Off +set_global_assignment -name SAVE_INTERMEDIATE_FITTING_RESULTS Off +set_global_assignment -name ENABLE_HOLD_BACK_OFF On +set_global_assignment -name CONFIGURATION_VCCIO_LEVEL Auto +set_global_assignment -name FORCE_CONFIGURATION_VCCIO Off +set_global_assignment -name SYNCHRONIZER_IDENTIFICATION Off +set_global_assignment -name ENABLE_BENEFICIAL_SKEW_OPTIMIZATION -value OFF +set_global_assignment -name OPTIMIZE_FOR_METASTABILITY On +set_global_assignment -name CRC_ERROR_OPEN_DRAIN Off +set_global_assignment -name MAX_GLOBAL_CLOCKS_ALLOWED "-1 (Unlimited)" +set_global_assignment -name MAX_REGIONAL_CLOCKS_ALLOWED "-1 (Unlimited)" +set_global_assignment -name MAX_PERIPHERY_CLOCKS_ALLOWED "-1 (Unlimited)" +set_global_assignment -name MAX_CLOCKS_ALLOWED "-1 (Unlimited)" +set_global_assignment -name ACTIVE_SERIAL_CLOCK FREQ_40MHz +set_global_assignment -name STRATIXIII_MRAM_COMPATIBILITY On +set_global_assignment -name FORCE_FITTER_TO_AVOID_PERIPHERY_PLACEMENT_WARNINGS Off +set_global_assignment -name EDA_SIMULATION_TOOL "" +set_global_assignment -name EDA_TIMING_ANALYSIS_TOOL "" +set_global_assignment -name EDA_BOARD_DESIGN_TIMING_TOOL "" +set_global_assignment -name EDA_BOARD_DESIGN_SYMBOL_TOOL "" +set_global_assignment -name EDA_BOARD_DESIGN_SIGNAL_INTEGRITY_TOOL "" +set_global_assignment -name EDA_BOARD_DESIGN_BOUNDARY_SCAN_TOOL "" +set_global_assignment -name EDA_BOARD_DESIGN_TOOL "" +set_global_assignment -name EDA_FORMAL_VERIFICATION_TOOL "" +set_global_assignment -name EDA_RESYNTHESIS_TOOL "" +set_global_assignment -name ON_CHIP_BITSTREAM_DECOMPRESSION On +set_global_assignment -name COMPRESSION_MODE Off +set_global_assignment -name CLOCK_SOURCE Internal +set_global_assignment -name CONFIGURATION_CLOCK_FREQUENCY "10 MHz" +set_global_assignment -name CONFIGURATION_CLOCK_DIVISOR 1 +set_global_assignment -name ENABLE_LOW_VOLTAGE_MODE_ON_CONFIG_DEVICE On +set_global_assignment -name FLEX6K_ENABLE_LOW_VOLTAGE_MODE_ON_CONFIG_DEVICE Off +set_global_assignment -name FLEX10K_ENABLE_LOW_VOLTAGE_MODE_ON_CONFIG_DEVICE On +set_global_assignment -name MAX7000S_JTAG_USER_CODE FFFF +set_global_assignment -name STRATIX_JTAG_USER_CODE FFFFFFFF +set_global_assignment -name APEX20K_JTAG_USER_CODE FFFFFFFF +set_global_assignment -name MERCURY_JTAG_USER_CODE FFFFFFFF +set_global_assignment -name FLEX10K_JTAG_USER_CODE 7F +set_global_assignment -name MAX7000_JTAG_USER_CODE FFFFFFFF +set_global_assignment -name MAX7000_USE_CHECKSUM_AS_USERCODE Off +set_global_assignment -name USE_CHECKSUM_AS_USERCODE Off +set_global_assignment -name SECURITY_BIT Off +set_global_assignment -name USE_CONFIGURATION_DEVICE On -family ACEX1K +set_global_assignment -name USE_CONFIGURATION_DEVICE On -family MAX7000B +set_global_assignment -name USE_CONFIGURATION_DEVICE On -family "HardCopy II" +set_global_assignment -name USE_CONFIGURATION_DEVICE On -family FLEX10KA +set_global_assignment -name USE_CONFIGURATION_DEVICE Off -family "Stratix IV" +set_global_assignment -name USE_CONFIGURATION_DEVICE Off -family "Cyclone III" +set_global_assignment -name USE_CONFIGURATION_DEVICE On -family "HardCopy Stratix" +set_global_assignment -name USE_CONFIGURATION_DEVICE On -family APEX20KE +set_global_assignment -name USE_CONFIGURATION_DEVICE On -family MAX7000AE +set_global_assignment -name USE_CONFIGURATION_DEVICE On -family Cyclone +set_global_assignment -name USE_CONFIGURATION_DEVICE On -family "Stratix II GX" +set_global_assignment -name USE_CONFIGURATION_DEVICE On -family FLEX10K +set_global_assignment -name USE_CONFIGURATION_DEVICE On -family "MAX II" +set_global_assignment -name USE_CONFIGURATION_DEVICE On -family APEX20KC +set_global_assignment -name USE_CONFIGURATION_DEVICE Off -family "Arria II GX" +set_global_assignment -name USE_CONFIGURATION_DEVICE On -family "Stratix GX" +set_global_assignment -name USE_CONFIGURATION_DEVICE Off -family "HardCopy III" +set_global_assignment -name USE_CONFIGURATION_DEVICE On -family MAX7000S +set_global_assignment -name USE_CONFIGURATION_DEVICE On -family FLEX6000 +set_global_assignment -name USE_CONFIGURATION_DEVICE On -family "APEX II" +set_global_assignment -name USE_CONFIGURATION_DEVICE On -family FLEX10KE +set_global_assignment -name USE_CONFIGURATION_DEVICE On -family "Cyclone II" +set_global_assignment -name USE_CONFIGURATION_DEVICE Off -family "HardCopy IV" +set_global_assignment -name USE_CONFIGURATION_DEVICE Off -family "Cyclone III LS" +set_global_assignment -name USE_CONFIGURATION_DEVICE Off -family "Stratix III" +set_global_assignment -name USE_CONFIGURATION_DEVICE On -family "Arria GX" +set_global_assignment -name USE_CONFIGURATION_DEVICE On -family MAX3000A +set_global_assignment -name USE_CONFIGURATION_DEVICE On -family "Stratix II" +set_global_assignment -name USE_CONFIGURATION_DEVICE On -family Stratix +set_global_assignment -name CYCLONEIII_CONFIGURATION_DEVICE Auto +set_global_assignment -name STRATIXII_CONFIGURATION_DEVICE Auto +set_global_assignment -name APEX20K_CONFIGURATION_DEVICE Auto +set_global_assignment -name MERCURY_CONFIGURATION_DEVICE Auto +set_global_assignment -name FLEX6K_CONFIGURATION_DEVICE Auto +set_global_assignment -name FLEX10K_CONFIGURATION_DEVICE Auto +set_global_assignment -name CYCLONE_CONFIGURATION_DEVICE Auto +set_global_assignment -name STRATIX_CONFIGURATION_DEVICE Auto +set_global_assignment -name APEX20K_CONFIG_DEVICE_JTAG_USER_CODE FFFFFFFF +set_global_assignment -name STRATIX_CONFIG_DEVICE_JTAG_USER_CODE FFFFFFFF +set_global_assignment -name MERCURY_CONFIG_DEVICE_JTAG_USER_CODE FFFFFFFF +set_global_assignment -name FLEX10K_CONFIG_DEVICE_JTAG_USER_CODE FFFFFFFF +set_global_assignment -name EPROM_USE_CHECKSUM_AS_USERCODE Off +set_global_assignment -name AUTO_INCREMENT_CONFIG_DEVICE_JTAG_USER_CODE On +set_global_assignment -name DISABLE_NCS_AND_OE_PULLUPS_ON_CONFIG_DEVICE Off +set_global_assignment -name GENERATE_TTF_FILE Off +set_global_assignment -name GENERATE_RBF_FILE Off +set_global_assignment -name GENERATE_HEX_FILE Off +set_global_assignment -name HEXOUT_FILE_START_ADDRESS 0 +set_global_assignment -name HEXOUT_FILE_COUNT_DIRECTION Up +set_global_assignment -name RESERVE_ALL_UNUSED_PINS_NO_OUTPUT_GND "As output driving an unspecified signal" +set_global_assignment -name RELEASE_CLEARS_BEFORE_TRI_STATES Off +set_global_assignment -name AUTO_RESTART_CONFIGURATION On +set_global_assignment -name HARDCOPYII_POWER_ON_EXTRA_DELAY Off +set_global_assignment -name STRATIXII_MRAM_COMPATIBILITY Off +set_global_assignment -name CYCLONEII_M4K_COMPATIBILITY On +set_global_assignment -name ENABLE_OCT_DONE Off +set_global_assignment -name USE_CHECKERED_PATTERN_AS_UNINITIALIZED_RAM_CONTENT Off +set_global_assignment -name START_TIME 0ns +set_global_assignment -name SIMULATION_MODE TIMING +set_global_assignment -name AUTO_USE_SIMULATION_PDB_NETLIST Off +set_global_assignment -name ADD_DEFAULT_PINS_TO_SIMULATION_OUTPUT_WAVEFORMS On +set_global_assignment -name SETUP_HOLD_DETECTION Off +set_global_assignment -name SETUP_HOLD_DETECTION_INPUT_REGISTERS_BIDIR_PINS_DISABLED Off +set_global_assignment -name CHECK_OUTPUTS Off +set_global_assignment -name SIMULATION_COVERAGE On +set_global_assignment -name SIMULATION_COMPLETE_COVERAGE_REPORT_PANEL On +set_global_assignment -name SIMULATION_MISSING_1_VALUE_COVERAGE_REPORT_PANEL On +set_global_assignment -name SIMULATION_MISSING_0_VALUE_COVERAGE_REPORT_PANEL On +set_global_assignment -name GLITCH_DETECTION Off +set_global_assignment -name GLITCH_INTERVAL 1ns +set_global_assignment -name SIMULATOR_GENERATE_SIGNAL_ACTIVITY_FILE Off +set_global_assignment -name SIMULATION_WITH_GLITCH_FILTERING_WHEN_GENERATING_SAF On +set_global_assignment -name SIMULATION_BUS_CHANNEL_GROUPING Off +set_global_assignment -name SIMULATION_VDB_RESULT_FLUSH On +set_global_assignment -name VECTOR_COMPARE_TRIGGER_MODE INPUT_EDGE +set_global_assignment -name SIMULATION_NETLIST_VIEWER Off +set_global_assignment -name SIMULATION_INTERCONNECT_DELAY_MODEL_TYPE TRANSPORT +set_global_assignment -name SIMULATION_CELL_DELAY_MODEL_TYPE TRANSPORT +set_global_assignment -name SIMULATOR_GENERATE_POWERPLAY_VCD_FILE Off +set_global_assignment -name SIMULATOR_PVT_TIMING_MODEL_TYPE AUTO +set_global_assignment -name SIMULATION_WITH_AUTO_GLITCH_FILTERING AUTO +set_global_assignment -name DRC_TOP_FANOUT 50 +set_global_assignment -name DRC_FANOUT_EXCEEDING 30 +set_global_assignment -name DRC_GATED_CLOCK_FEED 30 +set_global_assignment -name HARDCOPY_FLOW_AUTOMATION MIGRATION_ONLY +set_global_assignment -name ENABLE_DRC_SETTINGS Off +set_global_assignment -name CLK_RULE_CLKNET_CLKSPINES_THRESHOLD 25 +set_global_assignment -name DRC_DETAIL_MESSAGE_LIMIT 10 +set_global_assignment -name DRC_VIOLATION_MESSAGE_LIMIT 30 +set_global_assignment -name DRC_DEADLOCK_STATE_LIMIT 2 +set_global_assignment -name MERGE_HEX_FILE Off +set_global_assignment -name GENERATE_SVF_FILE Off +set_global_assignment -name GENERATE_ISC_FILE Off +set_global_assignment -name GENERATE_JAM_FILE Off +set_global_assignment -name GENERATE_JBC_FILE Off +set_global_assignment -name GENERATE_JBC_FILE_COMPRESSED On +set_global_assignment -name GENERATE_CONFIG_SVF_FILE Off +set_global_assignment -name GENERATE_CONFIG_ISC_FILE Off +set_global_assignment -name GENERATE_CONFIG_JAM_FILE Off +set_global_assignment -name GENERATE_CONFIG_JBC_FILE Off +set_global_assignment -name GENERATE_CONFIG_JBC_FILE_COMPRESSED On +set_global_assignment -name GENERATE_CONFIG_HEXOUT_FILE Off +set_global_assignment -name ISP_CLAMP_STATE_DEFAULT "Tri-state" +set_global_assignment -name SIGNALPROBE_ALLOW_OVERUSE Off +set_global_assignment -name SIGNALPROBE_DURING_NORMAL_COMPILATION Off +set_global_assignment -name LOGICLOCK_INCREMENTAL_COMPILE_ASSIGNMENT Off +set_global_assignment -name POWER_DEFAULT_TOGGLE_RATE 12.5% +set_global_assignment -name POWER_DEFAULT_INPUT_IO_TOGGLE_RATE 12.5% +set_global_assignment -name POWER_USE_PVA On +set_global_assignment -name POWER_USE_INPUT_FILE "No File" +set_global_assignment -name POWER_USE_INPUT_FILES Off +set_global_assignment -name POWER_VCD_FILTER_GLITCHES On +set_global_assignment -name POWER_REPORT_SIGNAL_ACTIVITY Off +set_global_assignment -name POWER_REPORT_POWER_DISSIPATION Off +set_global_assignment -name POWER_USE_DEVICE_CHARACTERISTICS TYPICAL +set_global_assignment -name POWER_AUTO_COMPUTE_TJ On +set_global_assignment -name POWER_TJ_VALUE 25 +set_global_assignment -name POWER_USE_TA_VALUE 25 +set_global_assignment -name POWER_USE_CUSTOM_COOLING_SOLUTION Off +set_global_assignment -name POWER_BOARD_TEMPERATURE 25 +set_global_assignment -name INCREMENTAL_COMPILATION FULL_INCREMENTAL_COMPILATION +set_global_assignment -name AUTO_EXPORT_INCREMENTAL_COMPILATION Off +set_global_assignment -name INCREMENTAL_COMPILATION_EXPORT_NETLIST_TYPE POST_FIT +set_global_assignment -name OUTPUT_IO_TIMING_ENDPOINT "Near End" +set_global_assignment -name RTLV_REMOVE_FANOUT_FREE_REGISTERS On +set_global_assignment -name RTLV_SIMPLIFIED_LOGIC On +set_global_assignment -name RTLV_GROUP_RELATED_NODES On +set_global_assignment -name RTLV_GROUP_COMB_LOGIC_IN_CLOUD Off +set_global_assignment -name RTLV_GROUP_COMB_LOGIC_IN_CLOUD_TMV Off +set_global_assignment -name RTLV_GROUP_RELATED_NODES_TMV On +set_global_assignment -name EQC_CONSTANT_DFF_DETECTION On +set_global_assignment -name EQC_DUPLICATE_DFF_DETECTION On +set_global_assignment -name EQC_BBOX_MERGE On +set_global_assignment -name EQC_LVDS_MERGE On +set_global_assignment -name EQC_RAM_UNMERGING On +set_global_assignment -name EQC_DFF_SS_EMULATION On +set_global_assignment -name EQC_RAM_REGISTER_UNPACK On +set_global_assignment -name EQC_MAC_REGISTER_UNPACK On +set_global_assignment -name EQC_SET_PARTITION_BB_TO_VCC_GND On +set_global_assignment -name EQC_STRUCTURE_MATCHING On +set_global_assignment -name EQC_AUTO_BREAK_CONE On +set_global_assignment -name EQC_POWER_UP_COMPARE Off +set_global_assignment -name EQC_AUTO_COMP_LOOP_CUT On +set_global_assignment -name EQC_AUTO_INVERSION On +set_global_assignment -name EQC_AUTO_TERMINATE On +set_global_assignment -name EQC_SUB_CONE_REPORT Off +set_global_assignment -name EQC_RENAMING_RULES On +set_global_assignment -name EQC_PARAMETER_CHECK On +set_global_assignment -name EQC_AUTO_PORTSWAP On +set_global_assignment -name EQC_DETECT_DONT_CARES On +set_global_assignment -name EQC_SHOW_ALL_MAPPED_POINTS Off +set_global_assignment -name DUTY_CYCLE 50 -section_id ? +set_global_assignment -name INVERT_BASE_CLOCK Off -section_id ? +set_global_assignment -name MULTIPLY_BASE_CLOCK_PERIOD_BY 1 -section_id ? +set_global_assignment -name DIVIDE_BASE_CLOCK_PERIOD_BY 1 -section_id ? +set_global_assignment -name EDA_INPUT_GND_NAME GND -section_id ? +set_global_assignment -name EDA_INPUT_VCC_NAME VCC -section_id ? +set_global_assignment -name EDA_INPUT_DATA_FORMAT NONE -section_id ? +set_global_assignment -name EDA_SHOW_LMF_MAPPING_MESSAGES Off -section_id ? +set_global_assignment -name EDA_RUN_TOOL_AUTOMATICALLY Off -section_id ? +set_global_assignment -name RESYNTHESIS_RETIMING FULL -section_id ? +set_global_assignment -name RESYNTHESIS_OPTIMIZATION_EFFORT Normal -section_id ? +set_global_assignment -name RESYNTHESIS_PHYSICAL_SYNTHESIS Normal -section_id ? +set_global_assignment -name USE_GENERATED_PHYSICAL_CONSTRAINTS On -section_id ? +set_global_assignment -name VCCPD_VOLTAGE 3.3V -section_id ? +set_global_assignment -name EDA_USER_COMPILED_SIMULATION_LIBRARY_DIRECTORY "" -section_id ? +set_global_assignment -name EDA_LAUNCH_CMD_LINE_TOOL Off -section_id ? +set_global_assignment -name EDA_NATIVELINK_GENERATE_SCRIPT_ONLY Off -section_id ? +set_global_assignment -name EDA_WAIT_FOR_GUI_TOOL_COMPLETION Off -section_id ? +set_global_assignment -name EDA_TRUNCATE_LONG_HIERARCHY_PATHS Off -section_id ? +set_global_assignment -name EDA_FLATTEN_BUSES Off -section_id ? +set_global_assignment -name EDA_MAP_ILLEGAL_CHARACTERS Off -section_id ? +set_global_assignment -name EDA_GENERATE_TIMING_CLOSURE_DATA Off -section_id ? +set_global_assignment -name EDA_GENERATE_POWER_INPUT_FILE Off -section_id ? +set_global_assignment -name EDA_TEST_BENCH_ENABLE_STATUS NOT_USED -section_id ? +set_global_assignment -name EDA_RTL_SIM_MODE NOT_USED -section_id ? +set_global_assignment -name EDA_MAINTAIN_DESIGN_HIERARCHY Off -section_id ? +set_global_assignment -name EDA_GENERATE_FUNCTIONAL_NETLIST Off -section_id ? +set_global_assignment -name EDA_WRITE_DEVICE_CONTROL_PORTS Off -section_id ? +set_global_assignment -name EDA_SIMULATION_VCD_OUTPUT_TCL_FILE Off -section_id ? +set_global_assignment -name EDA_SIMULATION_VCD_OUTPUT_SIGNALS_TO_TCL_FILE "All Except Combinational Logic Element Outputs" -section_id ? +set_global_assignment -name EDA_ENABLE_GLITCH_FILTERING Off -section_id ? +set_global_assignment -name EDA_WRITE_NODES_FOR_POWER_ESTIMATION OFF -section_id ? +set_global_assignment -name EDA_SETUP_HOLD_DETECTION_INPUT_REGISTERS_BIDIR_PINS_DISABLED Off -section_id ? +set_global_assignment -name EDA_WRITER_DONT_WRITE_TOP_ENTITY Off -section_id ? +set_global_assignment -name EDA_VHDL_ARCH_NAME structure -section_id ? +set_global_assignment -name EDA_IBIS_MODEL_SELECTOR Off -section_id ? +set_global_assignment -name EDA_IBIS_MUTUAL_COUPLING Off -section_id ? +set_global_assignment -name EDA_FORMAL_VERIFICATION_ALLOW_RETIMING Off -section_id ? +set_global_assignment -name EDA_BOARD_BOUNDARY_SCAN_OPERATION PRE_CONFIG -section_id ? +set_global_assignment -name EDA_GENERATE_RTL_SIMULATION_COMMAND_SCRIPT Off -section_id ? +set_global_assignment -name EDA_GENERATE_GATE_LEVEL_SIMULATION_COMMAND_SCRIPT Off -section_id ? +set_global_assignment -name SIM_VECTOR_COMPARED_CLOCK_OFFSET 0ns -section_id ? +set_global_assignment -name SIM_VECTOR_COMPARED_CLOCK_DUTY_CYCLE 50 -section_id ? +set_global_assignment -name APEX20K_CLIQUE_TYPE LAB -section_id ? -entity ? +set_global_assignment -name MAX7K_CLIQUE_TYPE LAB -section_id ? -entity ? +set_global_assignment -name MERCURY_CLIQUE_TYPE LAB -section_id ? -entity ? +set_global_assignment -name FLEX6K_CLIQUE_TYPE LAB -section_id ? -entity ? +set_global_assignment -name FLEX10K_CLIQUE_TYPE LAB -section_id ? -entity ? +set_global_assignment -name PARTITION_IMPORT_ASSIGNMENTS On -section_id ? -entity ? +set_global_assignment -name PARTITION_IMPORT_EXISTING_ASSIGNMENTS REPLACE_CONFLICTING -section_id ? -entity ? +set_global_assignment -name PARTITION_IMPORT_EXISTING_LOGICLOCK_REGIONS REPLACE_CONFLICTING -section_id ? -entity ? +set_global_assignment -name PARTITION_IMPORT_PROMOTE_ASSIGNMENTS On -section_id ? -entity ? Index: System09/trunk/rtl/System09_Terasic_DE1/system09.qws =================================================================== --- System09/trunk/rtl/System09_Terasic_DE1/system09.qws (nonexistent) +++ System09/trunk/rtl/System09_Terasic_DE1/system09.qws (revision 117) @@ -0,0 +1,18 @@ +[ProjectWorkspace] +ptn_Child1=Frames +[ProjectWorkspace.Frames] +ptn_Child1=ChildFrames +[ProjectWorkspace.Frames.ChildFrames] +ptn_Child1=Document-0 +ptn_Child2=Document-1 +ptn_Child3=Document-2 +[ProjectWorkspace.Frames.ChildFrames.Document-0] +ptn_Child1=ViewFrame-0 +[ProjectWorkspace.Frames.ChildFrames.Document-0.ViewFrame-0] +DocPathName=../VHDL/ps2_keyboard.vhd +DocumentCLSID={ca385d57-a4c7-11d1-a098-0020affa43f2} +IsChildFrameDetached=False +IsActiveChildFrame=False +ptn_Child1=StateMap +[ProjectWorkspace.Frames.ChildFrames.Document-0.ViewFrame-0.StateMap] +AFC_IN_REPORT=False Index: System09/trunk/rtl/System09_Terasic_DE1/System09_Terasic_DE1.vhd.bak =================================================================== --- System09/trunk/rtl/System09_Terasic_DE1/System09_Terasic_DE1.vhd.bak (nonexistent) +++ System09/trunk/rtl/System09_Terasic_DE1/System09_Terasic_DE1.vhd.bak (revision 117) @@ -0,0 +1,1116 @@ +--=============================================================================-- +-- -- +-- System09 - Synthesizable System On a Chip - VHDL FPGA core top level file. -- +-- -- +--=============================================================================-- +-- +-- +-- File name : System09_Terasic_DE1.vhd +-- +-- Entity name : System09 +-- +-- Purpose : Top level file for 6809 compatible system on a chip +-- Designed with Alera EP2C20 Cyclone 2 FPGA. +-- Implemented with Terasic DE1 FPGA board, +-- +-- Dependencies : ieee.Std_Logic_1164 +-- ieee.std_logic_unsigned +-- ieee.std_logic_arith +-- ieee.numeric_std +-- +-- Uses : cpu09 (..\VHDL\cpu09.vhd) CPU core +-- dat_ram (..\VHDL\datram.vhd) Dynamic Address Translation +-- mon_rom (..\Cyclone2\mon_rom.vhd) Monitor ROM +-- acia6850 (..\VHDL\acia6850.vhd) ACIA (UART) +-- ACIA_Clock (..\VHDL\ACIA_Clock.vhd) ACIA Baud Rate Clock Divider +-- keyboard (..\VHDL\keyboard.vhd) PS/2 Keyboard register interface +-- ps2_keyboard (..\VHDL\ps2_keyboard.vhd) PS/2 Keyboard interface logic +-- keymap_rom (..\Cyclone2\keymap_rom.vhd) PS/2 Keyboard key code look up table +-- vdu8 (..\VHDL\vdu8.vhd) Video Display Unit +-- (..\Cyclone2\char_rom.vhd) Character Generator ROM (B16_RAM) +-- (..\Cyclone2\ram_2k.vhd) Text & Attribute RAM Buffer +-- seven_segment (..\VHDL\SevenSegment.vhd) Seven Segment Display +-- +-- Author : John E. Kent +-- dilbert57@opencores.org +-- +-- Memory Map : +-- +-- $0000 - $DFFF System RAM (512K Mapped via DAT) +-- $E000 - ACIA (SWTPc) +-- $E010 - Reserved for SWTPc FD-01 FD1771 FDC +-- $E020 - Keyboard +-- $E030 - VDU +-- $E040 - Reserved for SWTPc MP-T (was Compact Flash) +-- $E050 - Timer +-- $E060 - Reserved for Bus Trap (Hardware Breakpoint Logic) +-- $E070 - Reserved for Trace Buffer +-- $E080 - Reserved for SWTPc MP-ID 6821 PIA (?) +-- $E090 - Reserved for SWTPc MP-ID 6840 PTM (?) +-- $E0A0 - Switches in / LEDS out +-- $E0B0 - 7 Segment hex display +-- $E0C0 - Reserved +-- $E0D0 - Reserved +-- $E0E0 - Reserved +-- $E0F0 - Reserved +-- $E100 - $E13F Reserved IDE / Compact Flash Card +-- $E140 - $E17F Reserved for Ethernet MAC (XESS) +-- $E180 - $E1BF Reserved for Expansion Slot 0 (XESS) +-- $E1C0 - $E1FF Reserved for Expansion Slot 1 (XESS) +-- $E200 - $EFFF Reserved for Future I/O +-- $F000 - $F7FF RAM for Sys09bug monitor extensions +-- $F800 - $FFFF Sys09bug ROM (Read only) +-- $FFF0 - $FFFF DAT - Dynamic Address Translation (Write Only) +-- +-- +-- Copyright (C) 2003 - 2010 John Kent +-- +-- This program is free software: you can redistribute it and/or modify +-- it under the terms of the GNU General Public License as published by +-- the Free Software Foundation, either version 3 of the License, or +-- (at your option) any later version. +-- +-- This program is distributed in the hope that it will be useful, +-- but WITHOUT ANY WARRANTY; without even the implied warranty of +-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +-- GNU General Public License for more details. +-- +-- You should have received a copy of the GNU General Public License +-- along with this program. If not, see . +-- +--===========================================================================-- +-- +-- Revision History: +-- +--===========================================================================-- +-- +-- Version 0.1 - 20 March 2003 +-- Version 0.2 - 30 March 2003 +-- Version 0.3 - 29 April 2003 +-- Version 0.4 - 29 June 2003 +-- +-- Version 0.5 - 19 July 2003 +-- prints out "Hello World" +-- +-- Version 0.6 - 5 September 2003 +-- Runs SBUG +-- +-- Version 1.0- 6 Sep 2003 - John Kent +-- Inverted sys_clk +-- Initial release to Open Cores +-- +-- Version 1.1 - 17 Jan 2004 - John Kent +-- Updated miniUart. +-- +-- Version 1.2 - 25 Jan 2004 - John Kent +-- removed signals "test_alu" and "test_cc" +-- Trap hardware re-instated. +-- +-- Version 1.3 - 11 Feb 2004 - John Kent +-- Designed forked off to produce System09_VDU +-- Added VDU component +-- VDU runs at 25MHz and divides the clock by 2 for the CPU +-- UART Runs at 57.6 Kbps +-- +-- Version 2.0 - 2 September 2004 - John Kent +-- ported to Digilent Xilinx Spartan3 starter board +-- removed Compaact Flash and Trap Logic. +-- Replaced SBUG with KBug9s +-- +-- Version 2.1 - 21 November 2006 - John Kent +-- Replaced KBug9s with Sys09bug 1.0 +-- Inverted bottom nybble of DAT register outputs +-- Changed ROM & I/O decoding to be compatible with SWTPc +-- Upped the serial baud rate to 115.2 KBd +-- added multiple global clock buffers +-- (Uart would not operate correctly) +-- +-- Version 2.2 - 22 December 2006 - John Kent +-- Increased CPU clock from 12.5MHz to 25 MHz. +-- Removed some of the global clock buffers +-- Added LED output register +-- Changed address decoding to 4K Blocks +-- +-- Version 2.3 - 1 June 2007 - John Kent +-- Updated VDU & ACIA +-- Changed decoding for Sys09Bug +-- +-- Version 2.4 - 31 January 2008 - John Kent +-- ACIA does not appear to work. +-- Made RAM OE and WE strobes synchonous to sys_clk +-- +-- Version 2.5 - 23rd Feburary 2009 - John Kent +-- Implemented recommendation to remove vga_clk clock buffer +-- +-- Version 2.6 - 5th september 2010 - John Kent +-- Renamed ACIA_6850 to acia6850 +-- Updated generics on VDU8 +-- Shortened the "keyboard" label +-- Fixed up address label on CPU09 +-- Removed Flex RAM +-- Map RAM at $F000 - $F7FF +-- +-- Vesrion 2.7 - 22nd October 2010 - John Kent +-- Ported from Digilent XC3S200 Starter to +-- Terasic EP2C20 DE1 board. +-- +--===========================================================================-- +library ieee; + use ieee.std_logic_1164.all; + use IEEE.STD_LOGIC_ARITH.ALL; + use IEEE.STD_LOGIC_UNSIGNED.ALL; + use ieee.numeric_std.all; + +entity System09_Terasic_DE1 is + port( + -- clocks + clock_24 : in std_logic_vector(1 downto 0); + clock_27 : in std_logic; + clock_50 : in std_logic; -- System Clock input + ext_clock : in std_logic; + + -- push button keys + key : in std_logic_vector(3 downto 0); -- RST, NMI + + -- SRAM interface signals + + sram_ce_n : out std_logic; + sram_we_n : out std_logic; + sram_oe_n : out std_logic; + sram_ub_n : out std_logic; + sram_lb_n : out std_logic; + sram_addr : out std_logic_vector(17 downto 0); + sram_dq : inout std_logic_vector(15 downto 0); + + -- PS/2 Keyboard + ps2_clk : inout Std_logic; + ps2_dat : inout Std_Logic; + + -- ACIA/UART Interface + uart_rxd : in Std_Logic; + uart_txd : out Std_Logic; + + -- CRTC output signals + vga_r : out std_logic_vector(3 downto 0); + vga_g : out std_logic_vector(3 downto 0); + vga_b : out std_logic_vector(3 downto 0); + vga_hs : out Std_Logic; + vga_vs : out Std_Logic; + + -- LEDS & Switches + ledg : out std_logic_vector(7 downto 0); + ledr : out std_logic_vector(9 downto 0); + sw : in std_logic_vector(9 downto 0); + + -- hexadecimal display + hex0 : out std_logic_vector(6 downto 0); + hex1 : out std_logic_vector(6 downto 0); + hex2 : out std_logic_vector(6 downto 0); + hex3 : out std_logic_vector(6 downto 0); + + -- gnereal purpose I/O + gpio_0 : in std_logic_vector(35 downto 0); + gpio_1 : in std_logic_vector(35 downto 0); + + -- i2c interface + i2c_sclk : in std_logic; + i2c_sdat : in std_logic; + + -- audio codec + aud_adcdat : in std_logic; + aud_adclrck : in std_logic; + aud_bclk : in std_logic; + aud_dacdat : in std_logic; + aud_daclrck : in std_logic; + aud_xck : in std_logic; + + -- dram + dram_addr : out std_logic_vector(11 downto 0); + dram_dq : in std_logic_vector(15 downto 0); + dram_cs_n : out std_logic; + dram_ba_0 : in std_logic; + dram_ba_1 : in std_logic; + dram_ldqm : in std_logic; + dram_udqm : in std_logic; + dram_ras_n : out std_logic; + dram_cas_n : out std_logic; + dram_we_n : out std_logic; + dram_cke : in std_logic; + dram_clk : in std_logic; + + -- Flash memory + fl_addr : out std_logic_vector(21 downto 0); + fl_dq : in std_logic_vector(7 downto 0); + fl_rst_n : in std_logic; + fl_oe_n : out std_logic; + fl_we_n : out std_logic; + + -- JTAG + tck : in std_logic; + tcs : in std_logic; + tdi : in std_logic; + tdo : in std_logic + ); +end System09_Terasic_DE1; + +------------------------------------------------------------------------------- +-- Architecture for System09 +------------------------------------------------------------------------------- +architecture my_computer of System09_Terasic_DE1 is + ----------------------------------------------------------------------------- + -- constants + ----------------------------------------------------------------------------- + constant SYS_CLK_FREQ : integer := 50000000; -- FPGA System Clock + constant VGA_CLK_FREQ : integer := 25000000; -- VGA Pixel Clock + constant CPU_CLK_FREQ : integer := 25000000; -- CPU Clock + constant BAUD_Rate : integer := 57600; -- Baud Rate + constant ACIA_CLK_FREQ : integer := BAUD_Rate * 16; + + type hold_state_type is ( hold_release_state, hold_request_state ); + + ----------------------------------------------------------------------------- + -- Signals + ----------------------------------------------------------------------------- + + signal sys_clk : std_logic; + signal vga_clk : std_logic; + signal pll_locked : std_logic; + + -- CPU Interface signals + signal cpu_clk : std_logic; + signal cpu_rst : std_logic; + signal cpu_rw : std_logic; + signal cpu_vma : std_logic; + signal cpu_halt : std_logic; + signal cpu_hold : std_logic; + signal cpu_firq : std_logic; + signal cpu_irq : std_logic; + signal cpu_nmi : std_logic; + signal cpu_addr : std_logic_vector(15 downto 0); + signal cpu_data_in : std_logic_vector(7 downto 0); + signal cpu_data_out : std_logic_vector(7 downto 0); + + -- Dynamic Address Translation + signal dat_cs : std_logic; + signal dat_addr : std_logic_vector(7 downto 0); + + -- BOOT ROM + signal rom_cs : Std_logic; + signal rom_data_out : Std_Logic_Vector(7 downto 0); + + -- ACIA Interface signals + signal acia_clk : std_logic; + signal acia_cs : Std_Logic; + signal acia_data_out : Std_Logic_Vector(7 downto 0); + signal acia_irq : Std_Logic; + signal acia_rxd : Std_Logic; + signal acia_txd : Std_Logic; + signal acia_dcd_n : Std_Logic; +-- signal acia_rts_n : Std_Logic; + signal acia_cts_n : Std_Logic; + + -- keyboard port + signal kbd_data_out : std_logic_vector(7 downto 0); + signal kbd_cs : std_logic; + signal kbd_irq : std_logic; + + -- LEDs + signal leds_data_out : std_logic_vector(7 downto 0); + signal leds_cs : std_logic; + + -- Video Display Unit + signal vdu_cs : std_logic; + signal vdu_data_out : std_logic_vector(7 downto 0); + signal vga_red : std_logic; + signal vga_green : std_logic; + signal vga_blue : std_logic; + + -- LEDs + signal led_cs : std_logic; + signal led_data_out : std_logic_vector(7 downto 0); + + -- 7 Segment Display + signal hex_cs : std_logic; + signal hex_data_out : std_logic_vector(7 downto 0); + signal hex0_reg : std_logic_vector(7 downto 0); + signal hex1_reg : std_logic_vector(7 downto 0); + signal hex2_reg : std_logic_vector(7 downto 0); + signal hex3_reg : std_logic_vector(7 downto 0); + + -- interrupt timer + signal tmr_data_out : std_logic_vector(7 downto 0); + signal tmr_cs : std_logic; + signal tmr_irq : std_logic; + + -- hardware break point (trap) + signal hbp_data_out : std_logic_vector(7 downto 0); + signal hbp_cs : std_logic; + signal hbp_irq : std_logic; + + -- RAM + signal sram_cs : std_logic; -- memory chip select + signal sram_data_out : std_logic_vector(7 downto 0); + signal sram_ce : std_logic; + signal sram_ub : std_logic; + signal sram_lb : std_logic; + signal sram_we : std_logic; + signal sram_oe : std_logic; + + -- System Clock Prescaler + signal clk_count : std_logic; + +----------------------------------------------------------------- +-- +-- CPU09 CPU core +-- +----------------------------------------------------------------- + +component cpu09 + port ( + clk : in std_logic; + rst : in std_logic; + vma : out std_logic; + addr : out std_logic_vector(15 downto 0); + rw : out std_logic; + data_in : in std_logic_vector(7 downto 0); + data_out : out std_logic_vector(7 downto 0); + halt : in std_logic; + hold : in std_logic; + irq : in std_logic; + nmi : in std_logic; + firq : in std_logic + ); +end component; + +---------------------------------------- +-- +-- Dynamic Address Translation Registers +-- +---------------------------------------- +component dat_ram + port ( + clk : in std_logic; + rst : in std_logic; + cs : in std_logic; + rw : in std_logic; + addr_lo : in std_logic_vector(3 downto 0); + addr_hi : in std_logic_vector(3 downto 0); + data_in : in std_logic_vector(7 downto 0); + data_out : out std_logic_vector(7 downto 0) + ); +end component; + +---------------------------------------- +-- +-- 4KByte Block RAM Monitor ROM +-- +---------------------------------------- +component mon_rom + Port ( + clk : in std_logic; + rst : in std_logic; + cs : in std_logic; + rw : in std_logic; + addr : in std_logic_vector (10 downto 0); + data_in : in std_logic_vector (7 downto 0); + data_out : out std_logic_vector (7 downto 0) + ); +end component; + +----------------------------------------------------------------- +-- +-- 6850 ACIA +-- +----------------------------------------------------------------- + +component acia6850 + port ( + clk : in Std_Logic; -- System Clock + rst : in Std_Logic; -- Reset input (active high) + cs : in Std_Logic; -- ACIA Chip Select + rw : in Std_Logic; -- Read / Not Write + addr : in Std_Logic; -- Register Select + data_in : in Std_Logic_Vector(7 downto 0); -- Data Bus In + data_out : out Std_Logic_Vector(7 downto 0); -- Data Bus Out + irq : out Std_Logic; -- Interrupt + RxC : in Std_Logic; -- Receive Baud Clock + TxC : in Std_Logic; -- Transmit Baud Clock + RxD : in Std_Logic; -- Receive Data + TxD : out Std_Logic; -- Transmit Data + DCD_n : in Std_Logic; -- Data Carrier Detect + CTS_n : in Std_Logic; -- Clear To Send + RTS_n : out Std_Logic -- Request To send + ); +end component; + +----------------------------------------------------------------- +-- +-- ACIA Clock divider +-- +----------------------------------------------------------------- + +component ACIA_Clock + generic ( + SYS_CLK_FREQ : integer := SYS_CLK_FREQ; + ACIA_CLK_FREQ : integer := ACIA_CLK_FREQ + ); + port ( + clk : in Std_Logic; -- System Clock Input + acia_clk : out Std_logic -- ACIA Clock output + ); +end component; + +---------------------------------------- +-- +-- PS/2 Keyboard +-- +---------------------------------------- + +component keyboard + generic( + KBD_CLK_FREQ : integer := CPU_CLK_FREQ + ); + port( + clk : in std_logic; + rst : in std_logic; + cs : in std_logic; + addr : in std_logic; + rw : in std_logic; + data_in : in std_logic_vector(7 downto 0); + data_out : out std_logic_vector(7 downto 0); + irq : out std_logic; + kbd_clk : inout std_logic; + kbd_data : inout std_logic + ); +end component; + +---------------------------------------- +-- +-- Video Display Unit. +-- +---------------------------------------- +component vdu8 + generic( + VGA_CLK_FREQ : integer := VGA_CLK_FREQ; -- HZ + VGA_HOR_CHARS : integer := 80; -- CHARACTERS 25.6us + VGA_HOR_CHAR_PIXELS : integer := 8; -- PIXELS 0.32us + VGA_HOR_FRONT_PORCH : integer := 16; -- PIXELS 0.64us + VGA_HOR_SYNC : integer := 96; -- PIXELS 3.84us + VGA_HOR_BACK_PORCH : integer := 48; -- PIXELS 1.92us + VGA_VER_CHARS : integer := 25; -- CHARACTERS 12.8ms + VGA_VER_CHAR_LINES : integer := 16; -- LINES 0.512ms + VGA_VER_FRONT_PORCH : integer := 10; -- LINES 0.320ms + VGA_VER_SYNC : integer := 2; -- LINES 0.064ms + VGA_VER_BACK_PORCH : integer := 34 -- LINES 1.088ms + ); + port( + -- control register interface + vdu_clk : in std_logic; -- CPU Clock - 12.5MHz + vdu_rst : in std_logic; + vdu_cs : in std_logic; + vdu_rw : in std_logic; + vdu_addr : in std_logic_vector(2 downto 0); + vdu_data_in : in std_logic_vector(7 downto 0); + vdu_data_out : out std_logic_vector(7 downto 0); + + -- vga port connections + vga_clk : in std_logic; -- VGA Pixel Clock - 25 MHz + vga_red_o : out std_logic; + vga_green_o : out std_logic; + vga_blue_o : out std_logic; + vga_hsync_o : out std_logic; + vga_vsync_o : out std_logic + ); +end component; + +---------------------------------------- +-- +-- Interrupt timer +-- +---------------------------------------- + +component timer is + port ( + clk : in std_logic; + rst : in std_logic; + cs : in std_logic; + addr : in std_logic; + rw : in std_logic; + data_in : in std_logic_vector(7 downto 0); + data_out : out std_logic_vector(7 downto 0); + irq : out std_logic + ); +end component; + +---------------------------------------- +-- +-- hardware break point (bus trap) +-- +---------------------------------------- + +component trap is + port ( + clk : in std_logic; + rst : in std_logic; + cs : in std_logic; + rw : in std_logic; + vma : in std_logic; + addr : in std_logic_vector(15 downto 0); + data_in : in std_logic_vector(7 downto 0); + data_out : out std_logic_vector(7 downto 0); + irq : out std_logic + ); +end component; + + +component pll IS + PORT + ( + areset : IN STD_LOGIC := '0'; + inclk0 : IN STD_LOGIC := '0'; + c0 : OUT STD_LOGIC ; + c1 : OUT STD_LOGIC ; + c2 : OUT STD_LOGIC ; + locked : OUT STD_LOGIC + ); +END component; + +begin + ----------------------------------------------------------------------------- + -- Instantiation of internal components + ----------------------------------------------------------------------------- + +my_cpu : cpu09 port map ( + clk => cpu_clk, + rst => cpu_rst, + vma => cpu_vma, + addr => cpu_addr(15 downto 0), + rw => cpu_rw, + data_in => cpu_data_in, + data_out => cpu_data_out, + halt => cpu_halt, + hold => cpu_hold, + irq => cpu_irq, + nmi => cpu_nmi, + firq => cpu_firq + ); + +my_dat : dat_ram port map ( + clk => cpu_clk, + rst => cpu_rst, + cs => dat_cs, + addr_hi => cpu_addr(15 downto 12), + addr_lo => cpu_addr(3 downto 0), + rw => cpu_rw, + data_in => cpu_data_out, + data_out => dat_addr(7 downto 0) + ); + +my_rom : mon_rom port map ( + clk => cpu_clk, + rst => cpu_rst, + cs => rom_cs, + rw => '1', + addr => cpu_addr(10 downto 0), + data_in => cpu_data_out, + data_out => rom_data_out + ); + +my_acia : acia6850 port map ( + clk => cpu_clk, + rst => cpu_rst, + cs => acia_cs, + addr => cpu_addr(0), + rw => cpu_rw, + data_in => cpu_data_out, + data_out => acia_data_out, + irq => acia_irq, + RxC => acia_clk, + TxC => acia_clk, + RxD => acia_rxd, + TxD => acia_txd, + DCD_n => acia_dcd_n, + CTS_n => acia_cts_n, + RTS_n => open + ); + + +---------------------------------------- +-- +-- ACIA Clock +-- +---------------------------------------- +my_ACIA_Clock : ACIA_Clock + generic map( + SYS_CLK_FREQ => SYS_CLK_FREQ, + ACIA_CLK_FREQ => ACIA_CLK_FREQ + ) + port map( + clk => sys_clk, + acia_clk => acia_clk + ); + + +---------------------------------------- +-- +-- PS/2 Keyboard Interface +-- +---------------------------------------- +my_keyboard : keyboard + generic map ( + KBD_CLK_FREQ => CPU_CLK_FREQ + ) + port map( + clk => cpu_clk, + rst => cpu_rst, + cs => kbd_cs, + addr => cpu_addr(0), + rw => cpu_rw, + data_in => cpu_data_out(7 downto 0), + data_out => kbd_data_out(7 downto 0), + irq => kbd_irq, + kbd_clk => ps2_clk, + kbd_data => ps2_dat + ); + +---------------------------------------- +-- +-- Video Display Unit instantiation +-- +---------------------------------------- +my_vdu : vdu8 + generic map( + VGA_CLK_FREQ => VGA_CLK_FREQ, -- 25MHZ + VGA_HOR_CHARS => 80, -- CHARACTERS 25.6us + VGA_HOR_CHAR_PIXELS => 8, -- PIXELS 0.32us + VGA_HOR_FRONT_PORCH => 16, -- PIXELS 0.64us + VGA_HOR_SYNC => 96, -- PIXELS 3.84us + VGA_HOR_BACK_PORCH => 48, -- PIXELS 1.92us + VGA_VER_CHARS => 25, -- CHARACTERS 12.8ms + VGA_VER_CHAR_LINES => 16, -- LINES 0.512ms + VGA_VER_FRONT_PORCH => 10, -- LINES 0.320ms + VGA_VER_SYNC => 2, -- LINES 0.064ms + VGA_VER_BACK_PORCH => 34 -- LINES 1.088ms + ) + port map( + + -- Control Registers + vdu_clk => cpu_clk, -- 12.5 MHz System Clock in + vdu_rst => cpu_rst, + vdu_cs => vdu_cs, + vdu_addr => cpu_addr(2 downto 0), + vdu_rw => cpu_rw, + vdu_data_in => cpu_data_out, + vdu_data_out => vdu_data_out, + + -- vga port connections + vga_clk => vga_clk, -- 25 MHz pixel clock + vga_red_o => vga_red, + vga_green_o => vga_green, + vga_blue_o => vga_blue, + vga_hsync_o => vga_hs, + vga_vsync_o => vga_vs + ); + +---------------------------------------- +-- +-- Interrupt timer +-- +---------------------------------------- + +my_timer : timer + port map ( + clk => cpu_clk, + rst => cpu_rst, + cs => tmr_cs, + addr => cpu_addr(0), + rw => cpu_rw, + data_in => cpu_data_out, + data_out => tmr_data_out, + irq => tmr_irq + ); + +---------------------------------------- +-- +-- hardware break point (bus trap) +-- +---------------------------------------- + +my_hw_bp : trap + port map ( + clk => cpu_clk, + rst => cpu_rst, + cs => hbp_cs, + rw => cpu_rw, + vma => cpu_vma, + addr => cpu_addr, + data_in => cpu_data_out, + data_out => hbp_data_out, + irq => hbp_irq + ); + +---------------------------------------- +-- +-- Phase Locked Loop Clock divider +-- + +my_pll : pll + PORT MAP + ( + areset => '0', + inclk0 => clock_50, + c0 => sys_clk, + c1 => cpu_clk, + c2 => vga_clk, + locked => pll_locked + ); + +---------------------------------------------------------------------- +-- +-- Process to decode memory map +-- +---------------------------------------------------------------------- + +mem_decode: process( cpu_addr, cpu_rw, cpu_vma, + dat_cs, dat_addr, + rom_data_out, + acia_data_out, + kbd_data_out, + vdu_data_out, + hex_data_out, + led_data_out, + tmr_data_out, + hbp_data_out, + sram_data_out + ) +begin + cpu_data_in <= (others=>'0'); + dat_cs <= '0'; + rom_cs <= '0'; + acia_cs <= '0'; + kbd_cs <= '0'; + vdu_cs <= '0'; + hex_cs <= '0'; + led_cs <= '0'; + sram_cs <= '0'; + tmr_cs <= '0'; + hbp_cs <= '0'; +-- pb_cs <= '0'; +-- ide_cs <= '0'; +-- ether_cs <= '0'; +-- slot1_cs <= '0'; +-- slot2_cs <= '0'; + + if cpu_addr( 15 downto 8 ) = "11111111" then + cpu_data_in <= rom_data_out; + dat_cs <= cpu_vma; -- write DAT + rom_cs <= cpu_vma; -- read ROM + -- + -- Sys09Bug Monitor ROM $F000 - $FFFF + -- + elsif dat_addr(3 downto 0) = "1111" then -- $XF000 - $XFFFF + if cpu_addr(11) = '1' then + -- + -- Monitor ROM $F800 - $FFFF + -- + cpu_data_in <= rom_data_out; + rom_cs <= cpu_vma; -- read ROM + else + -- + -- SRAM $F000 - $F7FF + -- + cpu_data_in <= sram_data_out; + sram_cs <= cpu_vma; + end if; + -- + -- IO Devices $E000 - $EFFF + -- + elsif dat_addr(3 downto 0) = "1110" then -- $XE000 - $XEFFF + case cpu_addr(11 downto 8) is + -- + -- SWTPC peripherals from $E000 to $E0FF + -- + when "0000" => + case cpu_addr(7 downto 4) is + -- + -- ACIA ($E000 - $E00F) + -- + when "0000" => + cpu_data_in <= acia_data_out; + acia_cs <= cpu_vma; + + -- + -- Reserved - FD1771 FDC ($E010 - $E01F) (SWTPC) + -- + + -- + -- Keyboard port ($E020 - $E02F) + -- + when "0010" => + cpu_data_in <= kbd_data_out; + kbd_cs <= cpu_vma; + + -- + -- VDU port ($E030 - $E03F) + -- + when "0011" => + cpu_data_in <= vdu_data_out; + vdu_cs <= cpu_vma; + + -- + -- Reserved - SWTPc MP-T ($E040 - $E04F) + -- + + -- + -- Reserved - Timer ($E050 - $E05F) (B5-X300) + -- + when "0101" => + cpu_data_in <= tmr_data_out; + tmr_cs <= cpu_vma; + + -- + -- Reserved - hardware break point (Bus Trap) ($E060 - $E06F) + -- + when "0110" => + cpu_data_in <= hbp_data_out; + hbp_cs <= cpu_vma; + + -- + -- Reserved - I/O port ($E070 - $E07F) (B5-X300) + -- + + -- + -- Reserved - PTM 6840 ($E080 - $E08F) (SWTPC) + -- + + -- + -- Reserved - PIA Timer ($E090 - $E09F) (SWTPC) + -- + + -- + -- Read Switched port ($E0A0 - $E0AF) + -- Write LEDS + -- + when "1010" => + cpu_data_in <= led_data_out; + led_cs <= cpu_vma; + + -- + -- 7 segment display port ($E0B0 - $E0BF) + -- + when "1011" => + cpu_data_in <= hex_data_out; + hex_cs <= cpu_vma; + + + when others => -- $EXC0 to $EXFF + null; + end case; + -- + -- $E100 to $EFFF reserved for future use + -- + when others => + null; + end case; + -- + -- Everything else is RAM + -- + else + cpu_data_in <= sram_data_out; + sram_cs <= cpu_vma; + end if; +end process; + + +-- +-- 1M byte SRAM Control +-- Processes to read and write memory based on bus signals +-- +sram_process: process( sys_clk, cpu_rst, + cpu_addr, cpu_rw, cpu_vma, cpu_data_out, + dat_addr, sram_cs, + sram_ce, sram_ub, sram_lb, sram_dq, + sram_we, sram_oe ) +begin + -- + -- Clock Hold on rising edge + -- + if( sys_clk'event and sys_clk='1' ) then + -- + -- sram_hold signal helps + -- + if( cpu_rst = '1' ) then + sram_we <= '0'; + sram_oe <= '0'; + else + if (sram_cs = '1') and (sram_we = '0') and (sram_oe = '0') then + sram_we <= not cpu_rw; + sram_oe <= cpu_rw; + else + sram_we <= '0'; + sram_oe <= '0'; + end if; + end if; + end if; + + sram_we_n <= not sram_we; + sram_oe_n <= not sram_oe; + + sram_ce <= sram_cs; + sram_ub <= not cpu_addr(0); + sram_lb <= cpu_addr(0); + sram_ce_n <= not sram_ce; + sram_ub_n <= not sram_ub; + sram_lb_n <= not sram_lb; + + sram_addr(17 downto 11) <= dat_addr(6 downto 0); + sram_addr(10 downto 0) <= cpu_addr(11 downto 1); + + if sram_we = '1' and sram_ce = '1' and sram_lb = '1' then + sram_dq(7 downto 0) <= cpu_data_out; + else + sram_dq(7 downto 0) <= "ZZZZZZZZ"; + end if; + + if sram_we = '1' and sram_ce = '1' and sram_ub = '1' then + sram_dq(15 downto 8) <= cpu_data_out; + else + sram_dq(15 downto 8) <= "ZZZZZZZZ"; + end if; + + if cpu_addr(0) = '0' then + sram_data_out <= sram_dq(15 downto 8); + else + sram_data_out <= sram_dq(7 downto 0); + end if; + +end process; + +-- +-- LEDS output register +-- +led_output : process( cpu_clk, cpu_rst, led_cs, cpu_rw, cpu_addr, cpu_data_out, sw ) +begin + if cpu_clk'event and cpu_clk='0' then + if cpu_rst = '1' then + ledr <= (others=>'0'); + ledg <= (others=>'0'); + else + if led_cs = '1' and cpu_rw = '0' then + if cpu_addr(0) = '0' then + ledr(7 downto 0) <= cpu_data_out; + else + ledg(7 downto 0) <= cpu_data_out; + end if; + end if; + end if; + end if; + led_data_out <= sw(7 downto 0); +end process; + +-- +-- 7 segment HEX display output register +-- +hex_output : process( cpu_clk, cpu_rst, hex_cs, cpu_rw, cpu_addr, cpu_data_out, + hex0_reg, hex1_reg, hex2_reg, hex3_reg ) +begin + if cpu_clk'event and cpu_clk='0' then + if cpu_rst = '1' then + hex0_reg <= (others=>'0'); + hex1_reg <= (others=>'0'); + hex2_reg <= (others=>'0'); + hex3_reg <= (others=>'0'); + else + if hex_cs = '1' and cpu_rw = '0' then + case cpu_addr(1 downto 0) is + when "00" => + hex0_reg <= cpu_data_out; + when "01" => + hex1_reg <= cpu_data_out; + when "10" => + hex2_reg <= cpu_data_out; + when "11" => + hex3_reg <= cpu_data_out; + end case; + end if; + end if; + end if; + + case cpu_addr(1 downto 0) is + when "00" => + hex_data_out <= hex0_reg; + when "01" => + hex_data_out <= hex1_reg; + when "10" => + hex_data_out <= hex2_reg; + when "11" => + hex_data_out <= hex3_reg; + end case; + + hex0 <= not hex0_reg(6 downto 0); + hex1 <= not hex1_reg(6 downto 0); + hex2 <= not hex2_reg(6 downto 0); + hex3 <= not hex3_reg(6 downto 0); + +end process; + +-- +-- Interrupts and other bus control signals +-- +interrupts : process( key, pll_locked, + acia_irq, kbd_irq, hbp_irq, tmr_irq ) +begin + cpu_rst <= not key(0); -- CPU reset is active high + cpu_firq <= kbd_irq; + cpu_nmi <= (not key(1)) or hbp_irq; + cpu_irq <= acia_irq or tmr_irq; + cpu_halt <= '0'; + cpu_hold <= '0'; +end process; + +-- +-- ACIA pin assignments +-- +acia_assignments : process( uart_rxd, acia_txd ) +begin + acia_dcd_n <= '0'; + acia_cts_n <= '0'; + acia_rxd <= uart_rxd; + uart_txd <= acia_txd; +end process; + +-- +-- assign vga colour bits to single bit RGB output of VDU +-- +vga_assignments : process( vga_red, vga_green, vga_blue ) +begin + vga_r <= (others=>vga_red); + vga_g <= (others=>vga_green); + vga_b <= (others=>vga_blue); +end process; + +-- +-- assign dram signals +-- +dram_assign : process( all ) +begin + dram_addr <= (others=>'0'); + dram_cs_n <= '1'; + dram_ras_n <= '1'; + dram_cas_n <= '1'; + dram_we_n <= '1'; +end process; + +-- +-- assign flash memory signals +-- +flash_assign : process( all ) +begin + fl_addr <= (others=>'0'); + fl_oe_n <= '1'; + fl_we_n <= '1'; + +end process; + +end my_computer; --===================== End of architecture =======================-- + Index: System09/trunk/rtl/System09_Terasic_DE1/undo_redo.txt =================================================================== --- System09/trunk/rtl/System09_Terasic_DE1/undo_redo.txt (nonexistent) +++ System09/trunk/rtl/System09_Terasic_DE1/undo_redo.txt (revision 117) @@ -0,0 +1,15 @@ +RPW + + Undo Commands + 1. ||Compilation Report||Flow Summary + 2. ||Compilation Report||Timing Analyzer||Clock Hold: 'pll:my_pll|altpll:altpll_component|_clk2' + 3. ||Compilation Report||Timing Analyzer||Clock Hold: 'pll:my_pll|altpll:altpll_component|_clk1' + 4. ||Compilation Report||Timing Analyzer||Clock Hold: 'pll:my_pll|altpll:altpll_component|_clk0' + 5. ||Compilation Report||Timing Analyzer||Clock Setup: 'pll:my_pll|altpll:altpll_component|_clk2' + 6. ||Compilation Report||Timing Analyzer||Clock Setup: 'pll:my_pll|altpll:altpll_component|_clk1' + 7. ||Compilation Report||Timing Analyzer||Clock Setup: 'pll:my_pll|altpll:altpll_component|_clk0' + 8. ||Compilation Report||Timing Analyzer||Clock Settings Summary + 9. ||Compilation Report||Flow Summary + 10. ||Compilation Report||Timing Analyzer||Timing Analyzer Summary + +

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.