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URL https://opencores.org/ocsvn/System09/System09/trunk

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  • This comparison shows the changes necessary to convert path 
    /
    from Rev 117 to Rev 118
    ↔ Reverse comparison
  •

Rev 117 → Rev 118

/System09/trunk/rtl/Spartan3/ram32k_b16.vhd
1,21 → 1,60
-- $Id: ram32k_b16.vhd,v 1.2 2008/03/14 15:52:43 dilbert57 Exp $
--===================================================================
--===========================================================================--
-- --
-- ram32k_b16.vhd - 32KByte Block RAM Component for Spartan 3/3E --
-- --
--===========================================================================--
--
-- File name : ram32k_b16.vhd
--
-- Entity name : ram_32k
--
-- Purpose : Implements 32K of Synchronous Static RAM
-- using 16 x Spartan 3/3E RAMB16_S9 block rams
-- Used in the Digilent Spartan 3E500 System09 design
--
-- Dependencies : ieee.Std_Logic_1164
-- ieee.std_logic_arith
-- unisim.vcomponents
--
-- Uses : RAMB16_S9
--
-- Author : John E. Kent
--
-- Email : dilbert57@opencores.org
--
-- Web : http://opencores.org/project,system09
--
--
-- Copyright (C) 2005 - 2010 John Kent
--
-- This program is free software: you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation, either version 3 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program. If not, see <http://www.gnu.org/licenses/>.
--
--===========================================================================--
-- --
-- Revision History --
-- --
--===========================================================================--
--
-- Version Author Date Changes
--
-- 0.1 John Kent 2006-04-24 Initial release
-- 0.2 John Kent 2005-06-29 Added CS term to CE decodes. (date ???)
-- 0.3 John Kent 2010-09-14 Renamed "rdata" to "data_out"
-- Renamed "wdata" to "data_in"
-- Added header description
--
-- 32K Block RAM
--
--===================================================================
--
-- Date: 24th April 2006
-- Author: John Kent
--
-- Revision History:
-- 24 April 2006 John Kent
-- Initial release
--
-- 29th June 2005 John Kent
-- Added CS term to CE decodes.
--
--
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
24,13 → 63,13
 
entity ram_32k is
Port (
clk : in std_logic;
rst : in std_logic;
cs : in std_logic;
rw : in std_logic;
addr : in std_logic_vector (14 downto 0);
rdata : out std_logic_vector (7 downto 0);
wdata : in std_logic_vector (7 downto 0)
clk : in std_logic;
rst : in std_logic;
cs : in std_logic;
addr : in std_logic_vector (14 downto 0);
rw : in std_logic;
data_in : in std_logic_vector (7 downto 0);
data_out : out std_logic_vector (7 downto 0)
);
end ram_32k;
 
37,25 → 76,25
architecture rtl of ram_32k is
 
 
signal we : std_logic;
signal dp : std_logic_vector(15 downto 0);
signal ce : std_logic_vector(15 downto 0);
signal rdata_0 : std_logic_vector(7 downto 0);
signal rdata_1 : std_logic_vector(7 downto 0);
signal rdata_2 : std_logic_vector(7 downto 0);
signal rdata_3 : std_logic_vector(7 downto 0);
signal rdata_4 : std_logic_vector(7 downto 0);
signal rdata_5 : std_logic_vector(7 downto 0);
signal rdata_6 : std_logic_vector(7 downto 0);
signal rdata_7 : std_logic_vector(7 downto 0);
signal rdata_8 : std_logic_vector(7 downto 0);
signal rdata_9 : std_logic_vector(7 downto 0);
signal rdata_a : std_logic_vector(7 downto 0);
signal rdata_b : std_logic_vector(7 downto 0);
signal rdata_c : std_logic_vector(7 downto 0);
signal rdata_d : std_logic_vector(7 downto 0);
signal rdata_e : std_logic_vector(7 downto 0);
signal rdata_f : std_logic_vector(7 downto 0);
signal we : std_logic;
signal dp : std_logic_vector(15 downto 0);
signal ce : std_logic_vector(15 downto 0);
signal data_out_0 : std_logic_vector(7 downto 0);
signal data_out_1 : std_logic_vector(7 downto 0);
signal data_out_2 : std_logic_vector(7 downto 0);
signal data_out_3 : std_logic_vector(7 downto 0);
signal data_out_4 : std_logic_vector(7 downto 0);
signal data_out_5 : std_logic_vector(7 downto 0);
signal data_out_6 : std_logic_vector(7 downto 0);
signal data_out_7 : std_logic_vector(7 downto 0);
signal data_out_8 : std_logic_vector(7 downto 0);
signal data_out_9 : std_logic_vector(7 downto 0);
signal data_out_a : std_logic_vector(7 downto 0);
signal data_out_b : std_logic_vector(7 downto 0);
signal data_out_c : std_logic_vector(7 downto 0);
signal data_out_d : std_logic_vector(7 downto 0);
signal data_out_e : std_logic_vector(7 downto 0);
signal data_out_f : std_logic_vector(7 downto 0);
 
begin
 
128,11 → 167,11
)
 
port map (
do => rdata_0,
do => data_out_0,
dop(0) => dp(0),
addr => addr(10 downto 0),
clk => clk,
di => wdata,
di => data_in,
dip(0) => dp(0),
en => ce(0),
ssr => rst,
208,11 → 247,11
)
 
port map (
do => rdata_1,
do => data_out_1,
dop(0) => dp(1),
addr => addr(10 downto 0),
clk => clk,
di => wdata,
di => data_in,
dip(0) => dp(1),
en => ce(1),
ssr => rst,
288,11 → 327,11
)
 
port map (
do => rdata_2,
do => data_out_2,
dop(0) => dp(2),
addr => addr(10 downto 0),
clk => clk,
di => wdata,
di => data_in,
dip(0) => dp(2),
en => ce(2),
ssr => rst,
368,11 → 407,11
)
 
port map (
do => rdata_3,
do => data_out_3,
dop(0) => dp(3),
addr => addr(10 downto 0),
clk => clk,
di => wdata,
di => data_in,
dip(0) => dp(3),
en => ce(3),
ssr => rst,
448,11 → 487,11
)
 
port map (
do => rdata_4,
do => data_out_4,
dop(0) => dp(4),
addr => addr(10 downto 0),
clk => clk,
di => wdata,
di => data_in,
dip(0) => dp(4),
en => ce(4),
ssr => rst,
528,11 → 567,11
)
 
port map (
do => rdata_5,
do => data_out_5,
dop(0) => dp(5),
addr => addr(10 downto 0),
clk => clk,
di => wdata,
di => data_in,
dip(0) => dp(5),
en => ce(5),
ssr => rst,
608,11 → 647,11
)
 
port map (
do => rdata_6,
do => data_out_6,
dop(0) => dp(6),
addr => addr(10 downto 0),
clk => clk,
di => wdata,
di => data_in,
dip(0) => dp(6),
en => ce(6),
ssr => rst,
688,11 → 727,11
)
 
port map (
do => rdata_7,
do => data_out_7,
dop(0) => dp(7),
addr => addr(10 downto 0),
clk => clk,
di => wdata,
di => data_in,
dip(0) => dp(7),
en => ce(7),
ssr => rst,
768,11 → 807,11
)
 
port map (
do => rdata_8,
do => data_out_8,
dop(0) => dp(8),
addr => addr(10 downto 0),
clk => clk,
di => wdata,
di => data_in,
dip(0) => dp(8),
en => ce(8),
ssr => rst,
848,11 → 887,11
)
 
port map (
do => rdata_9,
do => data_out_9,
dop(0) => dp(9),
addr => addr(10 downto 0),
clk => clk,
di => wdata,
di => data_in,
dip(0) => dp(9),
en => ce(9),
ssr => rst,
928,11 → 967,11
)
 
port map (
do => rdata_a,
do => data_out_a,
dop(0) => dp(10),
addr => addr(10 downto 0),
clk => clk,
di => wdata,
di => data_in,
dip(0) => dp(10),
en => ce(10),
ssr => rst,
1008,11 → 1047,11
)
 
port map (
do => rdata_b,
do => data_out_b,
dop(0) => dp(11),
addr => addr(10 downto 0),
clk => clk,
di => wdata,
di => data_in,
dip(0) => dp(11),
en => ce(11),
ssr => rst,
1088,11 → 1127,11
)
 
port map (
do => rdata_c,
do => data_out_c,
dop(0) => dp(12),
addr => addr(10 downto 0),
clk => clk,
di => wdata,
di => data_in,
dip(0) => dp(12),
en => ce(12),
ssr => rst,
1168,11 → 1207,11
)
 
port map (
do => rdata_d,
do => data_out_d,
dop(0) => dp(13),
addr => addr(10 downto 0),
clk => clk,
di => wdata,
di => data_in,
dip(0) => dp(13),
en => ce(13),
ssr => rst,
1248,11 → 1287,11
)
 
port map (
do => rdata_e,
do => data_out_e,
dop(0) => dp(14),
addr => addr(10 downto 0),
clk => clk,
di => wdata,
di => data_in,
dip(0) => dp(14),
en => ce(14),
ssr => rst,
1328,11 → 1367,11
)
 
port map (
do => rdata_f,
do => data_out_f,
dop(0) => dp(15),
addr => addr(10 downto 0),
clk => clk,
di => wdata,
di => data_in,
dip(0) => dp(15),
en => ce(15),
ssr => rst,
1340,46 → 1379,46
);
 
my_ram_32k : process ( cs, rw, addr,
rdata_0, rdata_1, rdata_2, rdata_3,
rdata_4, rdata_5, rdata_6, rdata_7,
rdata_8, rdata_9, rdata_a, rdata_b,
rdata_c, rdata_d, rdata_e, rdata_f )
data_out_0, data_out_1, data_out_2, data_out_3,
data_out_4, data_out_5, data_out_6, data_out_7,
data_out_8, data_out_9, data_out_a, data_out_b,
data_out_c, data_out_d, data_out_e, data_out_f )
begin
we <= not rw;
case addr(14 downto 11) is
when "0000" =>
rdata <= rdata_0;
data_out <= data_out_0;
when "0001" =>
rdata <= rdata_1;
data_out <= data_out_1;
when "0010" =>
rdata <= rdata_2;
data_out <= data_out_2;
when "0011" =>
rdata <= rdata_3;
data_out <= data_out_3;
when "0100" =>
rdata <= rdata_4;
data_out <= data_out_4;
when "0101" =>
rdata <= rdata_5;
data_out <= data_out_5;
when "0110" =>
rdata <= rdata_6;
data_out <= data_out_6;
when "0111" =>
rdata <= rdata_7;
data_out <= data_out_7;
when "1000" =>
rdata <= rdata_8;
data_out <= data_out_8;
when "1001" =>
rdata <= rdata_9;
data_out <= data_out_9;
when "1010" =>
rdata <= rdata_a;
data_out <= data_out_a;
when "1011" =>
rdata <= rdata_b;
data_out <= data_out_b;
when "1100" =>
rdata <= rdata_c;
data_out <= data_out_c;
when "1101" =>
rdata <= rdata_d;
data_out <= data_out_d;
when "1110" =>
rdata <= rdata_e;
data_out <= data_out_e;
when "1111" =>
rdata <= rdata_f;
data_out <= data_out_f;
when others =>
null;
end case;
/System09/trunk/rtl/Spartan3/sys09s3e_b16.vhd
0,0 → 1,348
--===========================================================================--
-- --
-- sys09s3e_b16.vhd - System09 Bug monitor ROM for the Spartan 3E500 --
-- --
--===========================================================================--
--
-- File name : sys09s3e_b16.vhd
--
-- Entity name : SYS09BUG_F000
-- SYS09BUG_F800
--
-- Purpose : Implements 4K Monitor ROM for System09
-- using 2 x Spartan 3E RAMB16_S9 block rams
-- Used in the Digilent Spartan 3E500 System09 design
--
-- Dependencies : ieee.Std_Logic_1164
-- ieee.std_logic_arith
-- unisim.vcomponents
--
-- Uses : RAMB16_S9
--
-- Author : John E. Kent
--
-- Email : dilbert57@opencores.org
--
-- Web : http://opencores.org/project,system09
--
--
-- Copyright (C) 2005 - 2010 John Kent
--
-- This program is free software: you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation, either version 3 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program. If not, see <http://www.gnu.org/licenses/>.
--
--===========================================================================--
-- --
-- Revision History --
-- --
--===========================================================================--
--
-- Version Author Date Changes
-- 0.1 John Kent unknown Initial Version
-- 0.2 John Kent 2010-09-14 Added Header
-- renamed rdata & wdata to data_out & data_in
--
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
library unisim;
use unisim.vcomponents.all;
 
entity SYS09BUG_F000 is
port(
clk : in std_logic;
rst : in std_logic;
cs : in std_logic;
addr : in std_logic_vector(10 downto 0);
rw : in std_logic;
data_in : in std_logic_vector(7 downto 0);
data_out : out std_logic_vector(7 downto 0)
);
end SYS09BUG_F000;
 
architecture rtl of SYS09BUG_F000 is
 
type data_array is array(0 to 0) of std_logic_vector(7 downto 0);
signal xdata : data_array;
signal en : std_logic_vector(0 downto 0);
signal dp : std_logic_vector(0 downto 0);
signal we : std_logic;
 
component RAMB16_S9
generic (
INIT_00, INIT_01, INIT_02, INIT_03,
INIT_04, INIT_05, INIT_06, INIT_07,
INIT_08, INIT_09, INIT_0A, INIT_0B,
INIT_0C, INIT_0D, INIT_0E, INIT_0F,
INIT_10, INIT_11, INIT_12, INIT_13,
INIT_14, INIT_15, INIT_16, INIT_17,
INIT_18, INIT_19, INIT_1A, INIT_1B,
INIT_1C, INIT_1D, INIT_1E, INIT_1F,
INIT_20, INIT_21, INIT_22, INIT_23,
INIT_24, INIT_25, INIT_26, INIT_27,
INIT_28, INIT_29, INIT_2A, INIT_2B,
INIT_2C, INIT_2D, INIT_2E, INIT_2F,
INIT_30, INIT_31, INIT_32, INIT_33,
INIT_34, INIT_35, INIT_36, INIT_37,
INIT_38, INIT_39, INIT_3A, INIT_3B,
INIT_3C, INIT_3D, INIT_3E, INIT_3F : bit_vector (255 downto 0)
);
 
port (
clk : in std_logic;
ssr : in std_logic;
en : in std_logic;
we : in std_logic;
addr : in std_logic_vector(10 downto 0);
di : in std_logic_vector( 7 downto 0);
dip : in std_logic_vector( 0 downto 0);
do : out std_logic_vector( 7 downto 0);
dop : out std_logic_vector( 0 downto 0)
);
end component RAMB16_S9;
 
begin
 
ROM00: RAMB16_S9
generic map (
INIT_00 => x"0000000000000000000000000000000000000000000000000000000000000000",
INIT_01 => x"0000000000000000000000000000000000000000000000000000000000000000",
INIT_02 => x"0000000000000000000000000000000000000000000000000000000000000000",
INIT_03 => x"0000000000000000000000000000000000000000000000000000000000000000",
INIT_04 => x"0000000000000000000000000000000000000000000000000000000000000000",
INIT_05 => x"0000000000000000000000000000000000000000000000000000000000000000",
INIT_06 => x"0000000000000000000000000000000000000000000000000000000000000000",
INIT_07 => x"0000000000000000000000000000000000000000000000000000000000000000",
INIT_08 => x"0000000000000000000000000000000000000000000000000000000000000000",
INIT_09 => x"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0a => x"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0b => x"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0c => x"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0d => x"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0e => x"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0f => x"0000000000000000000000000000000000000000000000000000000000000000",
INIT_10 => x"0000000000000000000000000000000000000000000000000000000000000000",
INIT_11 => x"0000000000000000000000000000000000000000000000000000000000000000",
INIT_12 => x"0000000000000000000000000000000000000000000000000000000000000000",
INIT_13 => x"0000000000000000000000000000000000000000000000000000000000000000",
INIT_14 => x"0000000000000000000000000000000000000000000000000000000000000000",
INIT_15 => x"0000000000000000000000000000000000000000000000000000000000000000",
INIT_16 => x"0000000000000000000000000000000000000000000000000000000000000000",
INIT_17 => x"0000000000000000000000000000000000000000000000000000000000000000",
INIT_18 => x"0000000000000000000000000000000000000000000000000000000000000000",
INIT_19 => x"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1a => x"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1b => x"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1c => x"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1d => x"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1e => x"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1f => x"0000000000000000000000000000000000000000000000000000000000000000",
INIT_20 => x"0000000000000000000000000000000000000000000000000000000000000000",
INIT_21 => x"0000000000000000000000000000000000000000000000000000000000000000",
INIT_22 => x"0000000000000000000000000000000000000000000000000000000000000000",
INIT_23 => x"0000000000000000000000000000000000000000000000000000000000000000",
INIT_24 => x"0000000000000000000000000000000000000000000000000000000000000000",
INIT_25 => x"0000000000000000000000000000000000000000000000000000000000000000",
INIT_26 => x"0000000000000000000000000000000000000000000000000000000000000000",
INIT_27 => x"0000000000000000000000000000000000000000000000000000000000000000",
INIT_28 => x"0000000000000000000000000000000000000000000000000000000000000000",
INIT_29 => x"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2a => x"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2b => x"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2c => x"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2d => x"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2e => x"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2f => x"0000000000000000000000000000000000000000000000000000000000000000",
INIT_30 => x"0000000000000000000000000000000000000000000000000000000000000000",
INIT_31 => x"0000000000000000000000000000000000000000000000000000000000000000",
INIT_32 => x"0000000000000000000000000000000000000000000000000000000000000000",
INIT_33 => x"0000000000000000000000000000000000000000000000000000000000000000",
INIT_34 => x"0000000000000000000000000000000000000000000000000000000000000000",
INIT_35 => x"0000000000000000000000000000000000000000000000000000000000000000",
INIT_36 => x"0000000000000000000000000000000000000000000000000000000000000000",
INIT_37 => x"0000000000000000000000000000000000000000000000000000000000000000",
INIT_38 => x"0000000000000000000000000000000000000000000000000000000000000000",
INIT_39 => x"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3a => x"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3b => x"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3c => x"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3d => x"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3e => x"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3f => x"0000000000000000000000000000000000000000000000000000000000000000"
)
port map (
clk => clk,
ssr => rst,
en => en(0),
we => we,
addr => addr(10 downto 0),
di => data_in,
dip(0) => dp(0),
do => xdata(0),
dop(0) => dp(0)
);
rom_glue: process (cs, rw, addr, xdata)
begin
en(0) <= cs;
data_out <= xdata(0);
we <= not rw;
end process;
end architecture rtl;
 
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
library unisim;
use unisim.vcomponents.all;
 
entity SYS09BUG_F800 is
port(
clk : in std_logic;
rst : in std_logic;
cs : in std_logic;
addr : in std_logic_vector(10 downto 0);
rw : in std_logic;
data_in : in std_logic_vector(7 downto 0);
data_out : out std_logic_vector(7 downto 0)
);
end SYS09BUG_F800;
 
architecture rtl of SYS09BUG_F800 is
 
type data_array is array(0 to 0) of std_logic_vector(7 downto 0);
signal xdata : data_array;
signal en : std_logic_vector(0 downto 0);
signal dp : std_logic_vector(0 downto 0);
signal we : std_logic;
 
component RAMB16_S9
generic (
INIT_00, INIT_01, INIT_02, INIT_03,
INIT_04, INIT_05, INIT_06, INIT_07,
INIT_08, INIT_09, INIT_0A, INIT_0B,
INIT_0C, INIT_0D, INIT_0E, INIT_0F,
INIT_10, INIT_11, INIT_12, INIT_13,
INIT_14, INIT_15, INIT_16, INIT_17,
INIT_18, INIT_19, INIT_1A, INIT_1B,
INIT_1C, INIT_1D, INIT_1E, INIT_1F,
INIT_20, INIT_21, INIT_22, INIT_23,
INIT_24, INIT_25, INIT_26, INIT_27,
INIT_28, INIT_29, INIT_2A, INIT_2B,
INIT_2C, INIT_2D, INIT_2E, INIT_2F,
INIT_30, INIT_31, INIT_32, INIT_33,
INIT_34, INIT_35, INIT_36, INIT_37,
INIT_38, INIT_39, INIT_3A, INIT_3B,
INIT_3C, INIT_3D, INIT_3E, INIT_3F : bit_vector (255 downto 0)
);
 
port (
clk : in std_logic;
ssr : in std_logic;
en : in std_logic;
we : in std_logic;
addr : in std_logic_vector(10 downto 0);
di : in std_logic_vector( 7 downto 0);
dip : in std_logic_vector( 0 downto 0);
do : out std_logic_vector( 7 downto 0);
dop : out std_logic_vector( 0 downto 0)
);
end component RAMB16_S9;
 
begin
 
ROM00: RAMB16_S9
generic map (
INIT_00 => x"A780A610C6C07F8E104EFE8ECFFE0DFB11FB82FBBDFCA8FC8AFC90FC4BF814F8",
INIT_01 => x"17431FE4A7D0866AAFDD8C30FB265AE26F0CC6450117D07FBF00E08EF9265AA0",
INIT_02 => x"092C2081891FF1270D817F843C0417BC021783FE8EDE01173A03175EFE8E9204",
INIT_03 => x"FE8C02300F2780E118FE8E20C0022F60C14C0417510417408B981F5804175E86",
INIT_04 => x"1F6E02178BFE8E121F2D297403173B341FBC2094ADC020F9021785FE8EF5264E",
INIT_05 => x"17275E81DD271881E127088111286703170C0417AE0317A4A6140417AE031721",
INIT_06 => x"321FAB0217BE203F31C2202131EA03173F86ED03170827A4A1A4A7390F260D81",
INIT_07 => x"F0C4201F0634F0C41000C3101F390124E1AC2034062914031705201F30C07F8E",
INIT_08 => x"10C69B0317370317E4AEF701178BFE8E103439623203279F03170527E4AC011F",
INIT_09 => x"03172E8602237E810425208180A610C6E1AE8B0317F5265A93031735031780A6",
INIT_0a => x"273F8184A60F2710355B8DFFFF8E10341A24C07F8C1E29C00217BC20EE265A7C",
INIT_0b => x"431F39FB265A1E8D08C6D37F8E104B03163F864E03173984A73F86A4AFA0A709",
INIT_0c => x"A60A24C07F8C21AEB3FE16ED7FBF00008E5102170C8D4AAF04272C8D1F304AAE",
INIT_0d => x"265A0427A1ACA0A608C6D37F8E1039A0A7A0A7A0A7FF8684A7A4A604263F8184",
INIT_0e => x"7FBFE7F98EEB7FBFC07FBEED7FBF1429390217EE02171C295F0117393D3139F7",
INIT_0f => x"27ED7FBE24273F8184A64AAEEC011770E0B671E0B73686431F392020450017C0",
INIT_10 => x"3B71E0B73F8673E0B7368670E0B671E0B7368670E0B70D86341FED7FBF1F301F",
INIT_11 => x"B7368672E0B7008670E0B7FF8673E0B73A8671E0B7328622FE16C07FBFEB7FBE",
INIT_12 => x"81260217D27F7F6402171186D6FCBD8435FD265A20C604343973E0B73E8671E0",
INIT_13 => x"E0EBE0E61034212991011726290234A80117F12631813D2739811F0217F92653",
INIT_14 => x"FFC102355FEB2080A70527E46AE0EB02340C2904358E01170434E46AE46AE4EB",
INIT_15 => x"E4AF0130492562AC4D2930344A0117E26F0E02161386D27F731602173F86BA27",
INIT_16 => x"03CB2F0017CCFE8E64E720C6022320008310062762A3E4ECF501171286D6FCBD",
INIT_17 => x"AF5B0117981F53F526646A65011780A684EB63EB62EB68011762AE750117981F",
INIT_18 => x"00169D011690356900177DFE8E10347120028D396532B301171486C326E4AC62",
INIT_19 => x"8DDC8D728D3948AF0229EB8DE78D618D394AAF0229F68DF28D910017E50016F8",
INIT_1a => x"BB8D6C8D3943A70229C78DC68D498D3944AF0229D58DD18D5E8D3946AF0229E0",
INIT_1b => x"1739C4A7808A0429A68DA58D5F8D3941A70229B18DB08D588D3942A70229BC8D",
INIT_1c => x"8DADFE8EF42048AEEA8D9BFE8EBF0016311FF48D8FFE8E39F726048180A63B01",
INIT_1d => x"204AAEC58D95FE8ED82046AECE8DA1FE8EE12044AED78DA7FE8EB4001643A6E1",
INIT_1e => x"900016C4FE8EC4A6AA8DBDFE8ED02042A6B38DB8FE8ED92041A6BC8DB3FE8ECF",
INIT_1f => x"098DD520CE8DC78DC08D17FF178BFE8EBF8DB88DB08DA98DA18D27FF178BFE8E",
INIT_20 => x"4848483229118D903561A710343C29088D011F42290E8DB400172D86121F4D29",
INIT_21 => x"22468112254181393080032239811D253081578D39E0AB04342829078D891F48",
INIT_22 => x"4444444402340235028D0235103439021A395780032266810725618139378003",
INIT_23 => x"3B8D3F8D2D860225E46880A608C602344D20078B022F3981308B0F840235048D",
INIT_24 => x"84A620E08E0926018584A6D07FBE10342D207F84048D0627D27F7D8235F1265A",
INIT_25 => x"34498D2086008D8235018520E0B605260185D07F9FA60234903501A6EE270185",
INIT_26 => x"A7518684A70386D07FBE138D903501A70235F6260885FA27028584A6D07FBE12",
INIT_27 => x"7F01E702C6F17FFD04E703E702A7EF7FFD0000CC30E08E39D27FB7FF86016D84",
INIT_28 => x"84A70520098D042420810D20608D0427F27F7D30E08E16345986028D1B86F27F",
INIT_29 => x"270C81890027100D81382716817C0027101A815A271B81342708819635AF0017",
INIT_2a => x"EF7FB66D205A34275DEF7FFC8F0016792619C15CEF7FFC45260A810F270B8124",
INIT_2b => x"816E27598114273DC1F27FF656200000CC5820212750814CEF7FB662204A2C27",
INIT_2c => x"224F812080F27F7F39F17FB70426F17F7D39F27F7F39F27FB704263D81312754",
INIT_2d => x"508102A74C84E720C6EF7FB6168D0000CC1B20E12218C120C0F17F7FF17FF6ED",
INIT_2e => x"EA2619C15C4FF02650814CEF7FFC3903E702A7EF7FFDF07FF64F39F27F7FF726",
INIT_2f => x"7FF6F42650C15C84A702E7EF7FF72086EF7FF604E75F012519C15C04E6E78D5A",
INIT_30 => x"FB035CFB0267FB0139F27FF702E7EF7FF75FE4205F03E7F07FF7082719C15CF0",
INIT_31 => x"4DAFFA5051FA4C8FF847E7F84546F9423BFB1946FB1830FB1524FB1051FB0472",
INIT_32 => x"0A0DFFFFFFFF7EF991F891F891F891F87EF9C5F95472F958DBF853E0FB5292F8",
INIT_33 => x"000A0D4B04202D202045335320524F4620362E31204755423930535953000000",
INIT_34 => x"3D53552020043D43502020043D5053202004202D20043F54414857043E040000",
INIT_35 => x"432020043D422020043D412020043D50442020043D58492020043D5949202004",
INIT_36 => x"C07F9F6E38F916D27FF7535FC07FCE103904315343565A4E4948464504203A43",
INIT_37 => x"FF8CCC7FBE49584F4AAF80E64AAE431FCA7F9F6EC87F9F6EC67F9F6EC47F9F6E",
INIT_38 => x"000000000000C27F9F6E42EE1F37F16E44AEC4EC10340822CE7FBC8B300F27FF",
INIT_39 => x"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3a => x"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3b => x"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3c => x"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3d => x"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3e => x"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3f => x"D0FEDCFEECFEE8FEE4FEE0FEF0FEDCFE00000000000000000000000000000000"
)
port map (
clk => clk,
ssr => rst,
en => en(0),
we => we,
addr => addr(10 downto 0),
di => data_in,
dip(0) => dp(0),
do => xdata(0),
dop(0) => dp(0)
);
rom_glue: process (cs, rw, addr, xdata)
begin
en(0) <= cs;
data_out <= xdata(0);
we <= not rw;
end process;
end architecture rtl;
 
/System09/trunk/rtl/Spartan3/sys09bug_s3e_rom2k_b16.vhd
1,8 → 1,56
--===========================================================================--
-- --
-- sys09bug_s3e_rom2k_b16.vhd - Sys09bug monitor ROM for the Spartan 3E500 --
-- --
--===========================================================================--
--
-- File name : sys09bug_s3e_rom2k_b16.vhd
--
-- Entity name : mon_rom
--
-- Purpose : Implements 2K Monitor ROM for System09
-- using 1 x Spartan 3E RAMB16_S9 block ram
-- Used in the Digilent Spartan 3E500 System09 design
--
-- Dependencies : ieee.Std_Logic_1164
-- ieee.std_logic_arith
-- unisim.vcomponents
--
-- Uses : RAMB16_S9
--
-- Author : John E. Kent
--
-- Email : dilbert57@opencores.org
--
-- Web : http://opencores.org/project,system09
--
--
-- Copyright (C) 2008 - 2010 John Kent
--
-- This program is free software: you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation, either version 3 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program. If not, see <http://www.gnu.org/licenses/>.
--
--===========================================================================--
-- --
-- Revision History --
-- --
--===========================================================================--
--
-- Version Author Date Changes
-- 0.1 John Kent 2008-01-08 Initial Version
-- 0.2 John Kent 2010-09-14 Added Header
-- renamed rdata & wdata to data_out & data_in
--
-- SYS09BUG MONITOR ROM FOR SYSTEM09 SPARTAN3E
-- John Kent
-- 8th January 2008
--
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
11,13 → 59,13
 
entity mon_rom is
Port (
clk : in std_logic;
rst : in std_logic;
cs : in std_logic;
rw : in std_logic;
addr : in std_logic_vector (10 downto 0);
rdata : out std_logic_vector (7 downto 0);
wdata : in std_logic_vector (7 downto 0)
clk : in std_logic;
rst : in std_logic;
cs : in std_logic;
addr : in std_logic_vector (10 downto 0);
rw : in std_logic;
data_in : in std_logic_vector (7 downto 0);
data_out : out std_logic_vector (7 downto 0)
);
end mon_rom;
 
97,11 → 145,11
)
 
port map (
do => rdata,
do => data_out,
dop(0) => dp,
addr => addr,
clk => clk,
di => wdata,
di => data_in,
dip(0) => dp,
en => cs,
ssr => rst,
/System09/trunk/rtl/Spartan3/keymap_rom_slice.vhd
109,11 → 109,11
 
begin
 
process( addr, rom_data, rom_out )
process( addr, rom_out )
begin
rom_out <= rom_data(conv_integer(addr(8 downto 5)));
data_out <= rom_out( conv_integer(addr(4 downto 0))*8+7 downto conv_integer(addr(4 downto 0))*8);
end;
end process;
 
end architecture rtl;
 
/System09/trunk/rtl/Spartan3/sys09s3s_b16.vhd
0,0 → 1,198
--===========================================================================--
-- --
-- Synthesizable Sys09_bug RAM using 2 x Xilinx RAMB16_S9 Block RAM --
-- --
--===========================================================================--
--
-- File name : sys09s3s_b16.vhd
--
-- Entity name : sys09bug_f800
--
-- Purpose : Implements 2KByte Sys09_bug ROM
-- for the 200K gate Digilent spartan 3 starter board
--
-- Dependencies : ieee.std_logic_1164
-- ieee.std_logic_arith
-- unisim.vcomponents
--
-- Uses : RAMB16_S9
--
-- Author : John E. Kent
--
-- Email : dilbert57@opencores.org
--
-- Web : http://opencores.org/project,system09
--
-- Description : Block RAM instatiation
--
-- Copyright (C) 2006 - 2010 John Kent
--
-- This program is free software: you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation, either version 3 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program. If not, see <http://www.gnu.org/licenses/>.
--
--===========================================================================--
-- --
-- Revision History --
-- --
--===========================================================================--
--
-- Version Date Author Changes
--
-- 1.1 2006-12-22 John Kent Made into 4K ROM/RAM.
-- 1.2 2010-06-17 John Kent Added GPL and header
-- Renamed data input and output signals
-- Removed ROM at $F000 to $F7FF
--
 
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
library unisim;
use unisim.vcomponents.all;
 
entity SYS09BUG_F800 is
port(
clk : in std_logic;
rst : in std_logic;
cs : in std_logic;
addr : in std_logic_vector(10 downto 0);
rw : in std_logic;
data_in : in std_logic_vector(7 downto 0);
data_out : out std_logic_vector(7 downto 0)
);
end SYS09BUG_F800;
 
architecture rtl of SYS09BUG_F800 is
 
signal dp : std_logic_vector(0 downto 0);
signal we : std_logic;
 
component RAMB16_S9
generic (
INIT_00, INIT_01, INIT_02, INIT_03,
INIT_04, INIT_05, INIT_06, INIT_07,
INIT_08, INIT_09, INIT_0A, INIT_0B,
INIT_0C, INIT_0D, INIT_0E, INIT_0F,
INIT_10, INIT_11, INIT_12, INIT_13,
INIT_14, INIT_15, INIT_16, INIT_17,
INIT_18, INIT_19, INIT_1A, INIT_1B,
INIT_1C, INIT_1D, INIT_1E, INIT_1F,
INIT_20, INIT_21, INIT_22, INIT_23,
INIT_24, INIT_25, INIT_26, INIT_27,
INIT_28, INIT_29, INIT_2A, INIT_2B,
INIT_2C, INIT_2D, INIT_2E, INIT_2F,
INIT_30, INIT_31, INIT_32, INIT_33,
INIT_34, INIT_35, INIT_36, INIT_37,
INIT_38, INIT_39, INIT_3A, INIT_3B,
INIT_3C, INIT_3D, INIT_3E, INIT_3F : bit_vector (255 downto 0)
);
 
port (
clk : in std_logic;
ssr : in std_logic;
en : in std_logic;
we : in std_logic;
addr : in std_logic_vector(10 downto 0);
di : in std_logic_vector( 7 downto 0);
dip : in std_logic_vector( 0 downto 0);
do : out std_logic_vector( 7 downto 0);
dop : out std_logic_vector( 0 downto 0)
);
end component RAMB16_S9;
 
begin
 
ROM00: RAMB16_S9
generic map (
INIT_00 => x"A780A610C6C0DF8E1062FE8E2EFA1AFB1EFB8FFBCEFCB9FC9BFCA1FC61F814F8",
INIT_01 => x"17431FE4A7D0866AAFDD8C30FB265AE26F0CC65B0117E0DFBF00E08EF9265AA0",
INIT_02 => x"031796FE8E0C0417F62A5A19048B0327856D0DC64FD0DF8E47031772FE8EA304",
INIT_03 => x"17408B981F5304175E86092C2081891FF1270D817F84370417B302179DFE8E2E",
INIT_04 => x"20F002179FFE8EF52662FE8C02300F2780E129FE8E20C0022F60C14704174C04",
INIT_05 => x"17A4A60F0417A50317211F650217A5FE8E121F2D296B03173B341FBC2094ADC0",
INIT_06 => x"27A4A1A4A7390F260D8117275E81DD271881E127088111285E0317070417A503",
INIT_07 => x"0B031705201F30C0DF8E321FA20217BE203F31C2202131E503173F86E8031708",
INIT_08 => x"279A03170527E4AC011FF0C4201F0634F0C41000C3101F390124E1AC20340629",
INIT_09 => x"265A8E03172C031780A610C69603172E0317E4AEEE0117A5FE8E103439623203",
INIT_0a => x"29B70217BC20EE265A7703172E8602237E810425208180A610C6E1AE860317F5",
INIT_0b => x"3984A73F86A4AFA0A709273F8184A60F271035558DFFFF8E10341A24C0DF8C1E",
INIT_0c => x"4AAF0427268D1F304AAE431F39FB265A188D08C6E3DF8E104603163F86490317",
INIT_0d => x"A7A0A7A0A7FF8684A7A4A604263F8184A60A24C0DF8C21AEB9FE16480217068D",
INIT_0e => x"0186398D46E0B7E086408D393D3139F7265A0427A1ACA0A608C6E3DF8E1039A0",
INIT_0f => x"178D47E0B7208645E0B744E0B743E0B74F42E0B701862D8D47E0B7EF8641E0B7",
INIT_10 => x"E0B6F926808547E0B63B341F4AAF00C08EF42600C28C80A740E0B6218D00C08E",
INIT_11 => x"54545454A6E6D0DF8E104444444462A6363439F927088547E0B639F227408547",
INIT_12 => x"FCBD8435FD265A20C60434B63562E762EA62A70F8462A65858585853A6E6E4E7",
INIT_13 => x"0234A80117F12631813D273981230217F92653812A0217E2DF7F6802171186E7",
INIT_14 => x"E0EB02340C2904358E01170434E46AE46AE4EBE0EBE0E6103421299101172629",
INIT_15 => x"0117E26F1202161386E2DF731A02173F86BA27FFC102355FEB2080A70527E46A",
INIT_16 => x"2320008310062762A3E4ECF901171286E7FCBDE4AF0130492562AC4D2930344A",
INIT_17 => x"1780A684EB63EB62EB68011762AE750117981F03CB2F0017E6FE8E64E720C602",
INIT_18 => x"10347120028D396532B701171486C326E4AC62AF5B0117981F53F526646A6501",
INIT_19 => x"8D618D394AAF0229F68DF28D910017E50016F80016A10116903569001797FE8E",
INIT_1a => x"498D3944AF0229D58DD18D5E8D3946AF0229E08DDC8D728D3948AF0229EB8DE7",
INIT_1b => x"8D3941A70229B18DB08D588D3942A70229BC8DBB8D6C8D3943A70229C78DC68D",
INIT_1c => x"BF0016311FF48DA9FE8E39F726048180A63F011739C4A7808A0429A68DA58D5F",
INIT_1d => x"8DBBFE8EE12044AED78DC1FE8EB4001643A6E18DC7FE8EF42048AEEA8DB5FE8E",
INIT_1e => x"D02042A6B38DD2FE8ED92041A6BC8DCDFE8ECF204AAEC58DAFFE8ED82046AECE",
INIT_1f => x"A5FE8EBF8DB88DB08DA98DA18D27FF17A5FE8E900016DEFE8EC4A6AA8DD7FE8E",
INIT_20 => x"3C29088D011F42290E8DB800172D86121F4D29098DD520CE8DC78DC08D17FF17",
INIT_21 => x"811D2530815B8D39E0AB04342829078D891F484848483229118D903561A71034",
INIT_22 => x"3439021A39578003226681072561813937800322468112254181393080032239",
INIT_23 => x"C602345120078B022F3981308B0F840235048D4444444402340235028D023510",
INIT_24 => x"207F84048D0627E2DF7D00F09F6E8235F1265A3F8D438D2D860225E46880A608",
INIT_25 => x"85E0DF9FA60234903501A6EE27018584A620E08E0926018584A6E0DFBE10342D",
INIT_26 => x"35F6260885FA27028584A6E0DFBE1234498D2086008D8235018520E0B6052601",
INIT_27 => x"0000CC30E08E39E2DFB7FF86016D84A7518684A70386E0DFBE138D903501A702",
INIT_28 => x"DF7D30E08E16345986028D1B86FEDF7F01E702C6FDDFFD04E703E702A7FBDFFD",
INIT_29 => x"1A815A271B81342708819635AF001784A70520098D042420810D20608D0427FE",
INIT_2a => x"19C15CFBDFFC45260A810F270B8124270C81890027100D81382716817C002710",
INIT_2b => x"5820212750814CFBDFB662204A2C27FBDFB66D205A34275DFBDFFC8F00167926",
INIT_2c => x"39FEDF7F39FEDFB704263D81312754816E27598114273DC1FEDFF656200000CC",
INIT_2d => x"1B20E12218C120C0FDDF7FFDDFF6ED224F812080FEDF7F39FDDFB70426FDDF7D",
INIT_2e => x"02A7FBDFFDFCDFF64F39FEDF7FF726508102A74C84E720C6FBDFB6168D0000CC",
INIT_2f => x"DFF604E75F012519C15C04E6E78D5AEA2619C15C4FF02650814CFBDFFC3903E7",
INIT_30 => x"5FE4205F03E7FCDFF7082719C15CFCDFF6F42650C15C84A702E7FBDFF72086FB",
INIT_31 => x"FB1953FB183DFB1531FB105EFB047FFB0369FB0274FB0139FEDFF702E7FBDFF7",
INIT_32 => x"55D5F94488F958F1F853EDFB52A8F84DBCFA505EFA4CA5F847FDF8455CF94248",
INIT_33 => x"2047554239305359530000000A0DFFFFFFFF94F9A7F8A7F8A7F8A7F894F992FC",
INIT_34 => x"57043E040000000A0D4B04202D202052455452415453335320524F4620362E31",
INIT_35 => x"3D59492020043D53552020043D43502020043D5053202004202D20043F544148",
INIT_36 => x"464504203A43432020043D422020043D412020043D50442020043D5849202004",
INIT_37 => x"000000000000000000000000000000000000000000000004315343565A4E4948",
INIT_38 => x"300B2784AC1084AF1084EEAA558E10A0D08E84A7F086FB264A80A70F86F0FF8E",
INIT_39 => x"2DA7D0DF8E10C0DFCE10FDFFB74444444443101F84EFD620ED26A0F08C00F089",
INIT_3a => x"1084AF10AA558E1084EE2227A0F08C00F08930FB2A4AA66F0C862FA7F0862E6F",
INIT_3b => x"2EA7D0DF8E10F186D520A5A70F88891F44444444101FD0DF8E1084EFE92684AC",
INIT_3c => x"8EF32D0C814C80E7A66F0427A6E6211F4F2CE7A66F1420F92A4A0526A6E60C86",
INIT_3d => x"9F6EC6DF9F6EC4DF9F6EC0DF9F6E62F816E2DFF753F9265A80A7A0A610C6F0FF",
INIT_3e => x"0822CEDFBC8B300F27FFFF8CCCDFBE49584F4AAF80E64AAE431FCADF9F6EC8DF",
INIT_3f => x"00FFB2FFC2FFBEFFBAFFB6FFC6FFB2FFC2DF9F6E42EE1F37F16E44AEC4EC1034"
)
port map (
clk => clk,
ssr => rst,
en => cs,
we => we,
addr => addr(10 downto 0),
di => data_in,
dip(0) => dp(0),
do => data_out,
dop(0) => dp(0)
);
rom_glue: process ( rw )
begin
we <= not rw;
end process;
end architecture rtl;
 
/System09/trunk/rtl/VHDL/ACIA_RX.vhd File deleted \ No newline at end of file
/System09/trunk/rtl/VHDL/ACIA_TX.vhd File deleted \ No newline at end of file
/System09/trunk/rtl/VHDL/vdu8_new.vhd
1,27 → 1,141
-- ---------------------------------------------------
-- Video Display terminal
-- ---------------------------------------------------
-- John Kent
-- 3th September 2004
-- Assumes a pixel clock input of 25 MHz
--===========================================================================--
-- --
-- vdu8_new.vhd - Synthesizable Colour Video Display Unit for System09 --
-- --
--===========================================================================--
--
-- Display Format is:
-- 80 characters across by 25 characters down.
-- 8 horizontal pixels / character
-- 16 vertical scan lines / character (2 scan lines/row)
-- File name : vdu8_new.vhd
--
-- Modified by Bert Cuzeau for compliance and code cleanliness
-- The effort is not over.
-- There are still signal initialized, which is BAD.\
-- Purpose : Implements a text based Colour Video Display Unit for System09
-- Supports 2KByte Text buffer and 2KByte Attribute memory
-- Displays 80 characters across by 25 character rows
-- Characters are 8 pixels across x 16 lines down.
-- Character attribute bita for foreground and backgrond colour
-- 1 bit for each Blue Green and Red signal
-- Supports 2 x 8 chunky graphics character mode.
-- Uses Generic arguments for setting the video synchronization timing.
-- (I'm not sure what is "new" about this version.)
--
-- Dependencies : ieee.Std_Logic_1164
-- ieee.std_logic_arith
-- ieee.std_logic_unsigned
-- ieee.numeric_std
-- unisim.vcomponents
--
-- 7th Februaury 2007 - John Kent
-- Added generics for VGA Timing
-- Uses : ram_2k (ram2k_b16.vhd) 2KByte Character & Attribute buffer
-- char_rom (char_rom2k_b16.vhd) 2KByte Character Generator ROM
--
-- Author : John E. Kent
--
-- Email : dilbert57@opencores.org
--
-- Web : http://opencores.org/project,system09
--
-- Description : Display Timing:
-- 800 pixels / line
-- 446 lines / frame
-- None interlaced
-- 25MHz pixel clock implies
-- 31.25 KHz line rate
-- 70.067 Hz frame rate
-- Timing settable by generics.
--
-- Display Size:
-- 80 characters across
-- 25 characters down.
--
-- Character Size:
-- 8 horizontal pixels across
-- 16 vertical scan lines down (2 scan lines/row)
--
-- Registers:
-- Base + 0 ASCII character register
-- Writing to this register writes an 8 bit byte
-- into the text buffer at the specified cursor position
-- Text Mode: ASCII Character (0 to 127)
-- Chunky Graphics Mode: B0 B1 (0 to 255)
-- B2 B3
-- B4 B5
-- B6 B7
-- Base + 1 Attibute bit (0 to 255)
-- Writing to the register writes an 8 bit byte
-- into the attribute buffer at the specified cursor position
-- B7 - 0 => Text Mode / 1 => Chunky Graphics Mode
-- B6 - 1 => Character Background Blue
-- B5 - 1 => Character Background Green
-- B4 - 1 => Character Background Red
-- B3 - 1 => Character Background & Foreground Alternates
-- B2 - 1 => Character Foreground Blue
-- B1 - 1 => Character Foreground Green
-- B0 - 1 => Character Foreground Red
-- Base + 2 Cursor Horizontal Position (0 to 79)
-- Base + 3 Cusror Vertical Position (0 to 24)
-- Base + 4 Vertical Scroll Offset (0 to 24)
-- Scrolls the display up by the specified number of character rows
--
--
-- Video Timing :
--
-- Horizontal 800 Pixels/ 25MHz Pixel Clock = 32usec Line period = 31.25 KHz Line Frequency
-- /--------------------------\_____________/---------------\______________/
-- 640 Pixels Display 16 Pixel FP 96 Pixel HS 48 Pixel BP
--
-- VGA_CLK_FREQ : integer := 25000000; -- HZ
-- VGA_HOR_FRONT_PORCH : integer := 16; -- PIXELS 0.64us (0.94us)
-- VGA_HOR_SYNC : integer := 96; -- PIXELS 3.84us (3.77us)
-- VGA_HOR_BACK_PORCH : integer := 48; -- PIXELS 1.92us (1.89us)
-- VGA_PIX_PER_CHAR : integer := 8; -- PIXELS 0.32us
-- VGA_HOR_CHARS : integer := 80; -- CHARACTERS 25.6us
--
-- Vertical 446 Lines * 32 usec Line rate = 14.272ms Frame Period = 70.07Hz Frame frequency
-- /---------------------------\____________/---------------\______________/
-- 400 Line Display 10 Line FP 2 Line VS 34 Line BP
--
-- VGA_VER_FRONT_PORCH : integer := 10; -- LINES 0.320ms
-- VGA_VER_SYNC : integer := 2; -- LINES 0.064ms
-- VGA_VER_BACK_PORCH : integer := 34; -- LINES 1.088ms
-- VGA_LIN_PER_CHAR : integer := 16; -- LINES 0.512ms
-- VGA_VER_CHARS : integer := 25; -- CHARACTERS 12.8ms
--
-- Copyright (C) 2003 - 2010 John Kent
--
-- This program is free software: you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation, either version 3 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program. If not, see <http://www.gnu.org/licenses/>.
--
--===========================================================================--
-- --
-- Revision History --
-- --
--===========================================================================--
--
-- Version Author Date Changes
--
-- 0.1 John Kent 2004-09-03 Initial release
--
-- 0.2 Bert Cuzeau 2007-01-16 Modified by for compliance and code cleanliness
-- The effort is not over.
-- There are still signal initialized, which is BAD.
--
-- 0.3 John Kent 2007-02-07 Added generics for VGA Timing
--
-- 0.4 John Kent 2010-06-16 Added GPL notice. Updated description
-- I'm not sure what is "new" about this version
--
 
Library IEEE;
use ieee.std_logic_1164.all;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
use ieee.numeric_std.all;
library unisim;
use unisim.vcomponents.all;
28,18 → 142,17
 
Entity vdu8 is
generic(
VDU_CLOCK_FREQUENCY : integer := 25000000; -- HZ
VGA_CLOCK_FREQUENCY : integer := 25000000; -- HZ
VGA_HOR_CHARS : integer := 80; -- CHARACTERS
VGA_VER_CHARS : integer := 25; -- CHARACTERS
VGA_PIXELS_PER_CHAR : integer := 8; -- PIXELS
VGA_LINES_PER_CHAR : integer := 16; -- LINES
VGA_HOR_BACK_PORCH : integer := 40; -- PIXELS
VGA_HOR_SYNC : integer := 96; -- PIXELS
VGA_HOR_FRONT_PORCH : integer := 24; -- PIXELS
VGA_VER_BACK_PORCH : integer := 13; -- LINES
VGA_VER_SYNC : integer := 2; -- LINES
VGA_VER_FRONT_PORCH : integer := 36 -- LINES
VGA_CLK_FREQ : integer := 25000000; -- HZ
VGA_HOR_CHARS : integer := 80; -- CHARACTERS 25.6us
VGA_HOR_CHAR_PIXELS : integer := 8; -- PIXELS 0.32us
VGA_HOR_FRONT_PORCH : integer := 16; -- PIXELS 0.64us
VGA_HOR_SYNC : integer := 96; -- PIXELS 3.84us
VGA_HOR_BACK_PORCH : integer := 48; -- PIXELS 1.92us
VGA_VER_CHARS : integer := 25; -- CHARACTERS 12.8ms
VGA_VER_CHAR_LINES : integer := 16; -- LINES 0.512ms
VGA_VER_FRONT_PORCH : integer := 10; -- LINES 0.320ms
VGA_VER_SYNC : integer := 2; -- LINES 0.064ms
VGA_VER_BACK_PORCH : integer := 34 -- LINES 1.088ms
);
port(
-- control register interface
68,30 → 181,26
-- Displayed Characters per row
constant HOR_DISP_CHR : integer := VGA_HOR_CHARS;
-- Last horizontal pixel displayed
constant HOR_DISP_END : integer := HOR_DISP_CHR * VGA_PIXELS_PER_CHAR;
constant HOR_DISP_END : integer := HOR_DISP_CHR * VGA_HOR_CHAR_PIXELS - 1;
-- Start of horizontal synch pulse
constant HOR_SYNC_BEG : integer := HOR_DISP_END + VGA_HOR_BACK_PORCH;
constant HOR_SYNC_BEG : integer := HOR_DISP_END + VGA_HOR_FRONT_PORCH;
-- End of Horizontal Synch pulse
constant HOR_SYNC_END : integer := HOR_SYNC_BEG + VGA_HOR_SYNC;
-- Last pixel in scan line
constant HOR_SCAN_END : integer := HOR_SYNC_END + VGA_HOR_FRONT_PORCH;
-- Total Characters across the screen
constant HOR_TOTAL_CHAR : integer := HOR_SCAN_END/VGA_PIXELS_PER_CHAR;
constant HOR_SCAN_END : integer := HOR_SYNC_END + VGA_HOR_BACK_PORCH;
 
-- Displayed Characters per Column
constant VER_DISP_CHR : integer := VGA_VER_CHARS;
-- last row displayed
constant VER_DISP_END : integer := VER_DISP_CHR * VGA_LINES_PER_CHAR;
constant VER_DISP_END : integer := VER_DISP_CHR * VGA_VER_CHAR_LINES - 1;
-- start of vertical synch pulse
constant VER_SYNC_BEG : integer := VER_DISP_END + VGA_VER_BACK_PORCH;
constant VER_SYNC_BEG : integer := VER_DISP_END + VGA_VER_FRONT_PORCH;
-- end of vertical synch pulse
constant VER_SYNC_END : integer := VER_SYNC_BEG + VGA_VER_SYNC;
-- Last scan row in the frame
constant VER_SCAN_END : integer := VER_SYNC_END + VGA_VER_FRONT_PORCH;
-- Total Characters down the screen
constant VER_TOTAL_CHAR : integer := VER_SCAN_END/VGA_LINES_PER_CHAR;
 
constant BLINK_PERIOD : integer := 500; -- Blink Rate in msec
constant VER_SCAN_END : integer := VER_SYNC_END + VGA_VER_BACK_PORCH;
 
constant BLINK_PERIOD : integer := 500; -- Blink Rate in msec
constant BLINK_RATE : integer := BLINK_PERIOD * (VGA_CLOCK_FREQUENCY/1000);
 
signal vga_rst : std_logic;
102,11 → 211,11
signal video_on_v : std_logic := '0';
signal video_on_h : std_logic := '0';
signal h_count : natural range 0 to HOR_SCAN_END := 0;
signal v_count : natural range 0 to VER_SCAN_END := 0;
signal v_count : natural range 0 to VER_SCAN_END := 0;
signal p_count : natural range 0 to VGA_PIXELS_PER_CHAR-1 := 0;
signal l_count : std_logic_vector(3 downto 0) := "0000";
signal c_count : std_logic_vector(6 downto 0) := "0000000";
signal r_count : std_logic_vector(5 downto 0) := "000000";
signal r_count : std_logic_vector(5 downto 0) := "000000";
signal blink_count : natural range 0 to BLINK_RATE := 0;
--
-- Character generator ROM
153,7 → 262,7
signal vga_addr : std_logic_vector(10 downto 0) := (others=>'0'); -- 2K byte character buffer
signal vga_data_out : std_logic_vector(7 downto 0);
signal attr_data_out : std_logic_vector(7 downto 0);
 
 
--
-- Character write handshake signals
--
330,13 → 439,13
vga0_rw <= '1';
col_addr <= c_count;
row_addr <= r_count + ("0" & reg_voffset(4 downto 0));
end case;
end case;
 
--
-- on vga_clk + 1 round off row address
--
vga1_cs <= vga0_cs;
vga1_rw <= vga0_rw;
vga1_rw <= vga0_rw;
if row_addr < VER_DISP_CHR then
row1_addr <= row_addr;
else
376,9 → 485,9
vga_blue_o <= '0';
-- Put all video signals through DFFs to elminate any delays that cause a blurry image
 
elsif falling_edge(vga_clk) then
elsif falling_edge(vga_clk) then
--
-- p_count = 0 load pixel shift register
-- p_count = 0 load pixel shift register
--
if p_count = 0 then
if (req_write = '1') and (ack_write = '0') then
387,31 → 496,31
ack_write <= '0';
else
ack_write <= ack_write;
end if;
 
end if;
 
--
-- Pipeline video enable
--
-- Pipeline video enable
--
video_on2 <= video_on1;
video_on <= video_on2;
--
-- Blink Cursor
--
video_on <= video_on2;
--
-- Blink Cursor
--
if blink_count > (BLINK_RATE/2) then
cursor_on <= cursor_on1 or attr_data_out(3);
else
cursor_on <= '0';
end if;
cursor_on <= cursor_on1 or attr_data_out(3);
else
cursor_on <= '0';
end if;
--
-- Set forground and background colours
--
-- Set forground and background colours
--
vga_fg_colour <= attr_data_out(2 downto 0);
vga_bg_colour <= attr_data_out(6 downto 4);
--
-- Attribute bit 7
vga_bg_colour <= attr_data_out(6 downto 4);
--
-- Attribute bit 7
-- 0 => text
-- 1 => chunky graphics
--
-- 1 => chunky graphics
--
if attr_data_out(7) = '0' then
vga_shift <= char_data_out;
else
430,10 → 539,10
vga_shift(3 downto 0) <= vga_data_out(7) & vga_data_out(7) & vga_data_out(7) & vga_data_out(7);
end case;
end if;
else
else
--
-- p_count /= 0 shift out pixel shift register
--
-- p_count /= 0 shift out pixel shift register
--
vga_shift <= vga_shift(6 downto 0) & '0';
end if;
 
460,13 → 569,13
-- Generate Horizontal and Vertical Timing Signals for Video Signal
--
vga_sync : process(vga_clk, vga_rst)
begin
if vga_rst = '1' then
h_count <= 0;
c_count <= "0000000";
begin
if vga_rst = '1' then
h_count <= 0;
c_count <= "0000000";
p_count <= 0;
v_count <= 0;
l_count <= "0000";
v_count <= 0;
l_count <= "0000";
r_count <= "000000";
horiz_sync <= '0';
vert_sync <= '0';
474,7 → 583,7
video_on_v <= '0';
cursor_on_h <= '0';
cursor_on_v <= '0';
blink_count <= BLINK_RATE;
blink_count <= BLINK_RATE;
elsif falling_edge(vga_clk) then
--
-- H_count counts pixels (640 + extra time for sync signals)
483,17 → 592,17
-- H_count 0 640 659 755 799
--
if h_count = HOR_SCAN_END then
h_count <= 0;
c_count <= "0000000";
h_count <= 0;
c_count <= "0000000";
p_count <= 0;
else
h_count <= h_count + 1;
p_count <= p_count + 1;
if p_count = VGA_PIXELS_PER_CHAR-1 then
p_count <= 0;
c_count <= c_count + "0000001";
h_count <= h_count + 1;
p_count <= p_count + 1;
if p_count = VGA_PIXELS_PER_CHAR-1 then
p_count <= 0;
c_count <= c_count + "0000001";
end if;
end if;
end if;
 
--
-- V_count counts rows of pixels
504,17 → 613,17
-- V_count 0 400 413 414 444
--
if (v_count = VER_SCAN_END) and (h_count = HOR_SCAN_END) then
v_count <= 0;
l_count <= "0000";
v_count <= 0;
l_count <= "0000";
r_count <= "000000";
elsif h_count = HOR_SYNC_END then
v_count <= v_count + 1;
l_count <= l_count + "0001";
if l_count = VGA_LINES_PER_CHAR-1 then
l_count <= "0000";
r_count <= r_count + "000001";
l_count <= l_count + "0001";
if l_count = VGA_LINES_PER_CHAR-1 then
l_count <= "0000";
r_count <= r_count + "000001";
end if;
end if;
end if;
 
--
-- Generate Horizontal Sync Signal
524,7 → 633,7
elsif h_count = HOR_SYNC_END then
horiz_sync <= '0';
end if;
 
 
--
-- Generate Vertical Sync Signal
--
532,10 → 641,10
vert_sync <= '1';
elsif v_count = VER_SYNC_END then
vert_sync <= '0';
end if;
end if;
 
--
-- Horizontal display enable
-- Horizontal display enable
--
if h_count = 0 then
video_on_h <= '1';
544,7 → 653,7
end if;
 
--
-- Verical display enable
-- Verical display enable
--
if v_count = 0 then
video_on_v <= '1';
552,18 → 661,18
video_on_v <= '0';
end if;
 
--
-- Horizontal cursor on
--
-- Horizontal cursor on
--
if c_count = reg_hcursor(6 downto 0) then
cursor_on_h <= '1';
else
cursor_on_h <= '0';
end if;
 
 
--
-- Vertical cursor on
--
-- Vertical cursor on
--
if r_count = ("0" & reg_vcursor(4 downto 0)) then
cursor_on_v <= '1';
else
570,30 → 679,30
cursor_on_v <= '0';
end if;
 
-- cursor_on is only active when on selected character
if blink_count = 0 then
blink_count <= BLINK_RATE;
-- cursor_on is only active when on selected character
if blink_count = 0 then
blink_count <= BLINK_RATE;
else
blink_count <= blink_count - 1;
blink_count <= blink_count - 1;
end if;
end if;
 
end process;
--
-- VGA reset = VDU reset
-- VGA = timing section
-- VDU = CPU registers
--
end process;
--
-- VGA reset = VDU reset
-- VGA = timing section
-- VDU = CPU registers
--
vga_rst <= vdu_rst;
--
-- VGA Sync for 640 pixels x 400 lines
-- negative horizonal sync
-- positive verical sync
--
--
-- VGA Sync for 640 pixels x 400 lines
-- negative horizonal sync
-- positive verical sync
--
vga_hsync_o <= not horiz_sync;
vga_vsync_o <= vert_sync;
--
-- video_on is high only when RGB data is displayed
-- video_on is high only when RGB data is displayed
--
video_on1 <= video_on_H and video_on_V;
cursor_on1 <= cursor_on_h and cursor_on_v;
/System09/trunk/rtl/VHDL/vdu8_bert.vhd
1,19 → 1,133
-- ---------------------------------------------------
-- Video Display terminal
-- ---------------------------------------------------
-- John Kent
-- 3th September 2004
-- Assumes a pixel clock input of 50 MHz
-- Generates a 12.5MHz CPU Clock output
--===========================================================================--
-- --
-- vdu8_bert.vhd - Synthesizable Colour Video Display Unit for System09 --
-- --
--===========================================================================--
--
-- Display Format is:
-- 80 characters across by 25 characters down.
-- 8 horizontal pixels / character
-- 16 vertical scan lines / character (2 scan lines/row)
-- File name : vdu8_bert.vhd
--
-- Modified by Bert Cuzeau for compliance and code cleanliness
-- The effort is not over.
-- There are still signal initialized, which is BAD.
-- Purpose : Implements a text based Colour Video Display Unit for System09
-- Supports 2KByte Text buffer and 2KByte Attribute memory
-- Displays 80 characters across by 25 character rows
-- Characters are 8 pixels across x 16 lines down.
-- Character attribute bita for foreground and backgrond colour
-- 1 bit for each Blue Green and Red signal
-- Supports 2 x 8 chunky graphics character mode.
-- Assumes a pixel clock input of 50 MHz
-- Generates a 12.5MHz CPU Clock output for old Spartan 2 boards.
-- Partially cleaned up by Bertrand Cuzeau
--
-- Dependencies : ieee.Std_Logic_1164
-- ieee.std_logic_unsigned
-- ieee.std_logic_arith
-- ieee.numeric_std
--
-- Uses : ram_2k (ram2k_b16.vhd) 2KByte Character & Attribute buffer
-- char_rom (char_rom2k_b16.vhd) 2KByte Character Generator ROM
--
-- Author : John E. Kent
--
-- Email : dilbert57@opencores.org
--
-- Web : http://opencores.org/project,system09
--
-- Description : Display Timing:
-- 800 pixels / line
-- 446 lines / frame
-- None interlaced
-- 25MHz pixel clock implies
-- 31.25 KHz line rate
-- 70.067 Hz frame rate
-- Timing settable by generics.
--
-- Display Size:
-- 80 characters across
-- 25 characters down.
--
-- Character Size:
-- 8 horizontal pixels across
-- 16 vertical scan lines down (2 scan lines/row)
--
-- Registers:
-- Base + 0 ASCII character register
-- Writing to this register writes an 8 bit byte
-- into the text buffer at the specified cursor position
-- Text Mode: ASCII Character (0 to 127)
-- Chunky Graphics Mode: B0 B1 (0 to 255)
-- B2 B3
-- B4 B5
-- B6 B7
-- Base + 1 Attibute bit (0 to 255)
-- Writing to the register writes an 8 bit byte
-- into the attribute buffer at the specified cursor position
-- B7 - 0 => Text Mode / 1 => Chunky Graphics Mode
-- B6 - 1 => Character Background Blue
-- B5 - 1 => Character Background Green
-- B4 - 1 => Character Background Red
-- B3 - 1 => Character Background & Foreground Alternates
-- B2 - 1 => Character Foreground Blue
-- B1 - 1 => Character Foreground Green
-- B0 - 1 => Character Foreground Red
-- Base + 2 Cursor Horizontal Position (0 to 79)
-- Base + 3 Cusror Vertical Position (0 to 24)
-- Base + 4 Vertical Scroll Offset (0 to 24)
-- Scrolls the display up by the specified number of character rows
--
-- Video Timing :
--
-- Horizontal 800 Pixels/ 25MHz Pixel Clock = 32usec Line period = 31.25 KHz Line Frequency
-- /--------------------------\_____________/---------------\______________/
-- 640 Pixels Display 16 Pixel FP 96 Pixel HS 48 Pixel BP
--
-- VGA_CLK_FREQ : integer := 25000000; -- HZ
-- VGA_HOR_FRONT_PORCH : integer := 16; -- PIXELS 0.64us (0.94us)
-- VGA_HOR_SYNC : integer := 96; -- PIXELS 3.84us (3.77us)
-- VGA_HOR_BACK_PORCH : integer := 48; -- PIXELS 1.92us (1.89us)
-- VGA_PIX_PER_CHAR : integer := 8; -- PIXELS 0.32us
-- VGA_HOR_CHARS : integer := 80; -- CHARACTERS 25.6us
--
-- Vertical 446 Lines * 32 usec Line rate = 14.272ms Frame Period = 70.07Hz Frame frequency
-- /---------------------------\____________/---------------\______________/
-- 400 Line Display 10 Line FP 2 Line VS 34 Line BP
--
-- VGA_VER_FRONT_PORCH : integer := 10; -- LINES 0.320ms
-- VGA_VER_SYNC : integer := 2; -- LINES 0.064ms
-- VGA_VER_BACK_PORCH : integer := 34; -- LINES 1.088ms
-- VGA_LIN_PER_CHAR : integer := 16; -- LINES 0.512ms
-- VGA_VER_CHARS : integer := 25; -- CHARACTERS 12.8ms
--
--
-- Copyright (C) 2003 - 2010 John Kent
--
-- This program is free software: you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation, either version 3 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program. If not, see <http://www.gnu.org/licenses/>.
--
--===========================================================================--
-- --
-- Revision History --
-- --
--===========================================================================--
--
-- Version Author Date Changes
--
-- 0.1 John Kent 2004-09-03 Initial release
--
-- 0.2 Bert Cuzeau 2007-01-16 Modified by for compliance and code cleanliness
-- The effort is not over.
-- There are still signal initialized, which is BAD.
--
-- 0.3 John Kent 2010-06-16 Added GPL notice. Updated description
--
 
Library IEEE;
use IEEE.std_logic_1164.all;
20,6 → 134,19
use IEEE.numeric_std.all;
 
Entity vdu8 is
generic(
VGA_CLK_FREQ : integer := 25000000; -- HZ
VGA_HOR_CHARS : integer := 80; -- CHARACTERS 25.6us
VGA_HOR_CHAR_PIXELS : integer := 8; -- PIXELS 0.32us
VGA_HOR_FRONT_PORCH : integer := 16; -- PIXELS 0.64us
VGA_HOR_SYNC : integer := 96; -- PIXELS 3.84us
VGA_HOR_BACK_PORCH : integer := 48; -- PIXELS 1.92us
VGA_VER_CHARS : integer := 25; -- CHARACTERS 12.8ms
VGA_VER_CHAR_LINES : integer := 16; -- LINES 0.512ms
VGA_VER_FRONT_PORCH : integer := 10; -- LINES 0.320ms
VGA_VER_SYNC : integer := 2; -- LINES 0.064ms
VGA_VER_BACK_PORCH : integer := 34 -- LINES 1.088ms
);
port(
-- control register interface
vdu_clk_in : in std_logic; -- 50MHz System clock
45,18 → 172,31
--
-- Synchronisation constants
--
constant HOR_DISP_END : integer := 639; -- Last horizontal pixel displayed
constant HOR_SYNC_BEG : integer := 679; -- Start of horizontal synch pulse
constant HOR_SYNC_END : integer := 775; -- End of Horizontal Synch pulse
constant HOR_SCAN_END : integer := 799; -- Last pixel in scan line
constant HOR_DISP_CHR : integer := 80; -- Number of characters displayed per row
--
-- Synchronisation constants
--
-- Displayed Characters per row
constant HOR_DISP_CHR : integer := VGA_HOR_CHARS;
-- Last horizontal pixel displayed
constant HOR_DISP_END : integer := (HOR_DISP_CHR * VGA_HOR_CHAR_PIXELS) - 1;
-- Start of horizontal synch pulse
constant HOR_SYNC_BEG : integer := HOR_DISP_END + VGA_HOR_FRONT_PORCH;
-- End of Horizontal Synch pulse
constant HOR_SYNC_END : integer := HOR_SYNC_BEG + VGA_HOR_SYNC;
-- Last pixel in scan line
constant HOR_SCAN_END : integer := HOR_SYNC_END + VGA_HOR_BACK_PORCH;
 
-- Number of displayed characters rows
constant VER_DISP_CHR : integer := VGA_VER_CHARS;
-- last row displayed
constant VER_DISP_END : integer := (VER_DISP_CHR * VGA_VER_CHAR_LINES) - 1;
-- start of vertical synch pulse
constant VER_SYNC_BEG : integer := VER_DISP_END + VGA_VER_FRONT_PORCH;
-- end of vertical synch pulse
constant VER_SYNC_END : integer := VER_SYNC_BEG + VGA_VER_SYNC;
-- Last scan row in the frame
constant VER_SCAN_END : integer := VER_SYNC_END + VGA_VER_BACK_PORCH;
 
constant VER_DISP_END : integer := 399; -- last row displayed
constant VER_SYNC_BEG : integer := 413; -- start of vertical synch pulse
constant VER_SYNC_END : integer := 414; -- end of vertical synch pulse
constant VER_SCAN_END : integer := 450; -- Last scan row in the frame
constant VER_DISP_CHR : integer := 25; -- Number of character rows displayed
 
signal horiz_sync : std_logic := '1';
signal vert_sync : std_logic := '1';
signal cursor_on_v : std_logic;
/System09/trunk/rtl/VHDL/peripheral_bus.vhd
86,8 → 86,8
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use ieee.std_logic_unsigned.all;
library unisim;
use unisim.vcomponents.all;
--library unisim;
-- use unisim.vcomponents.all;
 
-----------------------------------------------------------------------
-- Entity for peripheral bus --
/System09/trunk/rtl/VHDL/datram.vhd
87,8 → 87,8
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
library unisim;
use unisim.vcomponents.all;
--library unisim;
-- use unisim.vcomponents.all;
 
entity dat_ram is
port (
/System09/trunk/rtl/VHDL/ACIA_Clock.vhd
13,7 → 13,6
-- ieee.std_logic_arith
-- ieee.std_logic_unsigned
-- ieee.numeric_std
-- unisim.vcomponents
-- work.bit_funcs
--
-- Author : John E. Kent
55,8 → 54,8
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
use ieee.numeric_std.all;
library unisim;
use unisim.vcomponents.all;
--library unisim;
-- use unisim.vcomponents.all;
library work;
use work.bit_funcs.all;
 
/System09/trunk/rtl/VHDL/spi-master.vhd
11,10 → 11,7
-- Purpose : Implements a SPI Master Controller
--
-- Dependencies : ieee.std_logic_1164
-- ieee.std_logic_arith
-- ieee.std_logic_unsigned
-- ieee.numeric_std
-- unisim.vcomponents
--
-- Author : Hans Huebner
--
/System09/trunk/rtl/VHDL/ps2_keyboard.vhd
12,7 → 12,6
-- ieee.std_logic_unsigned
-- ieee.std_logic_arith
-- ieee.numeric_std
-- unisim.vcomponents
--
-- Author : Original Verilog version by John Clayton
-- Converted to VHDL by John E. Kent
145,7 → 144,7
-- they correspond to 60usec for a 49.152MHz clock.
--
-- Author: John Kent
-- 2001-02-10 Converted to VHDL
--2001-02-10 Converted to VHDL
-- 2004-09-11 Added ctrl key
-- Changed undefined key codes to x"ff"
-- Reversed clock polarity
154,9 → 153,9
-- 2007-02-06 Added Generic Clock parameter
-- 2010-05-31 Revised header, added GPL
-- 2010-06-17 Change some signal names for consistancy
-- 2010-10-24 Rearranged code to prevent shift key outputting characters
--
--
--
---------------------------------------------------------------------------------------
 
library ieee;
164,8 → 163,8
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
use ieee.numeric_std.all;
library unisim;
use unisim.vcomponents.all;
--library unisim;
-- use unisim.vcomponents.all;
 
entity ps2_keyboard is
generic (
203,7 → 202,10
constant LEFT_SHIFT : integer := 16#12#;
constant RIGHT_SHIFT : integer := 16#59#;
constant CTRL_CODE : integer := 16#14#;
constant CAPS_CODE : integer := 16#58#;
constant LEFT_ALT : integer := 16#11#;
constant CAPS_CODE : integer := 16#58#;
constant SCROLL_LOCK : integer := 16#7E#;
constant NUM_LOCK : integer := 16#77#;
 
 
-- constants
228,9 → 230,9
--constant TIMER_5USEC_BITS_PP : integer := 7; -- Number of bits needed for timer
 
-- Values for generic Clock up to 50 MHz
constant TIMER_60USEC_VALUE_PP : integer := CLK_FREQ_MHZ * 60; -- Number of sys_clks for 60usec.
constant TIMER_60USEC_VALUE_PP : integer := CLK_FREQ_MHZ * 60; -- Number of clock cycles for 60usec.
constant TIMER_60USEC_BITS_PP : integer := 12; -- Number of bits needed for timer
constant TIMER_5USEC_VALUE_PP : integer := CLK_FREQ_MHZ * 5; -- Number of sys_clks for debounce
constant TIMER_5USEC_VALUE_PP : integer := CLK_FREQ_MHZ * 5; -- Number of clock cycles for debounce
constant TIMER_5USEC_BITS_PP : integer := 8; -- Number of bits needed for timer
 
constant TRAP_SHIFT_KEYS_PP : integer := 1; -- Default: No shift key trap.
374,66 → 376,72
 
m1_state_logic : process( m1_state, q,
tx_shifting_done, tx_write,
ps2_clk_s, ps2_data_s,
timer_60usec_done, timer_5usec_done )
ps2_clk_s, ps2_data_s,
timer_60usec_done, timer_5usec_done )
begin
-- Output signals default to this value, unless changed in a state condition.
ps2_clk_hi_z <= '1';
ps2_data_hi_z <= '1';
tx_error <= '0';
enable_timer_60usec <= '0';
enable_timer_5usec <= '0';
ps2_clk_hi_z <= '1';
ps2_data_hi_z <= '1';
tx_error <= '0';
enable_timer_60usec <= '0';
enable_timer_5usec <= '0';
 
case (m1_state) is
when m1_rx_clk_h =>
enable_timer_60usec <= '1';
if (tx_write = '1') then
m1_next_state <= m1_tx_reset_timer;
elsif (ps2_clk_s = '0') then
m1_next_state <= m1_rx_falling_edge_marker;
else
m1_next_state <= m1_rx_clk_h;
case (m1_state) is
--
-- receive clock transitions
--
when m1_rx_clk_h =>
enable_timer_60usec <= '1';
if (tx_write = '1') then
m1_next_state <= m1_tx_reset_timer;
elsif (ps2_clk_s = '0') then
m1_next_state <= m1_rx_falling_edge_marker;
else
m1_next_state <= m1_rx_clk_h;
end if;
when m1_rx_falling_edge_marker =>
enable_timer_60usec <= '0';
m1_next_state <= m1_rx_clk_l;
when m1_rx_falling_edge_marker =>
enable_timer_60usec <= '0';
m1_next_state <= m1_rx_clk_l;
 
when m1_rx_clk_l =>
enable_timer_60usec <= '1';
if (tx_write = '1') then
m1_next_state <= m1_tx_reset_timer;
elsif (ps2_clk_s = '1') then
m1_next_state <= m1_rx_rising_edge_marker;
else
m1_next_state <= m1_rx_clk_l;
end if;
when m1_rx_clk_l =>
enable_timer_60usec <= '1';
if (tx_write = '1') then
m1_next_state <= m1_tx_reset_timer;
elsif (ps2_clk_s = '1') then
m1_next_state <= m1_rx_rising_edge_marker;
else
m1_next_state <= m1_rx_clk_l;
end if;
 
when m1_rx_rising_edge_marker =>
enable_timer_60usec <= '0';
m1_next_state <= m1_rx_clk_h;
 
--
-- write to keyboard (Tx)
--
when m1_tx_reset_timer =>
enable_timer_60usec <= '0';
m1_next_state <= m1_tx_force_clk_l;
 
when m1_rx_rising_edge_marker =>
enable_timer_60usec <= '0';
m1_next_state <= m1_rx_clk_h;
when m1_tx_force_clk_l =>
enable_timer_60usec <= '1';
ps2_clk_hi_z <= '0'; -- Force the ps2_clk line low.
if (timer_60usec_done = '1') then
m1_next_state <= m1_tx_first_wait_clk_h;
else
m1_next_state <= m1_tx_force_clk_l;
end if;
 
when m1_tx_reset_timer =>
enable_timer_60usec <= '0';
m1_next_state <= m1_tx_force_clk_l;
 
when m1_tx_force_clk_l =>
enable_timer_60usec <= '1';
ps2_clk_hi_z <= '0'; -- Force the ps2_clk line low.
if (timer_60usec_done = '1') then
m1_next_state <= m1_tx_first_wait_clk_h;
else
m1_next_state <= m1_tx_force_clk_l;
end if;
 
when m1_tx_first_wait_clk_h =>
enable_timer_5usec <= '1';
ps2_data_hi_z <= '0'; -- Start bit.
if (ps2_clk_s = '0') and (timer_5usec_done = '1') then
m1_next_state <= m1_tx_clk_l;
else
m1_next_state <= m1_tx_first_wait_clk_h;
end if;
when m1_tx_first_wait_clk_h =>
enable_timer_5usec <= '1';
ps2_data_hi_z <= '0'; -- Start bit.
if (ps2_clk_s = '0') and (timer_5usec_done = '1') then
m1_next_state <= m1_tx_clk_l;
else
m1_next_state <= m1_tx_first_wait_clk_h;
end if;
-- This state must be included because the device might possibly
-- delay for up to 10 milliseconds before beginning its clock pulses.
440,267 → 448,285
-- During that waiting time, we cannot drive the data (q[0]) because it
-- is possibly 1, which would cause the keyboard to abort its receive
-- and the expected clocks would then never be generated.
when m1_tx_first_wait_clk_l =>
ps2_data_hi_z <= '0';
if (ps2_clk_s = '0') then
m1_next_state <= m1_tx_clk_l;
else
m1_next_state <= m1_tx_first_wait_clk_l;
end if;
when m1_tx_first_wait_clk_l =>
ps2_data_hi_z <= '0';
if (ps2_clk_s = '0') then
m1_next_state <= m1_tx_clk_l;
else
m1_next_state <= m1_tx_first_wait_clk_l;
end if;
 
when m1_tx_wait_clk_h =>
enable_timer_5usec <= '1';
ps2_data_hi_z <= q(0);
if (ps2_clk_s = '1') and (timer_5usec_done = '1') then
m1_next_state <= m1_tx_rising_edge_marker;
else
m1_next_state <= m1_tx_wait_clk_h;
end if;
when m1_tx_wait_clk_h =>
enable_timer_5usec <= '1';
ps2_data_hi_z <= q(0);
if (ps2_clk_s = '1') and (timer_5usec_done = '1') then
m1_next_state <= m1_tx_rising_edge_marker;
else
m1_next_state <= m1_tx_wait_clk_h;
end if;
 
when m1_tx_rising_edge_marker =>
ps2_data_hi_z <= q(0);
m1_next_state <= m1_tx_clk_h;
when m1_tx_rising_edge_marker =>
ps2_data_hi_z <= q(0);
m1_next_state <= m1_tx_clk_h;
 
when m1_tx_clk_h =>
ps2_data_hi_z <= q(0);
if (tx_shifting_done = '1') then
m1_next_state <= m1_tx_wait_keyboard_ack;
elsif (ps2_clk_s = '0') then
m1_next_state <= m1_tx_clk_l;
else
m1_next_state <= m1_tx_clk_h;
end if;
when m1_tx_clk_h =>
ps2_data_hi_z <= q(0);
if (tx_shifting_done = '1') then
m1_next_state <= m1_tx_wait_keyboard_ack;
elsif (ps2_clk_s = '0') then
m1_next_state <= m1_tx_clk_l;
else
m1_next_state <= m1_tx_clk_h;
end if;
 
when m1_tx_clk_l =>
ps2_data_hi_z <= q(0);
if (ps2_clk_s = '1') then
m1_next_state <= m1_tx_wait_clk_h;
else
m1_next_state <= m1_tx_clk_l;
end if;
when m1_tx_clk_l =>
ps2_data_hi_z <= q(0);
if (ps2_clk_s = '1') then
m1_next_state <= m1_tx_wait_clk_h;
else
m1_next_state <= m1_tx_clk_l;
end if;
 
when m1_tx_wait_keyboard_ack =>
if (ps2_clk_s = '0') and (ps2_data_s = '1') then
m1_next_state <= m1_tx_error;
elsif (ps2_clk_s = '0') and (ps2_data_s = '0') then
m1_next_state <= m1_tx_done_recovery;
else
m1_next_state <= m1_tx_wait_keyboard_ack;
end if;
when m1_tx_wait_keyboard_ack =>
if (ps2_clk_s = '0') and (ps2_data_s = '1') then
m1_next_state <= m1_tx_error;
elsif (ps2_clk_s = '0') and (ps2_data_s = '0') then
m1_next_state <= m1_tx_done_recovery;
else
m1_next_state <= m1_tx_wait_keyboard_ack;
end if;
 
when m1_tx_done_recovery =>
if (ps2_clk_s = '1') and (ps2_data_s = '1') then
m1_next_state <= m1_rx_clk_h;
else
m1_next_state <= m1_tx_done_recovery;
end if;
when m1_tx_done_recovery =>
if (ps2_clk_s = '1') and (ps2_data_s = '1') then
m1_next_state <= m1_rx_clk_h;
else
m1_next_state <= m1_tx_done_recovery;
end if;
 
when m1_tx_error =>
tx_error <= '1';
if (ps2_clk_s = '1') and (ps2_data_s ='1') then
m1_next_state <= m1_rx_clk_h;
else
m1_next_state <= m1_tx_error;
end if;
when m1_tx_error =>
tx_error <= '1';
if (ps2_clk_s = '1') and (ps2_data_s ='1') then
m1_next_state <= m1_rx_clk_h;
else
m1_next_state <= m1_tx_error;
end if;
 
when others =>
m1_next_state <= m1_rx_clk_h;
end case;
when others =>
m1_next_state <= m1_rx_clk_h;
end case;
end process;
 
 
--
-- This is the bit counter
--
bit_counter: process(clk, reset, m1_state, bit_count )
begin
if clk'event and clk = '0' then
if ( reset = '1' ) or
( rx_shifting_done = '1' ) or
(m1_state = m1_tx_wait_keyboard_ack) then -- After tx is done.
bit_count <= "0000"; -- normal reset
elsif (timer_60usec_done = '1' ) and
(m1_state = m1_rx_clk_h) and
(ps2_clk_s = '1') then
bit_count <= "0000"; -- rx watchdog timer reset
elsif (m1_state = m1_rx_falling_edge_marker) or -- increment for rx
(m1_state = m1_tx_rising_edge_marker) then -- increment for tx
bit_count <= bit_count + 1;
end if;
end if;
if clk'event and clk = '0' then
if ( reset = '1' ) or ( rx_shifting_done = '1' ) or
(m1_state = m1_tx_wait_keyboard_ack) then -- After tx is done.
bit_count <= "0000"; -- normal reset
elsif (timer_60usec_done = '1' ) and
( m1_state = m1_rx_clk_h ) and
( ps2_clk_s = '1' ) then
bit_count <= "0000"; -- rx watchdog timer reset
elsif ( m1_state = m1_rx_falling_edge_marker ) or -- increment for rx
(m1_state = m1_tx_rising_edge_marker) then -- increment for tx
bit_count <= bit_count + 1;
end if;
end if;
 
if (bit_count = TOTAL_BITS) then
rx_shifting_done <= '1';
else
rx_shifting_done <= '0';
end if;
 
if (bit_count = (TOTAL_BITS-1)) then
tx_shifting_done <= '1';
else
tx_shifting_done <= '0';
end if;
end process;
 
assign: process( bit_count, tx_write, tx_data_empty_o, m1_state )
assign: process( bit_count, tx_write, m1_state, tx_data_empty_o, m1_state )
begin
if (bit_count = TOTAL_BITS) then
rx_shifting_done <= '1';
else
rx_shifting_done <= '0';
end if;
 
if (bit_count = (TOTAL_BITS-1)) then
tx_shifting_done <= '1';
else
tx_shifting_done <= '0';
end if;
 
-- This is the signal which enables loading of the shift register.
-- It also indicates "ack" to the device writing to the transmitter.
if ((tx_write = '1') and (m1_state = m1_rx_clk_h)) or
((tx_write = '1') and (m1_state = m1_rx_clk_l)) then
tx_data_empty_o <= '1';
else
tx_data_empty_o <= '0';
end if;
tx_data_empty <= tx_data_empty_o;
--
-- This is the signal which enables loading of the shift register.
-- It also indicates "ack" to the device writing to the transmitter.
--
if ((tx_write = '1') and (m1_state = m1_rx_clk_h)) or
((tx_write = '1') and (m1_state = m1_rx_clk_l)) then
tx_data_empty_o <= '1';
else
tx_data_empty_o <= '0';
end if;
tx_data_empty <= tx_data_empty_o;
end process;
 
-- This is the ODD parity bit for the transmitted word.
-- assign tx_parity_bit = ~^tx_data;
--
tx_parity_bit <= not( tx_data(7) xor tx_data(6) xor tx_data(5) xor tx_data(4) xor
tx_data(3) xor tx_data(2) xor tx_data(1) xor tx_data(0) );
 
-- This is the shift register
q_shift : process(clk, tx_data_empty_o, tx_parity_bit, tx_data,
m1_state, q, ps2_data_s, rx_shifting_done )
begin
if clk'event and clk='0' then
if (reset = '1') then
q <= "00000000000";
elsif (tx_data_empty_o = '1') then
q <= "1" & tx_parity_bit & tx_data & "0";
elsif ( (m1_state = m1_rx_falling_edge_marker) or
(m1_state = m1_tx_rising_edge_marker) ) then
q <= ps2_data_s & q((TOTAL_BITS-1) downto 1);
end if;
end if;
 
-- Create the signals which indicate special scan codes received.
-- These are the "unlatched versions."
if (q(8 downto 1) = EXTEND_CODE) and (rx_shifting_done = '1') then
extended <= '1';
else
extended <= '0';
end if;
if (q(8 downto 1) = RELEASE_CODE) and (rx_shifting_done = '1') then
released <= '1';
else
released <= '0';
end if;
--
-- This is the ODD parity bit for the transmitted word.
-- assign tx_parity_bit = ~^tx_data;
--
tx_parity_bit <= not( tx_data(7) xor tx_data(6) xor tx_data(5) xor tx_data(4) xor
tx_data(3) xor tx_data(2) xor tx_data(1) xor tx_data(0) );
if clk'event and clk='0' then
if (reset = '1') then
q <= (others=>'0');
elsif (tx_data_empty_o = '1') then
q <= "1" & tx_parity_bit & tx_data & "0";
elsif ( (m1_state = m1_rx_falling_edge_marker) or
(m1_state = m1_tx_rising_edge_marker) ) then
q <= ps2_data_s & q((TOTAL_BITS-1) downto 1);
end if;
end if;
 
end process;
 
 
--
-- This is the 60usec timer counter
--
timer60usec: process(clk, enable_timer_60usec, timer_60usec_count)
begin
if clk'event and clk = '0' then
if (enable_timer_60usec = '0') then
timer_60usec_count <= (others => '0');
elsif (timer_60usec_done = '0') then
timer_60usec_count <= timer_60usec_count + 1;
end if;
end if;
if clk'event and clk = '0' then
if (enable_timer_60usec = '0') then
timer_60usec_count <= (others => '0');
elsif (timer_60usec_done = '0') then
timer_60usec_count <= timer_60usec_count + 1;
end if;
end if;
 
if (timer_60usec_count = (TIMER_60USEC_VALUE_PP - 1)) then
timer_60usec_done <= '1';
else
timer_60usec_done <= '0';
end if;
if (timer_60usec_count = (TIMER_60USEC_VALUE_PP - 1)) then
timer_60usec_done <= '1';
else
timer_60usec_done <= '0';
end if;
end process;
 
 
--
-- This is the 5usec timer counter
--
timer5usec : process(clk, enable_timer_5usec, timer_5usec_count )
begin
if clk'event and clk = '0' then
if (enable_timer_5usec = '0') then
timer_5usec_count <= (others => '0');
elsif (timer_5usec_done = '0') then
timer_5usec_count <= timer_5usec_count + 1;
end if;
end if;
if clk'event and clk = '0' then
if (enable_timer_5usec = '0') then
timer_5usec_count <= (others => '0');
elsif (timer_5usec_done = '0') then
timer_5usec_count <= timer_5usec_count + 1;
end if;
end if;
 
if( timer_5usec_count = (TIMER_5USEC_VALUE_PP - 1)) then
timer_5usec_done <= '1';
else
timer_5usec_done <= '0';
end if;
if( timer_5usec_count = (TIMER_5USEC_VALUE_PP - 1)) then
timer_5usec_done <= '1';
else
timer_5usec_done <= '0';
end if;
end process;
 
--
-- Create the signals which indicate special scan codes received.
-- These are the "unlatched versions."
--
extend_release_decode : process( q, rx_shifting_done, extended, released )
begin
if (q(8 downto 1) = EXTEND_CODE) and (rx_shifting_done = '1') then
extended <= '1';
else
extended <= '0';
end if;
 
if (q(8 downto 1) = RELEASE_CODE) and (rx_shifting_done = '1') then
released <= '1';
else
released <= '0';
end if;
 
if (rx_shifting_done = '1') and (extended = '0') and (released = '0') then
rx_output_event <= '1';
else
rx_output_event <= '0';
end if;
 
end process;
 
 
--
-- Store the special scan code status bits
-- Not the final output, but an intermediate storage place,
-- until the entire set of output data can be assembled.
--
special_scan : process(clk, reset, rx_output_event, rx_shifting_done, extended, released )
begin
if clk'event and clk='0' then
if (reset = '1') or (rx_output_event = '1') then
hold_extended <= '0';
hold_released <= '0';
else
if (rx_shifting_done = '1') and (extended = '1') then
hold_extended <= '1';
end if;
if (rx_shifting_done = '1') and (released = '1') then
hold_released <= '1';
end if;
end if;
end if;
if clk'event and clk='0' then
if (reset = '1') or (rx_output_event = '1') then
hold_extended <= '0';
hold_released <= '0';
else
if (rx_shifting_done = '1') and (extended = '1') then
hold_extended <= '1';
end if;
if (rx_shifting_done = '1') and (released = '1') then
hold_released <= '1';
end if;
end if;
end if;
 
end process;
 
 
--
-- convert scan code to ascii code
--
scan_to_ascii : process( shift_key_on, caps_key_on, q )
begin
shift_key_plus_code <= shift_key_on & caps_key_on & q(7 downto 1);
end process;
 
--
-- These bits contain the status of the two shift keys
--
left_shift_proc : process(clk, reset, q, rx_shifting_done, hold_released )
begin
if clk'event and clk = '0' then
if (reset = '1') then
left_shift_key <= '0';
elsif (q(8 downto 1) = LEFT_SHIFT) and
(rx_shifting_done = '1') and
(hold_released = '0') then
left_shift_key <= '1';
elsif (q(8 downto 1) = LEFT_SHIFT) and
(rx_shifting_done = '1') and
(hold_released = '1') then
left_shift_key <= '0';
end if;
end if;
if clk'event and clk = '0' then
if (reset = '1') then
left_shift_key <= '0';
elsif (q(8 downto 1) = LEFT_SHIFT) and (rx_shifting_done = '1') then
left_shift_key <= not hold_released;
end if;
end if;
end process;
 
right_shift_proc : process(clk, reset, q, rx_shifting_done, hold_released )
begin
if clk'event and clk = '0' then
if (reset = '1') then
right_shift_key <= '0';
elsif (q(8 downto 1) = RIGHT_SHIFT) and
(rx_shifting_done = '1') and
(hold_released = '0') then
right_shift_key <= '1';
elsif (q(8 downto 1) = RIGHT_SHIFT) and
(rx_shifting_done = '1') and
(hold_released = '1') then
right_shift_key <= '0';
end if;
end if;
if clk'event and clk = '0' then
if (reset = '1') then
right_shift_key <= '0';
elsif (q(8 downto 1) = RIGHT_SHIFT) and (rx_shifting_done = '1') then
right_shift_key <= not hold_released;
end if;
end if;
end process;
 
shift_proc : process( left_shift_key, right_shift_key, shift_key_on, caps_key_on, q )
begin
shift_key_on <= left_shift_key or right_shift_key;
rx_shift_on <= shift_key_on;
end process;
 
shift_key_on <= left_shift_key or right_shift_key;
rx_shift_on <= shift_key_on;
 
--
-- Control keys
--
ctrl_proc : process(clk, reset, q, rx_shifting_done, hold_released )
begin
if clk'event and clk = '0' then
if (reset = '1') then
ctrl_key_on <= '0';
elsif (q(8 downto 1) = CTRL_CODE) and
(rx_shifting_done = '1') and
(hold_released = '0') then
ctrl_key_on <= '1';
elsif (q(8 downto 1) = CTRL_CODE) and
(rx_shifting_done = '1') and
(hold_released = '1') then
ctrl_key_on <= '0';
end if;
end if;
if clk'event and clk = '0' then
if (reset = '1') then
ctrl_key_on <= '0';
elsif (q(8 downto 1) = CTRL_CODE) and (rx_shifting_done = '1') then
ctrl_key_on <= not hold_released;
end if;
end if;
end process;
 
--
708,85 → 734,79
--
caps_proc : process(clk, reset, q, rx_shifting_done, hold_released, caps_key_on )
begin
if clk'event and clk = '0' then
if (reset = '1') then
caps_key_on <= '0';
elsif (q(8 downto 1) = CAPS_CODE) and
(rx_shifting_done = '1') and
(hold_released = '0') then
caps_key_on <= not caps_key_on;
end if;
end if;
if clk'event and clk = '0' then
if (reset = '1') then
caps_key_on <= '0';
elsif (q(8 downto 1) = CAPS_CODE) and (rx_shifting_done = '1') then
if (hold_released = '0') then
caps_key_on <= not caps_key_on;
end if;
end if;
end if;
end process;
 
 
--
-- Output the special scan code flags, the scan code and the ascii
special_scan_proc : process(clk, reset,
hold_extended, hold_released,
q, ascii, ctrl_key_on )
--
special_scan_proc : process(clk, reset, rx_output_strobe,
hold_extended, hold_released,
ascii, ctrl_key_on )
begin
if clk'event and clk = '0' then
if (reset = '1') then
rx_extended <= '0';
rx_released <= '0';
-- rx_scan_code <= "00000000";
rx_data <= "00000000";
elsif (rx_output_strobe = '1') then
rx_extended <= hold_extended;
rx_released <= hold_released;
-- rx_scan_code <= q(8 downto 1);
elsif ctrl_key_on = '1' then
rx_data <= ascii and x"1f";
else
rx_data <= ascii;
end if;
end if;
if clk'event and clk = '0' then
if (reset = '1') then
rx_extended <= '0';
rx_released <= '0';
rx_data <= (others=>'0');
elsif (rx_output_strobe = '1') then
rx_extended <= hold_extended;
rx_released <= hold_released;
if ctrl_key_on = '1' then
rx_data <= ascii and x"1f";
else
rx_data <= ascii;
end if;
end if;
end if;
end process;
 
 
--
-- Store the final rx output data only when all extend and release codes
-- are received and the next (actual key) scan code is also ready.
-- (the presence of rx_extended or rx_released refers to the
-- the current latest scan code received, not the previously latched flags.)
 
--
rx_output_proc : process( clk, reset,
rx_shifting_done, rx_output_strobe,
extended, released,
q, ascii, rx_read )
begin
if (rx_shifting_done = '1') and (extended = '0') and (released = '0') then
rx_output_event <= '1';
else
rx_output_event <= '0';
end if;
 
if clk'event and clk = '0' then
if reset = '1' then
rx_output_strobe <= '0';
elsif (rx_shifting_done = '1') and
(rx_output_strobe = '0') and
(extended = '0') and
(released = '0') and
(hold_released = '0' ) and
(ascii /= x"00" ) then
-- ((TRAP_SHIFT_KEYS_PP = 0) or
-- ( (q(8 downto 1) /= RIGHT_SHIFT) and
-- (q(8 downto 1) /= LEFT_SHIFT) and
-- (q(8 downto 1) /= CTRL_CODE) ) )then
rx_output_strobe <= '1';
elsif rx_read = '1' then
rx_output_strobe <= '0';
end if;
end if;
rx_data_ready <= rx_output_strobe;
extended, released,
hold_extended, hold_released,
q, ascii, rx_read )
begin
if clk'event and clk = '0' then
if reset = '1' then
rx_output_strobe <= '0';
elsif (rx_shifting_done = '1') and (rx_output_strobe = '0') and
(extended = '0') and (released = '0') and
(hold_released = '0' ) and
(ascii /= "00000000" ) then
-- ((TRAP_SHIFT_KEYS_PP = 0) or
-- ( (q(8 downto 1) /= RIGHT_SHIFT) and
-- (q(8 downto 1) /= LEFT_SHIFT) and
-- (q(8 downto 1) /= CTRL_CODE) ) )then
rx_output_strobe <= '1';
elsif rx_read = '1' then
rx_output_strobe <= '0';
end if;
end if;
rx_data_ready <= rx_output_strobe;
end process;
 
 
-- This part translates the scan code into an ASCII value...
-- Only the ASCII codes which I considered important have been included.
-- if you want more, just add the appropriate case statement lines...
-- (You will need to know the keyboard scan codes you wish to assign.)
-- The entries are listed in ascending order of ASCII value.
shift_key_plus_code <= shift_key_on & caps_key_on & q(7 downto 1);
 
 
--
-- This part translates the scan code into an ASCII value...
-- Only the ASCII codes which I considered important have been included.
-- if you want more, just add the appropriate case statement lines...
-- (You will need to know the keyboard scan codes you wish to assign.)
-- The entries are listed in ascending order of ASCII value.
--
--shift_map : process( shift_key_plus_code )
--begin
-- case shift_key_plus_code is
896,8 → 916,9
-- when x"10e" => ascii <= x"7e"; -- ~
-- when x"071" => ascii <= x"7f"; -- (Delete OR DEL on numeric keypad)
-- when x"171" => ascii <= x"7f"; -- (Delete OR DEL on numeric keypad)
-- when others => ascii <= x"ff"; -- 0xff used for unlisted characters.
-- when others => ascii <= x"00"; -- 0xff used for unlisted characters.
-- end case;
--end process;
 
 
end rtl;
/System09/trunk/rtl/VHDL/clock_dll.vhd
1,103 → 1,125
--===========================================================================----
--===========================================================================--
-- --
-- clock_dll.vhd - Synthesible System Clock Divider for Xilinx Spartan 3 --
-- --
--===========================================================================--
--
-- S Y N T H E Z I A B L E Clock_dll for System09 - SOC.
-- File name : clock_dll.vhd
--
--===========================================================================----
--
-- This core adheres to the GNU public license
-- No responsibility is taken for this design.
-- Use at own risk.
--
-- File name : Clock_dll.vhd
--
-- Purpose : Generates Clocks for System09
-- For BurchED B3-Spartan2+ and B5-X300
-- Assumes a 12.5 MHz system clock input
-- Generates a x1 (12.5 MHz) CPU clock
-- Generates a x2 (25.0 MHz) VGA clock
-- Generates a x4 (50.0 MHz) MEM clock
--
-- Dependencies : ieee.Std_Logic_1164
-- Purpose : Implements a a system clock divider for System09.
-- For Xilinx Spartan 3 and 3E FPGA boards
-- Assumes a 12.5 MHz system clock input
-- Generates a x1 (12.5 MHz) CPU clock
-- Generates a x2 (25.0 MHz) VGA clock
-- Generates a x4 (50.0 MHz) MEM clock
--
-- Dependencies : ieee.std_logic_1164
-- ieee.std_logic_arith
-- ieee.std_logic_unsigned
-- ieee.std_logic_arith
-- ieee.numeric_std
--
--
-- Revision History :
--
-- Rev : 0.1
-- Date : 7th September 2008
-- Description : Initial version.
--
--
-- ieee.numeric_std
-- unisim.vcomponents
--
-- Author : John E. Kent
--
-- Email : dilbert57@opencores.org
--
-- Web : http://opencores.org/project,system09
--
-- clock_dll.vhd is a system clock divider for system09.
--
-- Copyright (C) 2003 - 2010 John Kent
--
-- This program is free software: you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation, either version 3 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program. If not, see <http://www.gnu.org/licenses/>.
--
--===========================================================================--
-- --
-- Revision History --
-- --
--===========================================================================--
--
-- Revision Name Date Description
-- 0.1 John E. Kent 7th September 2008 Initial version
-- 1.0 John E. Kent 30th May 2010 Added GPL Header
--
library ieee;
use ieee.std_logic_1164.all;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
use ieee.numeric_std.all;
library unisim;
use unisim.vcomponents.all;
 
entity clock_dll is
entity clock_dll is
port(
clk_in : in std_Logic; -- System Clock input
clk_cpu : out std_logic; -- CPU Clock Out (x1)
clk_vga : out std_logic; -- VGA Pixel Clock Out (x2)
clk_mem : out std_logic; -- Memory Clock Out (x4)
locked : out std_logic -- DLL in lock
);
end entity;
 
clk_cpu : out std_logic; -- CPU Clock Out (x1)
clk_vga : out std_logic; -- VGA Pixel Clock Out (x2)
clk_mem : out std_logic; -- Memory Clock Out (x4)
locked : out std_logic -- DLL in lock
);
end entity;
 
architecture RTL of clock_dll is
 
signal CPU_CLK0 : std_ulogic;
signal CPU_CLK90 : std_ulogic;
signal CPU_CLK180 : std_ulogic;
signal CPU_CLK270 : std_ulogic;
signal CPU_CLK2X : std_ulogic;
signal CPU_CLKDV : std_ulogic;
signal CPU_LOCKED : std_ulogic;
signal CPU_CLKFB : std_ulogic;
signal CPU_CLKIN : std_ulogic;
signal CPU_RESET : std_ulogic;
 
signal VGA_CLK0 : std_ulogic;
signal VGA_CLK90 : std_ulogic;
signal VGA_CLK180 : std_ulogic;
signal VGA_CLK270 : std_ulogic;
signal VGA_CLK2X : std_ulogic;
signal VGA_CLKDV : std_ulogic;
signal VGA_LOCKED : std_ulogic;
 
signal CPU_CLK0 : std_ulogic;
signal CPU_CLK90 : std_ulogic;
signal CPU_CLK180 : std_ulogic;
signal CPU_CLK270 : std_ulogic;
signal CPU_CLK2X : std_ulogic;
signal CPU_CLKDV : std_ulogic;
signal CPU_LOCKED : std_ulogic;
signal CPU_CLKFB : std_ulogic;
signal CPU_CLKIN : std_ulogic;
signal CPU_RESET : std_ulogic;
 
signal VGA_CLK0 : std_ulogic;
signal VGA_CLK90 : std_ulogic;
signal VGA_CLK180 : std_ulogic;
signal VGA_CLK270 : std_ulogic;
signal VGA_CLK2X : std_ulogic;
signal VGA_CLKDV : std_ulogic;
signal VGA_LOCKED : std_ulogic;
signal VGA_CLKFB : std_ulogic;
signal VGA_CLKIN : std_ulogic;
signal VGA_CLKIN : std_ulogic;
signal VGA_RESET : std_ulogic;
signal VGA_RESET_N : std_ulogic;
 
-- Component Declaration for CLKDLL should be placed
-- after architecture statement but before begin keyword
 
component CLKDLL
-- synthesis translate_off
generic (
CLKDV_DIVIDE : real := 2.0; -- (1.5, 2.0, 2.5, 3.0, 4.0, 5.0, 8.0, 16.0)
DUTY_CYCLE_CORRECTION : Boolean := TRUE; -- (TRUE, FALSE)
STARTUP_WAIT : boolean := FALSE -- (TRUE, FALSE)
);
-- synthesis translate_on
port (
CLK0 : out STD_ULOGIC;
CLK180 : out STD_ULOGIC;
CLK270 : out STD_ULOGIC;
CLK2X : out STD_ULOGIC;
CLK90 : out STD_ULOGIC;
CLKDV : out STD_ULOGIC;
LOCKED : out STD_ULOGIC;
CLKFB : in STD_ULOGIC;
CLKIN : in STD_ULOGIC;
RST : in STD_ULOGIC
);
end component;
 
 
-- Component Declaration for CLKDLL should be placed
-- after architecture statement but before begin keyword
 
component CLKDLL
-- synthesis translate_off
generic (
CLKDV_DIVIDE : real := 2.0; -- (1.5, 2.0, 2.5, 3.0, 4.0, 5.0, 8.0, 16.0)
DUTY_CYCLE_CORRECTION : Boolean := TRUE; -- (TRUE, FALSE)
STARTUP_WAIT : boolean := FALSE -- (TRUE, FALSE)
);
-- synthesis translate_on
port (
CLK0 : out STD_ULOGIC;
CLK180 : out STD_ULOGIC;
CLK270 : out STD_ULOGIC;
CLK2X : out STD_ULOGIC;
CLK90 : out STD_ULOGIC;
CLKDV : out STD_ULOGIC;
LOCKED : out STD_ULOGIC;
CLKFB : in STD_ULOGIC;
CLKIN : in STD_ULOGIC;
RST : in STD_ULOGIC
);
end component;
 
component IBUFG
port (
i: in std_logic;
111,122 → 133,122
o: out std_logic
);
end component;
 
component SRL16
port (
Q : out std_logic;
D : in std_logic;
CLK : in std_logic;
A0 : in std_logic;
A1 : in std_logic;
A2 : in std_logic;
A3 : in std_logic
);
end component;
 
 
component SRL16
port (
Q : out std_logic;
D : in std_logic;
CLK : in std_logic;
A0 : in std_logic;
A1 : in std_logic;
A2 : in std_logic;
A3 : in std_logic
);
end component;
 
--
-- Start instantiation
--
begin
 
--
-- Start instantiation
--
begin
 
--
-- 12.5MHz CPU clock input
--
cpu_clkin_buffer : IBUFG
cpu_clkin_buffer : IBUFG
port map(
i => clk_in,
o => CPU_CLKIN
);
 
 
--
-- 12.5MHz CPU clock input
--
cpu_clkout_buffer : BUFG
cpu_clkout_buffer : BUFG
port map(
i => CPU_CLKIN,
o => clk_cpu
);
 
 
--
-- 25 MHz VGA clock input
--
cpu_clkfb_buffer : BUFG
cpu_clkfb_buffer : BUFG
port map(
i => CPU_CLK2X,
o => CPU_CLKFB
);
 
CLKDLL_CPU : CLKDLL
-- synthesis translate_off
generic map (
CLKDV_DIVIDE => 2.0, -- (1.5,2,2.5,3,4,5,8,16)
DUTY_CYCLE_CORRECTION => TRUE, -- (TRUE, FALSE)
STARTUP_WAIT => FALSE -- (TRUE, FALSE)
);
-- synthesis translate_on
port map (
CLK0 => CPU_CLK0,
CLK90 => CPU_CLK90,
CLK180 => CPU_CLK180,
CLK270 => CPU_CLK270,
CLK2X => CPU_CLK2X,
CLKDV => CPU_CLKDV,
LOCKED => CPU_LOCKED,
CLKFB => CPU_CLKFB,
CLKIN => CPU_CLKIN,
RST => CPU_RESET
);
 
CLKDLL_CPU : CLKDLL
-- synthesis translate_off
generic map (
CLKDV_DIVIDE => 2.0, -- (1.5,2,2.5,3,4,5,8,16)
DUTY_CYCLE_CORRECTION => TRUE, -- (TRUE, FALSE)
STARTUP_WAIT => FALSE -- (TRUE, FALSE)
);
-- synthesis translate_on
port map (
CLK0 => CPU_CLK0,
CLK90 => CPU_CLK90,
CLK180 => CPU_CLK180,
CLK270 => CPU_CLK270,
CLK2X => CPU_CLK2X,
CLKDV => CPU_CLKDV,
LOCKED => CPU_LOCKED,
CLKFB => CPU_CLKFB,
CLKIN => CPU_CLKIN,
RST => CPU_RESET
);
--
-- 25 MHz VGA clock output
--
vga_clkfb_buffer : BUFG
vga_clkfb_buffer : BUFG
port map(
i => VGA_CLK2X,
o => VGA_CLKFB
);
 
CLKDLL_VGA : CLKDLL
-- synthesis translate_off
generic map (
CLKDV_DIVIDE => 2.0, -- (1.5,2,2.5,3,4,5,8,16)
DUTY_CYCLE_CORRECTION => TRUE, -- (TRUE, FALSE)
STARTUP_WAIT => FALSE -- (TRUE, FALSE)
);
-- synthesis translate_on
port map (
CLK0 => VGA_CLK0,
CLK90 => VGA_CLK90,
CLK180 => VGA_CLK180,
CLK270 => VGA_CLK270,
CLK2X => VGA_CLK2X,
CLKDV => VGA_CLKDV,
LOCKED => VGA_LOCKED,
CLKFB => VGA_CLKFB,
CLKIN => VGA_CLKIN,
RST => VGA_RESET
);
my_srl16 : SRL16 port map (
Q => VGA_RESET_N,
D => CPU_LOCKED,
CLK => CPU_CLKFB,
A0 => '1',
A1 => '1',
A2 => '1',
A3 => '1'
);
 
clock_dll_assign : process( VGA_RESET_N, VGA_LOCKED,
clk_in, CPU_CLKFB, VGA_CLKFB )
begin
VGA_RESET <= not VGA_RESET_N;
VGA_CLKIN <= CPU_CLKFB;
CPU_RESET <= '0';
clk_vga <= CPU_CLKFB;
clk_mem <= VGA_CLKFB;
locked <= VGA_LOCKED;
end process;
 
end architecture;
 
CLKDLL_VGA : CLKDLL
-- synthesis translate_off
generic map (
CLKDV_DIVIDE => 2.0, -- (1.5,2,2.5,3,4,5,8,16)
DUTY_CYCLE_CORRECTION => TRUE, -- (TRUE, FALSE)
STARTUP_WAIT => FALSE -- (TRUE, FALSE)
);
-- synthesis translate_on
port map (
CLK0 => VGA_CLK0,
CLK90 => VGA_CLK90,
CLK180 => VGA_CLK180,
CLK270 => VGA_CLK270,
CLK2X => VGA_CLK2X,
CLKDV => VGA_CLKDV,
LOCKED => VGA_LOCKED,
CLKFB => VGA_CLKFB,
CLKIN => VGA_CLKIN,
RST => VGA_RESET
);
my_srl16 : SRL16 port map (
Q => VGA_RESET_N,
D => CPU_LOCKED,
CLK => CPU_CLKFB,
A0 => '1',
A1 => '1',
A2 => '1',
A3 => '1'
);
 
clock_dll_assign : process( VGA_RESET_N, VGA_LOCKED,
clk_in, CPU_CLKFB, VGA_CLKFB )
begin
VGA_RESET <= not VGA_RESET_N;
VGA_CLKIN <= CPU_CLKFB;
CPU_RESET <= '0';
clk_vga <= CPU_CLKFB;
clk_mem <= VGA_CLKFB;
locked <= VGA_LOCKED;
end process;
 
end architecture;
/System09/trunk/rtl/VHDL/vdu8.vhd
15,9 → 15,7
-- Supports 2 x 8 chunky graphics character mode.
-- Uses Generic arguments for setting the video synchronization timing.
--
-- Dependencies : ieee.Std_Logic_1164
-- ieee.std_logic_unsigned
-- ieee.std_logic_arith
-- Dependencies : ieee.std_logic_1164
-- ieee.numeric_std
--
-- Uses : ram_2k (ram2k_b16.vhd) 2KByte Character & Attribute buffer
133,8 → 131,8
Library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
Library unisim;
use unisim.vcomponents.all;
--Library unisim;
-- use unisim.vcomponents.all;
 
Entity vdu8 is
generic(
/System09/trunk/rtl/VHDL/pia6821.vhd
61,8 → 61,8
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
library unisim;
use unisim.vcomponents.all;
--library unisim;
-- use unisim.vcomponents.all;
 
entity pia6821 is
port (
/System09/trunk/rtl/VHDL/keyboard.vhd
14,7 → 14,6
-- ieee.std_logic_arith
-- ieee.std_logic_unsigned
-- ieee.numeric_std
-- unisim.vcomponents
--
-- Uses : ps2_keyboard_interface
--
88,8 → 87,8
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
use ieee.numeric_std.all;
library unisim;
use unisim.vcomponents.all;
--library unisim;
-- use unisim.vcomponents.all;
 
entity keyboard is
generic (
249,7 → 248,7
--
keyboard_status : process( kbd_data_ready, kbd_data_empty,
kbd_extended, kbd_released, kbd_shift_on, kbd_error,
kbd_control)
kbd_control, kbd_status )
begin
kbd_status(0) <= kbd_data_ready;
kbd_status(1) <= kbd_data_empty;
/System09/trunk/rtl/VHDL/pia_timer.vhd
122,7 → 122,7
signal ca1_rise : std_logic;
signal ca1_fall : std_logic;
signal ca1_edge : std_logic;
signal irqa1 : std_logic;
signal irqa1 : std_logic := '0';
 
signal ca2 : std_logic;
signal ca2_del : std_logic;
129,7 → 129,7
signal ca2_rise : std_logic;
signal ca2_fall : std_logic;
signal ca2_edge : std_logic;
signal irqa2 : std_logic;
signal irqa2 : std_logic := '0';
signal ca2_out : std_logic;
 
signal cb1 : std_logic;
137,7 → 137,7
signal cb1_rise : std_logic;
signal cb1_fall : std_logic;
signal cb1_edge : std_logic;
signal irqb1 : std_logic;
signal irqb1 : std_logic := '0';
 
signal cb2 : std_logic;
signal cb2_del : std_logic;
144,7 → 144,7
signal cb2_rise : std_logic;
signal cb2_fall : std_logic;
signal cb2_edge : std_logic;
signal irqb2 : std_logic;
signal irqb2 : std_logic := '0';
signal cb2_out : std_logic;
 
-- 74193 down counter
166,55 → 166,57
pa, pb )
variable count : integer;
begin
case addr is
when "00" =>
for count in 0 to 7 loop
if porta_ctrl(2) = '0' then
data_out(count) <= porta_ddr(count);
porta_read <= '0';
data_out <= "00000000";
porta_read <= '0';
portb_read <= '0';
 
case addr is
when "00" =>
for count in 0 to 7 loop
if porta_ctrl(2) = '0' then
data_out(count) <= porta_ddr(count);
porta_read <= '0';
else
if porta_ddr(count) = '1' then
data_out(count) <= porta_data(count);
else
if porta_ddr(count) = '1' then
data_out(count) <= porta_data(count);
else
data_out(count) <= pa(count);
end if;
porta_read <= cs;
data_out(count) <= pa(count);
end if;
end loop;
portb_read <= '0';
porta_read <= cs;
end if;
end loop;
portb_read <= '0';
 
when "01" =>
data_out <= irqa1 & irqa2 & porta_ctrl;
porta_read <= '0';
portb_read <= '0';
when "01" =>
data_out <= irqa1 & irqa2 & porta_ctrl;
porta_read <= '0';
portb_read <= '0';
 
when "10" =>
for count in 0 to 7 loop
if portb_ctrl(2) = '0' then
data_out(count) <= portb_ddr(count);
portb_read <= '0';
when "10" =>
for count in 0 to 7 loop
if portb_ctrl(2) = '0' then
data_out(count) <= portb_ddr(count);
portb_read <= '0';
else
if portb_ddr(count) = '1' then
data_out(count) <= portb_data(count);
else
if portb_ddr(count) = '1' then
data_out(count) <= portb_data(count);
else
data_out(count) <= pb(count);
end if;
portb_read <= cs;
end if;
end loop;
porta_read <= '0';
end if;
portb_read <= cs;
end if;
end loop;
porta_read <= '0';
 
when "11" =>
data_out <= irqb1 & irqb2 & portb_ctrl;
porta_read <= '0';
portb_read <= '0';
when "11" =>
data_out <= irqb1 & irqb2 & portb_ctrl;
porta_read <= '0';
portb_read <= '0';
 
when others =>
data_out <= "00000000";
porta_read <= '0';
portb_read <= '0';
when others =>
null;
end case;
 
end case;
end process;
 
---------------------------------
/System09/trunk/rtl/VHDL/ioport.vhd
55,8 → 55,8
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
library unisim;
use unisim.vcomponents.all;
--library unisim;
-- use unisim.vcomponents.all;
 
entity ioport is
port (
/System09/trunk/rtl/VHDL/acia6850.vhd
12,8 → 12,8
-- Asynchronous Communications Interface Adapter (ACIA)
--
-- Dependencies : ieee.std_logic_1164
-- ieee.numeric_std
-- unisim.vcomponents
-- ieee.numeric_std
-- ieee.std_logic_unsigned
--
-- Author : John E. Kent
--
125,8 → 125,8
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use ieee.std_logic_unsigned.all;
library unisim;
use unisim.vcomponents.all;
--library unisim;
-- use unisim.vcomponents.all;
 
-----------------------------------------------------------------------
-- Entity for ACIA_6850 --
340,11 → 340,12
-- Generate Read / Write strobes.
-----------------------------------------------------------------------------
 
ACIA_Read_Write : process(clk, ac_rst)
acia_read_write : process(clk, ac_rst)
begin
if falling_edge(clk) then
if ac_rst = '1' then
CtrlReg <= (others => '0');
if rst = '1' then
CtrlReg(1 downto 0) <= "11";
CtrlReg(7 downto 2) <= (others => '0');
TxReg <= (others => '0');
RxRd <= '0';
TxWr <= '0';
/System09/trunk/rtl/VHDL/Flasher.vhd
14,7 → 14,6
-- Dependencies : ieee.std_logic_1164
-- ieee.numeric_std
-- ieee.std_logic_unsigned
-- unisim.vcomponents
--
-- Author : John E. Kent
--
53,8 → 52,8
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use ieee.std_logic_unsigned.all;
library unisim;
use unisim.vcomponents.all;
--library unisim;
-- use unisim.vcomponents.all;
 
-----------------------------------------------------------------------
-- Entity for B3_SRAM --
/System09/trunk/rtl/VHDL/clock_div.vhd
1,42 → 1,65
--===========================================================================----
--===========================================================================
--
-- S Y N T H E Z I A B L E Clock_dll for System09 - SOC.
-- clock_div.vhd - Clock divider for System09
--
--===========================================================================----
--===========================================================================
--
-- File name : clock_div.vhd
--
-- Entity name : clock_div
--
-- This core adheres to the GNU public license
-- No responsibility is taken for this design.
-- Use at own risk.
-- Purpose : Generates Clocks for System09
-- For BurchED B3-Spartan2+ and B5-X300
-- Divides the input clock which is normally 50MHz
-- Generates a 1/1 (50.0 MHz) SYS clock
-- Generates a 1/2 (25.0 MHz) VGA clock
-- Generates a 1/4 (12.5 MHz) CPU clock
--
-- File name : Clock_dll.vhd
-- Dependencies : ieee.Std_Logic_1164
-- ieee.std_logic_unsigned
-- ieee.std_logic_arith
-- ieee.numeric_std
--
-- Purpose : Generates Clocks for System09
-- For BurchED B3-Spartan2+ and B5-X300
-- Assumes a 12.5 MHz system clock input
-- Generates a x1 (12.5 MHz) CPU clock
-- Generates a x2 (25.0 MHz) VGA clock
-- Generates a x4 (50.0 MHz) MEM clock
-- Uses : IBUFG
-- BUFG
--
-- Dependencies : ieee.Std_Logic_1164
-- ieee.std_logic_unsigned
-- ieee.std_logic_arith
-- ieee.numeric_std
-- Author : John E. Kent
-- dilbert57@opencores.org
--
-- Copyright (C) 2003 - 2010 John Kent
--
-- This program is free software: you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation, either version 3 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program. If not, see <http://www.gnu.org/licenses/>.
--
--===========================================================================
--
-- Revision History :
-- Revision History:
--
--===========================================================================
--
-- Rev : 0.1
-- Date : 7th September 2008
-- Description : Initial version.
--
-- Rev: Date: Author: Description:
--
-- 0.1 2008-09-07 John Kent Initial version
-- 0.2 2010-09-14 John Kent Updated header
--
--
library ieee;
use ieee.std_logic_1164.all;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
use ieee.numeric_std.all;
library unisim;
use unisim.vcomponents.all;
--library unisim;
-- use unisim.vcomponents.all;
 
entity clock_div is
port(
49,16 → 72,8
 
architecture RTL of clock_div is
 
signal div_clk : std_logic;
signal div_count : std_logic_vector(1 downto 0);
 
component IBUFG
port (
i: in std_logic;
o: out std_logic
);
end component;
 
 
component BUFG
port (
i: in std_logic;
66,7 → 81,6
);
end component;
 
 
--
-- Start instantiation
--
73,12 → 87,12
begin
 
--
-- 50.0MHz system clock
-- 50 MHz SYS clock output
--
sys_clk_buffer : IBUFG
sys_clk_buffer : BUFG
port map(
i => clk_in,
o => div_clk
o => sys_clk
);
 
--
102,12 → 116,11
--
-- Clock divider
--
clock_div : process( div_clk )
clock_div : process( clk_in )
begin
if rising_edge( div_clk) then
if rising_edge( clk_in ) then
div_count <= div_count + "01";
end if;
sys_clk <= div_clk;
end process;
 
end architecture;
/System09/trunk/rtl/System09_Digilent_3S500E/System09_Digilent_3S500E_X.ise Cannot display: file marked as a binary type. svn:mime-type = application/octet-stream
/System09/trunk/rtl/System09_Digilent_3S500E/System09_Digilent_3S500E_X.ise
System09/trunk/rtl/System09_Digilent_3S500E/System09_Digilent_3S500E_X.ise Property changes : Added: svn:mime-type ## -0,0 +1 ## +application/octet-stream \ No newline at end of property Index: System09/trunk/rtl/System09_Digilent_3S500E/System09_Digilent_3S500E.vhd =================================================================== --- System09/trunk/rtl/System09_Digilent_3S500E/System09_Digilent_3S500E.vhd (revision 117) +++ System09/trunk/rtl/System09_Digilent_3S500E/System09_Digilent_3S500E.vhd (revision 118) @@ -1,14 +1,14 @@ -- $Id: System09_Digilent_3S500E.vhd,v 1.3.2.1 2008/04/08 14:59:48 davidgb Exp $ ---===========================================================================---- +--=========================================================================== -- --- S Y N T H E Z I A B L E System09 - SOC. +-- System09 - SoC for the Digilent Spartan 3E Starter board -- ---===========================================================================---- +--=========================================================================== -- --- This core adheres to the GNU public license +-- File name : System09_Digilent_3S500E.vhd +-- +-- Entity name : my_system09 -- --- File name : System09_Digilent_3S500E.vhd --- -- Purpose : Top level file for 6809 compatible system on a chip -- Designed with Xilinx XC3S500E Spartan 3E FPGA. -- Implemented With Digilent Xilinx Starter FPGA board, @@ -18,19 +18,67 @@ -- ieee.std_logic_arith -- ieee.numeric_std -- --- Uses : mon_rom (kbug_rom2k.vhd) Monitor ROM --- cpu09 (cpu09.vhd) CPU core --- miniuart (minitUART3.vhd) ACIA / MiniUART --- (rxunit3.vhd) --- (tx_unit3.vhd) +-- Uses : clock_div (../vhdl/clock_div.vhd) System clock divider +-- flasher (../vhdl/flasher.vhd) LED flasher +-- ram_32k (../Spartan3/ram32k_b16.vhd) 32K block RAM +-- cpu09 (../vhdl/cpu09.vhd) CPU core +-- mon_rom (../spartan3/sys09bug_3se_rom2k_b16.vhd) Monitor ROM +-- acia6850 (../vhdl/acia6850.vhd) ACIA +-- ACIA_Clock (../vhdl/ACIA_Clock.vhd) ACIA Baud Clock Divider +-- keyboard (../vhdl/keyboard.vhd) PS/2 Keyboard Interface +-- vdu8 (../vhdl/vdu8.vhd) 80 x 25 Video Display +-- timer (../vhdl/timer.vhd) Timer component +-- pia_timer (../vhdl/pia_timer.vhd) PIA interrupt Timer cmponent +-- trap (../vhdl/trap.vhd) Hardware Breakpoint Bus Trap +-- vdu8 (../vhdl/vdu8.vhd) VDU -- -- Author : John E. Kent -- dilbert57@opencores.org +-- Memory Map : +-- +-- $0000 - $7FFF System Block RAM +-- $E000 - ACIA (SWTPc) +-- $E010 - Reserved for SWTPc FD-01 FD1771 FDC +-- $E020 - Keyboard +-- $E030 - VDU +-- $E040 - Reserved for SWTPc MP-T (was Compact Flash) +-- $E050 - Timer +-- $E060 - Bus Trap (Hardware Breakpoint Interrupt Logic) +-- $E070 - PIA Single Step Timer (was Reserved for Trace Buffer) +-- $E080 - Reserved for SWTPc MP-ID 6821 PIA (?) +-- $E090 - Reserved for SWTPc MP-ID 6840 PTM (?) +-- $E0A0 - reserved for SPP Printer Port +-- $E0B0 - Reserved +-- $E0C0 - Reserved +-- $E100 - $E13F Reserved IDE / Compact Flash Card +-- $E140 - $E17F Reserved for Ethernet MAC (XESS) +-- $E180 - $E1BF Reserved for Expansion Slot 0 (XESS) +-- $E1C0 - $E1FF Reserved for Expansion Slot 1 (XESS) +-- $E200 - $EFFF Dual Port RAM interface +-- $F000 - $F7FF Reserved SWTPc DMAF-2 +-- $F800 - $FFFF Sys09bug ROM (Read only) +-- $FFF0 - $FFFF Reserved for DAT - Dynamic Address Translation (Write Only) -- ---===========================================================================---- +-- Copyright (C) 2003 - 2010 John Kent +-- +-- This program is free software: you can redistribute it and/or modify +-- it under the terms of the GNU General Public License as published by +-- the Free Software Foundation, either version 3 of the License, or +-- (at your option) any later version. +-- +-- This program is distributed in the hope that it will be useful, +-- but WITHOUT ANY WARRANTY; without even the implied warranty of +-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +-- GNU General Public License for more details. +-- +-- You should have received a copy of the GNU General Public License +-- along with this program. If not, see . +-- +--=========================================================================== -- --- Revision History: ---===========================================================================-- +-- Revision History: +-- +--=========================================================================== -- Version 0.1 - 20 March 2003 -- Version 0.2 - 30 March 2003 -- Version 0.3 - 29 April 2003 @@ -82,7 +130,17 @@ -- $E050 - Timer -- $E060 - Bus trap -- $E070 - Parallel I/O --- +-- +-- Version 4.1 - July / september 2010 +-- Updated VDU interface +-- and possible other changes. +-- +-- Version 4.2 - 14th September 2010 +-- Replaced ACIA_6850 with acia6850 +-- Cleaned up decoding +-- Added Flasher component +-- Added Clock Divider component +-- --===========================================================================-- library ieee; use ieee.std_logic_1164.all; @@ -131,6 +189,10 @@ ----------------------------------------------------------------------------- -- Signals ----------------------------------------------------------------------------- + -- Clocks + signal sys_clk : std_logic; + signal vga_clk : std_logic; + -- BOOT ROM signal rom_cs : Std_logic; signal rom_data_out : Std_Logic_Vector(7 downto 0); @@ -140,11 +202,6 @@ signal uart_cs : Std_Logic; signal uart_irq : Std_Logic; signal uart_clk : Std_Logic; - signal rxbit : Std_Logic; - signal txbit : Std_Logic; - signal DCD_n : Std_Logic; - signal RTS_n : Std_Logic; - signal CTS_n : Std_Logic; -- timer signal timer_data_out : std_logic_vector(7 downto 0); @@ -163,38 +220,60 @@ signal pia_irq_b : Std_Logic; -- keyboard port - signal keyboard_data_out : std_logic_vector(7 downto 0); - signal keyboard_cs : std_logic; - signal keyboard_irq : std_logic; + signal kbd_data_out : std_logic_vector(7 downto 0); + signal kbd_cs : std_logic; + signal kbd_irq : std_logic; -- Video Display Unit - signal vga_clk : std_logic; - signal vdu_cs : std_logic; - signal vdu_data_out : std_logic_vector(7 downto 0); + signal vdu_cs : std_logic; + signal vdu_data_out : std_logic_vector(7 downto 0); -- RAM - signal ram_cs : std_logic; -- memory chip select - signal ram_data_out : std_logic_vector(7 downto 0); + signal ram_cs : std_logic; -- memory chip select + signal ram_data_out : std_logic_vector(7 downto 0); -- CPU Interface signals - signal cpu_reset : Std_Logic; - signal cpu_clk : Std_Logic; - signal cpu_rw : std_logic; - signal cpu_vma : std_logic; - signal cpu_halt : std_logic; - signal cpu_hold : std_logic; - signal cpu_firq : std_logic; - signal cpu_irq : std_logic; - signal cpu_nmi : std_logic; - signal cpu_addr : std_logic_vector(15 downto 0); - signal cpu_data_in : std_logic_vector(7 downto 0); - signal cpu_data_out : std_logic_vector(7 downto 0); + signal cpu_rst : Std_Logic; + signal cpu_clk : Std_Logic; + signal cpu_rw : std_logic; + signal cpu_vma : std_logic; + signal cpu_halt : std_logic; + signal cpu_hold : std_logic; + signal cpu_firq : std_logic; + signal cpu_irq : std_logic; + signal cpu_nmi : std_logic; + signal cpu_addr : std_logic_vector(15 downto 0); + signal cpu_data_in : std_logic_vector(7 downto 0); + signal cpu_data_out : std_logic_vector(7 downto 0); + +----------------------------------------------------------------- +-- +-- Clock generator +-- +----------------------------------------------------------------- + +component clock_div + port( + clk_in : in std_Logic; -- System Clock input + sys_clk : out std_logic; -- System Clock Out (1/1) + vga_clk : out std_logic; -- VGA Pixel Clock Out (1/2) + cpu_clk : out std_logic -- CPU Clock Out (1/4) + ); +end component; + +----------------------------------------------------------------- +-- +-- LED Flasher +-- +----------------------------------------------------------------- - -- CLK_50MHZ clock divide by 2 - signal clock_div : std_logic_vector(1 downto 0); - signal SysClk : std_logic; - signal Reset_n : std_logic; - signal CountL : std_logic_vector(23 downto 0); +component flasher + port ( + clk : in std_logic; -- Clock input + rst : in std_logic; -- Reset input (active high) + LED : out Std_Logic -- LED output + ); +end component; ----------------------------------------------------------------- -- @@ -206,9 +285,9 @@ port ( clk : in std_logic; rst : in std_logic; + vma : out std_logic; + addr : out std_logic_vector(15 downto 0); rw : out std_logic; - vma : out std_logic; - address : out std_logic_vector(15 downto 0); data_out : out std_logic_vector(7 downto 0); data_in : in std_logic_vector(7 downto 0); irq : in std_logic; @@ -247,8 +326,8 @@ clk : in std_logic; rst : in std_logic; cs : in std_logic; + addr : in std_logic_vector (14 downto 0); rw : in std_logic; - addr : in std_logic_vector (14 downto 0); data_in : in std_logic_vector (7 downto 0); data_out : out std_logic_vector (7 downto 0) ); @@ -265,8 +344,8 @@ clk : in std_logic; rst : in std_logic; cs : in std_logic; + addr : in std_logic_vector(1 downto 0); rw : in std_logic; - addr : in std_logic_vector(1 downto 0); data_in : in std_logic_vector(7 downto 0); data_out : out std_logic_vector(7 downto 0); irqa : out std_logic; @@ -281,7 +360,7 @@ -- ----------------------------------------------------------------- -component ACIA_6850 +component acia6850 port ( clk : in Std_Logic; -- System Clock rst : in Std_Logic; -- Reset input (active high) @@ -325,12 +404,12 @@ component timer port ( - clk : in std_logic; - rst : in std_logic; - cs : in std_logic; - rw : in std_logic; - addr : in std_logic; - data_in : in std_logic_vector(7 downto 0); + clk : in std_logic; + rst : in std_logic; + cs : in std_logic; + addr : in std_logic; + rw : in std_logic; + data_in : in std_logic_vector(7 downto 0); data_out : out std_logic_vector(7 downto 0); irq : out std_logic ); @@ -347,8 +426,8 @@ clk : in std_logic; rst : in std_logic; cs : in std_logic; + vma : in std_logic; rw : in std_logic; - vma : in std_logic; addr : in std_logic_vector(15 downto 0); data_in : in std_logic_vector(7 downto 0); data_out : out std_logic_vector(7 downto 0); @@ -364,19 +443,19 @@ component keyboard generic( - KBD_CLK_FREQ : integer := CPU_CLK_FREQ + KBD_CLK_FREQ : integer := CPU_CLK_FREQ ); port( - clk : in std_logic; - rst : in std_logic; - cs : in std_logic; - rw : in std_logic; - addr : in std_logic; - data_in : in std_logic_vector(7 downto 0); - data_out : out std_logic_vector(7 downto 0); - irq : out std_logic; - kbd_clk : inout std_logic; - kbd_data : inout std_logic + clk : in std_logic; + rst : in std_logic; + cs : in std_logic; + addr : in std_logic; + rw : in std_logic; + data_in : in std_logic_vector(7 downto 0); + data_out : out std_logic_vector(7 downto 0); + irq : out std_logic; + kbd_clk : inout std_logic; + kbd_data : inout std_logic ); end component; @@ -419,25 +498,49 @@ ); end component; +begin + +----------------------------------------------------------------------------- +-- Instantiation of internal components +----------------------------------------------------------------------------- + +---------------------------------------- +-- +-- Clock generator +-- +---------------------------------------- + +my_clock_div: clock_div port map ( + clk_in => CLK_50MHZ, -- Clock input + sys_clk => sys_clk, -- System Clock Out (1/1) + vga_clk => vga_clk, -- CPU/VGA Pixel Clock Out (1/2) + cpu_clk => open -- (1/4) + ); + +----------------------------------------- +-- +-- LED Flasher +-- +----------------------------------------- -component BUFG -port ( - i: in std_logic; - o: out std_logic +my_LED_flasher : flasher port map ( + clk => cpu_clk, + rst => cpu_rst, + LED => LED(0) ); -end component; + +---------------------------------------- +-- +-- 6809 compatible CPU +-- +---------------------------------------- -begin - ----------------------------------------------------------------------------- - -- Instantiation of internal components - ----------------------------------------------------------------------------- - my_cpu : cpu09 port map ( clk => cpu_clk, - rst => cpu_reset, + rst => cpu_rst, + vma => cpu_vma, + addr => cpu_addr(15 downto 0), rw => cpu_rw, - vma => cpu_vma, - address => cpu_addr(15 downto 0), data_out => cpu_data_out, data_in => cpu_data_in, irq => cpu_irq, @@ -449,10 +552,10 @@ my_rom : mon_rom port map ( clk => cpu_clk, - rst => cpu_reset, + rst => cpu_rst, cs => rom_cs, + addr => cpu_addr(10 downto 0), rw => '1', - addr => cpu_addr(10 downto 0), data_in => cpu_data_out, data_out => rom_data_out ); @@ -459,10 +562,10 @@ my_ram : ram_32k port map ( clk => cpu_clk, - rst => cpu_reset, + rst => cpu_rst, cs => ram_cs, + addr => cpu_addr(14 downto 0), rw => cpu_rw, - addr => cpu_addr(14 downto 0), data_in => cpu_data_out, data_out => ram_data_out ); @@ -469,10 +572,10 @@ my_pia : pia_timer port map ( clk => cpu_clk, - rst => cpu_reset, + rst => cpu_rst, cs => pia_cs, + addr => cpu_addr(1 downto 0), rw => cpu_rw, - addr => cpu_addr(1 downto 0), data_in => cpu_data_out, data_out => pia_data_out, irqa => pia_irq_a, @@ -479,28 +582,27 @@ irqb => pia_irq_b ); - ---------------------------------------- -- -- ACIA/UART Serial interface -- ---------------------------------------- -my_ACIA : ACIA_6850 port map ( +my_ACIA : acia6850 port map ( clk => cpu_clk, - rst => cpu_reset, + rst => cpu_rst, cs => uart_cs, + addr => cpu_addr(0), rw => cpu_rw, - addr => cpu_addr(0), data_in => cpu_data_out, data_out => uart_data_out, irq => uart_irq, RxC => uart_clk, TxC => uart_clk, - RxD => rxbit, - TxD => txbit, - DCD_n => dcd_n, - CTS_n => cts_n, - RTS_n => rts_n + RxD => RS232_DCE_RXD, + TxD => RS232_DCE_TXD, + DCD_n => '0', + CTS_n => '0', + RTS_n => open ); ---------------------------------------- @@ -514,7 +616,7 @@ ACIA_CLK_FREQ => ACIA_CLK_FREQ ) port map( - clk => SysClk, + clk => sys_clk, acia_clk => uart_clk ); @@ -527,19 +629,19 @@ ---------------------------------------- my_keyboard : keyboard generic map ( - KBD_CLK_FREQ => CPU_CLK_FREQ + KBD_CLK_FREQ => CPU_CLK_FREQ ) port map( - clk => cpu_clk, - rst => cpu_reset, - cs => keyboard_cs, - rw => cpu_rw, - addr => cpu_addr(0), - data_in => cpu_data_out(7 downto 0), - data_out => keyboard_data_out(7 downto 0), - irq => keyboard_irq, - kbd_clk => PS2_CLK, - kbd_data => PS2_DATA + clk => cpu_clk, + rst => cpu_rst, + cs => kbd_cs, + addr => cpu_addr(0), + rw => cpu_rw, + data_in => cpu_data_out(7 downto 0), + data_out => kbd_data_out(7 downto 0), + irq => kbd_irq, + kbd_clk => PS2_CLK, + kbd_data => PS2_DATA ); ---------------------------------------- @@ -559,16 +661,16 @@ VGA_VER_CHAR_LINES => 16, -- LINES VGA_VER_FRONT_PORCH => 10, -- LINES VGA_VER_SYNC => 2, -- LINES - VGA_VER_FRONT_PORCH => 34 -- LINES + VGA_VER_BACK_PORCH => 34 -- LINES ) port map( -- Control Registers vdu_clk => cpu_clk, -- 25 MHz System Clock in - vdu_rst => cpu_reset, + vdu_rst => cpu_rst, vdu_cs => vdu_cs, + vdu_addr => cpu_addr(2 downto 0), vdu_rw => cpu_rw, - vdu_addr => cpu_addr(2 downto 0), vdu_data_in => cpu_data_out, vdu_data_out => vdu_data_out, @@ -589,7 +691,7 @@ ---------------------------------------- my_timer : timer port map ( clk => cpu_clk, - rst => cpu_reset, + rst => cpu_rst, cs => timer_cs, rw => cpu_rw, addr => cpu_addr(0), @@ -605,7 +707,7 @@ ---------------------------------------- my_trap : trap port map ( clk => cpu_clk, - rst => cpu_reset, + rst => cpu_rst, cs => trap_cs, rw => cpu_rw, vma => cpu_vma, @@ -614,22 +716,6 @@ data_out => trap_data_out, irq => trap_irq ); - --- --- 25 MHz CPU clock --- -cpu_clk_buffer : BUFG port map( - i => clock_div(0), - o => cpu_clk - ); - --- --- 25 MHz VGA Pixel clock --- -vga_clk_buffer : BUFG port map( - i => clock_div(0), - o => vga_clk - ); ---------------------------------------------------------------------- -- @@ -637,8 +723,7 @@ -- ---------------------------------------------------------------------- -mem_decode: process( cpu_clk, Reset_n, - cpu_addr, cpu_rw, cpu_vma, +mem_decode: process( cpu_addr, cpu_rw, cpu_vma, rom_data_out, ram_data_out, timer_data_out, @@ -645,14 +730,20 @@ trap_data_out, pia_data_out, uart_data_out, - keyboard_data_out, + kbd_data_out, vdu_data_out ) -variable decode_addr : std_logic_vector(3 downto 0); begin --- decode_addr := dat_addr(3 downto 0) & cpu_addr(11); - decode_addr := cpu_addr(15 downto 12); + + rom_cs <= '0'; + ram_cs <= '0'; + uart_cs <= '0'; + timer_cs <= '0'; + trap_cs <= '0'; + pia_cs <= '0'; + kbd_cs <= '0'; + vdu_cs <= '0'; - case decode_addr is + case cpu_addr(15 downto 12) is -- -- SBUG/KBUG/SYS09BUG Monitor ROM $F800 - $FFFF -- @@ -659,20 +750,11 @@ when "1111" => -- $F000 - $FFFF cpu_data_in <= rom_data_out; rom_cs <= cpu_vma; -- read ROM - ram_cs <= '0'; - uart_cs <= '0'; - timer_cs <= '0'; - trap_cs <= '0'; - pia_cs <= '0'; - keyboard_cs <= '0'; - vdu_cs <= '0'; -- -- IO Devices $E000 - $EFFF -- when "1110" => -- $E000 - $E7FF - rom_cs <= '0'; - ram_cs <= '0'; case cpu_addr(7 downto 4) is -- -- UART / ACIA $E000 @@ -680,11 +762,6 @@ when "0000" => -- $E000 cpu_data_in <= uart_data_out; uart_cs <= cpu_vma; - timer_cs <= '0'; - trap_cs <= '0'; - pia_cs <= '0'; - keyboard_cs <= '0'; - vdu_cs <= '0'; -- -- WD1771 FDC sites at $E010-$E01F @@ -691,24 +768,13 @@ -- when "0001" => -- $E010 cpu_data_in <= (others => '0'); - uart_cs <= '0'; - timer_cs <= '0'; - trap_cs <= '0'; - pia_cs <= '0'; - keyboard_cs <= '0'; - vdu_cs <= '0'; -- -- Keyboard port $E020 - $E02F -- when "0010" => -- $E020 - cpu_data_in <= keyboard_data_out; - uart_cs <= '0'; - timer_cs <= '0'; - trap_cs <= '0'; - pia_cs <= '0'; - keyboard_cs <= cpu_vma; - vdu_cs <= '0'; + cpu_data_in <= kbd_data_out; + kbd_cs <= cpu_vma; -- -- VDU port $E030 - $E03F @@ -715,11 +781,6 @@ -- when "0011" => -- $E030 cpu_data_in <= vdu_data_out; - uart_cs <= '0'; - timer_cs <= '0'; - trap_cs <= '0'; - pia_cs <= '0'; - keyboard_cs <= '0'; vdu_cs <= cpu_vma; -- @@ -727,12 +788,6 @@ -- when "0100" => -- $E040 cpu_data_in <= (others => '0'); - uart_cs <= '0'; - timer_cs <= '0'; - trap_cs <= '0'; - pia_cs <= '0'; - keyboard_cs <= '0'; - vdu_cs <= '0'; -- -- Timer $E050 - $E05F @@ -739,12 +794,7 @@ -- when "0101" => -- $E050 cpu_data_in <= timer_data_out; - uart_cs <= '0'; timer_cs <= cpu_vma; - trap_cs <= '0'; - pia_cs <= '0'; - keyboard_cs <= '0'; - vdu_cs <= '0'; -- -- Bus Trap Logic $E060 - $E06F @@ -751,33 +801,17 @@ -- when "0110" => -- $E060 cpu_data_in <= trap_data_out; - uart_cs <= '0'; - timer_cs <= '0'; trap_cs <= cpu_vma; - pia_cs <= '0'; - keyboard_cs <= '0'; - vdu_cs <= '0'; -- - -- I/O port $E070 - $E07F + -- PIA Timer $E070 - $E07F -- when "0111" => -- $E070 cpu_data_in <= pia_data_out; - uart_cs <= '0'; - timer_cs <= '0'; - trap_cs <= '0'; pia_cs <= cpu_vma; - keyboard_cs <= '0'; - vdu_cs <= '0'; when others => -- $E080 to $E7FF cpu_data_in <= (others => '0'); - uart_cs <= '0'; - timer_cs <= '0'; - trap_cs <= '0'; - pia_cs <= '0'; - keyboard_cs <= '0'; - vdu_cs <= '0'; end case; -- @@ -786,73 +820,37 @@ when "1101" | "1100" | "1011" | "1010" | "1001" | "1000" => cpu_data_in <= (others => '0'); - rom_cs <= '0'; - ram_cs <= '0'; - uart_cs <= '0'; - timer_cs <= '0'; - trap_cs <= '0'; - pia_cs <= '0'; - keyboard_cs <= '0'; - vdu_cs <= '0'; + -- -- Everything else is RAM -- when others => cpu_data_in <= ram_data_out; - rom_cs <= '0'; ram_cs <= cpu_vma; - uart_cs <= '0'; - timer_cs <= '0'; - trap_cs <= '0'; - pia_cs <= '0'; - keyboard_cs <= '0'; - vdu_cs <= '0'; end case; end process; -- --- Interrupts and other bus control signals +-- Assign CPU clock, reset, interrupt, halt & hold signals +-- as well as LED signals -- -interrupts : process( Reset_n, - pia_irq_a, pia_irq_b, uart_irq, trap_irq, timer_irq, keyboard_irq +assign_signals : process( vga_clk, BTN_SOUTH, + pia_irq_a, pia_irq_b, uart_irq, trap_irq, timer_irq, kbd_irq ) -begin - cpu_reset <= not Reset_n; -- CPU reset is active high - cpu_irq <= uart_irq or keyboard_irq; - cpu_nmi <= pia_irq_a or trap_irq; - cpu_firq <= pia_irq_b or timer_irq; - cpu_halt <= '0'; - cpu_hold <= '0'; -end process; +begin + cpu_clk <= vga_clk; + cpu_rst <= BTN_SOUTH; -- CPU reset is active high + cpu_irq <= uart_irq or kbd_irq; + cpu_nmi <= pia_irq_a or trap_irq; + cpu_firq <= pia_irq_b or timer_irq; + cpu_halt <= '0'; + cpu_hold <= '0'; --- --- -my_led_flasher: process( SysClk, Reset_n, CountL ) -begin - if Reset_n = '0' then - CountL <= "000000000000000000000000"; - elsif(SysClk'event and SysClk = '0') then - CountL <= CountL + 1; - end if; - LED(7 downto 0) <= CountL(23 downto 16); + -- LED outputs + LED(7 downto 1) <= (others=>'1'); + end process; --- --- Clock divider --- -my_clock_divider: process( SysClk ) -begin - if SysClk'event and SysClk='0' then - clock_div <= clock_div + "01"; - end if; -end process; -DCD_n <= '0'; -CTS_n <= '0'; -Reset_n <= not BTN_SOUTH; -- CPU reset is active high -SysClk <= CLK_50MHZ; -rxbit <= RS232_DCE_RXD; -RS232_DCE_TXD <= txbit; - end my_computer; --===================== End of architecture =======================--

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