URL
https://opencores.org/ocsvn/System09/System09/trunk
Subversion Repositories System09
Compare Revisions
- This comparison shows the changes necessary to convert path
/
- from Rev 151 to Rev 152
- ↔ Reverse comparison
Rev 151 → Rev 152
/System09/trunk/rtl/System09_Digilent_Atlys/Makefile
147,7 → 147,8
-$(RM) *.cmd_log *.ngr *.bld *_summary.html *.nc1 *.pcf *.bgn tmp.ut |
-$(RM) *.pad *.placed_ncd_tracker *.routed_ncd_tracker *_pad.csv *.drc |
-$(RM) *.pad_txt $(DESIGN_NAME)_impact.cmd *.unroutes $(DESIGN_NAME)_vhdl.prj |
-$(RMDIR) _ngo _xmsgs xst xlnx_auto_0_xdb xst_tmp_dirs |
-$(RM) par_usage_statistics.html $(DESIGN_NAME)_envsettings.html |
-$(RMDIR) _ngo _xmsgs xst xlnx_auto_0_xdb xst_tmp_dirs iseconfig |
|
.PHONY: cleanall |
cleanall: clean |
/System09/trunk/rtl/System09_Digilent_Atlys/system09.gise
103,37 → 103,86
<status xil_pn:value="SuccessfullyRun"/> |
<status xil_pn:value="ReadyToRun"/> |
</transform> |
<transform xil_pn:end_ts="1589854160" xil_pn:in_ck="8454006537499441943" xil_pn:name="TRANEXT_xstsynthesize_spartan6" xil_pn:prop_ck="1974990584335492622" xil_pn:start_ts="1589854120"> |
<transform xil_pn:end_ts="1589987846" xil_pn:in_ck="7198331467256017067" xil_pn:name="TRANEXT_xstsynthesize_spartan6" xil_pn:prop_ck="1974990584335492622" xil_pn:start_ts="1589987807"> |
<status xil_pn:value="SuccessfullyRun"/> |
<status xil_pn:value="WarningsGenerated"/> |
<status xil_pn:value="ReadyToRun"/> |
<status xil_pn:value="OutOfDateForInputs"/> |
<status xil_pn:value="OutOfDateForOutputs"/> |
<status xil_pn:value="InputAdded"/> |
<status xil_pn:value="InputRemoved"/> |
<status xil_pn:value="OutputRemoved"/> |
<status xil_pn:value="OutputChanged"/> |
<outfile xil_pn:name="_xmsgs/xst.xmsgs"/> |
<outfile xil_pn:name="system09.lso"/> |
<outfile xil_pn:name="system09.ngc"/> |
<outfile xil_pn:name="system09.ngr"/> |
<outfile xil_pn:name="system09.prj"/> |
<outfile xil_pn:name="system09.stx"/> |
<outfile xil_pn:name="system09.syr"/> |
<outfile xil_pn:name="system09.xst"/> |
<outfile xil_pn:name="system09_xst.xrpt"/> |
<outfile xil_pn:name="webtalk_pn.xml"/> |
<outfile xil_pn:name="xst"/> |
</transform> |
<transform xil_pn:end_ts="1518994687" xil_pn:in_ck="6003168217582152378" xil_pn:name="TRAN_compileBCD2" xil_pn:prop_ck="-3128816144678396997" xil_pn:start_ts="1518994687"> |
<status xil_pn:value="SuccessfullyRun"/> |
<status xil_pn:value="ReadyToRun"/> |
</transform> |
<transform xil_pn:end_ts="1518994692" xil_pn:in_ck="-2676906326711859666" xil_pn:name="TRANEXT_ngdbuild_FPGA" xil_pn:prop_ck="3664377249183397421" xil_pn:start_ts="1518994687"> |
<transform xil_pn:end_ts="1589987895" xil_pn:in_ck="-2676906326711859666" xil_pn:name="TRANEXT_ngdbuild_FPGA" xil_pn:prop_ck="7427287850225075136" xil_pn:start_ts="1589987891"> |
<status xil_pn:value="SuccessfullyRun"/> |
<status xil_pn:value="NotReadyToRun"/> |
<status xil_pn:value="OutOfDateForInputs"/> |
<status xil_pn:value="OutOfDateForPredecessor"/> |
<status xil_pn:value="OutOfDateForOutputs"/> |
<status xil_pn:value="InputRemoved"/> |
<status xil_pn:value="OutputRemoved"/> |
<status xil_pn:value="WarningsGenerated"/> |
<status xil_pn:value="ReadyToRun"/> |
<outfile xil_pn:name="_ngo"/> |
<outfile xil_pn:name="_xmsgs/ngdbuild.xmsgs"/> |
<outfile xil_pn:name="system09.bld"/> |
<outfile xil_pn:name="system09.ngd"/> |
<outfile xil_pn:name="system09_ngdbuild.xrpt"/> |
</transform> |
<transform xil_pn:end_ts="1518994711" xil_pn:in_ck="190496098961729835" xil_pn:name="TRAN_postRouteTrce" xil_pn:prop_ck="445577401284416186" xil_pn:start_ts="1518994707"> |
<transform xil_pn:end_ts="1589987902" xil_pn:in_ck="-1009016811758874705" xil_pn:name="TRANEXT_map_spartan6" xil_pn:prop_ck="7013356299669423719" xil_pn:start_ts="1589987895"> |
<status xil_pn:value="SuccessfullyRun"/> |
<status xil_pn:value="NotReadyToRun"/> |
<status xil_pn:value="OutOfDateForInputs"/> |
<status xil_pn:value="ReadyToRun"/> |
<status xil_pn:value="OutOfDateForOutputs"/> |
<status xil_pn:value="InputRemoved"/> |
<status xil_pn:value="OutputRemoved"/> |
<status xil_pn:value="OutputChanged"/> |
<outfile xil_pn:name="_xmsgs/map.xmsgs"/> |
<outfile xil_pn:name="system09.pcf"/> |
<outfile xil_pn:name="system09_map.map"/> |
<outfile xil_pn:name="system09_map.mrp"/> |
<outfile xil_pn:name="system09_map.ncd"/> |
<outfile xil_pn:name="system09_map.ngm"/> |
<outfile xil_pn:name="system09_map.xrpt"/> |
<outfile xil_pn:name="system09_summary.xml"/> |
<outfile xil_pn:name="system09_usage.xml"/> |
</transform> |
<transform xil_pn:end_ts="1589987917" xil_pn:in_ck="-7782462315172532792" xil_pn:name="TRANEXT_par_spartan6" xil_pn:prop_ck="-3829590541433901613" xil_pn:start_ts="1589987902"> |
<status xil_pn:value="SuccessfullyRun"/> |
<status xil_pn:value="WarningsGenerated"/> |
<status xil_pn:value="ReadyToRun"/> |
<outfile xil_pn:name="_xmsgs/par.xmsgs"/> |
<outfile xil_pn:name="system09.ncd"/> |
<outfile xil_pn:name="system09.pad"/> |
<outfile xil_pn:name="system09.par"/> |
<outfile xil_pn:name="system09.ptwx"/> |
<outfile xil_pn:name="system09.unroutes"/> |
<outfile xil_pn:name="system09.xpi"/> |
<outfile xil_pn:name="system09_pad.csv"/> |
<outfile xil_pn:name="system09_pad.txt"/> |
<outfile xil_pn:name="system09_par.xrpt"/> |
</transform> |
<transform xil_pn:end_ts="1589987940" xil_pn:in_ck="6003168217582144753" xil_pn:name="TRANEXT_bitFile_spartan6" xil_pn:prop_ck="-5761130248037966628" xil_pn:start_ts="1589987931"> |
<status xil_pn:value="SuccessfullyRun"/> |
<status xil_pn:value="ReadyToRun"/> |
<outfile xil_pn:name="_xmsgs/bitgen.xmsgs"/> |
<outfile xil_pn:name="system09.bgn"/> |
<outfile xil_pn:name="system09.bit"/> |
<outfile xil_pn:name="system09.drc"/> |
<outfile xil_pn:name="system09.ut"/> |
<outfile xil_pn:name="webtalk.log"/> |
<outfile xil_pn:name="webtalk_pn.xml"/> |
</transform> |
<transform xil_pn:end_ts="1589987917" xil_pn:in_ck="190496098961729835" xil_pn:name="TRAN_postRouteTrce" xil_pn:prop_ck="-1758799009971969896" xil_pn:start_ts="1589987912"> |
<status xil_pn:value="SuccessfullyRun"/> |
<status xil_pn:value="ReadyToRun"/> |
<outfile xil_pn:name="_xmsgs/trce.xmsgs"/> |
<outfile xil_pn:name="system09.twr"/> |
<outfile xil_pn:name="system09.twx"/> |
</transform> |
</transforms> |
|
</generated_project> |
/System09/trunk/rtl/System09_Digilent_Atlys/system09.prj
1,7 → 1,6
vhdl work "common.vhd" |
vhdl work "../VHDL/bit_funcs.vhd" |
vhdl work "../../src/sys09bug/sys09swt.vhd" |
vhdl work "../../src/Flex9/flex9ram.vhd" |
vhdl work "../../src/sys09bug/sys09xes.vhd" |
vhdl work "../../src/Flex9/flex9ide.vhd" |
vhdl work "../VHDL/trap.vhd" |
vhdl work "../VHDL/timer.vhd" |
vhdl work "../VHDL/datram.vhd" |
8,4 → 7,5
vhdl work "../VHDL/cpu09.vhd" |
vhdl work "../VHDL/ACIA_Clock.vhd" |
vhdl work "../VHDL/acia6850.vhd" |
vhdl work "common.vhd" |
vhdl work "system09.vhd" |
/System09/trunk/rtl/System09_Digilent_Atlys/system09.ut
2,28 → 2,29
-g DebugBitstream:No |
-g Binary:no |
-g CRC:Enable |
-g ConfigRate:6 |
-g CclkPin:PullUp |
-g M0Pin:PullUp |
-g M1Pin:PullUp |
-g M2Pin:PullUp |
-g ProgPin:PullUp |
-g DonePin:PullUp |
-g HswapenPin:PullUp |
-g TckPin:PullUp |
-g TdiPin:PullUp |
-g TdoPin:PullUp |
-g TmsPin:PullUp |
-g UnusedPin:PullDown |
-g Reset_on_err:No |
-g ConfigRate:2 |
-g ProgPin:PullNone |
-g TckPin:PullNone |
-g TdiPin:PullNone |
-g TdoPin:PullNone |
-g TmsPin:PullNone |
-g UnusedPin:PullNone |
-g UserID:0xFFFFFFFF |
-g DCMShutdown:Disable |
-g DCIUpdateMode:AsRequired |
-g ExtMasterCclk_en:No |
-g SPI_buswidth:1 |
-g TIMER_CFG:0xFFFF |
-g multipin_wakeup:No |
-g StartUpClk:CClk |
-g DONE_cycle:4 |
-g GTS_cycle:5 |
-g GWE_cycle:6 |
-g LCK_cycle:NoWait |
-g Match_cycle:NoWait |
-g Security:None |
-g DonePipe:Yes |
-g DonePipe:No |
-g DriveDone:No |
-g en_sw_gsr:No |
-g drive_awake:No |
-g sw_clk:Startupclk |
-g sw_gwe_cycle:5 |
-g sw_gts_cycle:4 |
/System09/trunk/rtl/System09_Digilent_Atlys/system09.xise
15,70 → 15,42
<version xil_pn:ise_version="14.7" xil_pn:schema_version="2"/> |
|
<files> |
<file xil_pn:name="xsasdramcntl.vhd" xil_pn:type="FILE_VHDL"> |
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="1"/> |
<association xil_pn:name="Implementation" xil_pn:seqID="12"/> |
</file> |
<file xil_pn:name="common.vhd" xil_pn:type="FILE_VHDL"> |
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="3"/> |
<association xil_pn:name="Implementation" xil_pn:seqID="1"/> |
<association xil_pn:name="Implementation" xil_pn:seqID="10"/> |
</file> |
<file xil_pn:name="sdramcntl.vhd" xil_pn:type="FILE_VHDL"> |
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="4"/> |
<association xil_pn:name="Implementation" xil_pn:seqID="3"/> |
</file> |
<file xil_pn:name="../VHDL/timer.vhd" xil_pn:type="FILE_VHDL"> |
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="5"/> |
<association xil_pn:name="Implementation" xil_pn:seqID="7"/> |
<association xil_pn:name="Implementation" xil_pn:seqID="5"/> |
</file> |
<file xil_pn:name="../Spartan3/char_rom2k_b16.vhd" xil_pn:type="FILE_VHDL"> |
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="6"/> |
<association xil_pn:name="Implementation" xil_pn:seqID="0"/> |
</file> |
<file xil_pn:name="../Spartan3/keymap_rom_slice.vhd" xil_pn:type="FILE_VHDL"> |
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="7"/> |
<association xil_pn:name="Implementation" xil_pn:seqID="0"/> |
</file> |
<file xil_pn:name="../../src/Flex9/flex9ide.vhd" xil_pn:type="FILE_VHDL"> |
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="8"/> |
<association xil_pn:name="Implementation" xil_pn:seqID="5"/> |
<association xil_pn:name="Implementation" xil_pn:seqID="3"/> |
</file> |
<file xil_pn:name="../VHDL/ACIA_Clock.vhd" xil_pn:type="FILE_VHDL"> |
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="9"/> |
<association xil_pn:name="Implementation" xil_pn:seqID="10"/> |
<association xil_pn:name="Implementation" xil_pn:seqID="8"/> |
</file> |
<file xil_pn:name="../VHDL/acia6850.vhd" xil_pn:type="FILE_VHDL"> |
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="10"/> |
<association xil_pn:name="Implementation" xil_pn:seqID="11"/> |
<association xil_pn:name="Implementation" xil_pn:seqID="9"/> |
</file> |
<file xil_pn:name="../VHDL/vdu8.vhd" xil_pn:type="FILE_VHDL"> |
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="11"/> |
<association xil_pn:name="Implementation" xil_pn:seqID="0"/> |
</file> |
<file xil_pn:name="../../src/sys09bug/sys09xes.vhd" xil_pn:type="FILE_VHDL"> |
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="12"/> |
<association xil_pn:name="Implementation" xil_pn:seqID="4"/> |
<association xil_pn:name="Implementation" xil_pn:seqID="2"/> |
</file> |
<file xil_pn:name="../VHDL/ps2_keyboard.vhd" xil_pn:type="FILE_VHDL"> |
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="13"/> |
<association xil_pn:name="Implementation" xil_pn:seqID="0"/> |
</file> |
<file xil_pn:name="../VHDL/datram.vhd" xil_pn:type="FILE_VHDL"> |
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="14"/> |
<association xil_pn:name="Implementation" xil_pn:seqID="8"/> |
<association xil_pn:name="Implementation" xil_pn:seqID="6"/> |
</file> |
<file xil_pn:name="../VHDL/trap.vhd" xil_pn:type="FILE_VHDL"> |
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="15"/> |
<association xil_pn:name="Implementation" xil_pn:seqID="6"/> |
<association xil_pn:name="Implementation" xil_pn:seqID="4"/> |
</file> |
<file xil_pn:name="../VHDL/cpu09.vhd" xil_pn:type="FILE_VHDL"> |
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="16"/> |
<association xil_pn:name="Implementation" xil_pn:seqID="9"/> |
<association xil_pn:name="Implementation" xil_pn:seqID="7"/> |
</file> |
<file xil_pn:name="../VHDL/keyboard.vhd" xil_pn:type="FILE_VHDL"> |
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="17"/> |
<association xil_pn:name="Implementation" xil_pn:seqID="0"/> |
</file> |
<file xil_pn:name="../Spartan3/ram2k_b16.vhd" xil_pn:type="FILE_VHDL"> |
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="18"/> |
<association xil_pn:name="Implementation" xil_pn:seqID="0"/> |
85,7 → 57,7
</file> |
<file xil_pn:name="../VHDL/bit_funcs.vhd" xil_pn:type="FILE_VHDL"> |
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="31"/> |
<association xil_pn:name="Implementation" xil_pn:seqID="2"/> |
<association xil_pn:name="Implementation" xil_pn:seqID="1"/> |
</file> |
<file xil_pn:name="system09.ucf" xil_pn:type="FILE_UCF"> |
<association xil_pn:name="Implementation" xil_pn:seqID="0"/> |
92,7 → 64,7
</file> |
<file xil_pn:name="system09.vhd" xil_pn:type="FILE_VHDL"> |
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="72"/> |
<association xil_pn:name="Implementation" xil_pn:seqID="13"/> |
<association xil_pn:name="Implementation" xil_pn:seqID="11"/> |
</file> |
</files> |
|
220,7 → 192,7
<property xil_pn:name="Ignore User Timing Constraints Map" xil_pn:value="false" xil_pn:valueState="default"/> |
<property xil_pn:name="Ignore User Timing Constraints Par" xil_pn:value="false" xil_pn:valueState="default"/> |
<property xil_pn:name="Implementation Top" xil_pn:value="Architecture|system09|rtl" xil_pn:valueState="non-default"/> |
<property xil_pn:name="Implementation Top File" xil_pn:value="System09_Atlys.vhd" xil_pn:valueState="non-default"/> |
<property xil_pn:name="Implementation Top File" xil_pn:value="system09.vhd" xil_pn:valueState="non-default"/> |
<property xil_pn:name="Implementation Top Instance Path" xil_pn:value="/system09" xil_pn:valueState="non-default"/> |
<property xil_pn:name="Include 'uselib Directive in Verilog File" xil_pn:value="false" xil_pn:valueState="default"/> |
<property xil_pn:name="Include SIMPRIM Models in Verilog File" xil_pn:value="false" xil_pn:valueState="default"/> |
434,7 → 406,7
<property xil_pn:name="Use Synchronous Reset" xil_pn:value="Auto" xil_pn:valueState="default"/> |
<property xil_pn:name="Use Synchronous Set" xil_pn:value="Auto" xil_pn:valueState="default"/> |
<property xil_pn:name="Use Synthesis Constraints File" xil_pn:value="true" xil_pn:valueState="default"/> |
<property xil_pn:name="User Browsed Strategy Files" xil_pn:value="" xil_pn:valueState="default"/> |
<property xil_pn:name="User Browsed Strategy Files" xil_pn:value="C:/Xilinx/14.7/ISE_DS/ISE/data/default.xds" xil_pn:valueState="non-default"/> |
<property xil_pn:name="UserID Code (8 Digit Hexadecimal)" xil_pn:value="0xFFFFFFFF" xil_pn:valueState="default"/> |
<property xil_pn:name="VCCAUX Voltage Level spartan6" xil_pn:value="2.5V" xil_pn:valueState="default"/> |
<property xil_pn:name="VHDL Source Analysis Standard" xil_pn:value="VHDL-93" xil_pn:valueState="default"/> |