URL
https://opencores.org/ocsvn/System09/System09/trunk
Subversion Repositories System09
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- This comparison shows the changes necessary to convert path
/
- from Rev 28 to Rev 29
- ↔ Reverse comparison
Rev 28 → Rev 29
/branches/mkfiles_rev1/rtl/System09_Xess_XSA-3S1000/my_system09.xst
0,0 → 1,53
set -tmpdir "./xst/projnav.tmp" |
set -xsthdpdir "./xst" |
run |
-ifn my_system09.prj |
-ifmt mixed |
-ofn my_system09 |
-ofmt NGC |
-p xc3s1000-4-ft256 |
-top my_system09 |
-opt_mode Speed |
-opt_level 1 |
-iuc NO |
-lso my_system09.lso |
-keep_hierarchy NO |
-rtlview Yes |
-glob_opt AllClockNets |
-read_cores YES |
-write_timing_constraints NO |
-cross_clock_analysis NO |
-hierarchy_separator / |
-bus_delimiter <> |
-case maintain |
-slice_utilization_ratio 100 |
-verilog2001 YES |
-fsm_extract YES -fsm_encoding Auto |
-safe_implementation No |
-fsm_style lut |
-ram_extract Yes |
-ram_style Auto |
-rom_extract Yes |
-mux_style Auto |
-decoder_extract YES |
-priority_extract YES |
-shreg_extract YES |
-shift_extract YES |
-xor_collapse YES |
-rom_style Auto |
-mux_extract YES |
-resource_sharing YES |
-mult_style auto |
-iobuf YES |
-max_fanout 500 |
-bufg 8 |
-register_duplication YES |
-register_balancing No |
-slice_packing YES |
-optimize_primitives NO |
-use_clock_enable Yes |
-use_sync_set Yes |
-use_sync_reset Yes |
-iob auto |
-equivalent_register_removal YES |
-slice_utilization_ratio_maxmargin 5 |
/branches/mkfiles_rev1/rtl/System09_Xess_XSA-3S1000/my_system09.ise
Cannot display: file marked as a binary type.
svn:mime-type = application/octet-stream
branches/mkfiles_rev1/rtl/System09_Xess_XSA-3S1000/my_system09.ise
Property changes :
Added: svn:mime-type
## -0,0 +1 ##
+application/octet-stream
\ No newline at end of property
Index: branches/mkfiles_rev1/rtl/System09_Xess_XSA-3S1000/my_system09.ut
===================================================================
--- branches/mkfiles_rev1/rtl/System09_Xess_XSA-3S1000/my_system09.ut (nonexistent)
+++ branches/mkfiles_rev1/rtl/System09_Xess_XSA-3S1000/my_system09.ut (revision 29)
@@ -0,0 +1,28 @@
+-w
+-g DebugBitstream:No
+-g Binary:no
+-g CRC:Enable
+-g ConfigRate:6
+-g CclkPin:PullNone
+-g M0Pin:PullNone
+-g M1Pin:PullNone
+-g M2Pin:PullNone
+-g ProgPin:PullNone
+-g DonePin:PullNone
+-g TckPin:PullNone
+-g TdiPin:PullNone
+-g TdoPin:PullNone
+-g TmsPin:PullNone
+-g UnusedPin:PullNone
+-g UserID:0xFFFFFFFF
+-g DCMShutdown:Disable
+-g DCIUpdateMode:AsRequired
+-g StartUpClk:CClk
+-g DONE_cycle:4
+-g GTS_cycle:5
+-g GWE_cycle:6
+-g LCK_cycle:NoWait
+-g Match_cycle:Auto
+-g Security:None
+-g DonePipe:No
+-g DriveDone:No
Index: branches/mkfiles_rev1/rtl/System09_Xess_XSA-3S1000/my_system09.prj
===================================================================
--- branches/mkfiles_rev1/rtl/System09_Xess_XSA-3S1000/my_system09.prj (nonexistent)
+++ branches/mkfiles_rev1/rtl/System09_Xess_XSA-3S1000/my_system09.prj (revision 29)
@@ -0,0 +1,20 @@
+vhdl work "common.vhd"
+vhdl work "../VHDL/ACIA_Clock.vhd"
+vhdl work "../Spartan3/keymap_rom_slice.vhd"
+vhdl work "../../src/sys09bug/sys09xes.vhd"
+vhdl work "../../src/Flex9/flex9ide.vhd"
+vhdl work "../VHDL/ps2_keyboard.vhd"
+vhdl work "../VHDL/ACIA_TX.vhd"
+vhdl work "../VHDL/ACIA_RX.vhd"
+vhdl work "sdramcntl.vhd"
+vhdl work "../Spartan3/ram2k_b16.vhd"
+vhdl work "../Spartan3/char_rom2k_b16.vhd"
+vhdl work "../VHDL/vdu8.vhd"
+vhdl work "../VHDL/trap.vhd"
+vhdl work "../VHDL/timer.vhd"
+vhdl work "../VHDL/keyboard.vhd"
+vhdl work "../VHDL/datram.vhd"
+vhdl work "../VHDL/cpu09.vhd"
+vhdl work "../VHDL/ACIA_6850.vhd"
+vhdl work "xsasdramcntl.vhd"
+vhdl work "System09_Xess_XSA-3S1000.vhd"
Index: branches/mkfiles_rev1/rtl/System09_Xess_XSA-3S1000/System09_Xess_XSA-3S1000.vhd
===================================================================
--- branches/mkfiles_rev1/rtl/System09_Xess_XSA-3S1000/System09_Xess_XSA-3S1000.vhd (revision 28)
+++ branches/mkfiles_rev1/rtl/System09_Xess_XSA-3S1000/System09_Xess_XSA-3S1000.vhd (revision 29)
@@ -138,7 +138,7 @@
library unisim;
use unisim.vcomponents.all;
-entity My_System09 is
+entity my_system09 is
port(
CLKA : in Std_Logic; -- 100MHz Clock input
SW2_N : in Std_logic; -- Master Reset input (active low)
@@ -213,7 +213,7 @@
-------------------------------------------------------------------------------
-- Architecture for System09
-------------------------------------------------------------------------------
-architecture rtl of My_System09 is
+architecture rtl of my_system09 is
-----------------------------------------------------------------------------
-- constants