URL
https://opencores.org/ocsvn/System09/System09/trunk
Subversion Repositories System09
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/
- from Rev 32 to Rev 33
- ↔ Reverse comparison
Rev 32 → Rev 33
/branches/mkfiles_rev1/rtl/System09_Digilent_3S500E/my_system09.xst
0,0 → 1,53
set -tmpdir "./xst/projnav.tmp" |
set -xsthdpdir "./xst" |
run |
-ifn my_system09.prj |
-ifmt mixed |
-ofn my_system09 |
-ofmt NGC |
-p xc3s500e-4-fg320 |
-top my_system09 |
-opt_mode Speed |
-opt_level 1 |
-iuc NO |
-lso my_system09.lso |
-keep_hierarchy NO |
-rtlview Yes |
-glob_opt AllClockNets |
-read_cores YES |
-write_timing_constraints NO |
-cross_clock_analysis NO |
-hierarchy_separator / |
-bus_delimiter <> |
-case maintain |
-slice_utilization_ratio 100 |
-verilog2001 YES |
-fsm_extract YES -fsm_encoding Auto |
-safe_implementation No |
-fsm_style lut |
-ram_extract Yes |
-ram_style Auto |
-rom_extract Yes |
-mux_style Auto |
-decoder_extract YES |
-priority_extract YES |
-shreg_extract YES |
-shift_extract YES |
-xor_collapse YES |
-rom_style Auto |
-mux_extract YES |
-resource_sharing YES |
-mult_style auto |
-iobuf YES |
-max_fanout 500 |
-bufg 8 |
-register_duplication YES |
-register_balancing No |
-slice_packing YES |
-optimize_primitives NO |
-use_clock_enable Yes |
-use_sync_set Yes |
-use_sync_reset Yes |
-iob auto |
-equivalent_register_removal YES |
-slice_utilization_ratio_maxmargin 5 |
/branches/mkfiles_rev1/rtl/System09_Digilent_3S500E/my_system09.ise
Cannot display: file marked as a binary type.
svn:mime-type = application/octet-stream
branches/mkfiles_rev1/rtl/System09_Digilent_3S500E/my_system09.ise
Property changes :
Added: svn:mime-type
## -0,0 +1 ##
+application/octet-stream
\ No newline at end of property
Index: branches/mkfiles_rev1/rtl/System09_Digilent_3S500E/System09_Digilent_3S500E.vhd
===================================================================
--- branches/mkfiles_rev1/rtl/System09_Digilent_3S500E/System09_Digilent_3S500E.vhd (revision 32)
+++ branches/mkfiles_rev1/rtl/System09_Digilent_3S500E/System09_Digilent_3S500E.vhd (revision 33)
@@ -1,4 +1,4 @@
--- $Id: System09_Digilent_3S500E.vhd,v 1.3 2008-03-14 15:52:44 dilbert57 Exp $
+-- $Id: System09_Digilent_3S500E.vhd,v 1.3.2.1 2008-04-08 14:59:48 davidgb Exp $
--===========================================================================----
--
-- S Y N T H E Z I A B L E System09 - SOC.
@@ -88,7 +88,7 @@
use IEEE.STD_LOGIC_UNSIGNED.ALL;
use ieee.numeric_std.all;
-entity My_System09 is
+entity my_system09 is
port(
CLK_50MHZ : in Std_Logic; -- System Clock input
BTN_SOUTH : in Std_Logic;
@@ -111,12 +111,12 @@
-- LEDS & Switches
LED : out std_logic_vector(7 downto 0)
);
-end My_System09;
+end my_system09;
-------------------------------------------------------------------------------
-- Architecture for System09
-------------------------------------------------------------------------------
-architecture my_computer of My_System09 is
+architecture my_computer of my_system09 is
-----------------------------------------------------------------------------
-- constants
-----------------------------------------------------------------------------
@@ -330,9 +330,10 @@
addr : in std_logic;
data_in : in std_logic_vector(7 downto 0);
data_out : out std_logic_vector(7 downto 0);
- irq : out std_logic;
- timer_in : in std_logic;
- timer_out : out std_logic
+ irq : out std_logic
+ -- ;
+ -- timer_in : in std_logic;
+ -- timer_out : out std_logic
);
end component;
@@ -597,8 +598,9 @@
addr => cpu_addr(0),
data_in => cpu_data_out,
data_out => timer_data_out,
- irq => timer_irq,
- timer_in => CountL(5)
+ irq => timer_irq
+ -- ,
+ -- timer_in => CountL(5)
-- timer_out => timer_out
);
/branches/mkfiles_rev1/rtl/System09_Digilent_3S500E/my_system09.prj
0,0 → 1,17
vhdl work "../VHDL/ACIA_Clock.vhd" |
vhdl work "../Spartan3/keymap_rom_slice.vhd" |
vhdl work "../VHDL/ps2_keyboard.vhd" |
vhdl work "../VHDL/ACIA_TX.vhd" |
vhdl work "../VHDL/ACIA_RX.vhd" |
vhdl work "../Spartan3/ram2k_b16.vhd" |
vhdl work "../Spartan3/char_rom2k_b16.vhd" |
vhdl work "../VHDL/vdu8.vhd" |
vhdl work "../VHDL/trap.vhd" |
vhdl work "../VHDL/timer.vhd" |
vhdl work "../VHDL/pia_timer.vhd" |
vhdl work "../VHDL/keyboard.vhd" |
vhdl work "../VHDL/cpu09.vhd" |
vhdl work "../VHDL/ACIA_6850.vhd" |
vhdl work "../Spartan3/sys09bug_s3e_rom2k_b16.vhd" |
vhdl work "../Spartan3/ram32k_b16.vhd" |
vhdl work "System09_Digilent_3S500E.vhd" |
/branches/mkfiles_rev1/rtl/System09_Digilent_3S500E/Makefile
0,0 → 1,130
#=================================================================== |
# File: Makefile |
# Author: David Burnette |
# Created: July 5, 2007 |
# |
# Description: |
# Makefile to build the System09 by John Kent |
# |
# This makefile will build John Kent's entire System09 project |
# (RTL synthesis and monitor ROMs) and even download the final |
# bitstream to the prototype board. |
# |
# You can use Xilinx ISE interactively to add new RTL source files |
# to this project. |
# |
# Usage: |
# Use 'make help' to get a list of options. |
# |
# Dependencies: |
# Depends on makefile fragments in the 'MKFRAGS' directory. |
# |
# Revision History: |
# dgb 2007-07-05 Original version |
# |
# dgb 2008-04-07 Split out files into fragments. Modified |
# ROM source generation to be per src directory. |
# |
#=================================================================== |
|
MKFRAGS := ../../mkfiles |
export MKFRAGS |
|
#=================================================================== |
# User-modifiable variables |
# |
# This name must match the name of the design in Xilinx ISE (case |
# sensitive). |
DESIGN_NAME := my_system09 |
# |
# Constraint file (unfortunately it cannot be extracted from ISE) |
UCF_FILE := System09_Digilent_3S500E.ucf |
# |
# Technology family (unfortunately it cannot be extracted from ISE) |
FAMILY := spartan3 |
|
# List of ROM VHDL files |
roms: |
@$(MAKE) -C ../../src/sys09bug sys09s3e.vhd |
@$(MAKE) -C ../../src/Flex9 flex9cf8.vhd |
|
|
#=================================================================== |
# You should not need to edit anything below this line |
|
include ../../mkfiles/xilinx_rules.mk |
|
#=================================================================== |
# TARGETS |
|
all: roms bit |
|
roms: $(ROMFILES) |
|
debug_vars: |
@$(ECHO) "XST_FILE = '$(XST_FILE)'" |
@$(ECHO) "PRJ_FILE = '$(PRJ_FILE)'" |
@$(ECHO) "HDL_FILES = '$(HDL_FILES)'" |
@$(ECHO) "PART = '$(PART)'" |
@$(ECHO) "DEVICE = '$(DEVICE)'" |
@$(ECHO) "SPEED = '$(SPEED)'" |
@$(ECHO) "PACKAGE = '$(PACKAGE)'" |
@$(ECHO) "UCF_FILE = '$(UCF_FILE)'" |
@$(ECHO) "BSD_FILE = '$(BSD_FILE)'" |
@$(ECHO) "XSTHDPDIR = '$(XSTHDPDIR)'" |
@$(ECHO) "TMPDIR = '$(TMPDIR)'" |
|
bit: roms $(DESIGN_NAME).bit |
|
prom: $(DESIGN_NAME).mcs |
|
impact: $(DESIGN_NAME).bit |
@$(ECHO) |
@$(ECHO) "======= Downloading bitstream to XSA-3S1000 using Impact ============" |
-@$(RM) $(DESIGN_NAME)_impact.cmd |
@$(ECHO) "setMode -bscan" >>$(DESIGN_NAME)_impact.cmd |
@$(ECHO) "setCable -p auto" >>$(DESIGN_NAME)_impact.cmd |
@$(ECHO) "addDevice -p 1 -file $(BSD_FILE)" >>$(DESIGN_NAME)_impact.cmd |
@$(ECHO) "assignFile -p 1 -file $<" >>$(DESIGN_NAME)_impact.cmd |
@$(ECHO) "program -p 1" >>$(DESIGN_NAME)_impact.cmd |
@$(ECHO) "quit" >>$(DESIGN_NAME)_impact.cmd |
$(IMPACT) -batch $(DESIGN_NAME)_impact.cmd |
|
.PHONY: help |
help: |
@$(ECHO) "Use this Makefile to regenerate the entire System09 bitstream" |
@$(ECHO) "after modifying any of the source RTL or 6809 assembler code." |
@$(ECHO) "" |
@$(ECHO) "This makefile uses the following project files from the Xilinx ISE" |
@$(ECHO) " $(XST_FILE)" |
@$(ECHO) "" |
@$(ECHO) "You use Xilinx ISE interactively to add new RTL source files." |
@$(ECHO) "" |
@$(ECHO) " Availiable targets" |
@$(ECHO) |
@$(ECHO) " For building all or part of the system:" |
@$(ECHO) " roms - Run asm09 and then generate the VHDL RTL rom files" |
@$(ECHO) " bit - Rebuild the entire system and generate the bitstream file" |
@$(ECHO) " all - Rebuild everything" |
@$(ECHO) " prom - Rebuild the entire system and generate an MCS prom file" |
@$(ECHO) " exo - Rebuild the entire system and generate an EXO prom file" |
@$(ECHO) |
@$(ECHO) " For downloading the bitstream to the board:" |
@$(ECHO) " impact - Download the bitstream to the FPGA via iMPACT" |
@$(ECHO) |
@$(ECHO) " For project maintenance:" |
@$(ECHO) " help - Print this help text" |
@$(ECHO) " clean - Clean up the ISE files" |
@$(ECHO) "" |
|
.PHONY: clean |
clean: |
-$(MAKE) -C ../../src/sys09bug clean |
-$(MAKE) -C ../../src/Flex9 clean |
-$(RM) *.ncd *.ngc *.ngd *.twr *.bit *.mcs *.stx *.ucf.untf *.mrp |
-$(RM) *.ncl *.ngm *.prm *_pad.txt *.twx *.log *.syr *.par *.exo *.xpi |
-$(RM) *.cmd_log *.ngr *.bld *_summary.html *.nc1 *.pcf *.bgn |
-$(RM) *.pad *.placed_ncd_tracker *.routed_ncd_tracker *_pad.csv *.drc |
-$(RM) *.pad_txt $(DESIGN_NAME)_impact.cmd |
-$(RMDIR) _ngo _xmsgs |
|
/branches/mkfiles_rev1/rtl/System09_Digilent_3S500E/my_system09.lso
0,0 → 1,130
work |