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Rev 47 → Rev 48

/branches/mkfiles_rev1/src/boot/Makefile
7,7 → 7,7
# This makefile generates the S19 record file .S19 from the
# assembler source.
#
# This particular makefile handles generating FLEX bootstrap loader
# This particular makefile handles generating the FLEX bootstrap loader
#
# Usage:
# The targets generated by this makefile are:
18,13 → 18,10
#
# Target Descriptions:
# The first file listed is the source file passed to assembler.
# Remaining files are the dependencies. The option variables
# ADDRS, ENTITY and TOP_RAM are used by the s19tovhd utility
# to generate the VHDL file.
# Remaining files are the dependencies.
#
# Dependencies:
# This makefile depends on def_rules.mk and the top-level
# ram model file mon_rom_vhd.
# This makefile depends on def_rules.mk.
#
# Revision History:
# dgb 2008-04-07 Original version
/branches/mkfiles_rev1/src/Noice/MON6809.S19 File deleted
/branches/mkfiles_rev1/src/Noice/MON6809_b16.vhd File deleted
/branches/mkfiles_rev1/src/Noice/MON6809.LST File deleted
/branches/mkfiles_rev1/src/Noice/MON6809_b4_0.vhd File deleted
/branches/mkfiles_rev1/src/Noice/MON6809_b4_1.vhd File deleted
/branches/mkfiles_rev1/src/Noice/MON6809_b4_2.vhd File deleted
/branches/mkfiles_rev1/src/Noice/MON6809_b4_3.vhd File deleted
/branches/mkfiles_rev1/src/Noice/noice_rom_vhd
0,0 → 1,101
--
-- NOICE6809 Monitor Program
-- v1.0 - 21 November 2006 - John Knet
--
-- v1.1 - 22 december 2006 - John Kent
-- made into 4K ROM/RAM.
--
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
library unisim;
use unisim.vcomponents.all;
 
entity mon_rom is
Port (
clk : in std_logic;
rst : in std_logic;
cs : in std_logic;
rw : in std_logic;
addr : in std_logic_vector (11 downto 0);
rdata : out std_logic_vector (7 downto 0);
wdata : in std_logic_vector (7 downto 0)
);
end mon_rom;
 
architecture rtl of mon_rom is
 
signal we : std_logic;
signal cs0 : std_logic;
signal cs1 : std_logic;
signal dp0 : std_logic;
signal dp1 : std_logic;
signal rdata0 : std_logic_vector(7 downto 0);
signal rdata1 : std_logic_vector(7 downto 0);
 
component NOICE6809_F000
Port (
clk : in std_logic;
rst : in std_logic;
cs : in std_logic;
rw : in std_logic;
addr : in std_logic_vector (10 downto 0);
rdata : out std_logic_vector (7 downto 0);
wdata : in std_logic_vector (7 downto 0)
);
end component;
 
component NOICE6809_F800
Port (
clk : in std_logic;
rst : in std_logic;
cs : in std_logic;
rw : in std_logic;
addr : in std_logic_vector (10 downto 0);
rdata : out std_logic_vector (7 downto 0);
wdata : in std_logic_vector (7 downto 0)
);
end component;
 
begin
 
addr_f000 : NOICE6809_F000 port map (
clk => clk,
rst => rst,
cs => cs0,
rw => rw,
addr => addr(10 downto 0),
wdata => wdata,
rdata => rdata0
);
 
addr_f800 : NOICE6809_F800 port map (
clk => clk,
rst => rst,
cs => cs1,
rw => rw,
addr => addr(10 downto 0),
wdata => wdata,
rdata => rdata1
);
 
my_mon : process ( rw, addr, cs, rdata0, rdata1 )
begin
we <= not rw;
case addr(11) is
when '0' =>
cs0 <= cs;
cs1 <= '0';
rdata <= rdata0;
when '1' =>
cs0 <= '0';
cs1 <= cs;
rdata <= rdata1;
when others =>
null;
end case;
end process;
 
end architecture rtl;
 
/branches/mkfiles_rev1/src/Noice/Makefile
0,0 → 1,56
#-----------------------------------------------------------------
# File: Makefile
# Author: David Burnette
# Date: April 7, 2008
#
# Description:
# This makefile generates a VHDL file from assembler source.
# A translate rule in mktargets.mk handles compiling the .asm
# into a S19 record file (.S19) and then running s19tovhd to
# generate a VHDL file with SPARTAN3 block rams with INIT generics
# containing the binary data.
#
# This particular makefile handles generating the Noice debug rom.
#
# Usage:
# This make file is called recursively by the board-specific
# makefiles in the 'rtl' directory. The targets generated by
# this makefile are:
#
# make - makes all variants
# make all - makes all variants
# make MON6809.vhd - make the Noice rom
#
# Target Descriptions:
# The first file listed is the source file passed to assembler.
# Remaining files are the dependencies. The option variables
# ADDRS, ENTITY and TOP_RAM are used by the s19tovhd utility
# to generate the VHDL file.
#
# Dependencies:
# This makefile depends on def_rules.mk and the top-level
# ram model file mon_rom_vhd.
#
# Revision History:
# dgb 2008-04-07 Original version
#
#-----------------------------------------------------------------
 
ifeq "$(MKFRAGS)" ""
MKFRAGS := ../../mkfiles
endif
 
include $(MKFRAGS)/def_rules.mk
 
all: MON6809.vhd
 
MON6809.vhd: MON6809.ASM
MON6809.vhd: ADDRS=F000 F800
MON6809.vhd: ENTITY=NOICE6809
MON6809.vhd: TOP_RAM=noice_rom_vhd
 
.PHONY: clean
clean:
-$(RM) *.S19
-$(RM) *.lst
-$(RM) *.vhd

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