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Rev 26 → Rev 66

/testbench1.vhd
0,0 → 1,177
--===========================================================================----
--
-- T E S T B E N C H tesetbench1 - CPU09 Testbench.
--
-- www.OpenCores.Org - September 2003
-- This core adheres to the GNU public license
--
-- File name : Testbench1.vhd
--
-- Purpose : cpu09 Microprocessor Test Bench 1
-- Contains ROM to print out "Hello World"
-- on a none existant Uart
--
-- Dependencies : ieee.Std_Logic_1164
-- ieee.std_logic_unsigned
-- ieee.std_logic_arith
-- ieee.numeric_std
--
-- Uses : cpu09 (cpu09.vhd) CPU core
--
-- Author : John E. Kent
-- dilbert57@opencores.org
--
--===========================================================================----
--
-- Revision History:
--===========================================================================--
--
-- Version 0.1 - 12st April 2003 - John Kent
-- First version
--
-- Version 1.0- 6 Sep 2003 - John Kent
-- Initial release to Open Cores
--
-- Version 1.1 - 25th Jan 2004 - John Kent
-- removed "test_alu" and "test_cc"
--
--===========================================================================--
 
library ieee;
use ieee.std_logic_1164.all;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
use ieee.numeric_std.all;
-- library work;
-- use work.UART_Def.all;
-- use work.typedefines.all;
-- use work.memory.all;
 
entity my_testbench is
end my_testbench;
 
-------------------------------------------------------------------------------
-- Architecture for memio Controller Unit
-------------------------------------------------------------------------------
architecture behavior of my_testbench is
-----------------------------------------------------------------------------
-- Signals
-----------------------------------------------------------------------------
-- CPU Interface signals
signal SysClk : Std_Logic;
signal cpu_reset : Std_Logic;
signal cpu_rw : Std_Logic;
signal cpu_vma : Std_Logic;
signal cpu_addr : Std_Logic_Vector(15 downto 0);
signal cpu_data_in : Std_Logic_Vector(7 downto 0);
signal cpu_data_out: Std_Logic_Vector(7 downto 0);
signal cpu_irq : Std_Logic;
signal cpu_nmi : std_logic;
signal cpu_firq : Std_Logic;
 
 
constant width : integer := 8;
constant memsize : integer := 64;
 
type rom_array is array(0 to memsize-1) of std_logic_vector(width-1 downto 0);
 
constant rom_data : rom_array :=
(
"10001110", "11111000", "00101000", -- F800 - 8E F828 RESET LDX #MSG
"10000110", "00010001", -- F803 - 86 11 LDA #$11
"10110111", "11100000", "00000100", -- F805 - B7 E004 STA UARTCR
"10110110", "11100000", "00000100", -- F808 - B6 E004 POLL1 LDA UARTCR
"10000101", "00000010", -- F80B - 85 02 BITA #TXBE
"00100110", "11111001", -- F80D - 26 F9 BNE POLL1
"10100110", "10000000", -- F80F - A6 80 LDA ,X+
"00100111", "00000110", -- F811 - 27 06 BEQ POLL2
"00010010", -- F813 - 12 NOP
"10110111", "11100000", "00000101", -- F814 - B7 E005 STA UARTDR
"00100110", "11101111", -- F817 - 26 EF BNE POLL1
"10110110", "11100000", "00000100", -- F819 - B6 E004 POLL2 LDA UARTCR
"10000101", "00000001", -- F81C - 85 01 BITA #RXBF
"00100111", "11111001", -- F81E - 27 F9 BEQ POLL2
"10110110", "11100000", "00000101", -- F820 - B6 E005 LDA UARTDR
"01111110", "11111000", "00000000", -- F823 - 7E F800 JMP RESET
"00000000", "00000000", -- F826 - 00 00 fcb $00,$00
"01001000", "01100101", "01101100", -- F828 - 48 65 6c MSG FCC "Hel"
"01101100", "01101111", "00100000", -- F82B - 6c 6f 20 FCC "lo "
"01010111", "01101111", "01110010", -- F82E - 57 6f 72 FCC "Wor"
"01101100", "01100100", -- F831 - 6c 64 FCC "ld"
"00001010", "00001101", "00000000", -- F833 - 0a 0d 00 FCB LF,CR,NULL
"00000000", "00000000", -- F836 - 00 00 fcb null,null
"11111000", "00000000", -- F838 - F8 00 fdb $F800 ; Timer irq
"11111000", "00000000", -- F83A - F8 00 fdb $F800 ; Ext IRQ
"11111000", "00000000", -- F83C - F8 00 fcb $F800 ; SWI
"11111000", "00000000" -- F83E - F8 00 fdb $F800 ; Reset
);
 
component cpu09
port (
clk: in std_logic;
rst: in std_logic;
rw: out std_logic; -- Asynchronous memory interface
vma: out std_logic;
address: out std_logic_vector(15 downto 0);
data_in: in std_logic_vector(7 downto 0);
data_out: out std_logic_vector(7 downto 0);
halt: in std_logic;
hold: in std_logic;
irq: in std_logic;
nmi: in std_logic;
firq: in std_logic
);
end component cpu09;
 
 
begin
cpu : cpu09 port map (
clk => SysClk,
rst => cpu_reset,
rw => cpu_rw,
vma => cpu_vma,
address => cpu_addr(15 downto 0),
data_in => cpu_data_in,
data_out => cpu_data_out,
halt => '0',
hold => '0',
irq => cpu_irq,
nmi => cpu_nmi,
firq => cpu_firq
);
 
-- *** Test Bench - User Defined Section ***
tb : PROCESS
variable count : integer;
BEGIN
 
cpu_reset <= '0';
SysClk <= '0';
cpu_irq <= '0';
cpu_nmi <= '0';
cpu_firq <= '0';
 
for count in 0 to 512 loop
SysClk <= '0';
if count = 0 then
cpu_reset <= '1';
elsif count = 1 then
cpu_reset <= '0';
end if;
wait for 100 ns;
SysClk <= '1';
wait for 100 ns;
end loop;
 
wait; -- will wait forever
END PROCESS;
-- *** End Test Bench - User Defined Section ***
 
 
rom : PROCESS( cpu_addr )
begin
cpu_data_in <= rom_data(conv_integer(cpu_addr(5 downto 0)));
end process;
 
end behavior; --===================== End of architecture =======================--
 
/testbench2.vhd
0,0 → 1,301
--===========================================================================----
--
-- T E S T B E N C H tesetbench2 - CPU09 Testbench.
--
-- www.OpenCores.Org - September 2003
-- This core adheres to the GNU public license
--
-- File name : Testbench2.vhd
--
-- Purpose : cpu09 Microprocessor Test Bench 2
-- Contains ROM to read sector from
-- a none existant Compact Flash module
--
-- Dependencies : ieee.Std_Logic_1164
-- ieee.std_logic_unsigned
-- ieee.std_logic_arith
-- ieee.numeric_std
--
-- Uses : cpu09 (cpu09.vhd) CPU core
--
-- Author : John E. Kent
-- dilbert57@opencores.org
--
--===========================================================================----
--
-- Revision History:
--===========================================================================--
--
-- Version 0.1 - 12st April 2003 - John Kent
-- First version
--
-- Version 1.0- 6 Sep 2003 - John Kent
-- Initial release to Open Cores
--
-- Version 1.1 - 25th Jan 2004 - John Kent
-- removed "test_alu" and "test_cc"
--
--===========================================================================--
 
library ieee;
use ieee.std_logic_1164.all;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
use ieee.numeric_std.all;
 
entity my_testbench2 is
end my_testbench2;
 
-------------------------------------------------------------------------------
-- Architecture for memio Controller Unit
-------------------------------------------------------------------------------
architecture behavior of my_testbench2 is
-----------------------------------------------------------------------------
-- Signals
-----------------------------------------------------------------------------
 
-- CPU Interface signals
signal SysClk : Std_Logic;
signal cpu_reset : Std_Logic;
signal cpu_rw : Std_Logic;
signal cpu_vma : Std_Logic;
signal cpu_addr : Std_Logic_Vector(15 downto 0);
signal cpu_data_in : Std_Logic_Vector(7 downto 0);
signal cpu_data_out: Std_Logic_Vector(7 downto 0);
signal cpu_irq : Std_Logic;
signal cpu_nmi : Std_Logic;
signal cpu_firq : std_logic;
 
constant width : integer := 8;
constant memsize : integer := 128;
 
type rom_array is array(0 to memsize-1) of std_logic_vector(width-1 downto 0);
 
constant rom_data : rom_array :=
(
"00010000", -- $F800 LDS #$F878 (Point to dummy return to test stack)
"11001110",
"11111000",
"01111000",
"10000110", -- $F804 LDA #$E0 *** START
"11100000",
"00011111", -- $F806 TFR A,DPR
"10001011",
---------------------------
-- "10001101", -- $F80E BSR WAITRDY $F86A
-- "01100000",
"10001101", -- $F808 BSR $F874 -- test sub call
"01101010",
---------------------------
"10000110", -- $F80A LDA #$E0
"11100000",
"10010111", -- $F80C STA <$E016
"00010110",
---------------------------
-- "10001101", -- $F80E BSR WAITRDY $F86A
-- "01011010",
"10001101", -- $F80E BSR $F810
"00000000",
--------------------------
"10000110", -- $F810 LDA #$01
"00000001",
"10010111", -- $F812 STA <$E011
"00010001",
"10000110", -- $F814 LDA #$EF
"11101111",
"10010111", -- $F816 STA <$E017
"00010111",
--------------------------
-- "10001101", -- $F818 BSR WAITRDY $F86A
-- "01010000",
"10001101", -- $F818 BSR $F816
"00000000",
--------------------------
"00010000", -- $F81A LDY #$F800
"10001110",
"11111000",
"00000000",
"11000110", -- $F81E LDB #$7C
"01111100",
"10000110", -- $F820 LDA #$01 *** RDLP1
"00000001",
"10010111", -- $F822 STA <$E012
"00010010",
"11010111", -- $F824 STB <$E013
"00010011",
"10000110", -- $F826 LDA #$F4
"11110100",
"10010111", -- $F828 STA <$E014
"00010100",
"01001111", -- $F82A CLRA
"10010111", -- $F82B STA <$E015
"00010101",
"10001110", -- $F82D LDX #512
"00000010",
"00000000",
"10000110", -- $F830 LDA #$20
"00100000",
"10010111", -- $F832 STA <$E017
"00010111",
--------------------------
-- "10001101", -- $F834 BSR WAITRDY $F86A
-- "00110100",
"10001101", -- $F834 BSR *
"00000000",
--------------------------
"10010110", -- $F836 LDA <$E017 *** WAITDRQ
"00010111",
"10000101", -- $F838 BITA #$08
"00001000",
"00100111", -- $F83A BEQ WAITDRQ
"11111010",
"10010110", -- $F83C LDA <$E010
"00010000",
"10100111", -- $F83E STA ,Y+
"10100000",
"00110000", -- $F840 LEAX -1,X
"00011111",
"10001100", -- $F842 CMPX #$0000
"00000000",
"00000000",
"00100110", -- $F845 BNE RDLP2
"11110011",
--------------------------
-- "10001101", -- $F847 BSR WAITRDY $F86A
-- "00100001",
"10001101", -- $F847 BSR $F841
"00000000",
--------------------------
"01011100", -- $F849 INCB
"11000001", -- $F84A CMPB #$80
"10000000",
"00100110", -- $F84C BNE RDLP1
"11010110",
"10001110", -- $F84E LDX #$FF97
"11111111",
"10010111",
"00010000", -- $F851 LDY #$F000
"10001110",
"11110000",
"00000000",
"11000110", -- $F855 LDB #$61
"01100001",
"10100110", -- $F857 LDA 0,X+ *** MOVELP
"10000000",
"10100111", -- $F859 STA 0,Y+
"10100000",
"01011010", -- $F85B DECB
----------------------------
-- "00100110", -- $F85C BNE MOVELP
-- "11111001",
"00100110", --$F85C BNE $F861
"00000011",
----------------------------
"01111110", -- $F85E JMP $F000
"11110000",
"00000000",
"00001111", -- $F861 CLR <$E030
"00110000",
"01001111", -- $F863 CLRA
"00011111", -- $F864 TFR A,DPR
"10001011",
"01101110", -- $F866 JMP [$FFFE]
"10011111",
"11111111",
"11111110",
--
-- Wait for Ready
--
"10010110", -- $F86A LDA <$E017 *** WAITRDY
"00010111",
"00101011", -- $F86C BMI WAITRDY
"11111100",
"10010110", -- $F86E LDA <$E017
"00010111",
"10000101", -- $F870 BITA #$40
"01000000",
"00100111", -- $F872 BNE WAITRQY
"11110110",
"00111001", -- $F874 RTS
"00010010", -- $F875 NOP
"11111000", -- $F876 FDB $F80A -- dummy sub return
"00001010",
"11111000", -- $F878 FDB $F800
"00000000",
"11111000", -- $F87A FDB $F800
"00000000",
"11111000", -- $F87C FDB $F800
"00000000",
"11111000", -- $F87E FDB $F800
"00000000"
);
 
component cpu09
port (
clk: in std_logic;
rst: in std_logic;
rw: out std_logic; -- Asynchronous memory interface
vma: out std_logic;
address: out std_logic_vector(15 downto 0);
data_in: in std_logic_vector(7 downto 0);
data_out: out std_logic_vector(7 downto 0);
halt: in std_logic;
hold: in std_logic;
irq: in std_logic;
nmi: in std_logic;
firq: in std_logic
);
end component cpu09;
 
 
begin
cpu : cpu09 port map (
clk => SysClk,
rst => cpu_reset,
rw => cpu_rw,
vma => cpu_vma,
address => cpu_addr(15 downto 0),
data_in => cpu_data_in,
data_out => cpu_data_out,
halt => '0',
hold => '0',
irq => cpu_irq,
nmi => cpu_nmi,
firq => cpu_firq
);
 
-- *** Test Bench - User Defined Section ***
tb : PROCESS
variable count : integer;
BEGIN
 
cpu_reset <= '0';
SysClk <= '0';
cpu_irq <= '0';
cpu_nmi <= '0';
cpu_firq <= '0';
 
for count in 0 to 512 loop
SysClk <= '0';
if count = 0 then
cpu_reset <= '1';
elsif count = 1 then
cpu_reset <= '0';
end if;
wait for 100 ns;
SysClk <= '1';
wait for 100 ns;
end loop;
 
wait; -- will wait forever
END PROCESS;
-- *** End Test Bench - User Defined Section ***
 
 
rom : PROCESS( cpu_addr )
begin
cpu_data_in <= rom_data(conv_integer(cpu_addr(6 downto 0)));
end process;
 
end behavior; --===================== End of architecture =======================--
 
/ACIA_tb.vhd
0,0 → 1,197
--===========================================================================--
--
-- ACIA 6850 Test Bench
--
--
-- John Kent 6th February 2007
--
--
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
use ieee.numeric_std.all;
 
entity ACIA_6850_testbench is
end ACIA_6850_testbench;
 
-------------------------------------------------------------------------------
-- Architecture for ACIA 6850 Unit
-------------------------------------------------------------------------------
architecture behavior of ACIA_6850_testbench is
-----------------------------------------------------------------------------
-- Signals
-----------------------------------------------------------------------------
-- CPU Interface signals
signal SysClk : Std_Logic;
signal uart_reset : Std_Logic;
signal uart_cs : Std_Logic;
signal uart_rw : Std_Logic;
signal uart_addr : Std_Logic;
signal uart_data_in : Std_Logic_Vector(7 downto 0);
signal uart_data_out: Std_Logic_Vector(7 downto 0);
signal uart_irq : Std_Logic;
signal rxclk : Std_Logic;
signal txclk : Std_Logic;
signal rxbit : Std_Logic;
signal txbit : Std_Logic;
signal dcd_n : Std_Logic;
signal cts_n : Std_Logic;
signal rts_n : Std_Logic;
 
-----------------------------------------------------------------
--
-- ACIA 6850 UART
--
-----------------------------------------------------------------
component ACIA_6850
port (
--
-- CPU signals
--
clk : in Std_Logic; -- System Clock
rst : in Std_Logic; -- Reset input (active high)
cs : in Std_Logic; -- miniUART Chip Select
rw : in Std_Logic; -- Read / Not Write
irq : out Std_Logic; -- Interrupt
Addr : in Std_Logic; -- Register Select
DataIn : in Std_Logic_Vector(7 downto 0); -- Data Bus In
DataOut : out Std_Logic_Vector(7 downto 0); -- Data Bus Out
--
-- Uart Signals
--
RxC : in Std_Logic; -- Receive Baud Clock
TxC : in Std_Logic; -- Transmit Baud Clock
RxD : in Std_Logic; -- Receive Data
TxD : out Std_Logic; -- Transmit Data
DCD_n : in Std_Logic; -- Data Carrier Detect
CTS_n : in Std_Logic; -- Clear To Send
RTS_n : out Std_Logic ); -- Request To send
end component; --================== End of entity ==============================--
 
begin
 
-----------------------------------------------------------------------------
-- Instantiation of internal components
-----------------------------------------------------------------------------
 
my_acia : ACIA_6850 port map (
clk => SysClk,
rst => uart_reset,
cs => uart_cs,
rw => uart_rw,
Irq => uart_irq,
Addr => uart_addr,
Datain => uart_data_in,
DataOut => uart_data_out,
RxC => rxclk,
TxC => txclk,
RxD => rxbit,
TxD => txbit,
DCD_n => dcd_n,
CTS_n => cts_n,
RTS_n => rts_n
);
 
 
-- *** Test Bench - User Defined Section ***
tb : PROCESS
variable count : integer;
BEGIN
 
cts_n <= '0';
dcd_n <= '0';
 
for count in 0 to 4096 loop
if (count mod 16) = 0 then
rxclk <= '1';
txclk <= '1';
elsif (count mod 16) = 8 then
rxclk <= '0';
txclk <= '0';
end if;
 
case count is
when 0 =>
uart_reset <= '1';
uart_cs <= '0';
uart_rw <= '1';
uart_addr <= '0';
uart_data_in <= "00000000";
rxbit <= '1';
when 1 =>
uart_reset <= '0';
when 3 =>
uart_cs <= '1';
uart_rw <= '0'; -- write control
uart_addr <= '0';
uart_data_in <= "00010001";
when 4 =>
uart_cs <= '0';
uart_rw <= '1';
uart_addr <= '0';
uart_data_in <= "00000000";
when 5 =>
uart_cs <= '1';
uart_rw <= '0'; -- write data
uart_addr <= '1';
uart_data_in <= "01010101";
when 6 =>
uart_cs <= '0';
uart_rw <= '1';
uart_addr <= '1';
uart_data_in <= "00000000";
when 256 =>
rxbit <= '0'; -- start
when 512 =>
rxbit <= '1'; -- bit 0
when 768 =>
rxbit <= '0'; -- bit 1
when 1024 =>
rxbit <= '1'; -- bit 2
when 1280 =>
rxbit <= '1'; -- bit3
when 1536 =>
rxbit <= '0'; -- bit 4
when 1792 =>
rxbit <= '0'; -- bit 5
when 2048 =>
rxbit <= '1'; -- bit 6
when 2304 =>
rxbit <= '0'; -- bit 7
when 2560 =>
rxbit <= '1'; -- stop 1
when 2816 =>
rxbit <= '1'; -- stop 2
when 3100 =>
uart_cs <= '1';
uart_rw <= '1'; -- read control
uart_addr <= '0';
when 3101 =>
uart_cs <= '0';
uart_rw <= '1';
uart_addr <= '0';
when 3102 =>
uart_cs <= '1';
uart_rw <= '1'; -- read data
uart_addr <= '1';
when 3103 =>
uart_cs <= '0';
uart_rw <= '1';
uart_addr <= '1';
when others =>
null;
end case;
SysClk <= '1';
wait for 40 ns;
SysClk <= '0';
wait for 40 ns;
end loop;
 
wait; -- will wait forever
END PROCESS;
-- *** End Test Bench - User Defined Section ***
 
end behavior; --===================== End of architecture =======================--
 
/testbench3.vhd
0,0 → 1,187
--===========================================================================----
--
-- T E S T B E N C H tesetbench3 - CPU09 Testbench.
--
-- www.OpenCores.Org - September 2003
-- This core adheres to the GNU public license
--
-- File name : Testbench3.vhd
--
-- Purpose : cpu09 Microprocessor Test Bench 3
-- Contains ROM to test interrupts
--
-- Dependencies : ieee.Std_Logic_1164
-- ieee.std_logic_unsigned
-- ieee.std_logic_arith
-- ieee.numeric_std
--
-- Uses : cpu09 (cpu09.vhd) CPU core
--
-- Author : John E. Kent
-- dilbert57@opencores.org
--
--===========================================================================----
--
-- Revision History:
--===========================================================================--
--
-- Version 0.1 - 12 Apr 2003 - John Kent
-- First version
--
-- Version 1.0 - 6 Sep 2003 - John Kent
-- Initial release to Open Cores
--
-- Version 1.1 - 26 Feb 2004 - John kent
-- removed test_alu and test_cc signals from
-- CPU component.
--===========================================================================--
 
library ieee;
use ieee.std_logic_1164.all;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
use ieee.numeric_std.all;
 
entity my_testbench3 is
end my_testbench3;
 
-------------------------------------------------------------------------------
-- Architecture for memio Controller Unit
-------------------------------------------------------------------------------
architecture behavior of my_testbench3 is
-----------------------------------------------------------------------------
-- Signals
-----------------------------------------------------------------------------
signal cpu_irq : std_Logic;
signal cpu_firq : std_logic;
signal cpu_nmi : std_logic;
 
-- CPU Interface signals
signal SysClk : Std_Logic;
signal cpu_reset : Std_Logic;
signal cpu_rw : Std_Logic;
signal cpu_vma : Std_Logic;
signal cpu_addr : Std_Logic_Vector(15 downto 0);
signal cpu_data_in : Std_Logic_Vector(7 downto 0);
signal cpu_data_out: Std_Logic_Vector(7 downto 0);
 
constant width : integer := 8;
constant memsize : integer := 64;
 
type rom_array is array(0 to memsize-1) of std_logic_vector(width-1 downto 0);
 
constant rom_data : rom_array :=
(
"00010000", "11001110", "11111000", "00110000", -- F800 - 10CE F830 RET1 LDS #STACK
"00111111", -- F804 - 3F SWI
"00010000", "00111111", -- F805 - 103F SWIVEC SWI2
"00010001", "00111111", -- F807 - 113F SWI2VEC SWI3
"00111011", -- F809 - 3B SWI3VEC RTI
"00100000", "11111110", -- F80A - 20 FE BRA *
"10110001", -- F80C - B1 STACK3 FCB $B1 ; CC
"00110010", -- F80D - 32 FCB $32 ; ACCA
"00110011", -- F8OE - 33 FCB $33 ; ACCB
"00110100", -- F8OF - 34 FCB $34 ; DPR
"00110101", "00110110", -- F810 - 3536 FDB $3536 ; IX
"00110111", "00111000", -- F812 - 3738 FDB $3738 ; IY
"00111001", "00111010", -- F814 - 393A FDB $393A ; UP
"11111000", "00001001", -- F816 - F809 FDB SWI3VEC ; PC
"10100001", -- F818 - A1 STACK2 FCB $A1 ; CC
"00100010", -- F819 - 22 FCB $22 ; ACCA
"00100011", -- F81A - 23 FCB $23 ; ACCB
"00100100", -- F81B - 24 FCB $24 ; DPR
"00100101", "00100110", -- F81C - 2526 FDB $2526 ; IX
"00100111", "00101000", -- F81E - 2728 FDB $2728 ; IY
"00101001", "00101010", -- F820 - 292A FDB $292A ; UP
"11111000", "00001001", -- F822 - F809 FDB SWI3VEC ; PC
"10010001", -- F824 - 91 STACK1 FCB $91 ; CC
"00010010", -- F825 - 12 FCB $12 ; ACCA
"00010011", -- F826 - 13 FCB $13 ; ACCB
"00010100", -- F827 - 14 FCB $14 ; DPR
"00010101", "00010110", -- F828 - 1516 FDB $1516 ; IX
"00010111", "00011000", -- F82A - 1718 FDB $1718 ; IY
"00011001", "00011010", -- F82C - 191A FDB $191A ; UP
"11111000", "00000000", -- F82E - F800 FDB RESET ; PC
-- F830 STACK EQU *
--
-- Interrupt Cectors Start Here
--
"11111000", "00000000", -- F830 - F800 FDB RESET ; RESV
"11111000", "00001001", -- F832 - F809 FDB SWIVEC3 ; SWI3
"11111000", "00000111", -- F834 - F807 FDB SWIVEC2 ; SWI2
"11111000", "00000000", -- F836 - F800 fdb RESET ; FIRQ
"11111000", "00000000", -- F838 - F800 fdb RESET ; IRQ
"11111000", "00000101", -- F83A - F805 fdb SWIVEC ; SWI
"11111000", "00000000", -- F83C - F800 fcb RESET ; NMI
"11111000", "00000000" -- F83E - F800 fdb RESET ; Reset
);
 
component cpu09
port (
clk: in std_logic;
rst: in std_logic;
rw: out std_logic; -- Asynchronous memory interface
vma: out std_logic;
address: out std_logic_vector(15 downto 0);
data_in: in std_logic_vector(7 downto 0);
data_out: out std_logic_vector(7 downto 0);
halt: in std_logic;
hold: in std_logic;
irq: in std_logic;
nmi: in std_logic;
firq: in std_logic
);
end component cpu09;
 
 
begin
cpu : cpu09 port map (
clk => SysClk,
rst => cpu_reset,
rw => cpu_rw,
vma => cpu_vma,
address => cpu_addr(15 downto 0),
data_in => cpu_data_in,
data_out => cpu_data_out,
halt => '0',
hold => '0',
irq => cpu_irq,
nmi => cpu_nmi,
firq => cpu_firq
);
 
-- *** Test Bench - User Defined Section ***
tb : PROCESS
variable count : integer;
BEGIN
 
cpu_reset <= '0';
SysClk <= '0';
cpu_irq <= '0';
cpu_nmi <= '0';
cpu_firq <= '0';
 
for count in 0 to 512 loop
SysClk <= '0';
if count = 0 then
cpu_reset <= '1';
elsif count = 1 then
cpu_reset <= '0';
end if;
wait for 100 ns;
SysClk <= '1';
wait for 100 ns;
end loop;
 
wait; -- will wait forever
END PROCESS;
-- *** End Test Bench - User Defined Section ***
 
 
rom : PROCESS( cpu_addr )
begin
cpu_data_in <= rom_data(conv_integer(cpu_addr(5 downto 0)));
end process;
 
end behavior; --===================== End of architecture =======================--
 
/testbench4.vhd
0,0 → 1,158
--===========================================================================--
--
-- MC6809 Microprocessor Test Bench 4
-- Test Software - SBUG ROM
--
--
-- John Kent 12st April 2003
--
-- Version 1.1 - 25th Jan 2004 - John Kent
-- removed "test_alu" and "test_cc"
--
--
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use IEEE.STD_LOGIC_ARITH.ALL;
use ieee.numeric_std.all;
 
entity my_testbench is
end my_testbench;
 
-------------------------------------------------------------------------------
-- Architecture for memio Controller Unit
-------------------------------------------------------------------------------
architecture behavior of my_testbench is
-----------------------------------------------------------------------------
-- Signals
-----------------------------------------------------------------------------
signal cpu_irq : std_Logic;
signal cpu_firq : std_logic;
signal cpu_nmi : std_logic;
 
-- CPU Interface signals
signal SysClk : Std_Logic;
signal cpu_reset : Std_Logic;
signal cpu_rw : Std_Logic;
signal cpu_vma : Std_Logic;
signal cpu_addr : Std_Logic_Vector(15 downto 0);
signal cpu_data_in : Std_Logic_Vector(7 downto 0);
signal cpu_data_out: Std_Logic_Vector(7 downto 0);
signal cpu_halt : Std_logic;
signal cpu_hold : Std_logic;
signal rom_data_out: Std_Logic_Vector(7 downto 0);
signal ram_data_out: Std_Logic_Vector(7 downto 0);
signal ram_cs : Std_Logic;
component cpu09
port (
clk: in std_logic;
rst: in std_logic;
rw: out std_logic; -- Asynchronous memory interface
vma: out std_logic;
address: out std_logic_vector(15 downto 0);
data_in: in std_logic_vector(7 downto 0);
data_out: out std_logic_vector(7 downto 0);
halt: in std_logic;
hold: in std_logic;
irq: in std_logic;
nmi: in std_logic;
firq: in std_logic
);
end component;
 
 
component sbug_rom
Port (
MEMclk : in std_logic;
MEMaddr : in std_logic_vector (10 downto 0);
MEMrdata : out std_logic_vector (7 downto 0)
);
end component;
 
component block_ram
Port (
MEMclk : in std_logic;
MEMcs : in std_logic;
MEMrw : in std_logic;
MEMaddr : in std_logic_vector (10 downto 0);
MEMrdata : out std_logic_vector (7 downto 0);
MEMwdata : in std_logic_vector (7 downto 0)
);
end component;
 
begin
my_cpu : cpu09 port map (
clk => SysClk,
rst => cpu_reset,
rw => cpu_rw,
vma => cpu_vma,
address => cpu_addr(15 downto 0),
data_in => cpu_data_in,
data_out => cpu_data_out,
halt => cpu_halt,
hold => cpu_hold,
irq => cpu_irq,
nmi => cpu_nmi,
firq => cpu_firq
);
 
 
my_ram : block_ram port map (
MEMclk => SysClk,
MEMcs => ram_cs,
MEMrw => cpu_rw,
MEMaddr => cpu_addr(10 downto 0),
MEMrdata => ram_data_out,
MEMwdata => cpu_data_out
);
 
my_rom : sbug_rom port map (
MEMclk => SysClk,
MEMaddr => cpu_addr(10 downto 0),
MEMrdata => rom_data_out
);
 
-- *** Test Bench - User Defined Section ***
tb : PROCESS
variable count : integer;
BEGIN
 
cpu_reset <= '0';
SysClk <= '0';
cpu_irq <= '0';
cpu_nmi <= '0';
cpu_firq <= '0';
cpu_halt <= '0';
cpu_hold <= '0';
 
for count in 0 to 512 loop
SysClk <= '0';
if count = 0 then
cpu_reset <= '1';
elsif count = 1 then
cpu_reset <= '0';
end if;
wait for 100 ns;
SysClk <= '1';
wait for 100 ns;
end loop;
 
wait; -- will wait forever
END PROCESS;
-- *** End Test Bench - User Defined Section ***
 
 
rom : PROCESS( cpu_addr, rom_data_out, ram_data_out )
begin
if( cpu_addr(15 downto 11) = "11111" ) then
cpu_data_in <= rom_data_out;
ram_cs <= '0';
else
cpu_data_in <= ram_data_out;
ram_cs <= '1';
end if;
end process;
 
end behavior; --===================== End of architecture =======================--
 
/testbench5.vhd
0,0 → 1,191
--===========================================================================----
--
-- T E S T B E N C H tesetbench3 - CPU09 Testbench.
--
-- www.OpenCores.Org - September 2003
-- This core adheres to the GNU public license
--
-- File name : Testbench5.vhd
--
-- Purpose : cpu09 Microprocessor Test Bench 3
-- Contains ROM to test interrupts
--
-- Dependencies : ieee.Std_Logic_1164
-- ieee.std_logic_unsigned
-- ieee.std_logic_arith
-- ieee.numeric_std
--
-- Uses : cpu09 (cpu09.vhd) CPU core
--
-- Author : John E. Kent
-- dilbert57@opencores.org
--
--===========================================================================----
--
-- Revision History:
--===========================================================================--
--
-- Version 0.1 - 12st April 2003 - John Kent
-- First version
--
-- Version 1.0 - 6 Sep 2003 - John Kent
-- Initial release to Open Cores
--
-- Version 1.1 - 25th Jan 2004 - John Kent
-- removed "test_alu" and "test_cc"
--
--===========================================================================--
 
library ieee;
use ieee.std_logic_1164.all;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
use ieee.numeric_std.all;
 
entity my_testbench5 is
end my_testbench5;
 
-------------------------------------------------------------------------------
-- Architecture for test bench for cpu09
-------------------------------------------------------------------------------
architecture behavior of my_testbench5 is
-----------------------------------------------------------------------------
-- Signals
-----------------------------------------------------------------------------
signal cpu_irq : std_Logic;
signal cpu_firq : std_logic;
signal cpu_nmi : std_logic;
 
-- CPU Interface signals
signal SysClk : Std_Logic;
signal cpu_reset : Std_Logic;
signal cpu_rw : Std_Logic;
signal cpu_vma : Std_Logic;
signal cpu_addr : Std_Logic_Vector(15 downto 0);
signal cpu_data_in : Std_Logic_Vector(7 downto 0);
signal cpu_data_out: Std_Logic_Vector(7 downto 0);
 
constant width : integer := 8;
constant memsize : integer := 128;
 
type rom_array is array(0 to memsize-1) of std_logic_vector(width-1 downto 0);
 
constant rom_data : rom_array :=
(
x"10", x"CE", x"F8", x"30", -- F800 - 10CE F830 RESET LDS #$F830
x"CE", x"20", x"00", -- F804 - CE 2000 LDU #$2000
x"8E", x"F8", x"02", -- F807 - 8E 5000 LDX #$F802
x"10", x"8E", x"80", x"00", -- F80A - 108E 8000 LDY #$8000
x"86", x"55", -- F80E - 86 55 LDA #$55
x"C6", x"F0", -- F810 - C6 F0 LDB #$F0
x"97", x"40", -- F812 - 97 40 STA <$40
x"B7", x"90", x"00", -- F814 - B7 9000 STA $9000
x"A7", x"09", -- F817 - A7 09 STA 9,X ($F80B)
x"A7", x"29", -- F819 - A7 29 STA 9,Y ($8009)
x"A7", x"49", -- F81B - A7 49 STA 9,U ($2009)
x"A7", x"69", -- F81D - A7 69 STA 9,S ($F839)
x"A7", x"80", -- F81F - A7 80 STA ,X+ ($F802)
x"A7", x"81", -- F821 - A7 81 STA ,X++ ($F803)
x"A7", x"91", -- F823 - A7 91 STA [,X++] ($2000)
x"A7", x"82", -- F825 - A7 82 STA ,-X ($F806)
x"A7", x"83", -- F827 - A7 83 STA ,--X ($F804)
x"A7", x"93", -- F829 - A7 93 STA [,--X] ($2000)
x"A7", x"84", -- F82B - A7 84 STA ,X ($F802)
x"A7", x"94", -- F82D - A7 94 STA [,X] ($F830)
x"A7", x"85", -- F82F - A7 85 STA B,X ($F7F2)
x"A7", x"95", -- F831 - A7 95 STA [B,X] ($01A7)
x"A7", x"86", -- F833 - A7 86 STA A,X ($F857)
x"A7", x"96", -- F835 - A7 96 STA [A,X] ($A78C)
x"A7", x"88", x"FF", -- F837 - A7 88 FF STA -1,X ($F831)
x"A7", x"88", x"01", -- F83A - A7 88 01 STA 1,X ($F833)
x"A7", x"98", x"FF", -- F83D - A7 98 FF STA [-1,X] ([$F801])
x"A7", x"98", x"01", -- F840 - A7 98 01 STA [1,X] ([$F803])
x"A7", x"89", x"FF", x"FF", -- F843 - A7 89 FFFF STA -1,X ($F801)
x"A7", x"89", x"00", x"01", -- F847 - A7 89 0001 STA 1,X ($F803)
x"A7", x"99", x"FF", x"FF", -- F84B - A7 99 FFFF STA [-1,X] ([$F801])
x"A7", x"99", x"00", x"01", -- F84F - A7 99 0001 STA [1,X] ([$F803])
x"A7", x"8B", -- F853 - A7 8B STA D,X ($4BF2)
x"A7", x"9B", -- F855 - A7 9B STA [D,X] ([$4BF2]))
x"A7", x"8C", x"FF", -- F857 - A7 8C FF STA -1,X ($F801)
x"A7", x"8C", x"01", -- F85A - A7 8C 01 STA 1,X ($F803)
x"A7", x"9C", x"FF", -- F85D - A7 9C FF STA [-1,X] ([$F801])
x"A7", x"9C", x"01", -- F860 - A7 9C 01 STA [1,X] ([$F803])
x"A7", x"8D", x"FF", x"FF", -- F863 - A7 8D FFFF STA -1,X ($F801)
x"A7", x"8D", x"00", x"01", -- F867 - A7 8D 0001 STA 1,X ($F803)
x"A7", x"9D", x"FF", x"FF", -- F86B - A7 9D FFFF STA [-1,X] ([$F801])
x"A7", x"9D", x"00", x"01", -- F86F - A7 9D 0001 STA [1,X] ([$F803])
x"A7", x"8F", x"A0", x"00", -- F873 - A7 8F A000 STA $A000
x"A7", x"9F", x"A0", x"00", -- F877 - A7 9F A000 STA [$A000]
x"7E", x"F8", x"00", -- F87B - 7E F800 JMP RESET
x"F8", x"00" -- F87E - F800 fdb RESET ; Reset
);
 
component cpu09
port (
clk: in std_logic;
rst: in std_logic;
rw: out std_logic; -- Asynchronous memory interface
vma: out std_logic;
address: out std_logic_vector(15 downto 0);
data_in: in std_logic_vector(7 downto 0);
data_out: out std_logic_vector(7 downto 0);
halt: in std_logic;
hold: in std_logic;
irq: in std_logic;
nmi: in std_logic;
firq: in std_logic
);
end component cpu09;
 
 
begin
cpu : cpu09 port map (
clk => SysClk,
rst => cpu_reset,
rw => cpu_rw,
vma => cpu_vma,
address => cpu_addr(15 downto 0),
data_in => cpu_data_in,
data_out => cpu_data_out,
halt => '0',
hold => '0',
irq => cpu_irq,
nmi => cpu_nmi,
firq => cpu_firq
);
 
-- *** Test Bench - User Defined Section ***
tb : PROCESS
variable count : integer;
BEGIN
 
cpu_reset <= '0';
SysClk <= '0';
cpu_irq <= '0';
cpu_nmi <= '0';
cpu_firq <= '0';
 
for count in 0 to 512 loop
SysClk <= '0';
if count = 0 then
cpu_reset <= '1';
elsif count = 1 then
cpu_reset <= '0';
end if;
wait for 100 ns;
SysClk <= '1';
wait for 100 ns;
end loop;
 
wait; -- will wait forever
END PROCESS;
-- *** End Test Bench - User Defined Section ***
 
 
rom : PROCESS( cpu_addr )
begin
cpu_data_in <= rom_data(conv_integer(cpu_addr(6 downto 0)));
end process;
 
end behavior; --===================== End of architecture =======================--
 
/testbench6.vhd
0,0 → 1,183
--===========================================================================----
--
-- T E S T B E N C H tesetbench3 - CPU09 Testbench.
--
-- www.OpenCores.Org - September 2003
-- This core adheres to the GNU public license
--
-- File name : Testbench6.vhd
--
-- Purpose : cpu09 Microprocessor Test Bench 6
-- Tests STS indexed
--
-- Dependencies : ieee.Std_Logic_1164
-- ieee.std_logic_unsigned
-- ieee.std_logic_arith
-- ieee.numeric_std
--
-- Uses : cpu09 (cpu09.vhd) CPU core
--
-- Author : John E. Kent
-- dilbert57@opencores.org
--
--===========================================================================----
--
-- Revision History:
--===========================================================================--
--
-- Version 0.1 - 12st April 2003 - John Kent
-- First version
--
-- Version 1.0 - 6 Sep 2003 - John Kent
-- Initial release to Open Cores
--
-- Version 1.1 - 25th Jan 2004 - John Kent
-- removed "test_alu" and "test_cc"
--
--===========================================================================--
 
library ieee;
use ieee.std_logic_1164.all;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
use ieee.numeric_std.all;
 
entity my_testbench6 is
end my_testbench6;
 
-------------------------------------------------------------------------------
-- Architecture for memio Controller Unit
-------------------------------------------------------------------------------
architecture behavior of my_testbench6 is
-----------------------------------------------------------------------------
-- Signals
-----------------------------------------------------------------------------
signal cpu_irq : std_Logic;
signal cpu_firq : std_logic;
signal cpu_nmi : std_logic;
 
-- CPU Interface signals
signal SysClk : Std_Logic;
signal cpu_reset : Std_Logic;
signal cpu_rw : Std_Logic;
signal cpu_vma : Std_Logic;
signal cpu_addr : Std_Logic_Vector(15 downto 0);
signal cpu_data_in : Std_Logic_Vector(7 downto 0);
signal cpu_data_out: Std_Logic_Vector(7 downto 0);
 
constant width : integer := 8;
constant memsize : integer := 64;
 
type rom_array is array(0 to memsize-1) of std_logic_vector(width-1 downto 0);
 
constant rom_data : rom_array :=
(
x"10",x"CE", x"F8", x"30", -- F800 - 10CE F830 RET1 LDS #STACK
x"CE",x"B0",x"00", -- F804 - CE B000 LDU #$B000
x"10",x"EF",x"C8",x"00", -- F807 - 10EF C800 STS $00,U
x"12",x"12",x"12", -- F80B - 12 12 12
"00110011", -- F8OE - 33 FCB $33 ; ACCB
"00110100", -- F8OF - 34 FCB $34 ; DPR
"00110101", "00110110", -- F810 - 3536 FDB $3536 ; IX
"00110111", "00111000", -- F812 - 3738 FDB $3738 ; IY
"00111001", "00111010", -- F814 - 393A FDB $393A ; UP
"11111000", "00001001", -- F816 - F809 FDB SWI3VEC ; PC
"10100001", -- F818 - A1 STACK2 FCB $A1 ; CC
"00100010", -- F819 - 22 FCB $22 ; ACCA
"00100011", -- F81A - 23 FCB $23 ; ACCB
"00100100", -- F81B - 24 FCB $24 ; DPR
"00100101", "00100110", -- F81C - 2526 FDB $2526 ; IX
"00100111", "00101000", -- F81E - 2728 FDB $2728 ; IY
"00101001", "00101010", -- F820 - 292A FDB $292A ; UP
"11111000", "00001001", -- F822 - F809 FDB SWI3VEC ; PC
"10010001", -- F824 - 91 STACK1 FCB $91 ; CC
"00010010", -- F825 - 12 FCB $12 ; ACCA
"00010011", -- F826 - 13 FCB $13 ; ACCB
"00010100", -- F827 - 14 FCB $14 ; DPR
"00010101", "00010110", -- F828 - 1516 FDB $1516 ; IX
"00010111", "00011000", -- F82A - 1718 FDB $1718 ; IY
"00011001", "00011010", -- F82C - 191A FDB $191A ; UP
"11111000", "00000000", -- F82E - F800 FDB RESET ; PC
-- F830 STACK EQU *
--
-- Interrupt Cectors Start Here
--
"11111000", "00000000", -- F830 - F800 FDB RESET ; RESV
"11111000", "00001001", -- F832 - F809 FDB SWIVEC3 ; SWI3
"11111000", "00000111", -- F834 - F807 FDB SWIVEC2 ; SWI2
"11111000", "00000000", -- F836 - F800 fdb RESET ; FIRQ
"11111000", "00000000", -- F838 - F800 fdb RESET ; IRQ
"11111000", "00000101", -- F83A - F805 fdb SWIVEC ; SWI
"11111000", "00000000", -- F83C - F800 fcb RESET ; NMI
"11111000", "00000000" -- F83E - F800 fdb RESET ; Reset
);
 
component cpu09
port (
clk: in std_logic;
rst: in std_logic;
rw: out std_logic; -- Asynchronous memory interface
vma: out std_logic;
address: out std_logic_vector(15 downto 0);
data_in: in std_logic_vector(7 downto 0);
data_out: out std_logic_vector(7 downto 0);
halt: in std_logic;
hold: in std_logic;
irq: in std_logic;
nmi: in std_logic;
firq: in std_logic
);
end component cpu09;
 
 
begin
cpu : cpu09 port map (
clk => SysClk,
rst => cpu_reset,
rw => cpu_rw,
vma => cpu_vma,
address => cpu_addr(15 downto 0),
data_in => cpu_data_in,
data_out => cpu_data_out,
halt => '0',
hold => '0',
irq => cpu_irq,
nmi => cpu_nmi,
firq => cpu_firq
);
 
-- *** Test Bench - User Defined Section ***
tb : PROCESS
variable count : integer;
BEGIN
 
cpu_reset <= '0';
SysClk <= '0';
cpu_irq <= '0';
cpu_nmi <= '0';
cpu_firq <= '0';
 
for count in 0 to 512 loop
SysClk <= '0';
if count = 0 then
cpu_reset <= '1';
elsif count = 1 then
cpu_reset <= '0';
end if;
wait for 100 ns;
SysClk <= '1';
wait for 100 ns;
end loop;
 
wait; -- will wait forever
END PROCESS;
-- *** End Test Bench - User Defined Section ***
 
 
rom : PROCESS( cpu_addr )
begin
cpu_data_in <= rom_data(conv_integer(cpu_addr(5 downto 0)));
end process;
 
end behavior; --===================== End of architecture =======================--
 
/TB_vdu8.vhd
0,0 → 1,95
-- ------------------------------------------------------------
-- TB_vdu8 Test Bench
-- ------------------------------------------------------------
-- (c) Bertrand Cuzeau
--
 
Library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
use STD.textio.all;
use IEEE.std_logic_textio.all;
 
Entity TB_vdu8 is end;
 
Architecture TEST of tb_vdu8 is
 
subtype Byte is std_logic_vector (7 downto 0);
 
signal vdu_clk_in : std_logic := '0';
signal cpu_clk_out : std_logic;
signal vdu_rst : std_logic;
signal vdu_cs : std_logic := '0';
signal vdu_rw : std_logic := '1';
signal vdu_addr : std_logic_vector(2 downto 0) := "000";
signal vdu_data_in : std_logic_vector(7 downto 0);
signal vdu_data_out : std_logic_vector(7 downto 0);
signal vga_red_o : std_logic;
signal vga_green_o : std_logic;
signal vga_blue_o : std_logic;
signal vga_hsync_o : std_logic;
signal vga_vsync_o : std_logic;
 
constant Msg : string := "Hello! X";
signal done : boolean;
constant Period : time := 10 ns;
 
begin
 
vdu_clk_in <= '0' when Done else not vdu_clk_in after Period / 2;
vdu_rst <= '1', '0' after 16 * Period;
 
vdu: Entity work.vdu8
port map (
vdu_clk_in => vdu_clk_in ,
cpu_clk_out => cpu_clk_out ,
vdu_rst => vdu_rst ,
vdu_cs => vdu_cs ,
vdu_rw => vdu_rw ,
vdu_addr => vdu_addr ,
vdu_data_in => vdu_data_in ,
vdu_data_out => vdu_data_out ,
vga_red_o => vga_red_o ,
vga_green_o => vga_green_o ,
vga_blue_o => vga_blue_o ,
vga_hsync_o => vga_hsync_o ,
vga_vsync_o => vga_vsync_o
);
 
process
procedure Writebyte (b : Byte; Addr : integer) is
begin
wait for 500 ns;
vdu_cs <= '1';
vdu_data_in <= b;
vdu_addr <= std_logic_vector(to_unsigned(Addr,3));
wait for 100 ns;
vdu_rw <= '0';
wait for 200 ns;
vdu_rw <= '1';
vdu_cs <= '0';
end procedure;
 
procedure WriteChar (c : character; color:byte; x:integer; y:integer; offs:integer) is
begin
WriteByte(std_logic_vector(to_unsigned(character'pos(c),8)),0);
WriteByte(color,1);
WriteByte(std_logic_vector(to_unsigned(x,8)),2);
WriteByte(std_logic_vector(to_unsigned(y,8)),3);
WriteByte(std_logic_vector(to_unsigned(offs,8)),4);
end procedure;
 
begin
vdu_data_in <= x"00";
wait until vga_hsync_o='0';
for i in Msg'range loop
WriteChar(Msg(i), x"17",i,i,1); -- ?? bgB bgG bgR Blink?? fgB fgG fgR <<< TBV
end loop;
wait until vga_vsync_o='0';
wait for 5 ms;
report "End of Simulation";
done <= true;
wait;
end process;
 
end architecture TEST;

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