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    /System09/tags/V10/sw
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Rev 3 → Rev 66

/sbug_src.s19
0,0 → 1,65
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S9030000FC
/sbug_src.txt
0,0 → 1,1402
* NAM SBUG18 MP-09 MONITOR
OPT l
PAGE
*
* MONITOR PROGRAM FOR THE SOUTHWEST TECHNICAL
* PRODUCTS MP-09 CPU BOARD AS COMMENTED BY....
*
* ALLEN CLARK WALLACE WATSON
* 2502 REGAL OAKS LANE 4815 EAST 97th AVE.
* LUTZ, FLA. 33549 TEMPLE TERRACE, FLA. 33617
* PH. 813-977-0347 PH. 813-985-1359
*
* MODIFIED TO SBUG09 VER 1.8 BY: RANDY JARRETT
* 2561 NANTUCKET DR APT. E
* ATLANTA, GA 30345
* PH. 404-320-1043
*
*
* *** COMMANDS ***
*
* CONTROL A = ALTER THE "A" ACCUMULATOR
* CONTROL B = ALTER THE "B" ACCUMULATOR
* CONTROL C = ALTER THE CONDITION CODE REGISTER
* CONTROL D = ALTER THE DIRECT PAGE REGISTER
* CONTROL P = ALTER THE PROGRAM COUNTER
* CONTROL U = ALTER USER STACK POINTER
* CONTROL X = ALTER "X" INDEX REGISTER
* CONTROL Y = ALTER "Y" INDEX REGISTER
* B hhhh = SET BREAKPOINT AT LOCATION $hhhh
* D = BOOT A SWTPC 8 INCH FLOPPY SYSTEM
* U = BOOT A SWTPC 5 INCH FLOPPY SYSTEM
* E ssss-eeee = EXAMINE MEMORY FROM STARTING ADDRESS ssss
* -TO ENDING ADDRESS eeee.
* G = CONTINUE EXECUTION FROM BREAKPOINT OR SWI
* L = LOAD TAPE
* M hhhh = EXAMINE AND CHANGE MEMORY LOCATION hhhh
* P ssss-eeee = PUNCH TAPE, START ssss TO END eeee ADDR.
* Q ssss-eeee = TEST MEMORY FROM ssss TO eeee
* R = DISPLAY REGISTER CONTENTS
* S = DISPLAY STACK FROM ssss TO $DFC0
* X = REMOVE ALL BREAKPOINTS
*
*
TSTPAT EQU $55AA TEST PATTERN
*
*
*
ORG $DFC0
STACK RMB 2 TOP OF INTERNAL STACK / USER VECTOR
SWI3 RMB 2 SOFTWARE INTERRUPT VECTOR #3
SWI2 RMB 2 SOFTWARE INTERRUPT VECTOR #2
FIRQ RMB 2 FAST INTERRUPT VECTOR
IRQ RMB 2 INTERRUPT VECTOR
SWI RMB 2 SOFTWARE INTERRUPT VECTOR
SVCVO RMB 2 SUPERVISOR CALL VECTOR ORGIN
SVCVL RMB 2 SUPERVISOR CALL VECTOR LIMIT
LRARAM RMB 16 LRA ADDRESSES
CPORT RMB 2 RE-VECTORABLE CONTROL PORT
ECHO RMB 1 ECHO FLAG
BPTBL RMB 24 BREAKPOINT TABLE BASE ADDR
ACIAS EQU $E004 CONTROL PORT
Comreg EQU $E018 COMMAND REGISTER
Drvreg EQU $E014 DRIVE REGISTER
Secreg EQU $E01A SECTOR REGISTER
Datreg EQU $E01B DATA REGISTER
*
ADDREG EQU $F000 ADDRESS REGISTER
CNTREG EQU $F002 COUNT REGISTER
CCREG EQU $F010 CHANNEL CONTROL REGISTER
PRIREG EQU $F014 DMA PRIORITY REGISTER
AAAREG EQU $F015 ???
BBBREG EQU $F016 ???
COMREG EQU $F020 1791 COMMAND REGISTER
SECREG EQU $F022 SECTOR REGISTER
DRVREG EQU $F024 DRIVE SELECT LATCH
CCCREG EQU $F040 ???
*
IC11 EQU $FFF0 DAT RAM CHIP
*
ORG $F800
FDB MONITOR
FDB NEXTCMD
FDB INCH
FDB INCHE
FDB INCHEK
FDB OUTCH
FDB PDATA
FDB PCRLF
FDB PSTRNG
FDB LRA
*
* MONITOR
*
* VECTOR ADDRESS STRING IS.....
* $F8A1-$F8A1-$F8A1-$F8A1-$F8A1-$FAB0-$FFFF-$FFFF
*
MONITOR LDX #RAMVEC POINT TO VECTOR ADDR. STRING
LDY #STACK POINT TO RAM VECTOR LOCATION
LDB #$10 BYTES TO MOVE = 16
LOOPA LDA ,X+ GET VECTOR BYTE
STA ,Y+ PUT VECTORS IN RAM / $DFC0-$DFCF
DECB SUBTRACT 1 FROM NUMBER OF BYTES TO MOVE
BNE LOOPA CONTINUE UNTIL ALL VECTORS MOVED
*
* CONTENTS FROM TO FUNCTION
* $F8A1 $FE40 $DFC0 USER-V
* $F8A1 $FE42 $DFC2 SWI3-V
* $F8A1 $FE44 $DFC4 SWI2-V
* $F8A1 $FE46 $DFC6 FIRQ-V
* $F8A1 $FE48 $DFC8 IRQ-V
* $FAB0 $FE4A $DFCA SWI-V
* $FFFF $FE4C $DFCC SVC-VO
* $FFFF $FE4E $DFCE SVC-VL
*
LDX #ACIAS GET CONTROL PORT ADDR.
STX CPORT STORE ADDR. IN RAM
LBSR XBKPNT CLEAR OUTSTANDING BREAKPOINTS
LDB #12 CLEAR 12 BYTES ON STACK
CLRSTK CLR ,-S
DECB
BNE CLRSTK
LEAX MONITOR,PCR SET PC TO SBUG-E ENTRY
STX 10,S ON STACK
LDA #$D0 PRESET CONDITION CODES ON STACK
STA ,S
TFR S,U
LBSR ACINIZ INITIALIZE CONTROL PORT
LDX #MSG1 POINT TO 'SBUG 1.8' MESSAGE
LBSR PDATA PRINT MSG
LDX #LRARAM POINT TO LRA RAM STORAGE AREA
CLRA START TOTAL AT ZERO
LDB #13 TOTAL UP ALL ACTIVE RAM MEMORY
FNDREL TST B,X TEST FOR RAM AT NEXT LOC.
BEQ RELPAS IF NO RAM GO TO NEXT LOC.
ADDA #4 ELSE ADD 4K TO TOTAL
DAA ADJ. TOTAL FOR DECIMAL
RELPAS DECB SUB. 1 FROM LOCS. TO TEST
BPL FNDREL PRINT TOTAL OF RAM
LBSR OUT2H OUTPUT HEX BYTE AS ASCII
LDX #MSG2 POINT TO MSG 'K' CR/LF + 3 NULS
LBSR PDATA PRINT MSG
*
***** NEXTCMD *****
*
NEXTCMD LDX #MSG3 POINT TO MSG ">"
LBSR PSTRNG PRINT MSG
LBSR INCH GET ONE CHAR. FROM TERMINAL
ANDA #$7F STRIP PARITY FROM CHAR.
CMPA #$0D IS IT CARRIAGE RETURN ?
BEQ NEXTCMD IF CR THEN GET ANOTHER CHAR.
TFR A,B PUT CHAR. IN "B" ACCUM.
CMPA #$20 IS IT CONTROL OR DATA CHAR ?
BGE PRTCMD IF CMD CHAR IS DATA, PRNT IT
LDA #'^ ELSE CNTRL CHAR CMD SO...
LBSR OUTCH PRINT "^"
TFR B,A RECALL CNTRL CMD CHAR
ADDA #$40 CONVERT IT TO ASCII LETTER
PRTCMD LBSR OUTCH PRNT CMD CHAR
LBSR OUT1S PRNT SPACE
CMPB #$60
BLE NXTCH0
SUBB #$20
*
*
***** DO TABLE LOOKUP *****
* FOR COMMAND FUNCTIONS
*
*
NXTCH0 LDX #JMPTAB POINT TO JUMP TABLE
NXTCHR CMPB ,X+ DOES COMMAND MATCH TABLE ENTRY ?
BEQ JMPCMD BRANCH IF MATCH FOUND
LEAX 2,X POINT TO NEXT ENTRY IN TABLE
CMPX #TABEND REACHED END OF TABLE YET ?
BNE NXTCHR IF NOT END, CHECK NEXT ENTRY
LDX #MSG4 POINT TO MSG "WHAT?"
LBSR PDATA PRINT MSG
BRA NEXTCMD IF NO MATCH, PRMPT FOR NEW CMD
JMPCMD JSR [,X] JUMP TO COMMAND ROUTINE
BRA NEXTCMD PROMPT FOR NEW COMMAND
*
* "G" GO OR CONTINUE
*
GO TFR U,S
RTI RTI
*
* "R" DISPLAY REGISTERS
*
REGSTR LDX #MSG5 POINT TO MSG " - "
LBSR PSTRNG PRINT MSG
LBSR PRTSP $FCBF
LBSR PRTUS $FCCA
LBSR PRTDP $FCD5
LBSR PRTIX $FCE0
LBSR PRTIY $FCEB
LDX #MSG5 POINT TO MSG " - "
LBSR PSTRNG PRINT MSG
LBSR PRTPC $FCF5
LBSR PRTA $FCFF
LBSR PRTB $FD09
LBRA PRTCC $FD13
*
*
* ALTER "PC" PROGRAM COUNTER
*
*
ALTRPC LBSR PRTPC $FCF5 PRINT MSG " PC = "
LBSR OUT1S OUTPUT SPACE
LBSR IN1ADR GET NEW CONTENTS FOR "PC"
BVS ALTPCD EXIT IF INVALID HEX
STX 10,U POKE IN NEW CONTENTS
ALTPCD RTS ;
*
*
* ALTER "U" USER STACK POINTER
*
*
ALTRU LBSR PRTUS $FCCA PRINT MSG " US = "
LBSR OUT1S OUTPUT SPACE
LBSR IN1ADR
BVS ALTUD
STX 8,U
ALTUD RTS ;
*
*
* ALTER "Y" INDEX REGISTER
*
*
ALTRY LBSR PRTIY PRINT MSG " IY = "
LBSR OUT1S OUTPUT SPACE
LBSR IN1ADR
BVS ALTYD
STX 6,U $F8F0
ALTYD RTS ;
*
*
* ALTER "X" INDEX REGISTER
*
*
ALTRX LBSR PRTIX $FCE0 PRINT MSG " IX = "
LBSR OUT1S OUTPUT SPACE
LBSR IN1ADR
BVS ALTXD
STX 4,U
ALTXD RTS ;
*
*
* ALTER "DP" DIRECT PAGE REGISTER
*
*
ALTRDP LBSR PRTDP $FCD5 PRINT MSG " DP = "
LBSR OUT1S OUTPUT SPACE
LBSR BYTE INPUT BYTE (2 HEX CHAR)
BVS ALTDPD
STA 3,U
ALTDPD RTS ;
*
*
* ALTER "B" ACCUMULATOR
*
*
ALTRB LBSR PRTB $FD09 PRINT MSG " B = "
LBSR OUT1S OUTPUT SPACE
LBSR BYTE INPUT BYTE (2 HEX CHAR)
BVS ALTBD
STA 2,U
ALTBD RTS $F91C
*
*
* ALTER "A" ACCUMULATOR
*
*
ALTRA LBSR PRTA $FCFF RINT MSG " A = "
LBSR OUT1S OUTPUT SPACE
LBSR BYTE INPUT BYTE (2 HEX CHAR)
BVS ALTAD
STA 1,U
ALTAD RTS ;
*
*
* ALTER "CC" REGISTER
*
*
ALTRCC LBSR PRTCC $FD13 PRINT MSG " CC: "
LBSR OUT1S OUTPUT SPACE
LBSR BYTE INPUT BYTE (2 HEX CHAR)
BVS ALTCCD
ORA #$80 SETS "E" FLAG IN PRINT LIST
STA ,U
ALTCCD RTS ;
*
***** "M" MEMORY EXAMINE AND CHANGE *****
*
MEMCHG LBSR IN1ADR INPUT ADDRESS
BVS CHRTN IF NOT HEX, RETURN
TFR X,Y SAVE ADDR IN "Y"
MEMC2 LDX #MSG5 POINT TO MSG " - "
LBSR PSTRNG PRINT MSG
TFR Y,X FETCH ADDRESS
LBSR OUT4H PRINT ADDR IN HEX
LBSR OUT1S OUTPUT SPACE
LDA ,Y GET CONTENTS OF CURRENT ADDR.
LBSR OUT2H OUTPUT CONTENTS IN ASCII
LBSR OUT1S OUTPUT SPACE
LBSR BYTE LOOP WAITING FOR OPERATOR INPUT
BVC CHANGE IF VALID HEX GO CHANGE MEM. LOC.
CMPA #8 IS IT A BACKSPACE (CNTRL H)?
BEQ MEMC2 PROMPT OPERATOR AGAIN
CMPA #$18 IS IT A CANCEL (CNTRL X)?
BEQ MEMC2 PROMPT OPERATOR AGAIN
CMPA #'^ IS IT AN UP ARROW?
BEQ BACK DISPLAY PREVIOUS BYTE
CMPA #$D IS IT A CR?
BNE FORWRD DISPLAY NEXT BYTE
CHRTN RTS EXIT ROUTINE
*
*
CHANGE STA ,Y CHANGE BYTE IN MEMORY
CMPA ,Y DID MEMORY BYTE CHANGE?
BEQ FORWRD $F972
LBSR OUT1S OUTPUT SPACE
LDA #'? LOAD QUESTION MARK
LBSR OUTCH PRINT IT
FORWRD LEAY 1,Y POINT TO NEXT HIGHER MEM LOCATION
BRA MEMC2 PRINT LOCATION & CONTENTS
BACK LEAY -1,Y POINT TO LAST MEM LOCATION
BRA MEMC2 PRINT LOCATION & CONTENTS
*
* "S" DISPLAY STACK
* HEX-ASCII DISPLAY OF CURRENT STACK CONTENTS FROM
** CURRENT STACK POINTER TO INTERNAL STACK LIMIT.
*
DISSTK LBSR PRTSP PRINT CURRENT STACK POINTER
TFR U,Y
LDX #STACK LOAD INTERNAL STACK AS UPPER LIMIT
LEAX -1,X POINT TO CURRENT STACK
BRA MDUMP1 ENTER MEMORY DUMP OF STACK CONTENTS
*
* "E" DUMP MEMORY FOR EXAMINE IN HEX AND ASCII
* AFTER CALLING 'IN2ADR' LOWER ADDRESS IN Y-REG.
* UPPER ADDRESS IN X-REG.
* IF HEX ADDRESSES ARE INVALID (V)=1.
*
MEMDUMP LBSR IN2ADR INPUT ADDRESS BOUNDRIES
BVS EDPRTN NEW COMMAND IF ILLEGAL HEX
MDUMP1 PSHS Y COMPARE LOWER TO UPPER BOUNDS
CMPX ,S++ LOWER BOUNDS > UPPER BOUNDS?
BCC AJDUMP IF NOT, DUMP HEX AND ASCII
EDPRTN RTS ;
*
* ADJUST LOWER AND UPPER ADDRESS LIMITS
* TO EVEN 16 BYTE BOUNDRIES.
*
* IF LOWER ADDR = $4532
* LOWER BOUNDS WILL BE ADJUSTED TO = $4530.
*
* IF UPPER ADDR = $4567
* UPPER BOUNDS WILL BE ADJUSTED TO = $4570.
*
* ENTER WITH LOWER ADDRESS IN X-REG.
* -UPPER ADDRESS ON TOP OF STACK.
*
AJDUMP TFR X,D GET UPPER ADDR IN D-REG
ADDD #$10 ADD 16 TO UPPER ADDRESS
ANDB #$F0 MASK TO EVEN 16 BYTE BOUNDRY
PSHS A,B SAVE ON STACK AS UPPER DUMP LIMIT
TFR Y,D $F9A5 GET LOWER ADDRESS IN D-REG
ANDB #$F0 MASK TO EVEN 16 BYTE BOUNDRY
TFR D,X PUT IN X-REG AS LOWER DUMP LIMIT
NXTLIN CMPX ,S COMPARE LOWER TO UPPER LIMIT
BEQ SKPDMP IF EQUAL SKIP HEX-ASCII DUMP
LBSR INCHEK CHECK FOR INPUT FROM KEYBOARD
BEQ EDUMP IF NONE, CONTINUE WITH DUMP
SKPDMP LEAS 2,S READJUST STACK IF NOT DUMPING
RTS ;
*
* PRINT 16 HEX BYTES FOLLOWED BY 16 ASCII CHARACTERS
* FOR EACH LINE THROUGHOUT ADDRESS LIMITS.
*
EDUMP PSHS X PUSH LOWER ADDR LIMIT ON STACK
LDX #MSG5 POINT TO MSG " - "
LBSR PSTRNG PRINT MSG
LDX ,S LOAD LOWER ADDR FROM TOP OF STACK
LBSR OUT4H PRINT THE ADDRESS LBSR OUT2S PRINT 2 SPACES
LDB #$10 LOAD COUNT OF 16 BYTES TO DUMP
ELOOP LDA ,X+ GET FROM MEMORY HEX BYTE TO PRINT
LBSR OUT2H OUTPUT HEX BYTE AS ASCII
LBSR OUT1S OUTPUT SPACE
DECB $F9D1 DECREMENT BYTE COUNT
BNE ELOOP CONTINUE TIL 16 HEX BYTES PRINTED
*
* PRINT 16 ASCII CHARACTERS
* IF NOT PRINTABLE OR NOT VALID
* ASCII PRINT A PERIOD (.)
LBSR OUT2S 2 SPACES
LDX ,S++ GET LOW LIMIT FRM STACK - ADJ STACK
LDB #$10 SET ASCII CHAR TO PRINT = 16
EDPASC LDA ,X+ GET CHARACTER FROM MEMORY
CMPA #$20 IF LESS THAN $20, NON-PRINTABLE?
BCS PERIOD IF SO, PRINT PERIOD INSTEAD
CMPA #$7E IS IT VALID ASCII?
BLS PRASC IF SO PRINT IT
PERIOD LDA #'. LOAD A PERIOD (.)
PRASC LBSR OUTCH PRINT ASCII CHARACTER
DECB DECREMENT COUNT
BNE EDPASC
BRA NXTLIN
*
***** "Q" MEMORY TEST *****
*
MEMTST CLR ,-S CLEAR BYTE ON STACK
CLR ,-S CLEAR ANOTHER BYTE
LBSR IN2ADR GET BEGIN(Y) & END(X) ADDR. LIMITS
PSHS X,Y SAVE ADDRESSES ON STACK
BVS ADJSK6 EXIT IF NOT VALID HEX
CMPX 2,S COMPARE BEGIN TO END ADDR.
BCS ADJSK6 EXIT IF BEGIN > END ADDR.
LBSR OUT1S OUTPUT SPACE
MEMSET TFR Y,D PUT BEGIN ADDR. IN 'D'-ACCUM.
ADDD 4,S ADD PASS COUNT TO BEGIN ADDR
PSHS B ADD LS BYTE TO MS BYTE OF BEGIN ADDR
ADDA ,S+
STA ,Y+ SAVE THIS DATA BYTE AT BEGIN ADDR
CMPY ,S COMPARE END TO BEGIN ADDR
BCS MEMSET IF BEGIN LOWER, CONTINUE TO SET MEMORY
LDY 2,S RELOAD BEGIN ADDRESS
TEST1 TFR Y,D PUT BEGIN ADDR IN 'D'-ACC.
ADDD 4,S ADD PASS COUNT TO ADDRESS
PSHS A ADD MS BYTE TO LS BYTE OF ADDRESS
ADDB ,S+
EORB ,Y+ EX-OR THIS DATA WITH DATA IN MEMORY LOC.
BEQ GUDPAS IF (Z) SET, MEMORY BYTE OK
LDX #MSG5 POINT TO MSG " - "
LBSR PSTRNG PRINT MSG
LEAX -1,Y GET ERROR ADDRESS IN X-REG
LBSR OUT4H OUTPUT IT
PSHS X PUSH ERROR ADDR ON STACK
LDX #MSG8 POINT TO MSG " =>"
LBSR PDATA PRINT MSG
PULS X POP ERROR ADDR FROM STACK
LBSR LRA GET PHYSICAL ADDR FROM LRA
LBSR XASCII OUTPUT EXTENDED 4 BITS OF PHYSICAL ADDR
LBSR OUT4H OUTPUT LS 16 BITS OF PHYSICAL ADDR
LDX #MSG6 POINT TO MSG ", PASS "
LBSR PDATA PRINT MSG
LDX 4,S LOAD PASS COUNT
LBSR OUT4H OUTPUT IT
LDX #MSG7 POINT TO MSG ", BITS IN ERROR
LBSR PDATA PRINT MSG
TFR B,A GET ERROR BYTE INTO A-ACC
LDX #MSG9 POINT TO MSG "76543210"
LBSR BIASCI OUTPUT IN BINARY/ASCII FORMAT
LBSR INCHEK CHECK FOR INPUT FROM KEYBOARD $FA56
BNE ADJSK6 IF SO, EXIT MEMORY TEST
GUDPAS CMPY ,S COMPARE END ADDR TO BEGIN ADDR
BCS TEST1
LDA #'+ GET "PASS" SYMBOL IF MEMORY PASS OK
LBSR OUTCH OUTPUT SYMBOL TO TERMINAL
LBSR INCHEK INPUT FROM KEYBOARD?
BNE ADJSK6 IF SO, EXIT MEMORY TEST
LDY 2,S LOAD BEGIN ADDRESS
INC 5,S INCREMENT LS BYTE OF PASS COUNT
BNE MEMSET IF NOT ZERO, SET NEXT MEMORY BYTE
INC 4,S INCREMENT MS BYTE OF PASS COUNT
BNE MEMSET DONE WITH 65,535 PASSES OF MEMORY?
ADJSK6 LEAS 6,S ADJ STACK POINTER BY 6
RTS
*
***** "B" SET BREAKPOINT *****
*
BRKPNT LBSR IN1ADR GET BREAKPOINT ADDRESS
BVS EXITBP EXIT IF INVALID HEX ADDR.
CMPX #STACK ADDRESS ILLEGAL IF >=$DFC0
BCC BPERR IF ERROR PRINT (?), EXIT
PSHS X $FA82 PUSH BP ADDRESS ON STACK
LDX #$FFFF LOAD DUMMY ADDR TO TEST BP TABLE
BSR BPTEST TEST BP TABLE FOR FREE SPACE
PULS X POP BP ADDRESS FROM STACK
BEQ BPERR (Z) SET, OUT OF BP TABLE SPACE
LDA ,X GET DATA AT BREAKPOINT ADDRESS
CMPA #$3F IS IT A SWI?
BEQ BPERR IF SWI ALREADY, INDICATE ERROR
STA ,Y+ SAVE DATA BYTE IN BP TABLE
STX ,Y SAVE BP ADDRESS IN BP TABLE
LDA #$3F LOAD A SWI ($3F)
STA ,X SAVE SWI AT BREAKPOINT ADDRESS
EXITBP RTS ;
*
* INDICATE ERROR SETTING BREAKPOINT
*
BPERR LBSR OUT1S OUTPUT SPACE
LDA #'? LOAD (?), INDICATE BREAKPOINT ERROR
LBRA OUTCH PRINT "?"
*
*** "X" CLEAR OUTSTANDING BREAKPOINTS ***
*
XBKPNT LDY #BPTBL POINT TO BREAKPOINT TABLE
LDB #8 LOAD BREAKPOINT COUNTER
XBPLP BSR RPLSWI REMOVE USED ENTRY IN BP TABLE
DECB $FAAC DECREMENT BP COUNTER
BNE XBPLP END OF BREAKPOINT TABLE?
RTS
*
***** SWI ENTRY POINT *****
*
SWIE TFR S,U TRANSFER STACK TO USER POINTER
LDX 10,U LOAD PC FROM STACK INTO X-REG
LEAX -1,X ADJUST ADDR DOWN 1 BYTE.
BSR BPTEST FIND BREAKPOINT IN BP TABLE
BEQ REGPR IF FOUND, REPLACE DATA AT BP ADDR
STX 10,U SAVE BREAKPOINT ADDR IN STACK
BSR RPLSWI GO REPLACE SWI WITH ORIGINAL DATA
REGPR LBSR REGSTR GO PRINT REGISTERS
LBRA NEXTCMD GET NEXT COMMAND
RPLSWI LDX 1,Y LOAD BP ADDRESS FROM BP TABLE
CMPX #STACK COMPARE TO TOP AVAILABLE USER MEMORY
BCC FFSTBL GO RESET TABLE ENTRY TO $FF'S
LDA ,X GET DATA FROM BP ADDRESS
CMPA #$3F IS IT SWI?
BNE FFSTBL IF NOT, RESET TABLE ENTRY TO $FF'S
LDA ,Y GET ORIGINAL DATA FROM BP TABLE
STA ,X $FAD3 RESTORE DATA AT BP ADDRESS
FFSTBL LDA #$FF LOAD $FF IN A-ACC
STA ,Y+ RESET BREAKPOINT TABLE DATA TO $FF'S
STA ,Y+ RESET BREAKPOINT TABLE ADDR TO $FF'S
STA ,Y+
RTS
*
** SEARCH BREAKPOINT TABLE FOR MATCH **
*
BPTEST LDY #BPTBL POINT TO BREAKPOINT TABLE
LDB #8 LOAD BREAKPOINT COUNTER
FNDBP LDA ,Y+ LOAD DATA BYTE
CMPX ,Y++ COMPARE ADDRESS, IS IT SAME?
BEQ BPADJ IF SO, ADJUST POINTER FOR TABLE ENTRY
DECB IF NOT, DECREMENT BREAKPOINT COUNTER
BNE FNDBP AND LOOK FOR NEXT POSSIBLE MATCH
RTS ;
*
*
BPADJ LEAY -3,Y MOVE POINTER TO BEGIN OF BP ENTRY
RTS
*
*** "D" DISK BOOT FOR DMAF2 ***
*
DBOOT LDA #$DE
STA DRVREG
LDA #$FF
STA PRIREG $FAF8
STA CCREG
STA AAAREG
STA BBBREG
TST CCREG
LDA #$D8
STA COMREG
LBSR DLY
DBOOT0 LDA COMREG
BMI DBOOT0
LDA #$09
STA COMREG
LBSR DLY
*
DISKWT LDA COMREG FETCH DRIVE STATUS
BITA #1 TEST BUSY BIT
BNE DISKWT LOOP UNTIL NOT BUSY
*
BITA #$10
BNE DBOOT
*
LDX #$C000 LOGICAL ADDR. = $C000
BSR LRA GET 20 BIT PHYSICAL ADDR. OF LOG. ADDR.
ORA #$10
STA CCCREG
TFR X,D
COMA ;
COMB ;
STD ADDREG
LDX #$FEFF LOAD DMA BYTE COUNT = $100
STX CNTREG STORE IN COUNT REGISTER
LDA #$FF LOAD THE CHANNEL REGISTER
STA CCREG
LDA #$FE SET CHANNEL 0
STA PRIREG
LDA #1 SET SECTOR TO "1"
STA SECREG ISSUE COMMAND
LDA #$8C SET SINGLE SECTOR READ
STA COMREG ISSUE COMMAND
BSR DLY
*
* THE FOLLOWING CODE TESTS THE STATUS OF THE
* CHANNEL CONTROL REGISTER. IF "D7" IS NOT
* ZERO THEN IT WILL LOOP WAITING FOR "D7"
* TO GO TO ZERO. IF AFTER 65,536 TRIES IT
* IS STILL A ONE THE BOOT OPERATION WILL
* BE STARTED OVER FROM THE BEGINING.
*
CLRB ;
DBOOT1 PSHS B $FB55
CLRB ;
DBOOT2 TST CCREG
BPL DBOOT3
DECB ;
BNE DBOOT2
PULS B
DECB
BNE DBOOT1
BRA DBOOT
DBOOT3 PULS B
LDA COMREG
BITA #$1C
BEQ DBOOT4
RTS ;
*
*
DBOOT4 LDB #$DE
STB DRVREG
LDX #$C000
STX 10,U
TFR U,S $FB7B
RTI ;
*
***** LRA LOAD REAL ADDRESS *****
*
* THE FOLLOWING CODE LOADS THE 20-BIT
* PHYSICAL ADDRESS OF A MEMORY BYTE
* INTO THE "A" AND "X" REGISTERS. THIS
* ROUTINE IS ENTERED WITH THE LOGICAL
* ADDRESS OF A MEMORY BYTE IN THE "IX"
* REGISTER. EXIT IS MADE WITH THE HIGH-
* ORDER FOUR BITS OF THE 20-BIT PHYSICAL
* ADDRESS IN THE "A" REGISTER, AND THE
* LOW-ORDER 16-BITS OF THE 20-BIT
* PHYSICAL ADDRESS IN THE "IX" REGISTER.
* ALL OTHER REGISTERS ARE PRESERVED.
* THIS ROUTINE IS REQUIRED SINCE THE
* DMAF1 AND DMAF2 DISK CONTROLLERS MUST
* PRESENT PHYSICAL ADDRESSES ON THE
* SYSTEM BUS.
*
LRA PSHS A,B,X,Y PUSH REGISTERS ON STACK
LDA 2,S GET MSB LOGICAL ADDR FRM X REG ON STACK
LSRA ;
LSRA ADJ FOR INDEXED INTO
LSRA CORRESPONDING LOCATION
LSRA IN LRA TABLE
LDY #LRARAM LOAD LRA TABLE BASE ADDRESS
LDB A,Y GET PHYSICAL ADDR. DATA FROM LRA TABLE
LSRB ADJ. REAL ADDR. TO REFLECT EXTENDED
LSRB PHYSICAL ADDRESS.
LSRB EXTENDED MS 4-BITS ARE RETURNED
LSRB IN THE "A" ACCUMULATOR
STB ,S MS 4 BITS IN A ACCUM. STORED ON STACK
LDB A,Y LOAD REAL ADDRESS DATA FROM LRA TABLE
COMB COMP TO ADJ FOR PHYSICAL ADDR. IN X REG
ASLB ADJ DATA FOR RELOCATION IN X REG
ASLB ;
ASLB $FB97
ASLB ;
LDA 2,S GET MS BYTE OF LOGICAL ADDR.
ANDA #$0F MASK MS NIBBLE OF LOGICAL ADDRESS
STA 2,S SAVE IT IN X REG ON STACK
ORB 2,S SET MS BYTE IN X REG TO ADJ PHY ADDR.
*
* PLUS LS NIBBLE OF LOGICAL ADDRESS
STB 2,S SAVE AS LS 16 BITS OF PHY ADDR IN X REG
* ON STACK
PULS A,B,X,Y POP REGS. FROM STACK
RTS ;
*
* DELAY LOOP
*
DLY PSHS B SAVE CONTENTS OF "B"
LDB #$20 GET LOOP DELAY VALUE
SUB1 DECB SUBTRACT ONE FROM VALUE
BNE SUB1 LOOP UNTIL ZERO
PULS B RESTORE CONTENTS OF "B"
RTS ;
*
***** "U" MINIDISK BOOT *****
*
MINBOOT TST Comreg
CLR Drvreg SELECT DRIVE 0
*
* DELAY BEFORE ISSUING RESTORE COMMAND
LDB #3
LDX #0
LOOP LEAX 1,X $FBBB
CMPX #0
BNE LOOP
DECB $FBC2
BNE LOOP
*
LDA #$0F *LOAD HEAD, VERIFY, 20msec/step
STA Comreg ISSUE RESTORE COMMAND
BSR DELAY
LOOP1 LDB Comreg $FBCC
BITB #1
BNE LOOP1 LOOP UNTIL THRU
LDA #1
STA Secreg SET SECTOR REGISTER TO ONE
BSR DELAY
LDA #$8C LOAD HEAD, DELAY 10msec,
STA Comreg AND READ SINGLE RECORD
BSR DELAY
LDX #$C000
BRA LOOP3
*
LOOP2 BITB #2 $FBE6 DRQ?
BEQ LOOP3
LDA Datreg
STA ,X+
*
LOOP3 LDB Comreg FETCH STATUS
BITB #1 BUSY?
BNE LOOP2
BITB #$2C CRC ERROR OR LOST DATA?
BEQ LOOP4
RTS ;
LOOP4 LDX #$C000 $FBFB
STX 10,U
TFR U,S
RTI ;
*
* DELAY
*
DELAY LDB #$20
LOOP5 DECB ;
BNE LOOP5
RTS ;
*
***** "L" LOAD MIKBUG TAPE *****
*
LOAD LDA #$11 LOAD 'DC1' CASS. READ ON CODE
LBSR OUTCH OUTPUT IT TO TERMINAL PORT
CLR ECHO TURN OFF ECHO FLAG
LOAD1 LBSR ECHON INPUT 8 BIT BYTE WITH NO ECHO
LOAD2 CMPA #'S IS IT AN "S", START CHARACTER ?
BNE LOAD1 IF NOT, DISCARD AND GET NEXT CHAR.
LBSR ECHON
CMPA #'9 IS IT A "9" , END OF FILE CHAR ?
BEQ LOAD21 IF SO, EXIT LOAD
CMPA #'1 IS IT A "1" , FILE LOAD CHAR ?
BNE LOAD2 IF NOT, LOOK FOR START CHAR.
LBSR BYTE INPUT BYTE COUNT
PSHS A PUSH COUNT ON STACK
BVS LODERR (V) C-CODE SET, ILLEGAL HEX
LBSR IN1ADR INPUT LOAD ADDRESS
BVS LODERR (V) C-CODE SET, ADDR NOT HEX
PSHS X PUSH ADDR ON STACK
LDB ,S+ LOAD MSB OF ADDR AS CHECKSUM BYTE
ADDB ,S+ ADD LSB OF ADDR TO CHECKSUM
ADDB ,S ADD BYTE COUNT BYTE TO CHECKSUM
DEC ,S $FC37 DECREMENT BYTE COUNT 2 TO BYPASS
DEC ,S ADDRESS BYTES.
LOAD10 PSHS B PUSH CHECKSUM ON STACK
LBSR BYTE INPUT DATA BYTE (2 HEX CHAR)
PULS B POP CHECKSUM FROM STACK
BVS LODERR (V) SET, DATA BYTE NOT HEX
PSHS A PUSH DATA BYTE ON STACK
ADDB ,S+ ADD DATA TO CHECKSUM, AUTO INC STACK
DEC ,S DECREMENT BYTE COUNT 1
BEQ LOAD16 IF BYTE COUNT ZERO, TEST CHECKSUM
STA ,X+ SAVE DATA BYTE IN MEMORY
BRA LOAD10 GET NEXT DATA BYTE
LODERR CLRB ;ERROR CONDITION, ZERO CHECKSUM ;
LOAD16 PULS A ADJUST STACK (REMOVE BYTE COUNT)
CMPB #$FF CHECKSUM OK?
BEQ LOAD IF SO, LOAD NEXT LINE
LDA #'? LOAD (?) ERROR INDICATOR
LBSR OUTCH OUTPUT IT TO TERMINAL
LOAD21 COM ECHO TURN ECHO ON
LDA #$13 $FC5F LOAD 'DC3' CASS. READ OFF CODE
LBRA OUTCH OUTPUT IT
*
***** "P" PUNCH MIKBUG TAPE *****
*
PUNCH CLR ,-S CLEAR RESERVED BYTE ON STACK
LBSR IN2ADR GET BEGIN AND END ADDRESS
PSHS X,Y SAVE ADDRESSES ON STACK
BVS PUNEXT (V) C-CODE SET, EXIT PUNCH
CMPX 2,S COMPARE BEGIN TO END ADDR
BCS PUNEXT IF BEGIN GREATER THAN END, EXIT PUNCH
LEAX 1,X INCREMENT END ADDRESS
STX ,S STORE END ADDR ON STACK
LDA #$12 LOAD 'DC2' PUNCH ON CODE
LBSR OUTCH OUTPUT IT TO TERMINAL
PUNCH2 LDD ,S LOAD END ADDR IN D-ACC
SUBD 2,S SUBTRACT BEGIN FROM END
BEQ PUNCH3 SAME, PUNCH 32 BYTES DEFAULT
CMPD #$20 LESS THAN 32 BYTES?
BLS PUNCH4 PUNCH THAT MANY BYTES
PUNCH3 LDB #$20 LOAD BYTE COUNT OF 32.
PUNCH4 STB 4,S STORE ON STACK AS BYTE COUNT
LDX #MSG20 POINT TO MSG "S1"
LBSR PSTRNG PRINT MSG
ADDB #3 ADD 3 BYTES TO BYTE COUNT
TFR B,A GET BYTE COUNT IN A-ACC TO PUNCH
LBSR OUT2H OUTPUT BYTE COUNT
LDX 2,S LOAD BEGIN ADDRESS
LBSR OUT4H PUNCH ADDRESS
ADDB 2,S ADD ADDR MSB TO CHECKSUM
ADDB 3,S ADD ADDR LSB TO CHECKSUM
PUNCHL ADDB ,X ADD DATA BYTE TO CHECKSUM
LDA ,X+ LOAD DATA BYTE TO PUNCH
LBSR OUT2H OUTPUT DATA BYTE
DEC 4,S DECREMENT BYTE COUNT
BNE PUNCHL NOT DONE, PUNCH NEXT BYTE
COMB 1's COMPLIMENT CHECKSUM BYTE
TFR B,A GET IT IN A-ACC TO PUNCH
LBSR OUT2H OUTPUT CHECKSUM BYTE
STX 2,S SAVE X-REG IN STACK AS NEW PUNCH ADDR
CMPX ,S COMPARE IT TO END ADDR
BNE PUNCH2 $FCB5 PUNCH NOT DONE, CONT.
PUNEXT LDA #$14 LOAD 'DC4' PUNCH OFF CODE
LBSR OUTCH OUTPUT IT
LEAS 5,S READJUST STACK POINTER
RTS ;
*
*
PRTSP LDX #MSG10 POINT TO MSG "SP="
LBSR PDATA PRINT MSG
TFR U,X
LBRA OUT4H
PRTUS LDX #MSG12 POINT TO MSG "US="
LBSR PDATA PRINT MSG
LDX 8,U
LBRA OUT4H
PRTDP LDX #MSG15 POINT TO MSG "DP="
LBSR PDATA PRINT MSG
LDA 3,U
LBRA OUT2H OUTPUT HEX BYTE AS ASCII
PRTIX LDX #MSG14 POINT TO MSG "IX="
LBSR PDATA PRINT MSG
LDX 4,U $FCE6
LBRA OUT4H
PRTIY LDX #MSG13 POINT TO MSG "IY="
LBSR PDATA PRINT MSG
LDX 6,U
LBRA OUT4H
PRTPC LDX #MSG11 POINT TO MSG "PC="
LBSR PDATA PRINT MSG
LDX 10,U
BRA OUT4H
PRTA LDX #MSG16 POINT TO MSG "A="
LBSR PDATA PRINT MSG
LDA 1,U
BRA OUT2H OUTPUT HEX BYTE AS ASCII
PRTB LDX #MSG17 POINT TO MSG "B="
LBSR PDATA PRINT MSG
LDA 2,U
BRA OUT2H OUTPUT HEX BYTE AS ASCII
PRTCC LDX #MSG18 POINT TO MSG "CC:"
LBSR PDATA PRINT MSG
LDA ,U
LDX #MSG19 POINT TO MSG "EFHINZVC"
BRA BIASCI OUTPUT IN BINARY/ASCII FORMAT
*
* THE FOLLOWING ROUTINE LOOPS WAITING FOR THE
* OPERATOR TO INPUT TWO VALID HEX ADDRESSES.
* THE FIRST ADDRESS INPUT IS RETURNED IN "IY".
* THE SECOND IS RETURNED IN "IX". THE "V" BIT
* IN THE C-CODE REG. IS SET IF AN INVALID HEX
* ADDRESS IS INPUT.
*
IN2ADR BSR IN1ADR GET FIRST ADDRESS
BVS NOTHEX EXIT IF NOT VALID HEX
TFR X,Y SAVE FIRST ADDR. IN "IY"
LDA #'-
LBSR OUTCH PRINT " - "
*
* THE FOLLOWING ROUTINE LOOPS WAITING FOR THE
* OPERATOR TO INPUT ONE VALID HEX ADDRESS. THE
* ADDRESS IS RETURNED IN THE "X" REGISTER.
*
IN1ADR BSR BYTE INPUT BYTE (2 HEX CHAR)
BVS NOTHEX EXIT IF NOT VALID HEX
TFR D,X
BSR BYTE INPUT BYTE (2 HEX CHAR)
BVS NOTHEX
PSHS X
STA 1,S
PULS X
RTS ;
*
***** INPUT BYTE (2 HEX CHAR.) *****
*
BYTE BSR INHEX GET HEX LEFT
BVS NOTHEX EXIT IF NOT VALID HEX
ASLA ;
ASLA ;
ASLA ; SHIFT INTO LEFT NIBBLE
ASLA ;
TFR A,B PUT HEXL IN "B"
BSR INHEX GET HEX RIGHT
BVS NOTHEX EXIT IF NOT VALID HEX
PSHS B PUSH HEXL ON STACK
ADDA ,S+ ADD HEXL TO HEXR AND ADJ. STK
RTS RETURN WITH HEX L&R IN "A"
*
*
INHEX BSR ECHON INPUT ASCII CHAR.
CMPA #'0 IS IT > OR = "0" ?
BCS NOTHEX IF LESS IT AIN'T HEX
CMPA #'9 IS IT < OR = "9" ?
BHI INHEXA IF > MAYBE IT'S ALPHA
SUBA #$30 ASCII ADJ. NUMERIC
RTS ;
*
*
INHEXA CMPA #'A IS IT > OR = "A"
BCS NOTHEX IF LESS IT AIN'T HEX
CMPA #'F IS IT < OR = "F" ?
BHI INHEXL IF > IT AIN'T HEX
SUBA #$37 ASCII ADJ. ALPHA
RTS ;
*
INHEXL CMPA #'a IS IT > OR = "a"
BCS NOTHEX IF LESS IT AIN'T HEX
CMPA #'f IS IT < "f"
BHI NOTHEX IF > IT AIN'T HEX
SUBA #$57 ADJUST TO LOWER CASE
RTS ;
*
*
NOTHEX ORCC #2 SET (V) FLAG IN C-CODES REGISTER
RTS ;
*
*
OUT4H PSHS X PUSH X-REG. ON THE STACK
PULS A POP MS BYTE OF X-REG INTO A-ACC.
BSR OUTHL OUTPUT HEX LEFT
PULS A POP LS BYTE OF X-REG INTO A-ACC.
OUTHL EQU *
OUT2H PSHS A SAVE IT BACK ON STACK
LSRA CONVERT UPPER HEX NIBBLE TO ASCII
LSRA ;
LSRA ;
LSRA ;
BSR XASCII PRINT HEX NIBBLE AS ASCII
OUTHR PULS A CONVERT LOWER HEX NIBBLE TO ASCII
ANDA #$0F STRIP LEFT NIBBLE
XASCII ADDA #$30 ASCII ADJ
CMPA #$39 IS IT < OR = "9" ?
BLE OUTC IF LESS, OUTPUT IT
ADDA #7 IF > MAKE ASCII LETTER
OUTC BRA OUTCH OUTPUT CHAR
*
* BINARY / ASCII --- THIS ROUTINE
* OUTPUTS A BYTE IN ENHANCED
* BINARY FORMAT. THE ENHANCEMENT
* IS DONE BY SUBSTITUTING ASCII
* LETTERS FOR THE ONES IN THE BYTE.
* THE ASCII ENHANCEMENT LETTERS
* ARE OBTAINED FROM THE STRING
* POINTED TO BY THE INDEX REG. "X".
*
BIASCI PSHS A SAVE "A" ON STACK
LDB #8 PRESET LOOP# TO BITS PER BYTE
OUTBA LDA ,X+ GET LETTER FROM STRING
ASL ,S TEST BYTE FOR "1" IN B7
BCS PRTBA IF ONE PRINT LETTER
LDA #'- IF ZERO PRINT "-"
PRTBA BSR OUTCH PRINT IT
BSR OUT1S PRINT SPACE
DECB SUB 1 FROM #BITS YET TO PRINT
BNE OUTBA
PULS A
RTS
*
* PRINT STRING PRECEEDED BY A CR & LF.
*
PSTRNG BSR PCRLF PRINT CR/LF
BRA PDATA PRINT STRING POINTED TO BY IX
*
* PCRLF
*
PCRLF PSHS X SAVE IX
LDX #MSG2+1 POINT TO MSG CR/LF + 3 NULS
BSR PDATA PRINT MSG
PULS X RESTORE IX
RTS ;
PRINT BSR OUTCH
*
* PDATA
*
PDATA LDA ,X+ GET 1st CHAR. TO PRINT
CMPA #4 IS IT EOT?
BNE PRINT IF NOT EOT PRINT IT
RTS ;
*
*
ECHON TST ECHO IS ECHO REQUIRED ?
BEQ INCH ECHO NOT REQ. IF CLEAR
*
* INCHE
*
* ---GETS CHARACTER FROM TERMINAL AND
* ECHOS SAME. THE CHARACTER IS RETURNED
* IN THE "A" ACCUMULATOR WITH THE PARITY
* BIT MASKED OFF. ALL OTHER REGISTERS
* ARE PRESERVED.
*
INCHE BSR INCH GET CHAR FROM TERMINAL
ANDA #$7F STRIP PARITY FROM CHAR.
BRA OUTCH ECHO CHAR TO TERMINAL
*
* INCH
*
* GET CHARACTER FROM TERMINAL. RETURN
* CHARACTER IN "A" ACCUMULATOR AND PRESERVE
* ALL OTHER REGISTERS. THE INPUT CHARACTER
* IS 8 BITS AND IS NOT ECHOED.
*
*
INCH PSHS X SAVE IX
LDX CPORT POINT TO TERMINAL PORT
GETSTA LDA ,X FETCH PORT STATUS
BITA #1 TEST READY BIT, RDRF ?
BEQ GETSTA IF NOT RDY, THEN TRY AGAIN
LDA 1,X FETCH CHAR
PULS X RESTORE IX
RTS ;
*
* INCHEK
*
* CHECK FOR A CHARACTER AVAILABLE FROM
* THE TERMINAL. THE SERIAL PORT IS CHECKED
* FOR READ READY. ALL REGISTERS ARE
* PRESERVED, AND THE "Z" BIT WILL BE
* CLEAR IF A CHARACTER CAN BE READ.
*
*
INCHEK PSHS A SAVE A ACCUM.
LDA [CPORT] FETCH PORT STATUS
BITA #1 TEST READY BIT, RDRF ?
PULS A RESTORE A ACCUM.
RTS ;
*
OUT2S BSR OUT1S OUTPUT 2 SPACES
OUT1S LDA #$20 OUTPUT 1 SPACE
*
*
* OUTCH
*
* OUTPUT CHARACTER TO TERMINAL.
* THE CHAR. TO BE OUTPUT IS
* PASSED IN THE A REGISTER.
* ALL REGISTERS ARE PRESERVED.
*
OUTCH PSHS A,X SAVE A ACCUM AND IX
LDX CPORT GET ADDR. OF TERMINAL
FETSTA LDA ,X FETCH PORT STATUS
BITA #2 TEST TDRE, OK TO XMIT ?
BEQ FETSTA IF NOT LOOP UNTIL RDY
PULS A GET CHAR. FOR XMIT
STA 1,X XMIT CHAR.
PULS X RESTORE IX
RTS ;
*
*
ACINIZ LDX CPORT POINT TO CONTROL PORT ADDRESS
LDA #3 RESET ACIA PORT CODE
STA ,X STORE IN CONTROL REGISTER
LDA #$11 SET 8 DATA, 2 STOP AN 0 PARITY
STA ,X STORE IN CONTROL REGISTER
TST 1,X ANYTHING IN DATA REGISTER?
LDA #$FF TURN ON ECHO FLAG
STA ECHO
RTS
*
*
* MONITOR KEYBOARD COMMAND JUMP TABLE
*
*
JMPTAB EQU *
FCB 1 " ^A " $F91D
FDB ALTRA
FCB 2 " ^B " $F90F
FDB ALTRB
FCB 3 " ^C " $F92B
FDB ALTRCC
FCB 4 " ^D " $F901
FDB ALTRDP
FCB $10 " ^P " $F8C9
FDB ALTRPC
FCB $15 " ^U " $F8D7
FDB ALTRU
FCB $18 " ^X " $F8F3
FDB ALTRX
FCB $19 " ^Y " $F8E5
FDB ALTRY
*
FCC 'B'
FDB BRKPNT *$FA78
FCC 'D'
FDB DBOOT *$FAF1
FCC 'E'
FDB MEMDUMP *$F990
FCC 'G'
FDB GO *$F89F
FCC 'L'
FDB LOAD *$FC09
FCC 'M'
FDB MEMCHG *$F93B
FCC 'P'
FDB PUNCH *$FC64
FCC 'Q'
FDB MEMTST *$F9EF
FCC 'R'
FDB REGSTR *$F8A2
FCC 'S'
FDB DISSTK *$F984
FCC 'U'
FDB MINBOOT *$FBB0
FCC 'X'
FDB XBKPNT *$FAA4
*
TABEND EQU *
*
* ** 6809 VECTOR ADDRESSES **
*
* FOLLOWING ARE THE ADDRESSES OF THE VECTOR ROUTINES
* FOR THE 6809 PROCESSOR. DURING INITIALIZATION THEY
* ARE RELOCATED TO RAM FROM $DFC0 TO $DFCF. THEY ARE
* RELOCATED TO RAM SO THAT THE USER MAY REVECTOR TO
* HIS OWN ROUTINES IF HE SO DESIRES.
*
*
RAMVEC FDB SWIE USER-V
FDB RTI SWI3-V
FDB RTI SWI2-V
FDB RTI FIRQ-V
FDB RTI IRQ-V
FDB SWIE SWI-V
FDB $FFFF SVC-VO
FDB $FFFF SVC-VL
*
* PRINTABLE MESSAGE STRINGS
*
MSG1 FCB $0,$0,$0,$D,$A,$0,$0,$0 * 0, CR/LF, 0
FCC 'S-BUG 1.8 - '
FCB 4
MSG2 FCB 'K,$D,$A,$0,$0,$0,4 K, * CR/LF + 3 NULS
MSG3 FCC '>'
FCB 4
MSG4 FCC 'WHAT?'
FCB 4
MSG5 FCC ' - '
FCB 4'
MSG6 FCC ', PASS '
FCB 4
MSG7 FCC ', BITS IN ERROR: '
FCB 4
MSG8 FCC ' => '
FCB 4
MSG9 FCC '76543210'
MSG10 FCC ' SP='
FCB 4
MSG11 FCC ' PC='
FCB 4
MSG12 FCC ' US='
FCB 4
MSG13 FCC ' IY='
FCB 4
MSG14 FCC ' IX='
FCB 4
MSG15 FCC ' DP='
FCB 4
MSG16 FCC ' A='
FCB 4
MSG17 FCC ' B='
FCB 4
MSG18 FCC ' CC: '
FCB 4
MSG19 FCC 'EFHINZVC'
MSG20 FCC 'S1'
FCB 4
*
* MESSAGE EXPANSION AREA
*
FCB $FF,$FF,$FF,$FF,$FF,$FF,$FF,$FF
FCB $FF,$FF,$FF,$FF,$FF,$FF,$FF
*
* POWER UP/ RESET/ NMI ENTRY POINT
*
ORG $FF00
*
*
START LDX #IC11 POINT TO DAT RAM IC11
LDA #$F GET COMPLIMENT OF ZERO
*
*
* INITIALIZE DAT RAM --- LOADS $F-$0 IN LOCATIONS $0-$F
* OF DAT RAM, THUS STORING COMPLEMENT OF MSB OF ADDRESS
* IN THE DAT RAM. THE COMPLEMENT IS REQUIRED BECAUSE THE
* OUTPUT OF IC11, A 74S189, IS THE INVERSE OF THE DATA
* STORED IN IT.
*
*
DATLP STA ,X+ STORE & POINT TO NEXT RAM LOCATION
DECA GET COMP. VALUE FOR NEXT LOCATION
BNE DATLP ALL 16 LOCATIONS INITIALIZED ?
*
* NOTE: IX NOW CONTAINS $0000, DAT RAM IS NO LONGER
* ADDRESSED, AND LOGICAL ADDRESSES NOW EQUAL
* PHYSICAL ADDRESSES.
*
LDA #$F0
STA ,X STORE $F0 AT $FFFF
LDX #$D0A0 ASSUME RAM TO BE AT $D000-$DFFF
LDY #TSTPAT LOAD TEST DATA PATTERN INTO "Y"
TSTRAM LDU ,X SAVE DATA FROM TEST LOCATION
STY ,X STORE TEST PATTERN AT $D0A0
CMPY ,X IS THERE RAM AT THIS LOCATION ?
BEQ CNVADR IF MATCH THERE'S RAM, SO SKIP
LEAX -$1000,X ELSE POINT 4K LOWER
CMPX #$F0A0 DECREMENTED PAST ZER0 YET ?
BNE TSTRAM IF NOT CONTINUE TESTING FOR RAM
BRA START ELSE START ALL OVER AGAIN
*
*
* THE FOLLOWING CODE STORES THE COMPLEMENT OF
* THE MS CHARACTER OF THE FOUR CHARACTER HEX
* ADDRESS OF THE FIRST 4K BLOCK OF RAM LOCATED
* BY THE ROUTINE "TSTRAM" INTO THE DAT RAM. IT
* IS STORED IN RAM IN THE LOCATION THAT IS
* ADDRESSED WHEN THE PROCESSOR ADDRESS IS $D---,
* THUS IF THE FIRST 4K BLOCK OF RAM IS FOUND
* WHEN TESTING LOCATION $70A0, MEANING THERE
* IS NO RAM PHYSICALLY ADDRESSED IN THE RANGE
* $8000-$DFFF, THEN THE COMPLEMENT OF THE
* "7" IN THE $70A0 WILL BE STORED IN
* THE DAT RAM. THUS WHEN THE PROCESSOR OUTPUTS
* AN ADDRESS OF $D---, THE DAT RAM WILL RESPOND
* BY RECOMPLEMENTING THE "7" AND OUTPUTTING THE
* 7 ONTO THE A12-A15 ADDRESS LINES. THUS THE
* RAM THAT IS PHYSICALLY ADDRESSED AT $7---
* WILL RESPOND AND APPEAR TO THE 6809 THAT IT
* IS AT $D--- SINCE THAT IS THE ADDRESS THE
* 6809 WILL BE OUTPUTING WHEN THAT 4K BLOCK
* OF RAM RESPONDS.
*
*
CNVADR STU ,X RESTORE DATA AT TEST LOCATION
TFR X,D PUT ADDR. OF PRESENT 4K BLOCK IN D
COMA COMPLEMENT MSB OF THAT ADDRESS
LSRA PUT MS 4 BITS OF ADDRESS IN
LSRA LOCATION D0-D3 TO ALLOW STORING
LSRA IT IN THE DYNAMIC ADDRESS
LSRA TRANSLATION RAM.
STA $FFFD STORE XLATION FACTOR IN DAT "D"
*
LDS #STACK INITIALIZE STACK POINTER
*
*
* THE FOLLOWING CHECKS TO FIND THE REAL PHYSICAL ADDRESSES
* OF ALL 4K BLKS OF RAM IN THE SYSTEM. WHEN EACH 4K BLK
* OF RAM IS LOCATED, THE COMPLEMENT OF IT'S REAL ADDRESS
* IS THEN STORED IN A "LOGICAL" TO "REAL" ADDRESS XLATION
* TABLE THAT IS BUILT FROM $DFD0 TO $DFDF. FOR EXAMPLE IF
* THE SYSTEM HAS RAM THAT IS PHYSICALLY LOCATED (WIRED TO
* RESPOND) AT THE HEX LOCATIONS $0--- THRU $F---....
*
* 0 1 2 3 4 5 6 7 8 9 A B C D E F
* 4K 4K 4K 4K 4K 4K 4K 4K -- 4K 4K 4K 4K -- -- --
*
* ....FOR A TOTAL OF 48K OF RAM, THEN THE TRANSLATION TABLE
* CREATED FROM $DFD0 TO $DFDF WILL CONSIST OF THE FOLLOWING....
*
* 0 1 2 3 4 5 6 7 8 9 A B C D E F
* 0F 0E 0D 0C 0B 0A 09 08 06 05 00 00 04 03 F1 F0
*
*
* HERE WE SEE THE LOGICAL ADDRESSES OF MEMORY FROM $0000-$7FFF
* HAVE NOT BEEN SELECTED FOR RELOCATION SO THAT THEIR PHYSICAL
* ADDRESS WILL = THEIR LOGICAL ADDRESS; HOWEVER, THE 4K BLOCK
* PHYSICALLY AT $9000 WILL HAVE ITS ADDRESS TRANSLATED SO THAT
* IT WILL LOGICALLY RESPOND AT $8000. LIKEWISE $A,$B, AND $C000
* WILL BE TRANSLATED TO RESPOND TO $9000,$C000, AND $D000
* RESPECTIVELY. THE USER SYSTEM WILL LOGICALLY APPEAR TO HAVE
* MEMORY ADDRESSED AS FOLLOWS....
*
* 0 1 2 3 4 5 6 7 8 9 A B C D E F
* 4K 4K 4K 4K 4K 4K 4K 4K 4K 4K -- -- 4K 4K -- --
*
*
LDY #LRARAM POINT TO LOGICAL/REAL ADDR. TABLE
STA 13,Y STORE $D--- XLATION FACTOR AT $DFDD
CLR 14,Y CLEAR $DFDE
LDA #$F0 DESTINED FOR IC8 AN MEM EXPANSION ?
STA 15,Y STORE AT $DFDF
LDA #$0C PRESET NUMBER OF BYTES TO CLEAR
CLRLRT CLR A,Y CLEAR $DFDC THRU $DFD0
DECA SUB. 1 FROM BYTES LEFT TO CLEAR
BPL CLRLRT CONTINUE IF NOT DONE CLEARING
FNDRAM LEAX -$1000,X POINT TO NEXT LOWER 4K OF RAM
CMPX #$F0A0 TEST FOR DECREMENT PAST ZERO
BEQ FINTAB SKIP IF FINISHED
LDU ,X SAVE DATA AT CURRENT TEST LOCATION
LDY #TSTPAT LOAD TEST DATA PATTERN INTO Y REG.
STY ,X STORE TEST PATT. INTO RAM TEST LOC.
CMPY ,X VERIFY RAM AT TEST LOCATION
BNE FNDRAM IF NO RAM GO LOOK 4K LOWER
STU ,X ELSE RESTORE DATA TO TEST LOCATION
LDY #LRARAM POINT TO LOGICAL/REAL ADDR. TABLE
TFR X,D PUT ADDR. OF PRESENT 4K BLOCK IN D
LSRA PUT MS 4 BITS OF ADDR. IN LOC. D0-D3
LSRA TO ALLOW STORING IT IN THE DAT RAM.
LSRA
LSRA
TFR A,B SAVE OFFSET INTO LRARAM TABLE
EORA #$0F INVERT MSB OF ADDR. OF CURRENT 4K BLK
STA B,Y SAVE TRANSLATION FACTOR IN LRARAM TABLE
BRA FNDRAM GO TRANSLATE ADDR. OF NEXT 4K BLK
FINTAB LDA #$F1 DESTINED FOR IC8 AND MEM EXPANSION ?
LDY #LRARAM POINT TO LRARAM TABLE
STA 14,Y STORE $F1 AT $DFCE
*
* THE FOLLOWING CHECKS TO SEE IF THERE IS A 4K BLK OF
* RAM LOCATED AT $C000-$CFFF. IF NONE THERE IT LOCATES
* THE NEXT LOWER 4K BLK AN XLATES ITS ADDR SO IT
* LOGICALLY RESPONDS TO THE ADDRESS $C---.
*
*
LDA #$0C PRESET NUMBER HEX "C"
FINDC LDB A,Y GET ENTRY FROM LRARAM TABLE
BNE FOUNDC BRANCH IF RAM THIS PHYSICAL ADDR.
DECA ELSE POINT 4K LOWER
BPL FINDC GO TRY AGAIN
BRA XFERTF
FOUNDC CLR A,Y CLR XLATION FACTOR OF 4K BLOCK FOUND
STB $C,Y GIVE IT XLATION FACTOR MOVING IT TO $C---
*
* THE FOLLOWING CODE ADJUSTS THE TRANSLATION
* FACTORS SUCH THAT ALL REMAINING RAM WILL
* RESPOND TO A CONTIGUOUS BLOCK OF LOGICAL
* ADDRESSES FROM $0000 AND UP....
*
CLRA START AT ZERO
TFR Y,X START POINTER "X" START OF "LRARAM" TABLE.
COMPRS LDB A,Y GET ENTRY FROM "LRARAM" TABLE
BEQ PNTNXT IF IT'S ZER0 SKIP
CLR A,Y ELSE ERASE FROM TABLE
STB ,X+ AND ENTER ABOVE LAST ENTRY- BUMP
PNTNXT INCA GET OFFSET TO NEXT ENTRY
CMPA #$0C LAST ENTRY YET ?
BLT COMPRS
*
* THE FOLLOWING CODE TRANSFER THE TRANSLATION
* FACTORS FROM THE LRARAM TABLE TO IC11 ON
* THE MP-09 CPU CARD.
*
XFERTF LDX #IC11 POINT TO DAT RAM IC11
LDB #$10 GET NO. OF BYTES TO MOVE
FETCH LDA ,Y+ GET BYTE AND POINT TO NEXT
STA ,X+ POKE XLATION FACTOR IN IC11
DECB SUB 1 FROM BYTES TO MOVE
BNE FETCH CONTINUE UNTIL 16 MOVED
COMB SET "B" NON-ZERO
STB ECHO TURN ON ECHO FLAG
LBRA MONITOR INITIALIZATION IS COMPLETE
*
*
V1 JMP [STACK]
V2 JMP [SWI2]
V3 JMP [FIRQ]
V4 JMP [IRQ]
V5 JMP [SWI]
*
* SWI3 ENTRY POINT
*
SWI3E TFR S,U
LDX 10,U *$FFC8
LDB ,X+
STX 10,U
CLRA
ASLB
ROLA
LDX SVCVO
CMPX #$FFFF
BEQ SWI3Z
LEAX D,X
CMPX SVCVL
BHI SWI3Z
PSHS X
LDD ,U
LDX 4,U
JMP [,S++]
SWI3Z PULU A,B,X,CC,DP
LDU 2,U
JMP [SWI3]
*
* 6809 VECTORS
*
FDB V1 USER-V
FDB SWI3E SWI3-V
FDB V2 SWI2-V
FDB V3 FIRQ-V
FDB V4 IRQ-V
FDB V5 SWI-V
FDB V1 NMI-V
FDB START RESTART-V
END START
/sbug_src.lst
0,0 → 1,1412
0001 * NAM SBUG18 MP-09 MONITOR
0002 OPT l
sbug_src.txt page 2
0004 *
0005 * MONITOR PROGRAM FOR THE SOUTHWEST TECHNICAL
0006 * PRODUCTS MP-09 CPU BOARD AS COMMENTED BY....
0007 *
0008 * ALLEN CLARK WALLACE WATSON
0009 * 2502 REGAL OAKS LANE 4815 EAST 97th AVE.
0010 * LUTZ, FLA. 33549 TEMPLE TERRACE, FLA. 33617
0011 * PH. 813-977-0347 PH. 813-985-1359
0012 *
0013 * MODIFIED TO SBUG09 VER 1.8 BY: RANDY JARRETT
0014 * 2561 NANTUCKET DR APT. E
0015 * ATLANTA, GA 30345
0016 * PH. 404-320-1043
0017 *
0018 *
0019 * *** COMMANDS ***
0020 *
0021 * CONTROL A = ALTER THE "A" ACCUMULATOR
0022 * CONTROL B = ALTER THE "B" ACCUMULATOR
0023 * CONTROL C = ALTER THE CONDITION CODE REGISTER
0024 * CONTROL D = ALTER THE DIRECT PAGE REGISTER
0025 * CONTROL P = ALTER THE PROGRAM COUNTER
0026 * CONTROL U = ALTER USER STACK POINTER
0027 * CONTROL X = ALTER "X" INDEX REGISTER
0028 * CONTROL Y = ALTER "Y" INDEX REGISTER
0029 * B hhhh = SET BREAKPOINT AT LOCATION $hhhh
0030 * D = BOOT A SWTPC 8 INCH FLOPPY SYSTEM
0031 * U = BOOT A SWTPC 5 INCH FLOPPY SYSTEM
0032 * E ssss-eeee = EXAMINE MEMORY FROM STARTING ADDRESS ssss
0033 * -TO ENDING ADDRESS eeee.
0034 * G = CONTINUE EXECUTION FROM BREAKPOINT OR SWI
0035 * L = LOAD TAPE
0036 * M hhhh = EXAMINE AND CHANGE MEMORY LOCATION hhhh
0037 * P ssss-eeee = PUNCH TAPE, START ssss TO END eeee ADDR.
0038 * Q ssss-eeee = TEST MEMORY FROM ssss TO eeee
0039 * R = DISPLAY REGISTER CONTENTS
0040 * S = DISPLAY STACK FROM ssss TO $DFC0
0041 * X = REMOVE ALL BREAKPOINTS
0042 *
0043 *
0044 55aa TSTPAT EQU $55AA TEST PATTERN
0045 *
0046 *
0047 *
0048 dfc0 ORG $DFC0
0049 dfc0 STACK RMB 2 TOP OF INTERNAL STACK / USER VECTOR
0050 dfc2 SWI3 RMB 2 SOFTWARE INTERRUPT VECTOR #3
0051 dfc4 SWI2 RMB 2 SOFTWARE INTERRUPT VECTOR #2
0052 dfc6 FIRQ RMB 2 FAST INTERRUPT VECTOR
0053 dfc8 IRQ RMB 2 INTERRUPT VECTOR
0054 dfca SWI RMB 2 SOFTWARE INTERRUPT VECTOR
0055 dfcc SVCVO RMB 2 SUPERVISOR CALL VECTOR ORGIN
0056 dfce SVCVL RMB 2 SUPERVISOR CALL VECTOR LIMIT
0057 dfd0 LRARAM RMB 16 LRA ADDRESSES
0058 dfe0 CPORT RMB 2 RE-VECTORABLE CONTROL PORT
0059 dfe2 ECHO RMB 1 ECHO FLAG
0060 dfe3 BPTBL RMB 24 BREAKPOINT TABLE BASE ADDR
0061 e004 ACIAS EQU $E004 CONTROL PORT
0062 e018 Comreg EQU $E018 COMMAND REGISTER
0063 e014 Drvreg EQU $E014 DRIVE REGISTER
0064 e01a Secreg EQU $E01A SECTOR REGISTER
0065 e01b Datreg EQU $E01B DATA REGISTER
0066 *
0067 f000 ADDREG EQU $F000 ADDRESS REGISTER
0068 f002 CNTREG EQU $F002 COUNT REGISTER
0069 f010 CCREG EQU $F010 CHANNEL CONTROL REGISTER
0070 f014 PRIREG EQU $F014 DMA PRIORITY REGISTER
0071 f015 AAAREG EQU $F015 ???
0072 f016 BBBREG EQU $F016 ???
0073 f020 COMREG EQU $F020 1791 COMMAND REGISTER
0074 f022 SECREG EQU $F022 SECTOR REGISTER
0075 f024 DRVREG EQU $F024 DRIVE SELECT LATCH
0076 f040 CCCREG EQU $F040 ???
0077 *
0078 fff0 IC11 EQU $FFF0 DAT RAM CHIP
0079 *
0080 f800 ORG $F800
0081 f800 f8 14 FDB MONITOR
0082 f802 f8 61 FDB NEXTCMD
0083 f804 fd cf FDB INCH
0084 f806 fd c9 FDB INCHE
0085 f808 fd df FDB INCHEK
0086 f80a fd ee FDB OUTCH
0087 f80c fd bd FDB PDATA
0088 f80e fd b1 FDB PCRLF
0089 f810 fd ad FDB PSTRNG
0090 f812 fb 81 FDB LRA
0091 *
0092 * MONITOR
0093 *
0094 * VECTOR ADDRESS STRING IS.....
0095 * $F8A1-$F8A1-$F8A1-$F8A1-$F8A1-$FAB0-$FFFF-$FFFF
0096 *
0097 f814 8e fe 4f MONITOR LDX #RAMVEC POINT TO VECTOR ADDR. STRING
0098 f817 10 8e df c0 LDY #STACK POINT TO RAM VECTOR LOCATION
0099 f81b c6 10 LDB #$10 BYTES TO MOVE = 16
0100 f81d a6 80 LOOPA LDA ,X+ GET VECTOR BYTE
0101 f81f a7 a0 STA ,Y+ PUT VECTORS IN RAM / $DFC0-$DFCF
0102 f821 5a DECB SUBTRACT 1 FROM NUMBER OF BYTES TO MOVE
0103 f822 26 f9 BNE LOOPA CONTINUE UNTIL ALL VECTORS MOVED
0104 *
0105 * CONTENTS FROM TO FUNCTION
0106 * $F8A1 $FE40 $DFC0 USER-V
0107 * $F8A1 $FE42 $DFC2 SWI3-V
0108 * $F8A1 $FE44 $DFC4 SWI2-V
0109 * $F8A1 $FE46 $DFC6 FIRQ-V
0110 * $F8A1 $FE48 $DFC8 IRQ-V
0111 * $FAB0 $FE4A $DFCA SWI-V
0112 * $FFFF $FE4C $DFCC SVC-VO
0113 * $FFFF $FE4E $DFCE SVC-VL
0114 *
0115 f824 8e e0 04 LDX #ACIAS GET CONTROL PORT ADDR.
0116 f827 bf df e0 STX CPORT STORE ADDR. IN RAM
0117 f82a 17 02 7a LBSR XBKPNT CLEAR OUTSTANDING BREAKPOINTS
0118 f82d c6 0c LDB #12 CLEAR 12 BYTES ON STACK
0119 f82f 6f e2 CLRSTK CLR ,-S
0120 f831 5a DECB
0121 f832 26 fb BNE CLRSTK
0122 f834 30 8c dd LEAX MONITOR,PCR SET PC TO SBUG-E ENTRY
0123 f837 af 6a STX 10,S ON STACK
0124 f839 86 d0 LDA #$D0 PRESET CONDITION CODES ON STACK
0125 f83b a7 e4 STA ,S
0126 f83d 1f 43 TFR S,U
0127 f83f 17 05 be LBSR ACINIZ INITIALIZE CONTROL PORT
0128 f842 8e fe 5f LDX #MSG1 POINT TO 'SBUG 1.8' MESSAGE
0129 f845 17 05 75 LBSR PDATA PRINT MSG
0130 f848 8e df d0 LDX #LRARAM POINT TO LRA RAM STORAGE AREA
0131 f84b 4f CLRA START TOTAL AT ZERO
0132 f84c c6 0d LDB #13 TOTAL UP ALL ACTIVE RAM MEMORY
0133 f84e 6d 85 FNDREL TST B,X TEST FOR RAM AT NEXT LOC.
0134 f850 27 03 BEQ RELPAS IF NO RAM GO TO NEXT LOC.
0135 f852 8b 04 ADDA #4 ELSE ADD 4K TO TOTAL
0136 f854 19 DAA ADJ. TOTAL FOR DECIMAL
0137 f855 5a RELPAS DECB SUB. 1 FROM LOCS. TO TEST
0138 f856 2a f6 BPL FNDREL PRINT TOTAL OF RAM
0139 f858 17 05 26 LBSR OUT2H OUTPUT HEX BYTE AS ASCII
0140 f85b 8e fe 74 LDX #MSG2 POINT TO MSG 'K' CR/LF + 3 NULS
0141 f85e 17 05 5c LBSR PDATA PRINT MSG
0142 *
0143 ***** NEXTCMD *****
0144 *
0145 f861 8e fe 7b NEXTCMD LDX #MSG3 POINT TO MSG ">"
0146 f864 17 05 46 LBSR PSTRNG PRINT MSG
0147 f867 17 05 65 LBSR INCH GET ONE CHAR. FROM TERMINAL
0148 f86a 84 7f ANDA #$7F STRIP PARITY FROM CHAR.
0149 f86c 81 0d CMPA #$0D IS IT CARRIAGE RETURN ?
0150 f86e 27 f1 BEQ NEXTCMD IF CR THEN GET ANOTHER CHAR.
0151 f870 1f 89 TFR A,B PUT CHAR. IN "B" ACCUM.
0152 f872 81 20 CMPA #$20 IS IT CONTROL OR DATA CHAR ?
0153 f874 2c 09 BGE PRTCMD IF CMD CHAR IS DATA, PRNT IT
0154 f876 86 5e LDA #'^ ELSE CNTRL CHAR CMD SO...
0155 f878 17 05 73 LBSR OUTCH PRINT "^"
0156 f87b 1f 98 TFR B,A RECALL CNTRL CMD CHAR
0157 f87d 8b 40 ADDA #$40 CONVERT IT TO ASCII LETTER
0158 f87f 17 05 6c PRTCMD LBSR OUTCH PRNT CMD CHAR
0159 f882 17 05 67 LBSR OUT1S PRNT SPACE
0160 f885 c1 60 CMPB #$60
0161 f887 2f 02 BLE NXTCH0
0162 f889 c0 20 SUBB #$20
0163 *
0164 *
0165 ***** DO TABLE LOOKUP *****
0166 * FOR COMMAND FUNCTIONS
0167 *
0168 *
0169 f88b 8e fe 13 NXTCH0 LDX #JMPTAB POINT TO JUMP TABLE
0170 f88e e1 80 NXTCHR CMPB ,X+ DOES COMMAND MATCH TABLE ENTRY ?
0171 f890 27 0f BEQ JMPCMD BRANCH IF MATCH FOUND
0172 f892 30 02 LEAX 2,X POINT TO NEXT ENTRY IN TABLE
0173 f894 8c fe 4f CMPX #TABEND REACHED END OF TABLE YET ?
0174 f897 26 f5 BNE NXTCHR IF NOT END, CHECK NEXT ENTRY
0175 f899 8e fe 7d LDX #MSG4 POINT TO MSG "WHAT?"
0176 f89c 17 05 1e LBSR PDATA PRINT MSG
0177 f89f 20 c0 BRA NEXTCMD IF NO MATCH, PRMPT FOR NEW CMD
0178 f8a1 ad 94 JMPCMD JSR [,X] JUMP TO COMMAND ROUTINE
0179 f8a3 20 bc BRA NEXTCMD PROMPT FOR NEW COMMAND
0180 *
0181 * "G" GO OR CONTINUE
0182 *
0183 f8a5 1f 34 GO TFR U,S
0184 f8a7 3b RTI RTI
0185 *
0186 * "R" DISPLAY REGISTERS
0187 *
0188 f8a8 8e fe 83 REGSTR LDX #MSG5 POINT TO MSG " - "
0189 f8ab 17 04 ff LBSR PSTRNG PRINT MSG
0190 f8ae 17 04 11 LBSR PRTSP $FCBF
0191 f8b1 17 04 19 LBSR PRTUS $FCCA
0192 f8b4 17 04 21 LBSR PRTDP $FCD5
0193 f8b7 17 04 29 LBSR PRTIX $FCE0
0194 f8ba 17 04 31 LBSR PRTIY $FCEB
0195 f8bd 8e fe 83 LDX #MSG5 POINT TO MSG " - "
0196 f8c0 17 04 ea LBSR PSTRNG PRINT MSG
0197 f8c3 17 04 33 LBSR PRTPC $FCF5
0198 f8c6 17 04 3a LBSR PRTA $FCFF
0199 f8c9 17 04 41 LBSR PRTB $FD09
0200 f8cc 16 04 48 LBRA PRTCC $FD13
0201 *
0202 *
0203 * ALTER "PC" PROGRAM COUNTER
0204 *
0205 *
0206 f8cf 17 04 27 ALTRPC LBSR PRTPC $FCF5 PRINT MSG " PC = "
0207 f8d2 17 05 17 LBSR OUT1S OUTPUT SPACE
0208 f8d5 17 04 57 LBSR IN1ADR GET NEW CONTENTS FOR "PC"
0209 f8d8 29 02 BVS ALTPCD EXIT IF INVALID HEX
0210 f8da af 4a STX 10,U POKE IN NEW CONTENTS
0211 f8dc 39 ALTPCD RTS ;
0212 *
0213 *
0214 * ALTER "U" USER STACK POINTER
0215 *
0216 *
0217 f8dd 17 03 ed ALTRU LBSR PRTUS $FCCA PRINT MSG " US = "
0218 f8e0 17 05 09 LBSR OUT1S OUTPUT SPACE
0219 f8e3 17 04 49 LBSR IN1ADR
0220 f8e6 29 02 BVS ALTUD
0221 f8e8 af 48 STX 8,U
0222 f8ea 39 ALTUD RTS ;
0223 *
0224 *
0225 * ALTER "Y" INDEX REGISTER
0226 *
0227 *
0228 f8eb 17 04 00 ALTRY LBSR PRTIY PRINT MSG " IY = "
0229 f8ee 17 04 fb LBSR OUT1S OUTPUT SPACE
0230 f8f1 17 04 3b LBSR IN1ADR
0231 f8f4 29 02 BVS ALTYD
0232 f8f6 af 46 STX 6,U $F8F0
0233 f8f8 39 ALTYD RTS ;
0234 *
0235 *
0236 * ALTER "X" INDEX REGISTER
0237 *
0238 *
0239 f8f9 17 03 e7 ALTRX LBSR PRTIX $FCE0 PRINT MSG " IX = "
0240 f8fc 17 04 ed LBSR OUT1S OUTPUT SPACE
0241 f8ff 17 04 2d LBSR IN1ADR
0242 f902 29 02 BVS ALTXD
0243 f904 af 44 STX 4,U
0244 f906 39 ALTXD RTS ;
0245 *
0246 *
0247 * ALTER "DP" DIRECT PAGE REGISTER
0248 *
0249 *
0250 f907 17 03 ce ALTRDP LBSR PRTDP $FCD5 PRINT MSG " DP = "
0251 f90a 17 04 df LBSR OUT1S OUTPUT SPACE
0252 f90d 17 04 30 LBSR BYTE INPUT BYTE (2 HEX CHAR)
0253 f910 29 02 BVS ALTDPD
0254 f912 a7 43 STA 3,U
0255 f914 39 ALTDPD RTS ;
0256 *
0257 *
0258 * ALTER "B" ACCUMULATOR
0259 *
0260 *
0261 f915 17 03 f5 ALTRB LBSR PRTB $FD09 PRINT MSG " B = "
0262 f918 17 04 d1 LBSR OUT1S OUTPUT SPACE
0263 f91b 17 04 22 LBSR BYTE INPUT BYTE (2 HEX CHAR)
0264 f91e 29 02 BVS ALTBD
0265 f920 a7 42 STA 2,U
0266 f922 39 ALTBD RTS $F91C
0267 *
0268 *
0269 * ALTER "A" ACCUMULATOR
0270 *
0271 *
0272 f923 17 03 dd ALTRA LBSR PRTA $FCFF RINT MSG " A = "
0273 f926 17 04 c3 LBSR OUT1S OUTPUT SPACE
0274 f929 17 04 14 LBSR BYTE INPUT BYTE (2 HEX CHAR)
0275 f92c 29 02 BVS ALTAD
0276 f92e a7 41 STA 1,U
0277 f930 39 ALTAD RTS ;
0278 *
0279 *
0280 * ALTER "CC" REGISTER
0281 *
0282 *
0283 f931 17 03 e3 ALTRCC LBSR PRTCC $FD13 PRINT MSG " CC: "
0284 f934 17 04 b5 LBSR OUT1S OUTPUT SPACE
0285 f937 17 04 06 LBSR BYTE INPUT BYTE (2 HEX CHAR)
0286 f93a 29 04 BVS ALTCCD
0287 f93c 8a 80 ORA #$80 SETS "E" FLAG IN PRINT LIST
0288 f93e a7 c4 STA ,U
0289 f940 39 ALTCCD RTS ;
0290 *
0291 ***** "M" MEMORY EXAMINE AND CHANGE *****
0292 *
0293 f941 17 03 eb MEMCHG LBSR IN1ADR INPUT ADDRESS
0294 f944 29 2d BVS CHRTN IF NOT HEX, RETURN
0295 f946 1f 12 TFR X,Y SAVE ADDR IN "Y"
0296 f948 8e fe 83 MEMC2 LDX #MSG5 POINT TO MSG " - "
0297 f94b 17 04 5f LBSR PSTRNG PRINT MSG
0298 f94e 1f 21 TFR Y,X FETCH ADDRESS
0299 f950 17 04 26 LBSR OUT4H PRINT ADDR IN HEX
0300 f953 17 04 96 LBSR OUT1S OUTPUT SPACE
0301 f956 a6 a4 LDA ,Y GET CONTENTS OF CURRENT ADDR.
0302 f958 17 04 26 LBSR OUT2H OUTPUT CONTENTS IN ASCII
0303 f95b 17 04 8e LBSR OUT1S OUTPUT SPACE
0304 f95e 17 03 df LBSR BYTE LOOP WAITING FOR OPERATOR INPUT
0305 f961 28 11 BVC CHANGE IF VALID HEX GO CHANGE MEM. LOC.
0306 f963 81 08 CMPA #8 IS IT A BACKSPACE (CNTRL H)?
0307 f965 27 e1 BEQ MEMC2 PROMPT OPERATOR AGAIN
0308 f967 81 18 CMPA #$18 IS IT A CANCEL (CNTRL X)?
0309 f969 27 dd BEQ MEMC2 PROMPT OPERATOR AGAIN
0310 f96b 81 5e CMPA #'^ IS IT AN UP ARROW?
0311 f96d 27 17 BEQ BACK DISPLAY PREVIOUS BYTE
0312 f96f 81 0d CMPA #$D IS IT A CR?
0313 f971 26 0f BNE FORWRD DISPLAY NEXT BYTE
0314 f973 39 CHRTN RTS EXIT ROUTINE
0315 *
0316 *
0317 f974 a7 a4 CHANGE STA ,Y CHANGE BYTE IN MEMORY
0318 f976 a1 a4 CMPA ,Y DID MEMORY BYTE CHANGE?
0319 f978 27 08 BEQ FORWRD $F972
0320 f97a 17 04 6f LBSR OUT1S OUTPUT SPACE
0321 f97d 86 3f LDA #'? LOAD QUESTION MARK
0322 f97f 17 04 6c LBSR OUTCH PRINT IT
0323 f982 31 21 FORWRD LEAY 1,Y POINT TO NEXT HIGHER MEM LOCATION
0324 f984 20 c2 BRA MEMC2 PRINT LOCATION & CONTENTS
0325 f986 31 3f BACK LEAY -1,Y POINT TO LAST MEM LOCATION
0326 f988 20 be BRA MEMC2 PRINT LOCATION & CONTENTS
0327 *
0328 * "S" DISPLAY STACK
0329 * HEX-ASCII DISPLAY OF CURRENT STACK CONTENTS FROM
0330 ** CURRENT STACK POINTER TO INTERNAL STACK LIMIT.
0331 *
0332 f98a 17 03 35 DISSTK LBSR PRTSP PRINT CURRENT STACK POINTER
0333 f98d 1f 32 TFR U,Y
0334 f98f 8e df c0 LDX #STACK LOAD INTERNAL STACK AS UPPER LIMIT
0335 f992 30 1f LEAX -1,X POINT TO CURRENT STACK
0336 f994 20 05 BRA MDUMP1 ENTER MEMORY DUMP OF STACK CONTENTS
0337 *
0338 * "E" DUMP MEMORY FOR EXAMINE IN HEX AND ASCII
0339 * AFTER CALLING 'IN2ADR' LOWER ADDRESS IN Y-REG.
0340 * UPPER ADDRESS IN X-REG.
0341 * IF HEX ADDRESSES ARE INVALID (V)=1.
0342 *
0343 f996 17 03 8b MEMDUMP LBSR IN2ADR INPUT ADDRESS BOUNDRIES
0344 f999 29 06 BVS EDPRTN NEW COMMAND IF ILLEGAL HEX
0345 f99b 34 20 MDUMP1 PSHS Y COMPARE LOWER TO UPPER BOUNDS
0346 f99d ac e1 CMPX ,S++ LOWER BOUNDS > UPPER BOUNDS?
0347 f99f 24 01 BCC AJDUMP IF NOT, DUMP HEX AND ASCII
0348 f9a1 39 EDPRTN RTS ;
0349 *
0350 * ADJUST LOWER AND UPPER ADDRESS LIMITS
0351 * TO EVEN 16 BYTE BOUNDRIES.
0352 *
0353 * IF LOWER ADDR = $4532
0354 * LOWER BOUNDS WILL BE ADJUSTED TO = $4530.
0355 *
0356 * IF UPPER ADDR = $4567
0357 * UPPER BOUNDS WILL BE ADJUSTED TO = $4570.
0358 *
0359 * ENTER WITH LOWER ADDRESS IN X-REG.
0360 * -UPPER ADDRESS ON TOP OF STACK.
0361 *
0362 f9a2 1f 10 AJDUMP TFR X,D GET UPPER ADDR IN D-REG
0363 f9a4 c3 00 10 ADDD #$10 ADD 16 TO UPPER ADDRESS
0364 f9a7 c4 f0 ANDB #$F0 MASK TO EVEN 16 BYTE BOUNDRY
0365 f9a9 34 06 PSHS A,B SAVE ON STACK AS UPPER DUMP LIMIT
0366 f9ab 1f 20 TFR Y,D $F9A5 GET LOWER ADDRESS IN D-REG
0367 f9ad c4 f0 ANDB #$F0 MASK TO EVEN 16 BYTE BOUNDRY
0368 f9af 1f 01 TFR D,X PUT IN X-REG AS LOWER DUMP LIMIT
0369 f9b1 ac e4 NXTLIN CMPX ,S COMPARE LOWER TO UPPER LIMIT
0370 f9b3 27 05 BEQ SKPDMP IF EQUAL SKIP HEX-ASCII DUMP
0371 f9b5 17 04 27 LBSR INCHEK CHECK FOR INPUT FROM KEYBOARD
0372 f9b8 27 03 BEQ EDUMP IF NONE, CONTINUE WITH DUMP
0373 f9ba 32 62 SKPDMP LEAS 2,S READJUST STACK IF NOT DUMPING
0374 f9bc 39 RTS ;
0375 *
0376 * PRINT 16 HEX BYTES FOLLOWED BY 16 ASCII CHARACTERS
0377 * FOR EACH LINE THROUGHOUT ADDRESS LIMITS.
0378 *
0379 f9bd 34 10 EDUMP PSHS X PUSH LOWER ADDR LIMIT ON STACK
0380 f9bf 8e fe 83 LDX #MSG5 POINT TO MSG " - "
0381 f9c2 17 03 e8 LBSR PSTRNG PRINT MSG
0382 f9c5 ae e4 LDX ,S LOAD LOWER ADDR FROM TOP OF STACK
0383 f9c7 17 03 af LBSR OUT4H PRINT THE ADDRESS LBSR OUT2S PRINT 2 SPACES
0384 f9ca c6 10 LDB #$10 LOAD COUNT OF 16 BYTES TO DUMP
0385 f9cc a6 80 ELOOP LDA ,X+ GET FROM MEMORY HEX BYTE TO PRINT
0386 f9ce 17 03 b0 LBSR OUT2H OUTPUT HEX BYTE AS ASCII
0387 f9d1 17 04 18 LBSR OUT1S OUTPUT SPACE
0388 f9d4 5a DECB $F9D1 DECREMENT BYTE COUNT
0389 f9d5 26 f5 BNE ELOOP CONTINUE TIL 16 HEX BYTES PRINTED
0390 *
0391 * PRINT 16 ASCII CHARACTERS
0392 * IF NOT PRINTABLE OR NOT VALID
0393 * ASCII PRINT A PERIOD (.)
0394 f9d7 17 04 10 LBSR OUT2S 2 SPACES
0395 f9da ae e1 LDX ,S++ GET LOW LIMIT FRM STACK - ADJ STACK
0396 f9dc c6 10 LDB #$10 SET ASCII CHAR TO PRINT = 16
0397 f9de a6 80 EDPASC LDA ,X+ GET CHARACTER FROM MEMORY
0398 f9e0 81 20 CMPA #$20 IF LESS THAN $20, NON-PRINTABLE?
0399 f9e2 25 04 BCS PERIOD IF SO, PRINT PERIOD INSTEAD
0400 f9e4 81 7e CMPA #$7E IS IT VALID ASCII?
0401 f9e6 23 02 BLS PRASC IF SO PRINT IT
0402 f9e8 86 2e PERIOD LDA #'. LOAD A PERIOD (.)
0403 f9ea 17 04 01 PRASC LBSR OUTCH PRINT ASCII CHARACTER
0404 f9ed 5a DECB DECREMENT COUNT
0405 f9ee 26 ee BNE EDPASC
0406 f9f0 20 bf BRA NXTLIN
0407 *
0408 ***** "Q" MEMORY TEST *****
0409 *
0410 f9f2 6f e2 MEMTST CLR ,-S CLEAR BYTE ON STACK
0411 f9f4 6f e2 CLR ,-S CLEAR ANOTHER BYTE
0412 f9f6 17 03 2b LBSR IN2ADR GET BEGIN(Y) & END(X) ADDR. LIMITS
0413 f9f9 34 30 PSHS X,Y SAVE ADDRESSES ON STACK
0414 f9fb 29 7b BVS ADJSK6 EXIT IF NOT VALID HEX
0415 f9fd ac 62 CMPX 2,S COMPARE BEGIN TO END ADDR.
0416 f9ff 25 77 BCS ADJSK6 EXIT IF BEGIN > END ADDR.
0417 fa01 17 03 e8 LBSR OUT1S OUTPUT SPACE
0418 fa04 1f 20 MEMSET TFR Y,D PUT BEGIN ADDR. IN 'D'-ACCUM.
0419 fa06 e3 64 ADDD 4,S ADD PASS COUNT TO BEGIN ADDR
0420 fa08 34 04 PSHS B ADD LS BYTE TO MS BYTE OF BEGIN ADDR
0421 fa0a ab e0 ADDA ,S+
0422 fa0c a7 a0 STA ,Y+ SAVE THIS DATA BYTE AT BEGIN ADDR
0423 fa0e 10 ac e4 CMPY ,S COMPARE END TO BEGIN ADDR
0424 fa11 25 f1 BCS MEMSET IF BEGIN LOWER, CONTINUE TO SET MEMORY
0425 fa13 10 ae 62 LDY 2,S RELOAD BEGIN ADDRESS
0426 fa16 1f 20 TEST1 TFR Y,D PUT BEGIN ADDR IN 'D'-ACC.
0427 fa18 e3 64 ADDD 4,S ADD PASS COUNT TO ADDRESS
0428 fa1a 34 02 PSHS A ADD MS BYTE TO LS BYTE OF ADDRESS
0429 fa1c eb e0 ADDB ,S+
0430 fa1e e8 a0 EORB ,Y+ EX-OR THIS DATA WITH DATA IN MEMORY LOC.
0431 fa20 27 3c BEQ GUDPAS IF (Z) SET, MEMORY BYTE OK
0432 fa22 8e fe 83 LDX #MSG5 POINT TO MSG " - "
0433 fa25 17 03 85 LBSR PSTRNG PRINT MSG
0434 fa28 30 3f LEAX -1,Y GET ERROR ADDRESS IN X-REG
0435 fa2a 17 03 4c LBSR OUT4H OUTPUT IT
0436 fa2d 34 10 PSHS X PUSH ERROR ADDR ON STACK
0437 fa2f 8e fe a1 LDX #MSG8 POINT TO MSG " =>"
0438 fa32 17 03 88 LBSR PDATA PRINT MSG
0439 fa35 35 10 PULS X POP ERROR ADDR FROM STACK
0440 fa37 17 01 47 LBSR LRA GET PHYSICAL ADDR FROM LRA
0441 fa3a 17 03 50 LBSR XASCII OUTPUT EXTENDED 4 BITS OF PHYSICAL ADDR
0442 fa3d 17 03 39 LBSR OUT4H OUTPUT LS 16 BITS OF PHYSICAL ADDR
0443 fa40 8e fe 87 LDX #MSG6 POINT TO MSG ", PASS "
0444 fa43 17 03 77 LBSR PDATA PRINT MSG
0445 fa46 ae 64 LDX 4,S LOAD PASS COUNT
0446 fa48 17 03 2e LBSR OUT4H OUTPUT IT
0447 fa4b 8e fe 8f LDX #MSG7 POINT TO MSG ", BITS IN ERROR
0448 fa4e 17 03 6c LBSR PDATA PRINT MSG
0449 fa51 1f 98 TFR B,A GET ERROR BYTE INTO A-ACC
0450 fa53 8e fe a6 LDX #MSG9 POINT TO MSG "76543210"
0451 fa56 17 03 3e LBSR BIASCI OUTPUT IN BINARY/ASCII FORMAT
0452 fa59 17 03 83 LBSR INCHEK CHECK FOR INPUT FROM KEYBOARD $FA56
0453 fa5c 26 1a BNE ADJSK6 IF SO, EXIT MEMORY TEST
0454 fa5e 10 ac e4 GUDPAS CMPY ,S COMPARE END ADDR TO BEGIN ADDR
0455 fa61 25 b3 BCS TEST1
0456 fa63 86 2b LDA #'+ GET "PASS" SYMBOL IF MEMORY PASS OK
0457 fa65 17 03 86 LBSR OUTCH OUTPUT SYMBOL TO TERMINAL
0458 fa68 17 03 74 LBSR INCHEK INPUT FROM KEYBOARD?
0459 fa6b 26 0b BNE ADJSK6 IF SO, EXIT MEMORY TEST
0460 fa6d 10 ae 62 LDY 2,S LOAD BEGIN ADDRESS
0461 fa70 6c 65 INC 5,S INCREMENT LS BYTE OF PASS COUNT
0462 fa72 26 90 BNE MEMSET IF NOT ZERO, SET NEXT MEMORY BYTE
0463 fa74 6c 64 INC 4,S INCREMENT MS BYTE OF PASS COUNT
0464 fa76 26 8c BNE MEMSET DONE WITH 65,535 PASSES OF MEMORY?
0465 fa78 32 66 ADJSK6 LEAS 6,S ADJ STACK POINTER BY 6
0466 fa7a 39 RTS
0467 *
0468 ***** "B" SET BREAKPOINT *****
0469 *
0470 fa7b 17 02 b1 BRKPNT LBSR IN1ADR GET BREAKPOINT ADDRESS
0471 fa7e 29 1e BVS EXITBP EXIT IF INVALID HEX ADDR.
0472 fa80 8c df c0 CMPX #STACK ADDRESS ILLEGAL IF >=$DFC0
0473 fa83 24 1a BCC BPERR IF ERROR PRINT (?), EXIT
0474 fa85 34 10 PSHS X $FA82 PUSH BP ADDRESS ON STACK
0475 fa87 8e ff ff LDX #$FFFF LOAD DUMMY ADDR TO TEST BP TABLE
0476 fa8a 8d 55 BSR BPTEST TEST BP TABLE FOR FREE SPACE
0477 fa8c 35 10 PULS X POP BP ADDRESS FROM STACK
0478 fa8e 27 0f BEQ BPERR (Z) SET, OUT OF BP TABLE SPACE
0479 fa90 a6 84 LDA ,X GET DATA AT BREAKPOINT ADDRESS
0480 fa92 81 3f CMPA #$3F IS IT A SWI?
0481 fa94 27 09 BEQ BPERR IF SWI ALREADY, INDICATE ERROR
0482 fa96 a7 a0 STA ,Y+ SAVE DATA BYTE IN BP TABLE
0483 fa98 af a4 STX ,Y SAVE BP ADDRESS IN BP TABLE
0484 fa9a 86 3f LDA #$3F LOAD A SWI ($3F)
0485 fa9c a7 84 STA ,X SAVE SWI AT BREAKPOINT ADDRESS
0486 fa9e 39 EXITBP RTS ;
0487 *
0488 * INDICATE ERROR SETTING BREAKPOINT
0489 *
0490 fa9f 17 03 4a BPERR LBSR OUT1S OUTPUT SPACE
0491 faa2 86 3f LDA #'? LOAD (?), INDICATE BREAKPOINT ERROR
0492 faa4 16 03 47 LBRA OUTCH PRINT "?"
0493 *
0494 *** "X" CLEAR OUTSTANDING BREAKPOINTS ***
0495 *
0496 faa7 10 8e df e3 XBKPNT LDY #BPTBL POINT TO BREAKPOINT TABLE
0497 faab c6 08 LDB #8 LOAD BREAKPOINT COUNTER
0498 faad 8d 18 XBPLP BSR RPLSWI REMOVE USED ENTRY IN BP TABLE
0499 faaf 5a DECB $FAAC DECREMENT BP COUNTER
0500 fab0 26 fb BNE XBPLP END OF BREAKPOINT TABLE?
0501 fab2 39 RTS
0502 *
0503 ***** SWI ENTRY POINT *****
0504 *
0505 fab3 1f 43 SWIE TFR S,U TRANSFER STACK TO USER POINTER
0506 fab5 ae 4a LDX 10,U LOAD PC FROM STACK INTO X-REG
0507 fab7 30 1f LEAX -1,X ADJUST ADDR DOWN 1 BYTE.
0508 fab9 8d 26 BSR BPTEST FIND BREAKPOINT IN BP TABLE
0509 fabb 27 04 BEQ REGPR IF FOUND, REPLACE DATA AT BP ADDR
0510 fabd af 4a STX 10,U SAVE BREAKPOINT ADDR IN STACK
0511 fabf 8d 06 BSR RPLSWI GO REPLACE SWI WITH ORIGINAL DATA
0512 fac1 17 fd e4 REGPR LBSR REGSTR GO PRINT REGISTERS
0513 fac4 16 fd 9a LBRA NEXTCMD GET NEXT COMMAND
0514 fac7 ae 21 RPLSWI LDX 1,Y LOAD BP ADDRESS FROM BP TABLE
0515 fac9 8c df c0 CMPX #STACK COMPARE TO TOP AVAILABLE USER MEMORY
0516 facc 24 0a BCC FFSTBL GO RESET TABLE ENTRY TO $FF'S
0517 face a6 84 LDA ,X GET DATA FROM BP ADDRESS
0518 fad0 81 3f CMPA #$3F IS IT SWI?
0519 fad2 26 04 BNE FFSTBL IF NOT, RESET TABLE ENTRY TO $FF'S
0520 fad4 a6 a4 LDA ,Y GET ORIGINAL DATA FROM BP TABLE
0521 fad6 a7 84 STA ,X $FAD3 RESTORE DATA AT BP ADDRESS
0522 fad8 86 ff FFSTBL LDA #$FF LOAD $FF IN A-ACC
0523 fada a7 a0 STA ,Y+ RESET BREAKPOINT TABLE DATA TO $FF'S
0524 fadc a7 a0 STA ,Y+ RESET BREAKPOINT TABLE ADDR TO $FF'S
0525 fade a7 a0 STA ,Y+
0526 fae0 39 RTS
0527 *
0528 ** SEARCH BREAKPOINT TABLE FOR MATCH **
0529 *
0530 fae1 10 8e df e3 BPTEST LDY #BPTBL POINT TO BREAKPOINT TABLE
0531 fae5 c6 08 LDB #8 LOAD BREAKPOINT COUNTER
0532 fae7 a6 a0 FNDBP LDA ,Y+ LOAD DATA BYTE
0533 fae9 ac a1 CMPX ,Y++ COMPARE ADDRESS, IS IT SAME?
0534 faeb 27 04 BEQ BPADJ IF SO, ADJUST POINTER FOR TABLE ENTRY
0535 faed 5a DECB IF NOT, DECREMENT BREAKPOINT COUNTER
0536 faee 26 f7 BNE FNDBP AND LOOK FOR NEXT POSSIBLE MATCH
0537 faf0 39 RTS ;
0538 *
0539 *
0540 faf1 31 3d BPADJ LEAY -3,Y MOVE POINTER TO BEGIN OF BP ENTRY
0541 faf3 39 RTS
0542 *
0543 *** "D" DISK BOOT FOR DMAF2 ***
0544 *
0545 faf4 86 de DBOOT LDA #$DE
0546 faf6 b7 f0 24 STA DRVREG
0547 faf9 86 ff LDA #$FF
0548 fafb b7 f0 14 STA PRIREG $FAF8
0549 fafe b7 f0 10 STA CCREG
0550 fb01 b7 f0 15 STA AAAREG
0551 fb04 b7 f0 16 STA BBBREG
0552 fb07 7d f0 10 TST CCREG
0553 fb0a 86 d8 LDA #$D8
0554 fb0c b7 f0 20 STA COMREG
0555 fb0f 17 00 97 LBSR DLY
0556 fb12 b6 f0 20 DBOOT0 LDA COMREG
0557 fb15 2b fb BMI DBOOT0
0558 fb17 86 09 LDA #$09
0559 fb19 b7 f0 20 STA COMREG
0560 fb1c 17 00 8a LBSR DLY
0561 *
0562 fb1f b6 f0 20 DISKWT LDA COMREG FETCH DRIVE STATUS
0563 fb22 85 01 BITA #1 TEST BUSY BIT
0564 fb24 26 f9 BNE DISKWT LOOP UNTIL NOT BUSY
0565 *
0566 fb26 85 10 BITA #$10
0567 fb28 26 ca BNE DBOOT
0568 *
0569 fb2a 8e c0 00 LDX #$C000 LOGICAL ADDR. = $C000
0570 fb2d 8d 52 BSR LRA GET 20 BIT PHYSICAL ADDR. OF LOG. ADDR.
0571 fb2f 8a 10 ORA #$10
0572 fb31 b7 f0 40 STA CCCREG
0573 fb34 1f 10 TFR X,D
0574 fb36 43 COMA ;
0575 fb37 53 COMB ;
0576 fb38 fd f0 00 STD ADDREG
0577 fb3b 8e fe ff LDX #$FEFF LOAD DMA BYTE COUNT = $100
0578 fb3e bf f0 02 STX CNTREG STORE IN COUNT REGISTER
0579 fb41 86 ff LDA #$FF LOAD THE CHANNEL REGISTER
0580 fb43 b7 f0 10 STA CCREG
0581 fb46 86 fe LDA #$FE SET CHANNEL 0
0582 fb48 b7 f0 14 STA PRIREG
0583 fb4b 86 01 LDA #1 SET SECTOR TO "1"
0584 fb4d b7 f0 22 STA SECREG ISSUE COMMAND
0585 fb50 86 8c LDA #$8C SET SINGLE SECTOR READ
0586 fb52 b7 f0 20 STA COMREG ISSUE COMMAND
0587 fb55 8d 52 BSR DLY
0588 *
0589 * THE FOLLOWING CODE TESTS THE STATUS OF THE
0590 * CHANNEL CONTROL REGISTER. IF "D7" IS NOT
0591 * ZERO THEN IT WILL LOOP WAITING FOR "D7"
0592 * TO GO TO ZERO. IF AFTER 65,536 TRIES IT
0593 * IS STILL A ONE THE BOOT OPERATION WILL
0594 * BE STARTED OVER FROM THE BEGINING.
0595 *
0596 fb57 5f CLRB ;
0597 fb58 34 04 DBOOT1 PSHS B $FB55
0598 fb5a 5f CLRB ;
0599 fb5b 7d f0 10 DBOOT2 TST CCREG
0600 fb5e 2a 0a BPL DBOOT3
0601 fb60 5a DECB ;
0602 fb61 26 f8 BNE DBOOT2
0603 fb63 35 04 PULS B
0604 fb65 5a DECB
0605 fb66 26 f0 BNE DBOOT1
0606 fb68 20 8a BRA DBOOT
0607 fb6a 35 04 DBOOT3 PULS B
0608 fb6c b6 f0 20 LDA COMREG
0609 fb6f 85 1c BITA #$1C
0610 fb71 27 01 BEQ DBOOT4
0611 fb73 39 RTS ;
0612 *
0613 *
0614 fb74 c6 de DBOOT4 LDB #$DE
0615 fb76 f7 f0 24 STB DRVREG
0616 fb79 8e c0 00 LDX #$C000
0617 fb7c af 4a STX 10,U
0618 fb7e 1f 34 TFR U,S $FB7B
0619 fb80 3b RTI ;
0620 *
0621 ***** LRA LOAD REAL ADDRESS *****
0622 *
0623 * THE FOLLOWING CODE LOADS THE 20-BIT
0624 * PHYSICAL ADDRESS OF A MEMORY BYTE
0625 * INTO THE "A" AND "X" REGISTERS. THIS
0626 * ROUTINE IS ENTERED WITH THE LOGICAL
0627 * ADDRESS OF A MEMORY BYTE IN THE "IX"
0628 * REGISTER. EXIT IS MADE WITH THE HIGH-
0629 * ORDER FOUR BITS OF THE 20-BIT PHYSICAL
0630 * ADDRESS IN THE "A" REGISTER, AND THE
0631 * LOW-ORDER 16-BITS OF THE 20-BIT
0632 * PHYSICAL ADDRESS IN THE "IX" REGISTER.
0633 * ALL OTHER REGISTERS ARE PRESERVED.
0634 * THIS ROUTINE IS REQUIRED SINCE THE
0635 * DMAF1 AND DMAF2 DISK CONTROLLERS MUST
0636 * PRESENT PHYSICAL ADDRESSES ON THE
0637 * SYSTEM BUS.
0638 *
0639 fb81 34 36 LRA PSHS A,B,X,Y PUSH REGISTERS ON STACK
0640 fb83 a6 62 LDA 2,S GET MSB LOGICAL ADDR FRM X REG ON STACK
0641 fb85 44 LSRA ;
0642 fb86 44 LSRA ADJ FOR INDEXED INTO
0643 fb87 44 LSRA CORRESPONDING LOCATION
0644 fb88 44 LSRA IN LRA TABLE
0645 fb89 10 8e df d0 LDY #LRARAM LOAD LRA TABLE BASE ADDRESS
0646 fb8d e6 a6 LDB A,Y GET PHYSICAL ADDR. DATA FROM LRA TABLE
0647 fb8f 54 LSRB ADJ. REAL ADDR. TO REFLECT EXTENDED
0648 fb90 54 LSRB PHYSICAL ADDRESS.
0649 fb91 54 LSRB EXTENDED MS 4-BITS ARE RETURNED
0650 fb92 54 LSRB IN THE "A" ACCUMULATOR
0651 fb93 e7 e4 STB ,S MS 4 BITS IN A ACCUM. STORED ON STACK
0652 fb95 e6 a6 LDB A,Y LOAD REAL ADDRESS DATA FROM LRA TABLE
0653 fb97 53 COMB COMP TO ADJ FOR PHYSICAL ADDR. IN X REG
0654 fb98 58 ASLB ADJ DATA FOR RELOCATION IN X REG
0655 fb99 58 ASLB ;
0656 fb9a 58 ASLB $FB97
0657 fb9b 58 ASLB ;
0658 fb9c a6 62 LDA 2,S GET MS BYTE OF LOGICAL ADDR.
0659 fb9e 84 0f ANDA #$0F MASK MS NIBBLE OF LOGICAL ADDRESS
0660 fba0 a7 62 STA 2,S SAVE IT IN X REG ON STACK
0661 fba2 ea 62 ORB 2,S SET MS BYTE IN X REG TO ADJ PHY ADDR.
0662 *
0663 * PLUS LS NIBBLE OF LOGICAL ADDRESS
0664 fba4 e7 62 STB 2,S SAVE AS LS 16 BITS OF PHY ADDR IN X REG
0665 * ON STACK
0666 fba6 35 36 PULS A,B,X,Y POP REGS. FROM STACK
0667 fba8 39 RTS ;
0668 *
0669 * DELAY LOOP
0670 *
0671 fba9 34 04 DLY PSHS B SAVE CONTENTS OF "B"
0672 fbab c6 20 LDB #$20 GET LOOP DELAY VALUE
0673 fbad 5a SUB1 DECB SUBTRACT ONE FROM VALUE
0674 fbae 26 fd BNE SUB1 LOOP UNTIL ZERO
0675 fbb0 35 04 PULS B RESTORE CONTENTS OF "B"
0676 fbb2 39 RTS ;
0677 *
0678 ***** "U" MINIDISK BOOT *****
0679 *
0680 fbb3 7d e0 18 MINBOOT TST Comreg
0681 fbb6 7f e0 14 CLR Drvreg SELECT DRIVE 0
0682 *
0683 * DELAY BEFORE ISSUING RESTORE COMMAND
0684 fbb9 c6 03 LDB #3
0685 fbbb 8e 00 00 LDX #0
0686 fbbe 30 01 LOOP LEAX 1,X $FBBB
0687 fbc0 8c 00 00 CMPX #0
0688 fbc3 26 f9 BNE LOOP
0689 fbc5 5a DECB $FBC2
0690 fbc6 26 f6 BNE LOOP
0691 *
0692 fbc8 86 0f LDA #$0F *LOAD HEAD, VERIFY, 20msec/step
0693 fbca b7 e0 18 STA Comreg ISSUE RESTORE COMMAND
0694 fbcd 8d 37 BSR DELAY
0695 fbcf f6 e0 18 LOOP1 LDB Comreg $FBCC
0696 fbd2 c5 01 BITB #1
0697 fbd4 26 f9 BNE LOOP1 LOOP UNTIL THRU
0698 fbd6 86 01 LDA #1
0699 fbd8 b7 e0 1a STA Secreg SET SECTOR REGISTER TO ONE
0700 fbdb 8d 29 BSR DELAY
0701 fbdd 86 8c LDA #$8C LOAD HEAD, DELAY 10msec,
0702 fbdf b7 e0 18 STA Comreg AND READ SINGLE RECORD
0703 fbe2 8d 22 BSR DELAY
0704 fbe4 8e c0 00 LDX #$C000
0705 fbe7 20 09 BRA LOOP3
0706 *
0707 fbe9 c5 02 LOOP2 BITB #2 $FBE6 DRQ?
0708 fbeb 27 05 BEQ LOOP3
0709 fbed b6 e0 1b LDA Datreg
0710 fbf0 a7 80 STA ,X+
0711 *
0712 fbf2 f6 e0 18 LOOP3 LDB Comreg FETCH STATUS
0713 fbf5 c5 01 BITB #1 BUSY?
0714 fbf7 26 f0 BNE LOOP2
0715 fbf9 c5 2c BITB #$2C CRC ERROR OR LOST DATA?
0716 fbfb 27 01 BEQ LOOP4
0717 fbfd 39 RTS ;
0718 fbfe 8e c0 00 LOOP4 LDX #$C000 $FBFB
0719 fc01 af 4a STX 10,U
0720 fc03 1f 34 TFR U,S
0721 fc05 3b RTI ;
0722 *
0723 * DELAY
0724 *
0725 fc06 c6 20 DELAY LDB #$20
0726 fc08 5a LOOP5 DECB ;
0727 fc09 26 fd BNE LOOP5
0728 fc0b 39 RTS ;
0729 *
0730 ***** "L" LOAD MIKBUG TAPE *****
0731 *
0732 fc0c 86 11 LOAD LDA #$11 LOAD 'DC1' CASS. READ ON CODE
0733 fc0e 17 01 dd LBSR OUTCH OUTPUT IT TO TERMINAL PORT
0734 fc11 7f df e2 CLR ECHO TURN OFF ECHO FLAG
0735 fc14 17 01 ad LOAD1 LBSR ECHON INPUT 8 BIT BYTE WITH NO ECHO
0736 fc17 81 53 LOAD2 CMPA #'S IS IT AN "S", START CHARACTER ?
0737 fc19 26 f9 BNE LOAD1 IF NOT, DISCARD AND GET NEXT CHAR.
0738 fc1b 17 01 a6 LBSR ECHON
0739 fc1e 81 39 CMPA #'9 IS IT A "9" , END OF FILE CHAR ?
0740 fc20 27 3d BEQ LOAD21 IF SO, EXIT LOAD
0741 fc22 81 31 CMPA #'1 IS IT A "1" , FILE LOAD CHAR ?
0742 fc24 26 f1 BNE LOAD2 IF NOT, LOOK FOR START CHAR.
0743 fc26 17 01 17 LBSR BYTE INPUT BYTE COUNT
0744 fc29 34 02 PSHS A PUSH COUNT ON STACK
0745 fc2b 29 26 BVS LODERR (V) C-CODE SET, ILLEGAL HEX
0746 fc2d 17 00 ff LBSR IN1ADR INPUT LOAD ADDRESS
0747 fc30 29 21 BVS LODERR (V) C-CODE SET, ADDR NOT HEX
0748 fc32 34 10 PSHS X PUSH ADDR ON STACK
0749 fc34 e6 e0 LDB ,S+ LOAD MSB OF ADDR AS CHECKSUM BYTE
0750 fc36 eb e0 ADDB ,S+ ADD LSB OF ADDR TO CHECKSUM
0751 fc38 eb e4 ADDB ,S ADD BYTE COUNT BYTE TO CHECKSUM
0752 fc3a 6a e4 DEC ,S $FC37 DECREMENT BYTE COUNT 2 TO BYPASS
0753 fc3c 6a e4 DEC ,S ADDRESS BYTES.
0754 fc3e 34 04 LOAD10 PSHS B PUSH CHECKSUM ON STACK
0755 fc40 17 00 fd LBSR BYTE INPUT DATA BYTE (2 HEX CHAR)
0756 fc43 35 04 PULS B POP CHECKSUM FROM STACK
0757 fc45 29 0c BVS LODERR (V) SET, DATA BYTE NOT HEX
0758 fc47 34 02 PSHS A PUSH DATA BYTE ON STACK
0759 fc49 eb e0 ADDB ,S+ ADD DATA TO CHECKSUM, AUTO INC STACK
0760 fc4b 6a e4 DEC ,S DECREMENT BYTE COUNT 1
0761 fc4d 27 05 BEQ LOAD16 IF BYTE COUNT ZERO, TEST CHECKSUM
0762 fc4f a7 80 STA ,X+ SAVE DATA BYTE IN MEMORY
0763 fc51 20 eb BRA LOAD10 GET NEXT DATA BYTE
0764 fc53 5f LODERR CLRB ;ERROR CONDITION, ZERO CHECKSUM ;
0765 fc54 35 02 LOAD16 PULS A ADJUST STACK (REMOVE BYTE COUNT)
0766 fc56 c1 ff CMPB #$FF CHECKSUM OK?
0767 fc58 27 b2 BEQ LOAD IF SO, LOAD NEXT LINE
0768 fc5a 86 3f LDA #'? LOAD (?) ERROR INDICATOR
0769 fc5c 17 01 8f LBSR OUTCH OUTPUT IT TO TERMINAL
0770 fc5f 73 df e2 LOAD21 COM ECHO TURN ECHO ON
0771 fc62 86 13 LDA #$13 $FC5F LOAD 'DC3' CASS. READ OFF CODE
0772 fc64 16 01 87 LBRA OUTCH OUTPUT IT
0773 *
0774 ***** "P" PUNCH MIKBUG TAPE *****
0775 *
0776 fc67 6f e2 PUNCH CLR ,-S CLEAR RESERVED BYTE ON STACK
0777 fc69 17 00 b8 LBSR IN2ADR GET BEGIN AND END ADDRESS
0778 fc6c 34 30 PSHS X,Y SAVE ADDRESSES ON STACK
0779 fc6e 29 4a BVS PUNEXT (V) C-CODE SET, EXIT PUNCH
0780 fc70 ac 62 CMPX 2,S COMPARE BEGIN TO END ADDR
0781 fc72 25 46 BCS PUNEXT IF BEGIN GREATER THAN END, EXIT PUNCH
0782 fc74 30 01 LEAX 1,X INCREMENT END ADDRESS
0783 fc76 af e4 STX ,S STORE END ADDR ON STACK
0784 fc78 86 12 LDA #$12 LOAD 'DC2' PUNCH ON CODE
0785 fc7a 17 01 71 LBSR OUTCH OUTPUT IT TO TERMINAL
0786 fc7d ec e4 PUNCH2 LDD ,S LOAD END ADDR IN D-ACC
0787 fc7f a3 62 SUBD 2,S SUBTRACT BEGIN FROM END
0788 fc81 27 06 BEQ PUNCH3 SAME, PUNCH 32 BYTES DEFAULT
0789 fc83 10 83 00 20 CMPD #$20 LESS THAN 32 BYTES?
0790 fc87 23 02 BLS PUNCH4 PUNCH THAT MANY BYTES
0791 fc89 c6 20 PUNCH3 LDB #$20 LOAD BYTE COUNT OF 32.
0792 fc8b e7 64 PUNCH4 STB 4,S STORE ON STACK AS BYTE COUNT
0793 fc8d 8e fe eb LDX #MSG20 POINT TO MSG "S1"
0794 fc90 17 01 1a LBSR PSTRNG PRINT MSG
0795 fc93 cb 03 ADDB #3 ADD 3 BYTES TO BYTE COUNT
0796 fc95 1f 98 TFR B,A GET BYTE COUNT IN A-ACC TO PUNCH
0797 fc97 17 00 e7 LBSR OUT2H OUTPUT BYTE COUNT
0798 fc9a ae 62 LDX 2,S LOAD BEGIN ADDRESS
0799 fc9c 17 00 da LBSR OUT4H PUNCH ADDRESS
0800 fc9f eb 62 ADDB 2,S ADD ADDR MSB TO CHECKSUM
0801 fca1 eb 63 ADDB 3,S ADD ADDR LSB TO CHECKSUM
0802 fca3 eb 84 PUNCHL ADDB ,X ADD DATA BYTE TO CHECKSUM
0803 fca5 a6 80 LDA ,X+ LOAD DATA BYTE TO PUNCH
0804 fca7 17 00 d7 LBSR OUT2H OUTPUT DATA BYTE
0805 fcaa 6a 64 DEC 4,S DECREMENT BYTE COUNT
0806 fcac 26 f5 BNE PUNCHL NOT DONE, PUNCH NEXT BYTE
0807 fcae 53 COMB 1's COMPLIMENT CHECKSUM BYTE
0808 fcaf 1f 98 TFR B,A GET IT IN A-ACC TO PUNCH
0809 fcb1 17 00 cd LBSR OUT2H OUTPUT CHECKSUM BYTE
0810 fcb4 af 62 STX 2,S SAVE X-REG IN STACK AS NEW PUNCH ADDR
0811 fcb6 ac e4 CMPX ,S COMPARE IT TO END ADDR
0812 fcb8 26 c3 BNE PUNCH2 $FCB5 PUNCH NOT DONE, CONT.
0813 fcba 86 14 PUNEXT LDA #$14 LOAD 'DC4' PUNCH OFF CODE
0814 fcbc 17 01 2f LBSR OUTCH OUTPUT IT
0815 fcbf 32 65 LEAS 5,S READJUST STACK POINTER
0816 fcc1 39 RTS ;
0817 *
0818 *
0819 fcc2 8e fe ae PRTSP LDX #MSG10 POINT TO MSG "SP="
0820 fcc5 17 00 f5 LBSR PDATA PRINT MSG
0821 fcc8 1f 31 TFR U,X
0822 fcca 16 00 ac LBRA OUT4H
0823 fccd 8e fe ba PRTUS LDX #MSG12 POINT TO MSG "US="
0824 fcd0 17 00 ea LBSR PDATA PRINT MSG
0825 fcd3 ae 48 LDX 8,U
0826 fcd5 16 00 a1 LBRA OUT4H
0827 fcd8 8e fe cc PRTDP LDX #MSG15 POINT TO MSG "DP="
0828 fcdb 17 00 df LBSR PDATA PRINT MSG
0829 fcde a6 43 LDA 3,U
0830 fce0 16 00 9e LBRA OUT2H OUTPUT HEX BYTE AS ASCII
0831 fce3 8e fe c6 PRTIX LDX #MSG14 POINT TO MSG "IX="
0832 fce6 17 00 d4 LBSR PDATA PRINT MSG
0833 fce9 ae 44 LDX 4,U $FCE6
0834 fceb 16 00 8b LBRA OUT4H
0835 fcee 8e fe c0 PRTIY LDX #MSG13 POINT TO MSG "IY="
0836 fcf1 17 00 c9 LBSR PDATA PRINT MSG
0837 fcf4 ae 46 LDX 6,U
0838 fcf6 16 00 80 LBRA OUT4H
0839 fcf9 8e fe b4 PRTPC LDX #MSG11 POINT TO MSG "PC="
0840 fcfc 17 00 be LBSR PDATA PRINT MSG
0841 fcff ae 4a LDX 10,U
0842 fd01 20 76 BRA OUT4H
0843 fd03 8e fe d2 PRTA LDX #MSG16 POINT TO MSG "A="
0844 fd06 17 00 b4 LBSR PDATA PRINT MSG
0845 fd09 a6 41 LDA 1,U
0846 fd0b 20 74 BRA OUT2H OUTPUT HEX BYTE AS ASCII
0847 fd0d 8e fe d7 PRTB LDX #MSG17 POINT TO MSG "B="
0848 fd10 17 00 aa LBSR PDATA PRINT MSG
0849 fd13 a6 42 LDA 2,U
0850 fd15 20 6a BRA OUT2H OUTPUT HEX BYTE AS ASCII
0851 fd17 8e fe dc PRTCC LDX #MSG18 POINT TO MSG "CC:"
0852 fd1a 17 00 a0 LBSR PDATA PRINT MSG
0853 fd1d a6 c4 LDA ,U
0854 fd1f 8e fe e3 LDX #MSG19 POINT TO MSG "EFHINZVC"
0855 fd22 20 73 BRA BIASCI OUTPUT IN BINARY/ASCII FORMAT
0856 *
0857 * THE FOLLOWING ROUTINE LOOPS WAITING FOR THE
0858 * OPERATOR TO INPUT TWO VALID HEX ADDRESSES.
0859 * THE FIRST ADDRESS INPUT IS RETURNED IN "IY".
0860 * THE SECOND IS RETURNED IN "IX". THE "V" BIT
0861 * IN THE C-CODE REG. IS SET IF AN INVALID HEX
0862 * ADDRESS IS INPUT.
0863 *
0864 fd24 8d 09 IN2ADR BSR IN1ADR GET FIRST ADDRESS
0865 fd26 29 4e BVS NOTHEX EXIT IF NOT VALID HEX
0866 fd28 1f 12 TFR X,Y SAVE FIRST ADDR. IN "IY"
0867 fd2a 86 2d LDA #'-
0868 fd2c 17 00 bf LBSR OUTCH PRINT " - "
0869 *
0870 * THE FOLLOWING ROUTINE LOOPS WAITING FOR THE
0871 * OPERATOR TO INPUT ONE VALID HEX ADDRESS. THE
0872 * ADDRESS IS RETURNED IN THE "X" REGISTER.
0873 *
0874 fd2f 8d 0f IN1ADR BSR BYTE INPUT BYTE (2 HEX CHAR)
0875 fd31 29 43 BVS NOTHEX EXIT IF NOT VALID HEX
0876 fd33 1f 01 TFR D,X
0877 fd35 8d 09 BSR BYTE INPUT BYTE (2 HEX CHAR)
0878 fd37 29 3d BVS NOTHEX
0879 fd39 34 10 PSHS X
0880 fd3b a7 61 STA 1,S
0881 fd3d 35 10 PULS X
0882 fd3f 39 RTS ;
0883 *
0884 ***** INPUT BYTE (2 HEX CHAR.) *****
0885 *
0886 fd40 8d 11 BYTE BSR INHEX GET HEX LEFT
0887 fd42 29 32 BVS NOTHEX EXIT IF NOT VALID HEX
0888 fd44 48 ASLA ;
0889 fd45 48 ASLA ;
0890 fd46 48 ASLA ; SHIFT INTO LEFT NIBBLE
0891 fd47 48 ASLA ;
0892 fd48 1f 89 TFR A,B PUT HEXL IN "B"
0893 fd4a 8d 07 BSR INHEX GET HEX RIGHT
0894 fd4c 29 28 BVS NOTHEX EXIT IF NOT VALID HEX
0895 fd4e 34 04 PSHS B PUSH HEXL ON STACK
0896 fd50 ab e0 ADDA ,S+ ADD HEXL TO HEXR AND ADJ. STK
0897 fd52 39 RTS RETURN WITH HEX L&R IN "A"
0898 *
0899 *
0900 fd53 8d 6f INHEX BSR ECHON INPUT ASCII CHAR.
0901 fd55 81 30 CMPA #'0 IS IT > OR = "0" ?
0902 fd57 25 1d BCS NOTHEX IF LESS IT AIN'T HEX
0903 fd59 81 39 CMPA #'9 IS IT < OR = "9" ?
0904 fd5b 22 03 BHI INHEXA IF > MAYBE IT'S ALPHA
0905 fd5d 80 30 SUBA #$30 ASCII ADJ. NUMERIC
0906 fd5f 39 RTS ;
0907 *
0908 *
0909 fd60 81 41 INHEXA CMPA #'A IS IT > OR = "A"
0910 fd62 25 12 BCS NOTHEX IF LESS IT AIN'T HEX
0911 fd64 81 46 CMPA #'F IS IT < OR = "F" ?
0912 fd66 22 03 BHI INHEXL IF > IT AIN'T HEX
0913 fd68 80 37 SUBA #$37 ASCII ADJ. ALPHA
0914 fd6a 39 RTS ;
0915 *
0916 fd6b 81 61 INHEXL CMPA #'a IS IT > OR = "a"
0917 fd6d 25 07 BCS NOTHEX IF LESS IT AIN'T HEX
0918 fd6f 81 66 CMPA #'f IS IT < "f"
0919 fd71 22 03 BHI NOTHEX IF > IT AIN'T HEX
0920 fd73 80 57 SUBA #$57 ADJUST TO LOWER CASE
0921 fd75 39 RTS ;
0922 *
0923 *
0924 fd76 1a 02 NOTHEX ORCC #2 SET (V) FLAG IN C-CODES REGISTER
0925 fd78 39 RTS ;
0926 *
0927 *
0928 fd79 34 10 OUT4H PSHS X PUSH X-REG. ON THE STACK
0929 fd7b 35 02 PULS A POP MS BYTE OF X-REG INTO A-ACC.
0930 fd7d 8d 02 BSR OUTHL OUTPUT HEX LEFT
0931 fd7f 35 02 PULS A POP LS BYTE OF X-REG INTO A-ACC.
0932 fd81 OUTHL EQU *
0933 fd81 34 02 OUT2H PSHS A SAVE IT BACK ON STACK
0934 fd83 44 LSRA CONVERT UPPER HEX NIBBLE TO ASCII
0935 fd84 44 LSRA ;
0936 fd85 44 LSRA ;
0937 fd86 44 LSRA ;
0938 fd87 8d 04 BSR XASCII PRINT HEX NIBBLE AS ASCII
0939 fd89 35 02 OUTHR PULS A CONVERT LOWER HEX NIBBLE TO ASCII
0940 fd8b 84 0f ANDA #$0F STRIP LEFT NIBBLE
0941 fd8d 8b 30 XASCII ADDA #$30 ASCII ADJ
0942 fd8f 81 39 CMPA #$39 IS IT < OR = "9" ?
0943 fd91 2f 02 BLE OUTC IF LESS, OUTPUT IT
0944 fd93 8b 07 ADDA #7 IF > MAKE ASCII LETTER
0945 fd95 20 57 OUTC BRA OUTCH OUTPUT CHAR
0946 *
0947 * BINARY / ASCII --- THIS ROUTINE
0948 * OUTPUTS A BYTE IN ENHANCED
0949 * BINARY FORMAT. THE ENHANCEMENT
0950 * IS DONE BY SUBSTITUTING ASCII
0951 * LETTERS FOR THE ONES IN THE BYTE.
0952 * THE ASCII ENHANCEMENT LETTERS
0953 * ARE OBTAINED FROM THE STRING
0954 * POINTED TO BY THE INDEX REG. "X".
0955 *
0956 fd97 34 02 BIASCI PSHS A SAVE "A" ON STACK
0957 fd99 c6 08 LDB #8 PRESET LOOP# TO BITS PER BYTE
0958 fd9b a6 80 OUTBA LDA ,X+ GET LETTER FROM STRING
0959 fd9d 68 e4 ASL ,S TEST BYTE FOR "1" IN B7
0960 fd9f 25 02 BCS PRTBA IF ONE PRINT LETTER
0961 fda1 86 2d LDA #'- IF ZERO PRINT "-"
0962 fda3 8d 49 PRTBA BSR OUTCH PRINT IT
0963 fda5 8d 45 BSR OUT1S PRINT SPACE
0964 fda7 5a DECB SUB 1 FROM #BITS YET TO PRINT
0965 fda8 26 f1 BNE OUTBA
0966 fdaa 35 02 PULS A
0967 fdac 39 RTS
0968 *
0969 * PRINT STRING PRECEEDED BY A CR & LF.
0970 *
0971 fdad 8d 02 PSTRNG BSR PCRLF PRINT CR/LF
0972 fdaf 20 0c BRA PDATA PRINT STRING POINTED TO BY IX
0973 *
0974 * PCRLF
0975 *
0976 fdb1 34 10 PCRLF PSHS X SAVE IX
0977 fdb3 8e fe 75 LDX #MSG2+1 POINT TO MSG CR/LF + 3 NULS
0978 fdb6 8d 05 BSR PDATA PRINT MSG
0979 fdb8 35 10 PULS X RESTORE IX
0980 fdba 39 RTS ;
0981 fdbb 8d 31 PRINT BSR OUTCH
0982 *
0983 * PDATA
0984 *
0985 fdbd a6 80 PDATA LDA ,X+ GET 1st CHAR. TO PRINT
0986 fdbf 81 04 CMPA #4 IS IT EOT?
0987 fdc1 26 f8 BNE PRINT IF NOT EOT PRINT IT
0988 fdc3 39 RTS ;
0989 *
0990 *
0991 fdc4 7d df e2 ECHON TST ECHO IS ECHO REQUIRED ?
0992 fdc7 27 06 BEQ INCH ECHO NOT REQ. IF CLEAR
0993 *
0994 * INCHE
0995 *
0996 * ---GETS CHARACTER FROM TERMINAL AND
0997 * ECHOS SAME. THE CHARACTER IS RETURNED
0998 * IN THE "A" ACCUMULATOR WITH THE PARITY
0999 * BIT MASKED OFF. ALL OTHER REGISTERS
1000 * ARE PRESERVED.
1001 *
1002 fdc9 8d 04 INCHE BSR INCH GET CHAR FROM TERMINAL
1003 fdcb 84 7f ANDA #$7F STRIP PARITY FROM CHAR.
1004 fdcd 20 1f BRA OUTCH ECHO CHAR TO TERMINAL
1005 *
1006 * INCH
1007 *
1008 * GET CHARACTER FROM TERMINAL. RETURN
1009 * CHARACTER IN "A" ACCUMULATOR AND PRESERVE
1010 * ALL OTHER REGISTERS. THE INPUT CHARACTER
1011 * IS 8 BITS AND IS NOT ECHOED.
1012 *
1013 *
1014 fdcf 34 10 INCH PSHS X SAVE IX
1015 fdd1 be df e0 LDX CPORT POINT TO TERMINAL PORT
1016 fdd4 a6 84 GETSTA LDA ,X FETCH PORT STATUS
1017 fdd6 85 01 BITA #1 TEST READY BIT, RDRF ?
1018 fdd8 27 fa BEQ GETSTA IF NOT RDY, THEN TRY AGAIN
1019 fdda a6 01 LDA 1,X FETCH CHAR
1020 fddc 35 10 PULS X RESTORE IX
1021 fdde 39 RTS ;
1022 *
1023 * INCHEK
1024 *
1025 * CHECK FOR A CHARACTER AVAILABLE FROM
1026 * THE TERMINAL. THE SERIAL PORT IS CHECKED
1027 * FOR READ READY. ALL REGISTERS ARE
1028 * PRESERVED, AND THE "Z" BIT WILL BE
1029 * CLEAR IF A CHARACTER CAN BE READ.
1030 *
1031 *
1032 fddf 34 02 INCHEK PSHS A SAVE A ACCUM.
1033 fde1 a6 9f df e0 LDA [CPORT] FETCH PORT STATUS
1034 fde5 85 01 BITA #1 TEST READY BIT, RDRF ?
1035 fde7 35 02 PULS A RESTORE A ACCUM.
1036 fde9 39 RTS ;
1037 *
1038 fdea 8d 00 OUT2S BSR OUT1S OUTPUT 2 SPACES
1039 fdec 86 20 OUT1S LDA #$20 OUTPUT 1 SPACE
1040 *
1041 *
1042 * OUTCH
1043 *
1044 * OUTPUT CHARACTER TO TERMINAL.
1045 * THE CHAR. TO BE OUTPUT IS
1046 * PASSED IN THE A REGISTER.
1047 * ALL REGISTERS ARE PRESERVED.
1048 *
1049 fdee 34 12 OUTCH PSHS A,X SAVE A ACCUM AND IX
1050 fdf0 be df e0 LDX CPORT GET ADDR. OF TERMINAL
1051 fdf3 a6 84 FETSTA LDA ,X FETCH PORT STATUS
1052 fdf5 85 02 BITA #2 TEST TDRE, OK TO XMIT ?
1053 fdf7 27 fa BEQ FETSTA IF NOT LOOP UNTIL RDY
1054 fdf9 35 02 PULS A GET CHAR. FOR XMIT
1055 fdfb a7 01 STA 1,X XMIT CHAR.
1056 fdfd 35 10 PULS X RESTORE IX
1057 fdff 39 RTS ;
1058 *
1059 *
1060 fe00 be df e0 ACINIZ LDX CPORT POINT TO CONTROL PORT ADDRESS
1061 fe03 86 03 LDA #3 RESET ACIA PORT CODE
1062 fe05 a7 84 STA ,X STORE IN CONTROL REGISTER
1063 fe07 86 11 LDA #$11 SET 8 DATA, 2 STOP AN 0 PARITY
1064 fe09 a7 84 STA ,X STORE IN CONTROL REGISTER
1065 fe0b 6d 01 TST 1,X ANYTHING IN DATA REGISTER?
1066 fe0d 86 ff LDA #$FF TURN ON ECHO FLAG
1067 fe0f b7 df e2 STA ECHO
1068 fe12 39 RTS
1069 *
1070 *
1071 * MONITOR KEYBOARD COMMAND JUMP TABLE
1072 *
1073 *
1074 fe13 JMPTAB EQU *
1075 fe13 01 FCB 1 " ^A " $F91D
1076 fe14 f9 23 FDB ALTRA
1077 fe16 02 FCB 2 " ^B " $F90F
1078 fe17 f9 15 FDB ALTRB
1079 fe19 03 FCB 3 " ^C " $F92B
1080 fe1a f9 31 FDB ALTRCC
1081 fe1c 04 FCB 4 " ^D " $F901
1082 fe1d f9 07 FDB ALTRDP
1083 fe1f 10 FCB $10 " ^P " $F8C9
1084 fe20 f8 cf FDB ALTRPC
1085 fe22 15 FCB $15 " ^U " $F8D7
1086 fe23 f8 dd FDB ALTRU
1087 fe25 18 FCB $18 " ^X " $F8F3
1088 fe26 f8 f9 FDB ALTRX
1089 fe28 19 FCB $19 " ^Y " $F8E5
1090 fe29 f8 eb FDB ALTRY
1091 *
1092 fe2b 42 FCC 'B'
1093 fe2c fa 7b FDB BRKPNT *$FA78
1094 fe2e 44 FCC 'D'
1095 fe2f fa f4 FDB DBOOT *$FAF1
1096 fe31 45 FCC 'E'
1097 fe32 f9 96 FDB MEMDUMP *$F990
1098 fe34 47 FCC 'G'
1099 fe35 f8 a5 FDB GO *$F89F
1100 fe37 4c FCC 'L'
1101 fe38 fc 0c FDB LOAD *$FC09
1102 fe3a 4d FCC 'M'
1103 fe3b f9 41 FDB MEMCHG *$F93B
1104 fe3d 50 FCC 'P'
1105 fe3e fc 67 FDB PUNCH *$FC64
1106 fe40 51 FCC 'Q'
1107 fe41 f9 f2 FDB MEMTST *$F9EF
1108 fe43 52 FCC 'R'
1109 fe44 f8 a8 FDB REGSTR *$F8A2
1110 fe46 53 FCC 'S'
1111 fe47 f9 8a FDB DISSTK *$F984
1112 fe49 55 FCC 'U'
1113 fe4a fb b3 FDB MINBOOT *$FBB0
1114 fe4c 58 FCC 'X'
1115 fe4d fa a7 FDB XBKPNT *$FAA4
1116 *
1117 fe4f TABEND EQU *
1118 *
1119 * ** 6809 VECTOR ADDRESSES **
1120 *
1121 * FOLLOWING ARE THE ADDRESSES OF THE VECTOR ROUTINES
1122 * FOR THE 6809 PROCESSOR. DURING INITIALIZATION THEY
1123 * ARE RELOCATED TO RAM FROM $DFC0 TO $DFCF. THEY ARE
1124 * RELOCATED TO RAM SO THAT THE USER MAY REVECTOR TO
1125 * HIS OWN ROUTINES IF HE SO DESIRES.
1126 *
1127 *
1128 fe4f fa b3 RAMVEC FDB SWIE USER-V
1129 fe51 f8 a7 FDB RTI SWI3-V
1130 fe53 f8 a7 FDB RTI SWI2-V
1131 fe55 f8 a7 FDB RTI FIRQ-V
1132 fe57 f8 a7 FDB RTI IRQ-V
1133 fe59 fa b3 FDB SWIE SWI-V
1134 fe5b ff ff FDB $FFFF SVC-VO
1135 fe5d ff ff FDB $FFFF SVC-VL
1136 *
1137 * PRINTABLE MESSAGE STRINGS
1138 *
1139 fe5f 00 00 00 0d 0a 00 MSG1 FCB $0,$0,$0,$D,$A,$0,$0,$0 * 0, CR/LF, 0
00 00
1140 fe67 53 2d 42 55 47 20 FCC 'S-BUG 1.8 - '
31 2e 38 20 2d 20
1141 fe73 04 FCB 4
1142 fe74 4b 0d 0a 00 00 00 MSG2 FCB 'K,$D,$A,$0,$0,$0,4 K, * CR/LF + 3 NULS
04
1143 fe7b 3e MSG3 FCC '>'
1144 fe7c 04 FCB 4
1145 fe7d 57 48 41 54 3f MSG4 FCC 'WHAT?'
1146 fe82 04 FCB 4
1147 fe83 20 2d 20 MSG5 FCC ' - '
1148 fe86 04 FCB 4'
1149 fe87 2c 20 50 41 53 53 MSG6 FCC ', PASS '
20
1150 fe8e 04 FCB 4
1151 fe8f 2c 20 42 49 54 53 MSG7 FCC ', BITS IN ERROR: '
20 49 4e 20 45 52
52 4f 52 3a 20
1152 fea0 04 FCB 4
1153 fea1 20 3d 3e 20 MSG8 FCC ' => '
1154 fea5 04 FCB 4
1155 fea6 37 36 35 34 33 32 MSG9 FCC '76543210'
31 30
1156 feae 20 20 53 50 3d MSG10 FCC ' SP='
1157 feb3 04 FCB 4
1158 feb4 20 20 50 43 3d MSG11 FCC ' PC='
1159 feb9 04 FCB 4
1160 feba 20 20 55 53 3d MSG12 FCC ' US='
1161 febf 04 FCB 4
1162 fec0 20 20 49 59 3d MSG13 FCC ' IY='
1163 fec5 04 FCB 4
1164 fec6 20 20 49 58 3d MSG14 FCC ' IX='
1165 fecb 04 FCB 4
1166 fecc 20 20 44 50 3d MSG15 FCC ' DP='
1167 fed1 04 FCB 4
1168 fed2 20 20 41 3d MSG16 FCC ' A='
1169 fed6 04 FCB 4
1170 fed7 20 20 42 3d MSG17 FCC ' B='
1171 fedb 04 FCB 4
1172 fedc 20 20 43 43 3a 20 MSG18 FCC ' CC: '
1173 fee2 04 FCB 4
1174 fee3 45 46 48 49 4e 5a MSG19 FCC 'EFHINZVC'
56 43
1175 feeb 53 31 MSG20 FCC 'S1'
1176 feed 04 FCB 4
1177 *
1178 * MESSAGE EXPANSION AREA
1179 *
1180 feee ff ff ff ff ff ff FCB $FF,$FF,$FF,$FF,$FF,$FF,$FF,$FF
ff ff
1181 fef6 ff ff ff ff ff ff FCB $FF,$FF,$FF,$FF,$FF,$FF,$FF
ff
1182 *
1183 * POWER UP/ RESET/ NMI ENTRY POINT
1184 *
1185 ff00 ORG $FF00
1186 *
1187 *
1188 ff00 8e ff f0 START LDX #IC11 POINT TO DAT RAM IC11
1189 ff03 86 0f LDA #$F GET COMPLIMENT OF ZERO
1190 *
1191 *
1192 * INITIALIZE DAT RAM --- LOADS $F-$0 IN LOCATIONS $0-$F
1193 * OF DAT RAM, THUS STORING COMPLEMENT OF MSB OF ADDRESS
1194 * IN THE DAT RAM. THE COMPLEMENT IS REQUIRED BECAUSE THE
1195 * OUTPUT OF IC11, A 74S189, IS THE INVERSE OF THE DATA
1196 * STORED IN IT.
1197 *
1198 *
1199 ff05 a7 80 DATLP STA ,X+ STORE & POINT TO NEXT RAM LOCATION
1200 ff07 4a DECA GET COMP. VALUE FOR NEXT LOCATION
1201 ff08 26 fb BNE DATLP ALL 16 LOCATIONS INITIALIZED ?
1202 *
1203 * NOTE: IX NOW CONTAINS $0000, DAT RAM IS NO LONGER
1204 * ADDRESSED, AND LOGICAL ADDRESSES NOW EQUAL
1205 * PHYSICAL ADDRESSES.
1206 *
1207 ff0a 86 f0 LDA #$F0
1208 ff0c a7 84 STA ,X STORE $F0 AT $FFFF
1209 ff0e 8e d0 a0 LDX #$D0A0 ASSUME RAM TO BE AT $D000-$DFFF
1210 ff11 10 8e 55 aa LDY #TSTPAT LOAD TEST DATA PATTERN INTO "Y"
1211 ff15 ee 84 TSTRAM LDU ,X SAVE DATA FROM TEST LOCATION
1212 ff17 10 af 84 STY ,X STORE TEST PATTERN AT $D0A0
1213 ff1a 10 ac 84 CMPY ,X IS THERE RAM AT THIS LOCATION ?
1214 ff1d 27 0b BEQ CNVADR IF MATCH THERE'S RAM, SO SKIP
1215 ff1f 30 89 f0 00 LEAX -$1000,X ELSE POINT 4K LOWER
1216 ff23 8c f0 a0 CMPX #$F0A0 DECREMENTED PAST ZER0 YET ?
1217 ff26 26 ed BNE TSTRAM IF NOT CONTINUE TESTING FOR RAM
1218 ff28 20 d6 BRA START ELSE START ALL OVER AGAIN
1219 *
1220 *
1221 * THE FOLLOWING CODE STORES THE COMPLEMENT OF
1222 * THE MS CHARACTER OF THE FOUR CHARACTER HEX
1223 * ADDRESS OF THE FIRST 4K BLOCK OF RAM LOCATED
1224 * BY THE ROUTINE "TSTRAM" INTO THE DAT RAM. IT
1225 * IS STORED IN RAM IN THE LOCATION THAT IS
1226 * ADDRESSED WHEN THE PROCESSOR ADDRESS IS $D---,
1227 * THUS IF THE FIRST 4K BLOCK OF RAM IS FOUND
1228 * WHEN TESTING LOCATION $70A0, MEANING THERE
1229 * IS NO RAM PHYSICALLY ADDRESSED IN THE RANGE
1230 * $8000-$DFFF, THEN THE COMPLEMENT OF THE
1231 * "7" IN THE $70A0 WILL BE STORED IN
1232 * THE DAT RAM. THUS WHEN THE PROCESSOR OUTPUTS
1233 * AN ADDRESS OF $D---, THE DAT RAM WILL RESPOND
1234 * BY RECOMPLEMENTING THE "7" AND OUTPUTTING THE
1235 * 7 ONTO THE A12-A15 ADDRESS LINES. THUS THE
1236 * RAM THAT IS PHYSICALLY ADDRESSED AT $7---
1237 * WILL RESPOND AND APPEAR TO THE 6809 THAT IT
1238 * IS AT $D--- SINCE THAT IS THE ADDRESS THE
1239 * 6809 WILL BE OUTPUTING WHEN THAT 4K BLOCK
1240 * OF RAM RESPONDS.
1241 *
1242 *
1243 ff2a ef 84 CNVADR STU ,X RESTORE DATA AT TEST LOCATION
1244 ff2c 1f 10 TFR X,D PUT ADDR. OF PRESENT 4K BLOCK IN D
1245 ff2e 43 COMA COMPLEMENT MSB OF THAT ADDRESS
1246 ff2f 44 LSRA PUT MS 4 BITS OF ADDRESS IN
1247 ff30 44 LSRA LOCATION D0-D3 TO ALLOW STORING
1248 ff31 44 LSRA IT IN THE DYNAMIC ADDRESS
1249 ff32 44 LSRA TRANSLATION RAM.
1250 ff33 b7 ff fd STA $FFFD STORE XLATION FACTOR IN DAT "D"
1251 *
1252 ff36 10 ce df c0 LDS #STACK INITIALIZE STACK POINTER
1253 *
1254 *
1255 * THE FOLLOWING CHECKS TO FIND THE REAL PHYSICAL ADDRESSES
1256 * OF ALL 4K BLKS OF RAM IN THE SYSTEM. WHEN EACH 4K BLK
1257 * OF RAM IS LOCATED, THE COMPLEMENT OF IT'S REAL ADDRESS
1258 * IS THEN STORED IN A "LOGICAL" TO "REAL" ADDRESS XLATION
1259 * TABLE THAT IS BUILT FROM $DFD0 TO $DFDF. FOR EXAMPLE IF
1260 * THE SYSTEM HAS RAM THAT IS PHYSICALLY LOCATED (WIRED TO
1261 * RESPOND) AT THE HEX LOCATIONS $0--- THRU $F---....
1262 *
1263 * 0 1 2 3 4 5 6 7 8 9 A B C D E F
1264 * 4K 4K 4K 4K 4K 4K 4K 4K -- 4K 4K 4K 4K -- -- --
1265 *
1266 * ....FOR A TOTAL OF 48K OF RAM, THEN THE TRANSLATION TABLE
1267 * CREATED FROM $DFD0 TO $DFDF WILL CONSIST OF THE FOLLOWING....
1268 *
1269 * 0 1 2 3 4 5 6 7 8 9 A B C D E F
1270 * 0F 0E 0D 0C 0B 0A 09 08 06 05 00 00 04 03 F1 F0
1271 *
1272 *
1273 * HERE WE SEE THE LOGICAL ADDRESSES OF MEMORY FROM $0000-$7FFF
1274 * HAVE NOT BEEN SELECTED FOR RELOCATION SO THAT THEIR PHYSICAL
1275 * ADDRESS WILL = THEIR LOGICAL ADDRESS; HOWEVER, THE 4K BLOCK
1276 * PHYSICALLY AT $9000 WILL HAVE ITS ADDRESS TRANSLATED SO THAT
1277 * IT WILL LOGICALLY RESPOND AT $8000. LIKEWISE $A,$B, AND $C000
1278 * WILL BE TRANSLATED TO RESPOND TO $9000,$C000, AND $D000
1279 * RESPECTIVELY. THE USER SYSTEM WILL LOGICALLY APPEAR TO HAVE
1280 * MEMORY ADDRESSED AS FOLLOWS....
1281 *
1282 * 0 1 2 3 4 5 6 7 8 9 A B C D E F
1283 * 4K 4K 4K 4K 4K 4K 4K 4K 4K 4K -- -- 4K 4K -- --
1284 *
1285 *
1286 ff3a 10 8e df d0 LDY #LRARAM POINT TO LOGICAL/REAL ADDR. TABLE
1287 ff3e a7 2d STA 13,Y STORE $D--- XLATION FACTOR AT $DFDD
1288 ff40 6f 2e CLR 14,Y CLEAR $DFDE
1289 ff42 86 f0 LDA #$F0 DESTINED FOR IC8 AN MEM EXPANSION ?
1290 ff44 a7 2f STA 15,Y STORE AT $DFDF
1291 ff46 86 0c LDA #$0C PRESET NUMBER OF BYTES TO CLEAR
1292 ff48 6f a6 CLRLRT CLR A,Y CLEAR $DFDC THRU $DFD0
1293 ff4a 4a DECA SUB. 1 FROM BYTES LEFT TO CLEAR
1294 ff4b 2a fb BPL CLRLRT CONTINUE IF NOT DONE CLEARING
1295 ff4d 30 89 f0 00 FNDRAM LEAX -$1000,X POINT TO NEXT LOWER 4K OF RAM
1296 ff51 8c f0 a0 CMPX #$F0A0 TEST FOR DECREMENT PAST ZERO
1297 ff54 27 22 BEQ FINTAB SKIP IF FINISHED
1298 ff56 ee 84 LDU ,X SAVE DATA AT CURRENT TEST LOCATION
1299 ff58 10 8e 55 aa LDY #TSTPAT LOAD TEST DATA PATTERN INTO Y REG.
1300 ff5c 10 af 84 STY ,X STORE TEST PATT. INTO RAM TEST LOC.
1301 ff5f 10 ac 84 CMPY ,X VERIFY RAM AT TEST LOCATION
1302 ff62 26 e9 BNE FNDRAM IF NO RAM GO LOOK 4K LOWER
1303 ff64 ef 84 STU ,X ELSE RESTORE DATA TO TEST LOCATION
1304 ff66 10 8e df d0 LDY #LRARAM POINT TO LOGICAL/REAL ADDR. TABLE
1305 ff6a 1f 10 TFR X,D PUT ADDR. OF PRESENT 4K BLOCK IN D
1306 ff6c 44 LSRA PUT MS 4 BITS OF ADDR. IN LOC. D0-D3
1307 ff6d 44 LSRA TO ALLOW STORING IT IN THE DAT RAM.
1308 ff6e 44 LSRA
1309 ff6f 44 LSRA
1310 ff70 1f 89 TFR A,B SAVE OFFSET INTO LRARAM TABLE
1311 ff72 88 0f EORA #$0F INVERT MSB OF ADDR. OF CURRENT 4K BLK
1312 ff74 a7 a5 STA B,Y SAVE TRANSLATION FACTOR IN LRARAM TABLE
1313 ff76 20 d5 BRA FNDRAM GO TRANSLATE ADDR. OF NEXT 4K BLK
1314 ff78 86 f1 FINTAB LDA #$F1 DESTINED FOR IC8 AND MEM EXPANSION ?
1315 ff7a 10 8e df d0 LDY #LRARAM POINT TO LRARAM TABLE
1316 ff7e a7 2e STA 14,Y STORE $F1 AT $DFCE
1317 *
1318 * THE FOLLOWING CHECKS TO SEE IF THERE IS A 4K BLK OF
1319 * RAM LOCATED AT $C000-$CFFF. IF NONE THERE IT LOCATES
1320 * THE NEXT LOWER 4K BLK AN XLATES ITS ADDR SO IT
1321 * LOGICALLY RESPONDS TO THE ADDRESS $C---.
1322 *
1323 *
1324 ff80 86 0c LDA #$0C PRESET NUMBER HEX "C"
1325 ff82 e6 a6 FINDC LDB A,Y GET ENTRY FROM LRARAM TABLE
1326 ff84 26 05 BNE FOUNDC BRANCH IF RAM THIS PHYSICAL ADDR.
1327 ff86 4a DECA ELSE POINT 4K LOWER
1328 ff87 2a f9 BPL FINDC GO TRY AGAIN
1329 ff89 20 14 BRA XFERTF
1330 ff8b 6f a6 FOUNDC CLR A,Y CLR XLATION FACTOR OF 4K BLOCK FOUND
1331 ff8d e7 2c STB $C,Y GIVE IT XLATION FACTOR MOVING IT TO $C---
1332 *
1333 * THE FOLLOWING CODE ADJUSTS THE TRANSLATION
1334 * FACTORS SUCH THAT ALL REMAINING RAM WILL
1335 * RESPOND TO A CONTIGUOUS BLOCK OF LOGICAL
1336 * ADDRESSES FROM $0000 AND UP....
1337 *
1338 ff8f 4f CLRA START AT ZERO
1339 ff90 1f 21 TFR Y,X START POINTER "X" START OF "LRARAM" TABLE.
1340 ff92 e6 a6 COMPRS LDB A,Y GET ENTRY FROM "LRARAM" TABLE
1341 ff94 27 04 BEQ PNTNXT IF IT'S ZER0 SKIP
1342 ff96 6f a6 CLR A,Y ELSE ERASE FROM TABLE
1343 ff98 e7 80 STB ,X+ AND ENTER ABOVE LAST ENTRY- BUMP
1344 ff9a 4c PNTNXT INCA GET OFFSET TO NEXT ENTRY
1345 ff9b 81 0c CMPA #$0C LAST ENTRY YET ?
1346 ff9d 2d f3 BLT COMPRS
1347 *
1348 * THE FOLLOWING CODE TRANSFER THE TRANSLATION
1349 * FACTORS FROM THE LRARAM TABLE TO IC11 ON
1350 * THE MP-09 CPU CARD.
1351 *
1352 ff9f 8e ff f0 XFERTF LDX #IC11 POINT TO DAT RAM IC11
1353 ffa2 c6 10 LDB #$10 GET NO. OF BYTES TO MOVE
1354 ffa4 a6 a0 FETCH LDA ,Y+ GET BYTE AND POINT TO NEXT
1355 ffa6 a7 80 STA ,X+ POKE XLATION FACTOR IN IC11
1356 ffa8 5a DECB SUB 1 FROM BYTES TO MOVE
1357 ffa9 26 f9 BNE FETCH CONTINUE UNTIL 16 MOVED
1358 ffab 53 COMB SET "B" NON-ZERO
1359 ffac f7 df e2 STB ECHO TURN ON ECHO FLAG
1360 ffaf 16 f8 62 LBRA MONITOR INITIALIZATION IS COMPLETE
1361 *
1362 *
1363 ffb2 6e 9f df c0 V1 JMP [STACK]
1364 ffb6 6e 9f df c4 V2 JMP [SWI2]
1365 ffba 6e 9f df c6 V3 JMP [FIRQ]
1366 ffbe 6e 9f df c8 V4 JMP [IRQ]
1367 ffc2 6e 9f df ca V5 JMP [SWI]
1368 *
1369 * SWI3 ENTRY POINT
1370 *
1371 ffc6 1f 43 SWI3E TFR S,U
1372 ffc8 ae 4a LDX 10,U *$FFC8
1373 ffca e6 80 LDB ,X+
1374 ffcc af 4a STX 10,U
1375 ffce 4f CLRA
1376 ffcf 58 ASLB
1377 ffd0 49 ROLA
1378 ffd1 be df cc LDX SVCVO
1379 ffd4 8c ff ff CMPX #$FFFF
1380 ffd7 27 0f BEQ SWI3Z
1381 ffd9 30 8b LEAX D,X
1382 ffdb bc df ce CMPX SVCVL
1383 ffde 22 08 BHI SWI3Z
1384 ffe0 34 10 PSHS X
1385 ffe2 ec c4 LDD ,U
1386 ffe4 ae 44 LDX 4,U
1387 ffe6 6e f1 JMP [,S++]
1388 ffe8 37 1f SWI3Z PULU A,B,X,CC,DP
1389 ffea ee 42 LDU 2,U
1390 ffec 6e 9f df c2 JMP [SWI3]
1391 *
1392 * 6809 VECTORS
1393 *
1394 fff0 ff b2 FDB V1 USER-V
1395 fff2 ff c6 FDB SWI3E SWI3-V
1396 fff4 ff b6 FDB V2 SWI2-V
1397 fff6 ff ba FDB V3 FIRQ-V
1398 fff8 ff be FDB V4 IRQ-V
1399 fffa ff c2 FDB V5 SWI-V
1400 fffc ff b2 FDB V1 NMI-V
1401 fffe ff 00 FDB START RESTART-V
1402 END START
/asref.man
0,0 → 1,2245
 
 
 
 
 
 
 
 
 
MOTOROLA
 
FREEWARE
 
8-BIT CROSS ASSEMBLERS
 
USER'S MANUAL
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
EDITED BY
 
KEVIN ANDERSON
 
FIELD APPLICATIONS ENGINEER
 
 
 
 
 
 
 
 
 
 
 
 
 
 
TABLE OF CONTENTS
 
CHAPTER 1......................................................... 1
 
1.1 INTRODUCTION .......................................... 1
1.2 ASSEMBLY LANGUAGE ..................................... 1
1.3 OPERATING ENVIRONMENT ................................. 2
1.4 ASSEMBLER PROCESSING .................................. 2
 
CHAPTER 2 ........................................................ 3
 
2.1 INTRODUCTION .......................................... 3
2.2 SOURCE STATEMENT FORMAT ............................... 3
2.2.1 Label Field .................................... 3
2.2.2 Operation Field ................................ 4
2.2.3 Operand Field .................................. 4
2.2.3.1 M6800/6801 Operand Syntax ................ 5
2.2.3.2 M6800/M68HC04 Operand Syntax ............. 5
2.2.3.3 M6805/M68HC05 Operand Syntax ............. 5
2.2.3.4 M6809 Operand Syntax ..................... 5
2.2.3.5 M68HC11 Operand Syntax ................... 6
2.2.3.6 Expressions .............................. 6
2.2.3.7 Operators ................................ 7
2.2.3.8 Symbols .................................. 7
2.2.3.9 Constants ................................ 7
2.2.4 Comment Field .................................. 8
2.3 ASSEMBLER OUTPUT ...................................... 9
 
CHAPTER 3 - RUNNING THE ASSEMBLERS ............................... 10
 
3.1 ASSEMBLER INVOCATION .................................. 10
3.2 ERROR MESSAGES ........................................ 11
 
CHAPTER 4 - ASSEMBLER DIRECTIVES ................................. 12
 
4.1 INTRODUCTION .......................................... 12
4.2 BSZ - BLOCK STORAGE OF ZEROS .......................... 12
4.3 EQU - EQUATE SYMBOL TO A VALUE ........................ 13
4.4 FCB - FORM CONSTANT BYTE .............................. 13
4.5 FCC - FORM CONSTANT CHARACTER STRING .................. 13
4.6 FDB - FROM DOUBLE BYTE CONSTANT ....................... 13
4.7 FILL - FILL MEMORY .................................... 14
4.8 OPT - ASSEMBLER OUTPUT OPTIONS ........................ 14
4.9 ORG - SET PROGRAM COUNTER TO ORIGIN ................... 14
4.10 PAGE - TOP OF PAGE ................................... 15
4.11 RMB - RESERVE MEMORY BYTES ........................... 15
4.12 ZMB - ZERO MEMORY BYTES .............................. 15
 
APPENDIX A - CHARACTER SET ....................................... 16
 
APPENDIX B - ADDRESSING MODES .................................... 18
 
B.1 M6800/M6801 ADDRESSING MODES .......................... 18
B.2 M6804/68HC04 ADDRESSING MODES ......................... 19
B.3 M6805/68HC05 ADDRESSING MODES ......................... 21
 
 
 
i
 
 
 
 
 
 
 
TABLE OF CONTENTS
 
B.4 M6809 ADDRESSING MODES ................................ 22
B.5 M68HC11 ADDRESSING MODES .............................. 26
 
APPENDIX C - DIRECTIVE SUMMARY ................................... 28
 
APPENDIX D - ASSEMBLER LISTING FORMAT ............................ 29
 
APPENDIX E - S-RECORD INFORMATION ................................ 30
 
E.1 INTRODUCTION .......................................... 30
E.2 S-RECORD CONTENT ...................................... 30
E.3 S-RECORD TYPES ........................................ 30
E.4 S-RECORD EXAMPLE ...................................... 31
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
ii
 
 
 
 
 
 
 
CHAPTER 1
GENERAL INFORMATION
 
 
1.1 INTRODUCTION
 
This is the user's reference manual for the IBM-PC hosted Motorola
Freeware 8 bit cross assemblers. It details the features and
capabilities of the cross assemblers, assembler syntax and directives,
options, and listings. It is intended as a detailed reference and an
introduction for those unfamiliar with Motorola assembler syntax and
format. Those experienced with Motorola assembler products may wish
to examine the file ASEMBLER.DOC available with the cross assemblers,
which briefly describes the differences between these assemblers and
earlier, non-pc based versions.
 
Assemblers are programs that process assembly language source program
statements and translate them into executable machine language object
files. A programmer writes his source program using any text editor
or word processor that can produce an ASCII text output. With some
word processors this is known as "non document" mode. Non document
mode produces a file without the non-printable embedded control
characters that are used in document formating. (Caution: assembling
a file that has been formatted with embedded control characters may
produce assembler errors. The solution is to convert the source file
to ASCII text.) Once the source code is written, the source file is
assembled by processing the file via the assembler.
 
Cross assemblers (such as the Motorola Freeware Assemblers) allow
source programs written and edited on one computer (the host) to
generate executable code for another computer (the target). The
executable object file can then be downloaded and run on the target
system. In this case the host is an IBM-PC or compatible and the
target system is based on a Motorola 8-bit microprocessor (6800, 6801,
6803, 6805, 68HC05, 6809, or 68HC11).
 
The assemblers are the executable programs AS*.EXE where * is any of
0, 1, 4, 5, 9, or 11 depending on which microprocessor you are writing
code for. The details of executing the assembler programs are found
in Chapter 3. The assembly language format and syntax for the various
processors is very similar with slight variations due to varied
programming resources (instructions, addressing modes, and registers).
These variations are explained in Appendix B.
 
 
1.2 ASSEMBLY LANGUAGE
 
The symbolic language used to code source programs to be processed by
the Assembler is called assembly language. The language is a
collection of mnemonic symbols representing: operations (i.e., machine
instruction mnemonics or directives to the assembler), symbolic names,
operators, and special symbols. The assembly language provides
mnemonic operation codes for all machine instructions in the
instruction set. The instructions are defined and explained in the
Programming Reference Manuals for the specific devices, available from
Motorola. The assembly language also contains mnemonic directives
 
 
 
 
 
 
 
Freeware Assemblers User's Manual
 
 
which specify auxiliary actions to be performed by the Assembler.
These directives are not always translated into machine language.
 
 
1.3 OPERATING ENVIRONMENT
 
These assemblers will run on any IBM-PC, XT, AT, PS-2, or true
compatible. The assemblers may be run off of a floppy disk drive or
they may be copied onto a hard drive for execution. DOS 2.0 or later
is required.
 
 
1.4 ASSEMBLER PROCESSING
 
The Macro Assembler is a two-pass assembler. During the first pass,
the source program is read to develop the symbol table. During the
second pass, the object file is created (assembled) with reference to
the table developed in pass one. It is during the second pass that
the source program listing is also produced.
 
Each source statement is processed completely before the next source
statement is read. As each statement is processed, the Assembler
examines the label, operation code, and operand fields. The operation
code table is scanned for a match with a known opcode. During the
processing of a standard operation code mnemonic, the standard
machine code is inserted into the object file. If an Assembler
directive is being processed, the proper action is taken.
 
Any errors that are detected by the Assembler are displayed before the
actual line containing the error is printed. If no source listing is
being produced, error messages are still displayed to indicate that
the assembly process did not proceed normally.
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
2
 
 
 
 
Freeware Assemblers User's Manual
 
 
CHAPTER 2
CODING ASSEMBLY LANGUAGE PROGRAMS
 
 
2.1 INTRODUCTION
 
Programs written in assembly language consist of a sequence of source
statements. Each source statement consists of a sequence of ASCII
characters ending with a carriage return. Appendix A contains a list
of the supported character set.
 
 
2.2 SOURCE STATEMENT FORMAT
 
Each source statement may include up to four fields: a label (or "*"
for a comment line), an operation (instruction mneumonic or assembler
directive), an operand, and a comment.
 
 
2.2.1 Label Field
 
The label field occurs as the first field of a source statement. The
label field can take one of the following forms:
 
1. An asterisk (*) as the first character in the label field indicates
that the rest of the source statement is a comment. Comments are
ignored by the Assembler, and are printed on the source listing only
for the programmer's information.
 
2. A whitespace character (blank or tab) as the first character
indicates that the label field is empty. The line has no label and is
not a comment.
 
3. A symbol character as the first character indicates that the line
has a label. Symbol characters are the upper or lower case letters a-
z, digits 0-9, and the special characters, period (.), dollar sign
($), and underscore (_). Symbols consist of one to 15 characters, the
first of which must be alphabetic or the special characters period (.)
or underscore (_). All characters are significant and upper and lower
case letters are distinct.
 
A symbol may occur only once in the label field. If a symbol does
occur more than once in a label field, then each reference to that
symbol will be flagged with an error.
 
With the exception of some directives, a label is assigned the value
of the program counter of the first byte of the instruction or data
being assembled. The value assigned to the label is absolute.
Labels may optionally be ended with a colon (:). If the colon is
used it is not part of the label but merely acts to set the label off
from the rest of the source line. Thus the following code fragments
are equivalent:
 
here: deca
bne here
 
 
 
3
 
 
 
 
Freeware Assemblers User's Manual
 
 
here deca
bne here
 
A label may appear on a line by itself. The assembler interprets this
as set the value of the label equal to the current value of the
program counter.
 
The symbol table has room for at least 2000 symbols of length 8
characters or less. Additional characters up to 15 are permissible at
the expense of decreasing the maximum number of symbols possible in
the table.
 
 
2.2.2 Operation Field
 
The operation field occurs after the label field, and must be preceded
by at least one whitespace character. The operation field must contain
a legal opcode mneumonic or an assembler directive. Upper case
characters in this field are converted to lower case before being
checked as a legal mneumonic. Thus 'nop', 'NOP', and 'NoP' are
recognized as the same mneumonic. Entries in the operation field may
be one of two types:
 
Opcode. These correspond directly to the machine instructions. The
operation code includes any register name associated with the
instruction. These register names must not be separated from the
opcode with any whitespace characters. Thus 'clra' means clear
accumulator A, but 'clr a' means clear memory location identified by
the label 'a'.
 
Directive. These are special operation codes known to the Assembler
which control the assembly process rather than being translated into
machine instructions.
 
 
2.2.3 Operand Field
 
The operand field's interpretation is dependent on the contents of the
operation field. The operand field, if required, must follow the
operation field, and must be preceded by at least one whitespace
character. The operand field may contain a symbol, an expression, or a
combination of symbols and expressions separated by commas.
 
The operand field of machine instructions is used to specify the
addressing mode of the instruction, as well as the operand of the
instruction. The following tables summarize the operand field
formats for the various processor families. (NOTE: in these tables
parenthesis "()" signify optional elements and angle brackets "<>"
denote an expression is inserted. These syntax elements are present
only for clarification of the format and are not inserted as part of
the actual source program. All other characters are significant and
must be used when required.)
 
 
 
 
 
 
4
 
 
 
 
Freeware Assemblers User's Manual
 
 
2.2.3.1 M6800/6801 Operand Syntax
 
The format of the operand field for M6800/6801 instructions is:
 
Operand Format M6800/M6801 Addressing Mode
-------------- ---------------------------
no operand accumulator and inherent
<expression> direct, extended, or relative
#<expression> immediate
<expression>,X indexed
 
Details of the M6800/6801 addressing modes may be found in Appendix B.
 
 
2.2.3.2 M6804/68HC Operand Syntax
 
For the M6804/68HC04, the following operand formats exist:
 
Operand Format M6804/68HC04 Addressing Mode
-------------- ----------------------------
no operand accumulator and inherent
<expression> direct, extended, or relative
#<expression> immediate
<expression> bit set or clear
<expression>,<expression> bit test and branch
[<x> or <y>] register indirect
<expression>,#<expression> move indirect
 
Details of the M6804/68HC04 addressing modes may be found in Appendix
B.
 
 
2.2.3.3 M6805/M68HC05 Operand Syntax
 
For the M6805/68HC05, the operand formats are:
 
Operand Format M6805/68HC05 Addressing Mode
-------------- ----------------------------
no operand accumulator and inherent
<expression> direct, extended, or relative
#<expression> immediate
<expression>,X indexed
<expression>,<expression> bit set or clear
<expression>,<expression>,<expression> bit test and branch
 
Details of the M6805/68HC05 addressing modes may be found in Appendix
B.
 
 
2.2.3.4 M6809 Operand Syntax
 
For the M6809, the following operand formats are used:
 
 
 
 
 
 
5
 
 
 
 
Freeware Assemblers User's Manual
 
 
Operand Format M6809 Addressing Mode
-------------- ---------------------
no operand accumulator and inherent
<expression> direct, extended, or relative
#<expression> immediate
<expression>,X indexed
<<expression> forced direct
><expression> forced extended
<expression>] extended indirect
<expression>,R indexed
<<expression>,R forced 8-bit offset indexed
><expression>,R forced 16-bit offset indexed
[<expression>,R] indexed indirect
<[<expression>,R] forced 8-bit offset indexed indirect
>[<expression>,R] forced 16-bit offset indexed indirect
Q+ auto increment by 1
Q++ auto increment by 2
[Q++] auto increment indirect
-Q auto decrement by
--Q auto decrement by 2
[--Q] auto decrement indirect
W1,[W2,...,Wn] immediate
 
where R is one of the registers PCR, S, U, X, or Y, and Q is one of
the registers S, U, X, or Y. Wi (i=1 to n) is one of the symbols A,
B, CC, D, DP, PC, S, U, X, or Y.
 
Details of the M6809 addressing modes may be found in Appendix B.
 
 
2.2.3.5 M68HC11 Operand Syntax
 
For the M68HC11, the following operand formats exist:
 
Operand Format M68HC11 Addressing Mode
-------------- -----------------------
no operand accumulator and inherent
<expression> direct, extended, or relative
#<expression> immediate
<expression>,X indexed with X register
<expression>,Y indexed with Y register
<expression> <expression> bit set or clear
<expression> <expression> <expression> bit test and branch
 
The bit manipulation instruction operands are separated by spaces in
this case since the HC11 allows bit manipulation instructions on
indexed addresses. Thus a ',X' or ',Y' may be added to the final two
formats above to form the indexed effective address calculation.
 
Details of the M68HC11 addressing modes may be found in Appendix B.
The operand fields of assembler directives are described in Chapter 4.
 
 
2.2.3.6 Expressions. An expression is a combination of symbols,
constants, algebraic operators, and parentheses. The expression is
used to specify a value which is to be used as an operand.
 
 
6
 
 
 
 
Freeware Assemblers User's Manual
 
 
Expressions may consist of symbols, constants, or the character '*'
(denoting the current value of the program counter) joined together by
one of the operators: + - * / % & | ^ .
 
 
2.2.3.7 Operators. The operators are the same as in c:
 
+ add
- subtract
* multiply
/ divide
% remainder after division
& bitwise and
| bitwise or
^ bitwise exclusive or
 
Expressions are evaluated left to right and there is no provision for
parenthesized expressions. Arithmetic is carried out in signed two-
complement integer precision (that's 16 bits on the IBM PC).
 
 
2.2.3.8 Symbols. Each symbol is associated with a 16-bit integer
value which is used in place of the symbol during the expression
evaluation. The asterisk (*) used in an expression as a symbol
represents the current value of the location counter (the first byte
of a multi-byte instruction).
 
 
2.2.3.9 Constants. Constants represent quantities of data that do
not vary in value during the execution of a program. Constants may be
presented to the assembler in one of five formats: decimal,
hexadecimal, binary, or octal, or ASCII. The programmer indicates the
number format to the assembler with the following prefixes:
 
$ HEX
% BINARY
@ OCTAL
' ASCII
 
Unprefixed constants are interpreted as decimal. The assembler
converts all constants to binary machine code and are displayed in the
assembly listing as hex.
 
A decimal constant consists of a string of numeric digits. The value
of a decimal constant must fall in the range 0-65535, inclusive. The
following example shows both valid and invalid decimal constants:
 
VALID INVALID REASON INVALID
----- ------- --------------
12 123456 more than 5 digits
12345 12.3 invalid character
 
A hexadecimal constant consists of a maximum of four characters from
the set of digits (0-9) and the upper case alphabetic letters (A-F),
and is preceded by a dollar sign ($). Hexadecimal constants must be
 
 
 
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Freeware Assemblers User's Manual
 
 
in the range $0000 to $FFFF. The following example shows both valid
and invalid hexadecimal constants:
 
VALID INVALID REASON INVALID
----- ------- --------------
$12 ABCD no preceding "$"
$ABCD $G2A invalid character
$001F $2F018 too many digits
 
A binary constant consists of a maximum of 16 ones or zeros preceded
by a percent sign (%). The following example shows both valid and
invalid binary constants:
 
VALID INVALID REASON INVALID
----- ------- --------------
%00101 1010101 missing percent
%1 %10011000101010111 too many digits
%10100 %210101 invalid digit
 
An octal constant consists of a maximum of six numeric digits,
excluding the digits 8 and 9, preceded by a commercial at-sign (@).
Octal constants must be in the ranges @0 to @177777. The following
example shows both valid and invalid octal constan
ts:
 
VALID INVALID REASON INVALID
----- ------- --------------
@17634 @2317234 too many digits
@377 @277272 out of range
@177600 @23914 invalid character
 
A single ASCII character can be used as a constant in expressions.
ASCII constants are preceded by a single quote ('). Any character,
including the single quote, can be used as a character constant. The
following example shows both valid and inval
id character constants:
 
VALID INVALID REASON INVALID
----- ------- --------------
'* 'VALID too long
 
For the invalid case above the assembler will not indicate an error.
Rather it will assemble the first character and ignore the remainder.
 
 
2.2.4 Comment Field
 
The last field of an Assembler source statement is the comment field.
This field is optional and is only printed on the source listing for
documentation purposes. The comment field is separated from the
operand field (or from the operation field if no operand is required)
by at least one whitespace character. The comment field can contain
any printable ASCII characters.
 
 
 
 
 
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Freeware Assemblers User's Manual
 
 
2.3 ASSEMBLER OUTPUT
 
The Assembler output includes an optional listing of the source
program and an object file which is in the Motorola S Record format.
Details of the S Record format may be found in Appendix E. The
Assembler will normally suppress the printing of the source listing.
This condition, as well as others, can be overridden via options
supplied on the command line that invoked the Assembler.
 
Each line of the listing contains a reference line number, the address
and bytes assembled, and the original source input line. If an input
line causes more than 6 bytes to be output (e.g. a long FCC
directive), additional bytes (up to 64) are listed on succeeding lines
with no address preceding them.
 
The assembly listing may optionally contain a symbol table or a cross
reference table of all symbols appearing in the program. These are
always printed at the end of the assembly listing if either the symbol
table or cross reference table options (Paragraph 4.8) are in effect.
The symbol table contains the name of each symbol, along with its
defined value. The cross reference table additionally contains the
assembler-maintained source line number of every reference to every
symbol. The format of the cross reference table is shown in Appendix
D.
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
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Freeware Assemblers User's Manual
 
 
CHAPTER 3
RUNNING THE ASSEMBLERS
 
 
3.1 ASSEMBLER INVOCATION
 
The Motorola Freeware Assembly programs are named as*.exe where '*' is
any of 0, 1, 4, 5, 9, or 11 depending on which processor family you
wish to assemble code for. For example, to generate M6800 code run
the as0.exe program. To generate M68HC05 code run the as5.exe
program, and so forth. To run the assembler enter the following
command line:
 
as* file1 (file2 . . . ) ( - option1 option2 . . . )
 
where file1, file2, etc are the names of the source files you wish to
assemble. The source filenames may have extensions but the assembler
does not check for any particular extension ( however, do not use the
.S19 extension since that is the extension of the object file created
by the assembler. Its creation would overwrite the source file when
it is written to the disk).
 
The options are one or more of the following:
 
l enables output listing
no disables output listing (default).
cre enables the cross reference table generation
s enables the symbol table generation
c enables cycle counting
noc disables cycle counting
 
The minus sign preceding the option should be separated from the last
file name by a space. These options may also be indicated to the
assembler by the use of the OPT directive in the source file. The OPT
directive is described in Paragraph 4.8.
 
The object file created is written to disk and given the name
'FILENAME.S19' where 'FILENAME' is the name of the first source file
specified on the command line. Any errors and the optional listing
(if specified) are displayed on the screen. The listing and/or error
messages may be saved to a file for later examination or printing by
append an i/o redirection command to the command line. On the PC i/o
redirection is indicated with the greater-than ('>') symbol followed
by any new or existing file name.
 
Command line examples:
 
The command line
 
as5 myfile
 
would run the M6805/68HC05 assembler on the source file 'myfile'. The
object file would be written to 'myfile.s19' and any errors would
appear on the screen.
 
 
 
 
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The command line
 
as9 test.asm nexttest.s -l
 
would run the M6809 assembler on the source files 'test.asm' and
'nexttest.s'. The object file would be written to 'test.s19' and any
errors and the assembly listing would appear on the screen.
 
The command line
 
as9 test.asm nexttest.s -l cre s >test.lst
 
would run the M6809 assembler on the source files 'test.asm' and
'nexttest.s'. The object file would be written to 'test.s19'. A
listing would be created followed by a symbol table and cross
reference which would all be written to the file test.lst
.
 
3.2 ERROR MESSAGES
 
Error diagnostic messages are placed in the listing file just before
the line containing the error. The format of the error line is:
 
Line_number: Description of error
 
or
 
Line_number: Warning ---- Description of error
 
Errors in pass one cause cancellation of pass two. Warning do not
cause cancellation of pass two but are indications of a possible
problem. Error messages are meant to be self-explanatory.
 
If more than one file is being assembled, the file name precedes the
error:
 
File_name,Line_number: Description of error
 
Some errors are classed as fatal and cause an immediate termination of
the assembly. Generally this happens when a temporary file cannot be
created or is lost during assembly.
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
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Freeware Assemblers User's Manual
 
 
CHAPTER 4
ASSEMBLER DIRECTIVES
 
 
4.1 INTRODUCTION
 
The Assembler directives are instructions to the Assembler, rather
than instructions to be directly translated into object code. This
chapter describes the directives that are recognized by the Freeware
Assemblers. Detailed descriptions of each directive are arranged
alphabetically. The notations used in this chapter are:
 
( ) Parentheses denote an optional element.
 
XYZ The names of the directives are printed in capital letters.
 
< > The element names are printed in lower case and contained in
angle brackets. All elements outside of the angle brackets '<>' must
be specified as-is. For example, the syntactical element (<number>,)
requires the comma to be specified if the optional element <number> is
selected. The following elements are used in the subsequent
descriptions:
 
 
<comment> A statement's comment field
<label> A statement label
<expression> An Assembler expression
<expr> An Assembler expression
<number> A numeric constant
<string> A string of ASCII characters
<delimiter> A string delimiter
<option> An Assembler option
<symbol> An Assembler symbol
<sym> An Assembler symbol
<sect> A relocatable program section
<reg list> M6809 register list
<reg exp> M6809 register expression
 
 
In the following descriptions of the various directives, the syntax,
or format, of the directive is given first. This will be followed
with the directive's description.
 
4.2 BSZ - BLOCK STORAGE OF ZEROS
 
(<label>) BSZ <expression> (<comment>)
 
The BSZ directive causes the Assembler to allocate a block of bytes.
Each byte is assigned the initial value of zero. The number of bytes
allocated is given by the expression in the operand field. If the
expression contains symbols that are either undefined or forward
referenced (i.e. the definition occurs later on in the file), or if
the expression has a value of zero, an error will be generated.
 
 
 
 
 
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4.3 EQU - EQUATE SYMBOL TO A VALUE
 
<label> EQU <expression> (<comment>)
 
The EQU directive assigns the value of the expression in the operand
field to the label. The EQU directive assigns a value other than the
program counter to the label. The label cannot be redefined anywhere
else in the program. The expression cannot contain any forward
references or undefined symbols. Equates with forward references are
flagged with Phasing Errors.
 
4.4 FCB - FORM CONSTANT BYTE
 
(<label>) FCB <expr>(,<expr>,...,<expr>) (<comment>)
 
The FCB directive may have one or more operands separated by commas.
The value of each operand is truncated to eight bits, and is stored in
a single byte of the object program. Multiple operands are stored in
successive bytes. The operand may be a numeric constant, a character
constant, a symbol, or an expression. If multiple operands are
present, one or more of them can be null (two adjacent commas), in
which case a single byte of zero will be assigned for that operand.
An error will occur if the upper eight bits of the evaluated operands'
values are not all ones or all zeros.
 
4.5 FCC - FORM CONSTANT CHARACTER STRING
 
(<label>) FCC <delimiter><string><delimiter> (<comment>)
 
The FCC directive is used to store ASCII strings into consecutive
bytes of memory. The byte storage begins at the current program
counter. The label is assigned to the first byte in the string. Any
of the printable ASCII characters can be contained in the string. The
string is specified between two identical delimiters which can be any
printable ASCII character. The first non-blank character after the FCC
directive is used as the delimiter.
 
Example:
 
LABEL1 FCC , ABC,
 
assembles ASCII ABC at location LABEL1
 
 
4.6 FDB - FORM DOUBLE BYTE CONSTANT
 
(<label>) FDB <expr>(,<expr>,...,<expr>) (<comment>)
 
The FDB directive may have one or more operands separated by commas.
The 16-bit value corresponding to each operand is stored into two
consecutive bytes of the object program. The storage begins at the
current program counter. The label is assigned to the first 16-bit
value. Multiple operands are stored in successive bytes. The operand
may be a numeric constant, a character constant, a symbol, or an
expression. If multiple operands are present, one or more of them can
 
 
 
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Freeware Assemblers User's Manual
 
 
be null (two adjacent commas), in which case two bytes of zeros will
be assigned for that operand.
 
4.7 FILL - FILL MEMORY
 
(<label>) FILL <expression>,<expression>
 
The FILL directive causes the assembler to initialize an area of
memory with a constant value. The first expression signifies the one
byte value to be placed in the memory and the second expression
indicates the total number of successive bytes to be initialized. The
first expression must evaluate to the range 0-255. Expressions cannot
contain forward references or undefined symbols.
 
4.8 OPT - ASSEMBLER OUTPUT OPTIONS
 
OPT <option>(,<option>,...,<option>) (<comment>)
 
The OPT directive is used to control the format of the Assembler
output. The options are specified in the operand field, separated by
commas. All options have a default condition. Some options can be
initialized from the command line that invoked the Assembler, however
the options contained in the source file take precedence over any
entered on the command line. In the following descriptions, the
parenthetical inserts specify "DEFAULT", if the option is the default
condition. All options must be entered in lower case.
 
c - Enable cycle counting in the listing. The total cycle count
for that instruction will appear in the listing after the assembled
bytes and before the source code.
 
cre - Print a cross reference table at the end of the source
listing. This option, if used, must be specified before the first
symbol in the source program is encountered. The cross reference
listing format may be found in Appendix D.
 
l - Print the listing from this point on. A description of the
listing format can be found in Appendix D.
 
noc - (DEFAULT) Disable cycle counting in the listing. If the "c"
option was used previously in the program, this option will cause
cycle counting to cease until the next "OPT c" statement.
 
nol - (DEFAULT) Do not print the listing from this point on. An
"OPT l" can re-enble listing at a later point in the program.
 
s - Print symbol table at end of source listing. The symbol table
format can be found in Appendix D.
 
 
4.9 ORG - SET PROGRAM COUNTER TO ORIGIN
 
ORG <expression> (<comment>)
 
The ORG directive changes the program counter to the value specified
by the expression in the operand field. Subsequent statements are
 
 
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Freeware Assemblers User's Manual
 
 
assembled into memory locations starting with the new program counter
value. If no ORG directive is encountered in a source program, the
program counter is initialized to zero. Expressions cannot contain
forward references or undefined symbols.
 
 
4.10 PAGE - TOP OF PAGE
 
PAGE
 
The PAGE directive causes the Assembler to advance the paper to the
top of the next page. If no source listing is being produced, the PAGE
directive will have no effect. The directive is not printed on the
source listing.
 
 
4.11 RMB - RESERVE MEMORY BYTES
 
(<label>) RMB <expression> (<comment>)
 
The RMB directive causes the location counter to be advanced by the
value of the expression in the operand field. This directive reserves
a block of memory the length of which in bytes is equal to the value
of the expression. The block of memory reserved is not initialized to
any given value. The expression cannot contain any forward references
or undefined symbols. This directive is commonly used to reserve a
scratchpad or table area for later use.
 
4.12 ZMB - ZERO MEMORY BYTES (same as BSZ)
 
(<label>) ZMB <expression> (<comment>)
 
The ZMB directive causes the Assembler to allocate a block of bytes.
Each byte is assigned the initial value of zero. The number of bytes
allocated is given by the expression in the operand field. If the
expression contains symbols that are either undefined or forward
references, or if the expression has a value of zero, an error will be
generated.
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
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Freeware Assemblers User's Manual
 
 
APPENDIX A
CHARACTER SET
 
 
The character set recognized by the Freeware Assemblers is a subset of
ASCII. The ASCII code is shown in the following figure. The following
characters are recognized by the Assembler:
 
1. The upper case letters A through Z and lower case letters a
through z.
 
2. The digits 0 through 9.
 
3. Five arithmetic operators: +, -, *, / and % (remainder
after division).
 
4. Three logical operators: &, |, and ^.
 
5. The special symbol characters: underscore (_), period (.),
and dollar sign ($). Only the underscore and period may be
used as the first character of a symbol.
 
6. The characters used as prefixes for constants and
addressing modes:
 
# Immediate addressing
$ Hexadecimal constant
& Decimal constant
@ Octal constant
% Binary constant
' ASCII character constant
 
7. The characters used as suffixes for constants and
addressing modes:
 
,X Indexed addressing
,PCR M6809 indexed addressing
,S M6809 indexed addressing
,U M6809 indexed addressing
,Y M6809 and M68HC11 indexed addressing
 
8. Three separator characters: space, carriage return, and
comma.
 
9. The character "*" to indicate comments. Comments may
contain any printable characters from the ASCII set.
 
10. The special symbol backslash "\" to indicate line
continuation. When the assembler encounters the line
continuation character it fetches the next line and adds it
to the end of the first line. This continues until a line
is seen which doesn't end with a backslash or until the
system maximum buffer size has been collected (typically
greater or equal to 256).
 
 
 
 
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Freeware Assemblers User's Manual
 
 
11. For the M6809 Assembler, the character "<" preceding an
expression to indicate direct addressing mode or 8-bit
offset in indexed mode, and the character ">" preceding an
expression to indicate extended addressing mode or 16-bit
offset in indexed mode.
 
12. For the M6809 Assembler, the characters used to indicate
auto increment and auto decrement in the indexed mode: +,
++, -, --.
 
 
 
 
ASCII CHARACTER CODES
 
 
BITS 4 to 6 -- 0 1 2 3 4 5 6 7
----------- -------------------------------------
 
0 NUL DLE SP 0 @ P ` p
B 1 SOH DC1 : 1 A Q a q
I 2 STX DC2 ! 2 B R b r
T 3 ETX DC3 # 3 C S c s
S 4 EOT DC4 $ 4 D T d t
5 ENQ NAK % 5 E U e u
0 6 ACK SYN & 6 F V f v
7 BEL ETB ' 7 G W g w
T 8 BS CAN ( 8 H X h x
O 9 HT EM ) 9 I Y i y
A LF SUB * : J Z j z
3 B VT ESC + ; K [ k {
C FF FS , < L \ l ;
D CR GS - = M ] m }
E SO RS . > N ^ n ~
F S1 US / ? O _ o DEL
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
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Freeware Assemblers User's Manual
 
 
APPENDIX B
ADDRESSING MODES
 
B.1 M6800/M6801 ADDRESSING MODES.
 
INHERENT OR ACCUMULATOR ADDRESSING
The M6800 includes some instructions which require no operands. These
instructions are self-contained and employ the inherent addressing or
the accumulator addressing mode.
 
 
IMMEDIATE ADDRESSING
Immediate addressing refers to the use of one or two bytes of
information that immediately follow the operation code in memory.
Immediate addressing is indicated by preceding the operand field with
the pound sign or number sign character (#). The expression following
the # will be assigned one or two bytes of storage, depending on the
instruction.
 
 
RELATIVE ADDRESSING
Relative addressing is used by branch instructions. Branches can only
be executed within the range -126 to +129 bytes relative to the first
byte of the branch instruction. For this mode, the programmer
specifies the branch address expression and places it in the operand
field. The actual branch offset is calculated by the assembler and put
into the second byte of the branch instruction. The offset is the
two's complement of the difference between the location of the byte
immediately following the branch instruction and the location of the
destination of the branch. Branches out of bounds are flagged as
errors by the assembler.
 
 
INDEXED ADDRESSING
Indexed addressing is relative to the index register. The address is
calculated at the time of instruction execution by adding a one-byte
displacement (in the second byte of the instruction) to the current
contents of the X register. Since no sign extension is performed on
this one-byte displacement, the offset cannot be negative. Indexed
addressing is indicated by the characters ",X" following the
expression in the operand field. The special case of ",X", without a
preceding expression, is treated as "0,X".
 
 
DIRECT AND EXTENDED ADDRESSING
Direct and extended addressing utilize one (direct) or two (extended)
bytes to contain the address of the operand. Direct addressing is
limited to the first 256 bytes of memory. Direct and extended
addressing are indicated by only having an expression in the operand
field. Direct addressing will be used by the Assembler whenever
possible.
 
 
 
 
 
 
 
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Freeware Assemblers User's Manual
 
 
B.2 M6804/M68HC04 ADDRESSING MODES.
 
INHERENT OR ACCUMULATOR ADDRESSING
The M6800 includes some instructions which require no operands. These
instructions are self-contained and employ the inherent addressing or
the accumulator addressing mode.
 
 
IMMEDIATE ADDRESSING
Immediate addressing refers to the use of one byte of information that
immediately follows the operation code in memory. Immediate addressing
is indicated by preceding the operand field with the pound sign or
number sign character (#). The expression following the # will be
assigned one byte of storage.
 
 
RELATIVE ADDRESSING
Relative addressing is used by branch instructions. Branches can only
be executed within the range -15 to +16 bytes relative to the first
byte of the branch instruction. For this mode, the programmer
specifies the branch address expression and places it in the operand
field. The actual branch offset is calculated by the assembler and put
into the second byte of the branch instruction. The offset is the
two's complement of the difference between the location of the byte
immediately following the branch instruction and the location of the
destination of the branch. Branches out of bounds are flagged as
errors by the assembler.
 
 
DIRECT AND EXTENDED ADDRESSING
Direct and extended addressing utilize byte to contain the address of
the operand. Direct addressing is limited to the first 256 bytes of
memory. Extended addressing concatenates the four least-significant
bits of the opcode with the byte following the opcode to form a 12-bit
address. Direct and extended addressing are indicated by only having
an expression in the operand field. Direct addressing will be used by
the Assembler whenever possible.
 
 
SHORT DIRECT
Some opcodes allow 4 memory locations in data space ram ($80, $81,
$82, and $83 to be referenced as part of the opcode. The opcode
determines the data space RAM location, and the instruction is only
one byte. The X and Y registers are at locations $80 and $81,
respectively. An expression used with short direct addressing must
not be forward referenced (that is its definition must occur before,
not after this point in the file) and must equate to the range $80-
$83.
 
 
BIT SET AND CLEAR
In the bit set/clear addressing mode, the bit to be set or cleared is
part of the opcode. The byte following the opcode specifies the
direct address of the byte which will have the bit set or cleared.
Any bit in the 256 byte data space memory that can be written (with
 
 
 
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Freeware Assemblers User's Manual
 
 
the exception of the data direction registers) can be set or cleared
with these two byte instructions.
 
 
BIT TEST AND BRANCH
The bit test and branch addressing mode is a combination of the direct
addressing and relative addressing. The bit to be tested, and it
condition (set or clear), is included in the opcode. The data space
address of the byte to be tested is in the single byte immediately
following the opcode byte and follows direct addressing rules. The
third byte is sign extended by the processor during execution to form
the 12-bit relative address which is added to the program counter if
the condition is true. This allows branches based on any readable bit
in the data space. The branch span is -125 to +130 from the opcode
address. The branch target address is used by the programmer to
signify the relative offset -- the assembler calculates the offset
value. Branches out of bounds are flagged as errors by the
assembler.
 
 
REGISTER INDIRECT
In the register indirect mode, the operand is at the address in data
space pointed to by the contents of one of the indirect registers, X
or Y. The particular indirect register is encoded in bit 4 of the
opcode by the assembler. The assembler operand syntax for register
indirect is
 
[<X> or <Y>]
 
 
MOVE IMMEDIATE
The MVI (move immediate) instruction has its own format:
 
mvi <expression 1>,#<expression 2>
 
where <expression 1> is a direct address and <expression 2> is the
data value to be written.
 
 
MISCELLANEOUS SYNTAX ISSUES
The registers in the 6804/HC6804 are memory locations and have
addresses assigned to them. The assembler has predefined
 
a = A = $FF
b = B = $80
c = C = $81
 
This also means that for the '04 assembler clr x is equivalent to clrx
since x is both a register and a memory location.
 
The '04 series has separate program and data spaces. There is no
program memory in the range $10-$7F. Bytes assembled into that range
will go into the data space.
 
 
 
 
 
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Freeware Assemblers User's Manual
 
 
B.3 M6805/68HC05 ADDRESSING MODES.
 
INHERENT OR ACCUMULATOR ADDRESSING
The M6805 includes some instructions which require no operands. These
instructions are self-contained, and employ the inherent addressing or
the accumulator addressing mode.
 
 
IMMEDIATE ADDRESSING
Immediate addressing refers to the use of one byte of information that
immediately follows the operation code in memory. Immediate addressing
is indicated by preceding the operand field with the pound sign or
number sign character (#). The expression following the # will be
assigned one byte of storage.
 
 
RELATIVE ADDRESSING
Relative addressing is used by branch instructions. Branches can only
be executed within the range -126 to +129 bytes relative to the first
byte of the branch instruction. For this mode, the programmer
specifies the branch address expression and places it in the operand
field. The actual branch offset is calculated by the assembler and put
into the second byte of the branch instruction. The offset is the
two's complement of the difference between the location of the byte
immediately following the branch instruction and the location of the
destination of the branch. Branches out of bounds are flagged as
errors by the assembler.
 
 
INDEXED ADDRESSING
Indexed addressing is relative to the index register. The address is
calculated at the time of instruction execution by adding a one- or
two-byte displacement to the current contents of the X register. The
displacement immediately follows the operation code in memory. If the
displacement is zero, no offset is added to the index register. In
this case, only the operation code resides in memory. Since no sign
extension is performed on a one-byte displacement, the offset cannot
be negative. Indexed addressing is indicated by the characters ",X"
following the expression in the operand field. The special case of
",X", without a preceding expression, is treated as "0,X". Some
instructions do not allow a two-byte displacement.
 
 
DIRECT AND EXTENDED ADDRESSING
Direct and extended addressing utilize one (direct) or two (extended)
bytes to contain the address of the operand. Direct addressing is
limited to the first 256 bytes of memory. Direct and extended
addressing are indicated by only having an expression in the operand
field. Some instructions do not allow extended addressing. Direct
addressing will be used by the Macro Assembler whenever possible.
 
 
BIT SET OR CLEAR
The addressing mode used for this type of instruction is direct,
although the format of the operand field is different from the direct
addressing mode described above. The operand takes the form
 
 
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Freeware Assemblers User's Manual
 
 
<expression 1>, <expression 2>. <expression 1> indicates which bit is
to be set or cleared. It must be an absolute expression in the range
0-7. It is used in generating the operation code. <expression 2> is
handled as a direct address, as described above. Since the bit
manipulation address is direct, only the first 256 locations may be
operated on by bit manipulation operations.
 
 
BIT TEST AND BRANCH
This combines two addressing modes: direct and relative. The format of
the operand is: <expression 1>, <expression 2>, <expression 3>.
<expression 1> and <expression 2> are handled in the same manner as
described above in "bit set or clear". <expression 3> is used to
generate a relative address, as described above in "relative
addressing".
 
 
B.4 M6809 ADDRESSING MODES.
 
INHERENT OR ACCUMULATOR ADDRESSING
The M6809 includes some instructions which require no operands. These
instructions are self-contained, and employ the inherent addressing or
the accumulator addressing mode.
 
 
IMMEDIATE ADDRESSING
Immediate addressing refers to the use of one or two bytes of
information that immediately follow the operation code in memory.
Immediate addressing is indicated by preceding the operand field with
the pound sign or number sign (#) -- i.e., #<expression>. The
expression following the # will be assigned one or two bytes of
storage, depending on the instruction. All instructions referencing
the accumulator "A" or "B", or the condition code register "CC", will
generate a one-byte immediate value. Also, immediate addressing used
with the PSHS, PULS, PSHU, and PULU instructions generates a one-byte
immediate value. Immediate operands used in all other instructions
generate a two-byte value.
 
The register list operand does not take the form #<expression> but
still generates one byte of immediate data. The form of the operand
is:
 
R1,R2,...,Rn
 
where Ri (i=1 to n) is one of the symbols A, B, CC, D, DP, PC, S, U,
X or Y. The number and type of symbols vary, depending on the specific
instruction.
 
For the instructions PSHS, PULS, PSHU, and PULU, any of the above
register names may be included in the register list. The only
restriction is that "U" cannot be specified with PSHU or PULU, and "S"
cannot be specified with PSHS or PULS. The one-byte immediate value
assigned to the operand is calculated by the assembler and is
determined by the registers specified. Each register name causes the
assembler to set a bit in the immediate byte as follows:
 
 
 
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Freeware Assemblers User's Manual
 
 
Register Bit
-------- ---
 
PC 7
U,S 6
Y 5
X 4
DP 3
B,D 2
A,D 1
CC 0
 
 
For the instructions EXG and TFR, exactly two of the above register
names must be included in the register list. The other restriction is
the size of the registers specified. For the EXG instruction, the two
registers must be the same size. For the TFR instruction, the two
registers must be the same size, or the first can be a 16-bit register
and the second an 8-bit register. In the case where the transfer is
from a 16-bit register to an 8-bit register, the least significant 8
bits are transferred. The 8-bit registers are A, B, CC, and DP. The
16-bit registers are D, PC, S, U, X, and Y. The one-byte immediate
value assigned to the operand by the assembler is determined by the
register names. The most significant four bits of the immediate byte
contain the value of the first register name; the least significant
four bits contain the value of the second register, as shown by the
following table:.
 
 
Register Value (hex)
-------- -----------
 
D 0
X 1
Y 2
U 3
S 4
PC 5
A 8
B 9
CC A
DP B
 
 
RELATIVE ADDRESSING
Relative addressing is used by branch instructions. There are two
forms of the branch instruction. The short branch can only be executed
within the range -126 to +129 bytes relative to the first byte of the
branch instruction. For this mode, the programmer specifies the branch
address expression and places it in the operand field. The actual
branch offset is calculated by the assembler and put into the second
byte of the branch instruction. The long branch can execute in the
full range of addressing from 0000-FFFF (hexadecimal) because a two-
byte offset is calculated by the assembler and put into the operand
field of the branch instruction. The offset is the two's complement
of the difference between the location of the byte immediately
 
 
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Freeware Assemblers User's Manual
 
 
following the branch instruction and the location of the destination
of the branch.
 
 
DIRECT AND EXTENDED ADDRESSING
Direct and extended addressing utilize one (direct) or two (extended)
bytes to contain the address of the operand. Direct and extended
addressing are indicated by having only an expression in the operand
field (i.e., <expression>). Direct addressing will be used whenever
possible.
 
Regardless of the criteria described above, it is possible to force
the Assembler to use the direct addressing mode by preceding the
operand with the "<" character. Similarly, extended addressing can be
forced by preceding the operand with the ">" character. These two
operand forms are: <<expression> and ><expression>.
 
 
INDEXED ADDRESSING
Indexed addressing is relative to one of the index registers. The
general form is <expression>,R. The address is calculated at the time
of instruction execution by adding the value of <expression> to the
current contents of the index register. The other general form is
[<expression>,R]. In this indirect form, the address is calculated
at the time of instruction execution by first adding the value of
<expression> to the current contents of the index register, and then
retrieving the two bytes from the calculated address and address+1.
This two-byte value is used as the effective address of the operand.
The allowable forms of indexed addressing are described below. In the
description below, R refers to one of the index registers S, U, X, or
Y.
 
The accumulator offset mode allows one of the accumulators to be
specified instead of an <expression>. Valid forms are:.
 
<acc>,R and [<acc>,R]
 
where <acc> is one of the accumulators A, B, or D. This form
generates a one-byte operand (post-byte only). When accumulator A or B
is specified, sign extension occurs prior to adding the value in the
accumulator to the index register.
 
The valid forms for the automatic increment/decrement mode are shown
below. For each row, the three entries shown are equivalent.
 
 
R+ ,R+ 0,R+
-R ,-R 0,-R
R++ ,R++ 0,R++
--R ,--R 0,--R
[R++] ,R++] [0,R++]
[--R] [,--R] [0,--R]
 
 
In this form, the only valid expression is 0. Like the accumulator
offset mode, this form generates a one-byte operand (post-byte only).
 
 
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Freeware Assemblers User's Manual
 
 
The valid forms for the expression offset mode are:
 
 
R ,R <expression>,R
[R] [,R] [<expression>,R]
<R <,R <<expression>,R
<[R] <[,R] <[<expression>,R]
>R >,R ><expression>,R
>[R] >[,R] >[<expression>,R]
 
 
The "<" and ">" characters force an 8- or 16-bit offset, respectively,
and are described below. If no expression is specified, or if an
expression with a value of zero is specified, only the postbyte of
the operand is generated. If an expression with a value in the range
-16 to +15 is specified without indirection, a one- byte operand is
generated which contains the expression's value, as well as the index
register indicator. At execution time, the expression's value is
expanded to 16 bits with sign extension before being added to the
index register.
 
All other forms will generate a post-byte, as well as either a one- or
two-byte offset which contains the value of the expression. The size
of the offset is determined by the type and size of the expression.
Expressions with values in the range -128 to +127 generate an 8-bit
offset. All other cases will result in a 16-bit offset being
generated. In the case where an 8-bit offset is generated, the value
is expanded to 16 bits with sign extension at execution time.
 
Regardless of the criteria described above, it is possible to force
the Assembler to generate an 8-bit offset by preceding the operand
with the "<" character. Similarly, a 16-bit offset can be forced by
preceding the operand with the ">" character.
 
If the relative address calculated is not in the range -128 to +127,
or if the expression references a symbol that has not yet been
defined, a two-byte offset is generated after the post-byte. A one-
byte offset is generated if the relative address is in the range -128
to +127.
 
Like the expression offset mode, a one-byte offset can be forced by
preceding the operand with a "<". A ">" forces a two-byte offset. A
byte overflow error is generated if a one-byte offset is forced when
the relative address is not in the range -12
8 to +127.
 
The extended indirect mode has the form:
 
[<expression>]
 
Although extended indirect is a logical extension of the extended
addressing mode, this mode is implemented using an encoding of the
postbyte under the indexed addressing mode. A post-byte and a two-
byte offset which contains the value of the expression is generated.
 
 
 
 
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Freeware Assemblers User's Manual
 
 
B.5 M68HC11 ADDRESSING MODES.
 
PREBYTE
The number of combinations of instructions and addressing modes for
the 68HC11 is larger than that possible to be encoded in an 8-bit word
(256 combinations). To expand the opcode map, certain opcodes ($18,
$1A, and $CD) cause the processor to fetch the next address to find
the actual instruction. These opcodes are known as prebytes and are
inserted automatically by the assembler for those instructions that
require it.l In general the instructions contained in the alternate
maps are those involving the Y register or addressing modes that
involve the Y index register. Thus the programmer make the tradeoff
between the convenience of using the second index register and the
additional time and code space used by the prebyte.
 
 
INHERENT OR ACCUMULATOR ADDRESSING
The M68HC11 includes some instructions which require no operands.
These instructions are self-contained, and employ the inherent
addressing or the accumulator addressing mode.
 
 
IMMEDIATE ADDRESSING
Immediate addressing refers to the use of one or more bytes of
information that immediately follow the operation code in memory.
Immediate addressing is indicated by preceding the operand field with
the pound sign or number sign character (#). The expression following
the # will be assigned one byte of storage.
 
 
RELATIVE ADDRESSING
Relative addressing is used by branch instructions. Branches can only
be executed within the range -126 to +129 bytes relative to the first
byte of the branch instruction. For this mode, the programmer
specifies the branch address expression and places it in the operand
field. The actual branch offset is calculated by the assembler and put
into the second byte of the branch instruction. The offset is the
two's complement of the difference between the location of the byte
immediately following the branch instruction and the location of the
destination of the branch. Branches out of bounds are flagged as
errors by the assembler.
 
 
INDEXED ADDRESSING
Indexed addressing is relative one of the index registers X or Y. The
address is calculated at the time of instruction execution by adding a
one-byte displacement to the current contents of the X register. The
displacement immediately follows the operation code in memory. If the
displacement is zero, zero resides in the byte following the opcode.
Since no sign extension is performed on a one-byte displacement, the
offset cannot be negative. Indexed addressing is indicated by the
characters ",X" following the expression in the operand field. The
special case of ",X", without a preceding expression, is treated as
"0,X".
 
 
 
 
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Freeware Assemblers User's Manual
 
 
DIRECT AND EXTENDED ADDRESSING
Direct and extended addressing utilize one (direct) or two (extended)
bytes to contain the address of the operand. Direct addressing is
limited to the first 256 bytes of memory. Direct and extended
addressing are indicated by only having an expression in the operand
field. Direct addressing will be used by the Assembler whenever
possible.
 
 
BIT(S) SET OR CLEAR
The addressing mode used for this type of instruction is direct,
although the format of the operand field is different from the direct
addressing mode described above. The operand takes the form
<expression 1> <expression 2> where the two expressions are separated
by a blank. <expression 1> signifies the operand address and may be
either a direct or an indexed address. When the address mode is
indexed, <expression 1> is followed by ',R' where R is either X or Y.
This allows bit manipulation instructions to operate across the
complete 64K address map. <expression 2> is the mask byte. The
bit(s) to be set or cleared are indicated by ones in the corresponding
location(s) in the mask byte. The mask byte must be an expression in
the range 0-255 and is encoded by the programmer.
 
 
BIT TEST AND BRANCH
This combines two addressing modes: direct or indexed and relative.
The format of the operand is: <expression 1> <expression 2>
<expression 3> where the expressions are separated by blanks.
<expression 1> identifies the operand an may indicate either a direct
or indexed address. Indexed addresses are signified with ',R'
following the expression where R is either X or Y. <expression 2> is
the mask byte. The bit(s) to be set or cleared are indicated by ones
in the corresponding location(s) in the mask byte. The mask byte must
be an expression in the range 0-255 and is encoded by the programmer.
<expression 3> is used to generate a relative address, as described
above in "relative addressing".
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
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Freeware Assemblers User's Manual
 
 
APPENDIX C
DIRECTIVE SUMMARY
 
 
A complete description of all directives appears in Chapter 4.
 
 
ASSEMBLY CONTROL
 
ORG Origin program counter
 
SYMBOL DEFINITION
 
EQU Assign permanent value
 
DATA DEFINITION/STORAGE ALLOCATION
 
BSZ Block storage of zero; single bytes
 
FCB Form constant byte
 
FCC Form constant character string
 
FDB Form constant double byte
 
FILL Initialize a block of memory to a constant
 
RMB Reserve memory; single bytes
 
ZMB Zero Memory Bytes; same and BSZ
 
 
LISTING CONTROL
 
OPT c Enable cycle counting
 
OPT cre Print cross reference table
 
OPT l Print source listing from this point
 
OPT nol Inhibit printing of source listing from this point
 
OPT s Print symbol table
 
PAGE Print subsequent statements on top of next page
 
 
 
 
 
 
 
 
 
 
 
 
 
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Freeware Assemblers User's Manual
 
 
APPENDIX D
ASSEMBLER LISTING FORMAT
 
 
The Assembler listing has the following format:
 
LINE# ADDR OBJECT CODE BYTES [ # CYCLES] SOURCE LINE
 
The LINE# is a 4 digit decimal number printed as a reference. This
reference number is used in the cross reference. The ADDR is the hex
value of the address for the first byte of the object code for this
instruction. The OBJECT CODE BYTES are the assembled object code of
the source line in hex. If an source line causes more than 6 bytes
to be output (e.g. a long FCC directive), additional bytes (up to 64)
are listed on succeeding lines with no address preceding them.
 
The # CYCLES will only appear in the listing if the "c" option is in
effect. It is enclosed in brackets which helps distinguish it from
the source listing. The SOURCE LINE is reprinted exactly from the
source program, including labels.
 
The symbol table has the following format:
 
SYMBOL ADDR
 
The symbol is taken directly from the label field in the source
program. The ADDR is the hexadecimal address of the location
referenced by the symbol.
 
The cross reference listing has the following format:
 
SYMBOL ADDR *LOC1 LOC2 LOC3 ...
 
The SYMBOL and ADDR are the same as above. The * indicates the start
of the line reference numbers. The LOCs are the decimal line numbers
of the assembler listing where the label occurs.
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
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Freeware Assemblers User's Manual
 
 
APPENDIX E
S-RECORD INFORMATION
 
 
E.1 INTRODUCTION
 
The S-record output format encodes program and data object modules
into a printable (ASCII) format. This allows viewing of the object
file with standard tools and allows display of the module while
transferring from one computer to the next or during loads between a
host and target. The S-record format also includes information for
use in error checking to insure the integrity of data transfers.
 
 
E.2 S-RECORD CONTENT
 
S-Records are character strings made of several fields which identify
the record type, record length, memory address, code/data, and
checksum. Each byte of binary data is encoded as a 2-character
hexadecimal number: the first character representing the high-order
4 bits, and the second the low-order 4 bits of the byte.
 
The 5 fields which comprise an S-record are:
 
TYPE RECORD LENGTH ADDRESS CODE/DATA CHECKSUM
 
The fields are defined as follows:
 
FIELD CHARACTERS CONTENTS
----- ---------- --------
Type 2 S-record type - S1, S9, etc.
 
Record 2 The count of the character pairs in the
length record, excluding the type and record
length.
 
Address 4, 6, The 2-, 3-, or 4-byte address at which
or 8 the data field is to be loaded into
memory.
 
Code/data 0-2n From 0 to n bytes of executable code,
memory loadable data, or descriptive
information.
 
Checksum 2 The least significant byte of the one's
complement of the sum of the values
represented by the pairs of characters
making up the record length, address,
and the code/data fields.
 
Each record may be terminated with a CR/LF/NULL.
 
 
E.3 S-RECORD TYPES
 
Eight types of s-records have been defined to accommodate various
 
 
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Freeware Assemblers User's Manual
 
 
encoding, transportation, and decoding needs. The Freeware
assemblers use only two types, the S1 and S9:
 
S1 A record containing code/data and the 2-byte
address at which the code/data is to reside.
 
S9 A termination record for a block of S1 records. The address
field may optionally contain the 2-byte address of the
instruction to which control is to be passed. If not
specified, the first entry point specifica
tion encountered in the object module input will be used.
There is no code/data field.
 
E.4 S-RECORD EXAMPLE
 
The following is a typical S-record module:
 
S1130000285F245F2212226A000424290008237C2A
S11300100002000800082629001853812341001813
S113002041E900084E42234300182342000824A952
S107003000144ED492
S9030000FC
 
The module consists of four code/data records and an S9 termination
record.
 
The first S1 code/data record is explained as follows:
 
S1 S-record type S1, indicating a code/data record to be
loaded/verified at a 2-byte address.
 
13 Hex 13 (decimal 19), indicating 19 character pairs,
representing 19 bytes of binary data, follow.
 
00 Four-character 2-byte address field: hex address 0000,
indicates location where the following data is to be loaded.
 
The next 16 character pairs are the ASCII bytes of the actual
program code/data
 
2A Checksum of the first S1 record.
 
The second and third S1 code/data records each also contain $13
character pairs and are ended with checksums. The fourth S1 code/data
record contains 7 character pairs.
 
The S9 termination record is explained as follows:
 
S9 S-record type S9, indicating a termination record.
 
03 Hex 03, indicating three character pairs (3 bytes) to
follow.
 
00 Four character 2-byte address field, zeroes.
00
 
FC Checksum of S9 record.
 
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