URL
https://opencores.org/ocsvn/System09/System09/trunk
Subversion Repositories System09
Compare Revisions
- This comparison shows the changes necessary to convert path
/System09/trunk
- from Rev 172 to Rev 173
- ↔ Reverse comparison
Rev 172 → Rev 173
/rtl/System09_Digilent_Atlys/system09.gise
68,6 → 68,7
<file xil_pn:fileType="FILE_WEBTALK" xil_pn:name="system09_usage.xml"/> |
<file xil_pn:branch="Implementation" xil_pn:fileType="FILE_XST_PROJECT" xil_pn:name="system09_vhdl.prj"/> |
<file xil_pn:fileType="FILE_XRPT" xil_pn:name="system09_xst.xrpt"/> |
<file xil_pn:fileType="FILE_HTML" xil_pn:name="usage_statistics_webtalk.html"/> |
<file xil_pn:fileType="FILE_LOG" xil_pn:name="webtalk.log"/> |
<file xil_pn:fileType="FILE_FITTER_REPORT" xil_pn:name="webtalk_pn.xml"/> |
<file xil_pn:fileType="FILE_DIRECTORY" xil_pn:name="xlnx_auto_0_xdb"/> |
75,35 → 76,35
</files> |
|
<transforms xmlns="http://www.xilinx.com/XMLSchema"> |
<transform xil_pn:end_ts="1518994649" xil_pn:name="TRAN_copyInitialToXSTAbstractSynthesis" xil_pn:start_ts="1518994649"> |
<transform xil_pn:end_ts="1611118912" xil_pn:name="TRAN_copyInitialToXSTAbstractSynthesis" xil_pn:start_ts="1611118912"> |
<status xil_pn:value="SuccessfullyRun"/> |
<status xil_pn:value="ReadyToRun"/> |
</transform> |
<transform xil_pn:end_ts="1518994649" xil_pn:name="TRAN_schematicsToHdl" xil_pn:prop_ck="824444824769715144" xil_pn:start_ts="1518994649"> |
<transform xil_pn:end_ts="1611118912" xil_pn:name="TRAN_schematicsToHdl" xil_pn:prop_ck="3688993175894000260" xil_pn:start_ts="1611118912"> |
<status xil_pn:value="SuccessfullyRun"/> |
<status xil_pn:value="ReadyToRun"/> |
</transform> |
<transform xil_pn:end_ts="1518994649" xil_pn:name="TRAN_regenerateCores" xil_pn:prop_ck="5444443152150271503" xil_pn:start_ts="1518994649"> |
<transform xil_pn:end_ts="1611118912" xil_pn:name="TRAN_regenerateCores" xil_pn:prop_ck="7998624334607291317" xil_pn:start_ts="1611118912"> |
<status xil_pn:value="SuccessfullyRun"/> |
<status xil_pn:value="ReadyToRun"/> |
</transform> |
<transform xil_pn:end_ts="1518994649" xil_pn:name="TRAN_SubProjectAbstractToPreProxy" xil_pn:start_ts="1518994649"> |
<transform xil_pn:end_ts="1611118912" xil_pn:name="TRAN_SubProjectAbstractToPreProxy" xil_pn:start_ts="1611118912"> |
<status xil_pn:value="SuccessfullyRun"/> |
<status xil_pn:value="ReadyToRun"/> |
</transform> |
<transform xil_pn:end_ts="1518994649" xil_pn:name="TRAN_xawsTohdl" xil_pn:prop_ck="-5881944901013327088" xil_pn:start_ts="1518994649"> |
<transform xil_pn:end_ts="1611118912" xil_pn:name="TRAN_xawsTohdl" xil_pn:prop_ck="-2491246652047045050" xil_pn:start_ts="1611118912"> |
<status xil_pn:value="SuccessfullyRun"/> |
<status xil_pn:value="ReadyToRun"/> |
</transform> |
<transform xil_pn:end_ts="1518994649" xil_pn:name="TRAN_SubProjectPreToStructuralProxy" xil_pn:prop_ck="-7493580321282947067" xil_pn:start_ts="1518994649"> |
<transform xil_pn:end_ts="1611118912" xil_pn:name="TRAN_SubProjectPreToStructuralProxy" xil_pn:prop_ck="8977612015756273942" xil_pn:start_ts="1611118912"> |
<status xil_pn:value="SuccessfullyRun"/> |
<status xil_pn:value="ReadyToRun"/> |
</transform> |
<transform xil_pn:end_ts="1518994649" xil_pn:name="TRAN_platgen" xil_pn:prop_ck="-2873745161008578983" xil_pn:start_ts="1518994649"> |
<transform xil_pn:end_ts="1611118912" xil_pn:name="TRAN_platgen" xil_pn:prop_ck="-1223916495889636993" xil_pn:start_ts="1611118912"> |
<status xil_pn:value="SuccessfullyRun"/> |
<status xil_pn:value="ReadyToRun"/> |
</transform> |
<transform xil_pn:end_ts="1589987846" xil_pn:in_ck="7198331467256017067" xil_pn:name="TRANEXT_xstsynthesize_spartan6" xil_pn:prop_ck="1974990584335492622" xil_pn:start_ts="1589987807"> |
<transform xil_pn:end_ts="1611118959" xil_pn:in_ck="4010317442951213546" xil_pn:name="TRANEXT_xstsynthesize_spartan6" xil_pn:prop_ck="1974990584335492622" xil_pn:start_ts="1611118912"> |
<status xil_pn:value="SuccessfullyRun"/> |
<status xil_pn:value="WarningsGenerated"/> |
<status xil_pn:value="ReadyToRun"/> |
121,13 → 122,12
<outfile xil_pn:name="webtalk_pn.xml"/> |
<outfile xil_pn:name="xst"/> |
</transform> |
<transform xil_pn:end_ts="1518994687" xil_pn:in_ck="6003168217582152378" xil_pn:name="TRAN_compileBCD2" xil_pn:prop_ck="-3128816144678396997" xil_pn:start_ts="1518994687"> |
<transform xil_pn:end_ts="1611118959" xil_pn:in_ck="6003168217582152378" xil_pn:name="TRAN_compileBCD2" xil_pn:prop_ck="-3128816144678396997" xil_pn:start_ts="1611118959"> |
<status xil_pn:value="SuccessfullyRun"/> |
<status xil_pn:value="ReadyToRun"/> |
</transform> |
<transform xil_pn:end_ts="1589987895" xil_pn:in_ck="-2676906326711859666" xil_pn:name="TRANEXT_ngdbuild_FPGA" xil_pn:prop_ck="7427287850225075136" xil_pn:start_ts="1589987891"> |
<transform xil_pn:end_ts="1611118965" xil_pn:in_ck="-2676906326711859666" xil_pn:name="TRANEXT_ngdbuild_FPGA" xil_pn:prop_ck="7427287850225075136" xil_pn:start_ts="1611118959"> |
<status xil_pn:value="SuccessfullyRun"/> |
<status xil_pn:value="WarningsGenerated"/> |
<status xil_pn:value="ReadyToRun"/> |
<outfile xil_pn:name="_ngo"/> |
<outfile xil_pn:name="_xmsgs/ngdbuild.xmsgs"/> |
135,7 → 135,7
<outfile xil_pn:name="system09.ngd"/> |
<outfile xil_pn:name="system09_ngdbuild.xrpt"/> |
</transform> |
<transform xil_pn:end_ts="1589987902" xil_pn:in_ck="-1009016811758874705" xil_pn:name="TRANEXT_map_spartan6" xil_pn:prop_ck="7013356299669423719" xil_pn:start_ts="1589987895"> |
<transform xil_pn:end_ts="1611118985" xil_pn:in_ck="-1009016811758874705" xil_pn:name="TRANEXT_map_spartan6" xil_pn:prop_ck="7013356299669423719" xil_pn:start_ts="1611118965"> |
<status xil_pn:value="SuccessfullyRun"/> |
<status xil_pn:value="ReadyToRun"/> |
<status xil_pn:value="OutOfDateForOutputs"/> |
150,9 → 150,8
<outfile xil_pn:name="system09_summary.xml"/> |
<outfile xil_pn:name="system09_usage.xml"/> |
</transform> |
<transform xil_pn:end_ts="1589987917" xil_pn:in_ck="-7782462315172532792" xil_pn:name="TRANEXT_par_spartan6" xil_pn:prop_ck="-3829590541433901613" xil_pn:start_ts="1589987902"> |
<transform xil_pn:end_ts="1611119008" xil_pn:in_ck="-7782462315172532792" xil_pn:name="TRANEXT_par_spartan6" xil_pn:prop_ck="-3829590541433901613" xil_pn:start_ts="1611118985"> |
<status xil_pn:value="SuccessfullyRun"/> |
<status xil_pn:value="WarningsGenerated"/> |
<status xil_pn:value="ReadyToRun"/> |
<outfile xil_pn:name="_xmsgs/par.xmsgs"/> |
<outfile xil_pn:name="system09.ncd"/> |
165,7 → 164,7
<outfile xil_pn:name="system09_pad.txt"/> |
<outfile xil_pn:name="system09_par.xrpt"/> |
</transform> |
<transform xil_pn:end_ts="1589987940" xil_pn:in_ck="6003168217582144753" xil_pn:name="TRANEXT_bitFile_spartan6" xil_pn:prop_ck="-5761130248037966628" xil_pn:start_ts="1589987931"> |
<transform xil_pn:end_ts="1611119026" xil_pn:in_ck="6003168217582144753" xil_pn:name="TRANEXT_bitFile_spartan6" xil_pn:prop_ck="-5761130248037966628" xil_pn:start_ts="1611119008"> |
<status xil_pn:value="SuccessfullyRun"/> |
<status xil_pn:value="ReadyToRun"/> |
<outfile xil_pn:name="_xmsgs/bitgen.xmsgs"/> |
173,10 → 172,11
<outfile xil_pn:name="system09.bit"/> |
<outfile xil_pn:name="system09.drc"/> |
<outfile xil_pn:name="system09.ut"/> |
<outfile xil_pn:name="usage_statistics_webtalk.html"/> |
<outfile xil_pn:name="webtalk.log"/> |
<outfile xil_pn:name="webtalk_pn.xml"/> |
</transform> |
<transform xil_pn:end_ts="1589987917" xil_pn:in_ck="190496098961729835" xil_pn:name="TRAN_postRouteTrce" xil_pn:prop_ck="-1758799009971969896" xil_pn:start_ts="1589987912"> |
<transform xil_pn:end_ts="1611119008" xil_pn:in_ck="190496098961729835" xil_pn:name="TRAN_postRouteTrce" xil_pn:prop_ck="-1758799009971969896" xil_pn:start_ts="1611119002"> |
<status xil_pn:value="SuccessfullyRun"/> |
<status xil_pn:value="ReadyToRun"/> |
<outfile xil_pn:name="_xmsgs/trce.xmsgs"/> |
/rtl/System09_Digilent_Atlys/system09.prj
9,4 → 9,5
vhdl work "../VHDL/acia6850.vhd" |
vhdl work "common.vhd" |
vhdl work "../Spartan3/ram32k_b16.vhd" |
vhdl work "../Spartan3/ram16k_b16.vhd" |
vhdl work "system09.vhd" |
/rtl/System09_Digilent_Atlys/system09.vhd
202,8 → 202,11
signal CTS_n : Std_Logic; |
|
-- RAM |
signal ram_cs : std_logic; |
signal ram_data_out : std_logic_vector(7 downto 0); |
signal ram1_cs : std_logic; |
signal ram1_data_out : std_logic_vector(7 downto 0); |
signal ram2_cs : std_logic; |
signal ram2_data_out : std_logic_vector(7 downto 0); |
signal ram3_cs : std_logic; |
|
-- CPU Interface signals |
signal cpu_reset : Std_Logic; |
323,7 → 326,26
); |
end component; |
|
|
---------------------------------------- |
-- |
-- 16KBytes Block RAM 8000 |
-- $8000 - $BFFF |
-- |
---------------------------------------- |
|
component ram_16k |
Port ( |
clk : in std_logic; |
rst : in std_logic; |
cs : in std_logic; |
rw : in std_logic; |
addr : in std_logic_vector (13 downto 0); |
data_out : out std_logic_vector (7 downto 0); |
data_in : in std_logic_vector (7 downto 0) |
); |
end component; |
|
----------------------------------------------------------------- |
-- |
-- 6850 Compatible ACIA / UART |
486,13 → 508,24
port map ( |
clk => cpu_clk, |
rst => cpu_reset, |
cs => ram_cs, |
cs => ram1_cs, |
rw => cpu_rw, |
addr => cpu_addr(14 downto 0), |
data_out => ram_data_out, |
data_out => ram1_data_out, |
data_in => cpu_data_out |
); |
|
|
my_16k : ram_16k |
port map ( |
clk => cpu_clk, |
rst => cpu_reset, |
cs => ram2_cs, |
rw => cpu_rw, |
addr => cpu_addr(13 downto 0), |
data_out => ram2_data_out, |
data_in => cpu_data_out |
); |
|
my_acia : acia6850 |
port map ( |
clk => cpu_clk, |
588,7 → 621,7
acia_data_out, |
timer_data_out, |
trap_data_out, |
ram_data_out |
ram1_data_out, ram2_data_out |
) |
begin |
cpu_data_in <= (others=>'0'); |
598,8 → 631,9
acia_cs <= '0'; |
timer_cs <= '0'; |
trap_cs <= '0'; |
ram_cs <= '0'; |
|
ram1_cs <= '0'; |
ram2_cs <= '0'; |
|
if cpu_addr( 15 downto 8 ) = "11111111" then -- $FFxx |
cpu_data_in <= rom_data_out; |
dat_cs <= cpu_vma; -- write DAT |
687,15 → 721,22
-- 32k RAM $00000 - $07FFF |
-- |
elsif dat_addr(7 downto 1) = "0000000" then -- $00000 - $07FFF |
cpu_data_in <= ram_data_out; |
ram_cs <= cpu_vma; |
cpu_data_in <= ram1_data_out; |
ram1_cs <= cpu_vma; |
|
-- |
-- 16k RAM $08000 - $0BFFF |
-- |
elsif dat_addr(7 downto 1) = "0000100" then -- $08000 - $0BFFF |
cpu_data_in <= ram2_data_out; |
ram2_cs <= cpu_vma; |
|
-- |
-- Everything else is RAM |
-- |
else |
cpu_data_in <= ram_data_out; |
ram_cs <= cpu_vma; |
cpu_data_in <= (others => '0'); |
ram3_cs <= cpu_vma; |
end if; |
|
end process; |
/rtl/System09_Digilent_Atlys/system09.xise
60,12 → 60,16
</file> |
<file xil_pn:name="system09.vhd" xil_pn:type="FILE_VHDL"> |
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="72"/> |
<association xil_pn:name="Implementation" xil_pn:seqID="12"/> |
<association xil_pn:name="Implementation" xil_pn:seqID="13"/> |
</file> |
<file xil_pn:name="../Spartan3/ram32k_b16.vhd" xil_pn:type="FILE_VHDL"> |
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="65"/> |
<association xil_pn:name="Implementation" xil_pn:seqID="11"/> |
</file> |
<file xil_pn:name="../Spartan3/ram16k_b16.vhd" xil_pn:type="FILE_VHDL"> |
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="65"/> |
<association xil_pn:name="Implementation" xil_pn:seqID="12"/> |
</file> |
</files> |
|
<properties> |