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Subversion Repositories System09

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  • This comparison shows the changes necessary to convert path 
    /System09
    from Rev 102 to Rev 103
    ↔ Reverse comparison
  •

Rev 102 → Rev 103

/trunk/rtl/Cyclone2/sys09bug_rom_inst.vhd
0,0 → 1,5
sys09bug_rom_inst : sys09bug_rom PORT MAP (
address => address_sig,
clock => clock_sig,
q => q_sig
);
/trunk/rtl/Cyclone2/sys09bug_rom.cmp
0,0 → 1,23
--Copyright (C) 1991-2009 Altera Corporation
--Your use of Altera Corporation's design tools, logic functions
--and other software and tools, and its AMPP partner logic
--functions, and any output files from any of the foregoing
--(including device programming or simulation files), and any
--associated documentation or information are expressly subject
--to the terms and conditions of the Altera Program License
--Subscription Agreement, Altera MegaCore Function License
--Agreement, or other applicable license agreement, including,
--without limitation, that your use is for the sole purpose of
--programming logic devices manufactured by Altera and sold by
--Altera or its authorized distributors. Please refer to the
--applicable agreement for further details.
 
 
component sys09bug_rom
PORT
(
address : IN STD_LOGIC_VECTOR (11 DOWNTO 0);
clock : IN STD_LOGIC := '1';
q : OUT STD_LOGIC_VECTOR (7 DOWNTO 0)
);
end component;
/trunk/rtl/Cyclone2/sys09bug_rom.vhd
0,0 → 1,171
-- megafunction wizard: %ROM: 1-PORT%
-- GENERATION: STANDARD
-- VERSION: WM1.0
-- MODULE: altsyncram
 
-- ============================================================
-- File Name: sys09bug_rom.vhd
-- Megafunction Name(s):
-- altsyncram
--
-- Simulation Library Files(s):
-- altera_mf
-- ============================================================
-- ************************************************************
-- THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
--
-- 9.0 Build 235 06/17/2009 SP 2 SJ Full Version
-- ************************************************************
 
 
--Copyright (C) 1991-2009 Altera Corporation
--Your use of Altera Corporation's design tools, logic functions
--and other software and tools, and its AMPP partner logic
--functions, and any output files from any of the foregoing
--(including device programming or simulation files), and any
--associated documentation or information are expressly subject
--to the terms and conditions of the Altera Program License
--Subscription Agreement, Altera MegaCore Function License
--Agreement, or other applicable license agreement, including,
--without limitation, that your use is for the sole purpose of
--programming logic devices manufactured by Altera and sold by
--Altera or its authorized distributors. Please refer to the
--applicable agreement for further details.
 
 
LIBRARY ieee;
USE ieee.std_logic_1164.all;
 
LIBRARY altera_mf;
USE altera_mf.all;
 
ENTITY sys09bug_rom IS
PORT
(
address : IN STD_LOGIC_VECTOR (11 DOWNTO 0);
clock : IN STD_LOGIC := '1';
q : OUT STD_LOGIC_VECTOR (7 DOWNTO 0)
);
END sys09bug_rom;
 
 
ARCHITECTURE SYN OF sys09bug_rom IS
 
SIGNAL sub_wire0 : STD_LOGIC_VECTOR (7 DOWNTO 0);
 
 
 
COMPONENT altsyncram
GENERIC (
clock_enable_input_a : STRING;
clock_enable_output_a : STRING;
init_file : STRING;
intended_device_family : STRING;
lpm_hint : STRING;
lpm_type : STRING;
numwords_a : NATURAL;
operation_mode : STRING;
outdata_aclr_a : STRING;
outdata_reg_a : STRING;
ram_block_type : STRING;
widthad_a : NATURAL;
width_a : NATURAL;
width_byteena_a : NATURAL
);
PORT (
clock0 : IN STD_LOGIC ;
address_a : IN STD_LOGIC_VECTOR (11 DOWNTO 0);
q_a : OUT STD_LOGIC_VECTOR (7 DOWNTO 0)
);
END COMPONENT;
 
BEGIN
q <= sub_wire0(7 DOWNTO 0);
 
altsyncram_component : altsyncram
GENERIC MAP (
clock_enable_input_a => "BYPASS",
clock_enable_output_a => "BYPASS",
init_file => "sys09bug_c27.hex",
intended_device_family => "Cyclone II",
lpm_hint => "ENABLE_RUNTIME_MOD=NO",
lpm_type => "altsyncram",
numwords_a => 4096,
operation_mode => "ROM",
outdata_aclr_a => "NONE",
outdata_reg_a => "CLOCK0",
ram_block_type => "M4K",
widthad_a => 12,
width_a => 8,
width_byteena_a => 1
)
PORT MAP (
clock0 => clock,
address_a => address,
q_a => sub_wire0
);
 
 
 
END SYN;
 
-- ============================================================
-- CNX file retrieval info
-- ============================================================
-- Retrieval info: PRIVATE: ADDRESSSTALL_A NUMERIC "0"
-- Retrieval info: PRIVATE: AclrAddr NUMERIC "0"
-- Retrieval info: PRIVATE: AclrByte NUMERIC "0"
-- Retrieval info: PRIVATE: AclrOutput NUMERIC "0"
-- Retrieval info: PRIVATE: BYTE_ENABLE NUMERIC "0"
-- Retrieval info: PRIVATE: BYTE_SIZE NUMERIC "8"
-- Retrieval info: PRIVATE: BlankMemory NUMERIC "0"
-- Retrieval info: PRIVATE: CLOCK_ENABLE_INPUT_A NUMERIC "0"
-- Retrieval info: PRIVATE: CLOCK_ENABLE_OUTPUT_A NUMERIC "0"
-- Retrieval info: PRIVATE: Clken NUMERIC "0"
-- Retrieval info: PRIVATE: IMPLEMENT_IN_LES NUMERIC "0"
-- Retrieval info: PRIVATE: INIT_FILE_LAYOUT STRING "PORT_A"
-- Retrieval info: PRIVATE: INIT_TO_SIM_X NUMERIC "0"
-- Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone II"
-- Retrieval info: PRIVATE: JTAG_ENABLED NUMERIC "0"
-- Retrieval info: PRIVATE: JTAG_ID STRING "NONE"
-- Retrieval info: PRIVATE: MAXIMUM_DEPTH NUMERIC "0"
-- Retrieval info: PRIVATE: MIFfilename STRING "sys09bug_c27.hex"
-- Retrieval info: PRIVATE: NUMWORDS_A NUMERIC "4096"
-- Retrieval info: PRIVATE: RAM_BLOCK_TYPE NUMERIC "2"
-- Retrieval info: PRIVATE: RegAddr NUMERIC "1"
-- Retrieval info: PRIVATE: RegOutput NUMERIC "1"
-- Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
-- Retrieval info: PRIVATE: SingleClock NUMERIC "1"
-- Retrieval info: PRIVATE: UseDQRAM NUMERIC "0"
-- Retrieval info: PRIVATE: WidthAddr NUMERIC "12"
-- Retrieval info: PRIVATE: WidthData NUMERIC "8"
-- Retrieval info: PRIVATE: rden NUMERIC "0"
-- Retrieval info: CONSTANT: CLOCK_ENABLE_INPUT_A STRING "BYPASS"
-- Retrieval info: CONSTANT: CLOCK_ENABLE_OUTPUT_A STRING "BYPASS"
-- Retrieval info: CONSTANT: INIT_FILE STRING "sys09bug_c27.hex"
-- Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone II"
-- Retrieval info: CONSTANT: LPM_HINT STRING "ENABLE_RUNTIME_MOD=NO"
-- Retrieval info: CONSTANT: LPM_TYPE STRING "altsyncram"
-- Retrieval info: CONSTANT: NUMWORDS_A NUMERIC "4096"
-- Retrieval info: CONSTANT: OPERATION_MODE STRING "ROM"
-- Retrieval info: CONSTANT: OUTDATA_ACLR_A STRING "NONE"
-- Retrieval info: CONSTANT: OUTDATA_REG_A STRING "CLOCK0"
-- Retrieval info: CONSTANT: RAM_BLOCK_TYPE STRING "M4K"
-- Retrieval info: CONSTANT: WIDTHAD_A NUMERIC "12"
-- Retrieval info: CONSTANT: WIDTH_A NUMERIC "8"
-- Retrieval info: CONSTANT: WIDTH_BYTEENA_A NUMERIC "1"
-- Retrieval info: USED_PORT: address 0 0 12 0 INPUT NODEFVAL address[11..0]
-- Retrieval info: USED_PORT: clock 0 0 0 0 INPUT VCC clock
-- Retrieval info: USED_PORT: q 0 0 8 0 OUTPUT NODEFVAL q[7..0]
-- Retrieval info: CONNECT: @address_a 0 0 12 0 address 0 0 12 0
-- Retrieval info: CONNECT: q 0 0 8 0 @q_a 0 0 8 0
-- Retrieval info: CONNECT: @clock0 0 0 0 0 clock 0 0 0 0
-- Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
-- Retrieval info: GEN_FILE: TYPE_NORMAL sys09bug_rom.vhd TRUE
-- Retrieval info: GEN_FILE: TYPE_NORMAL sys09bug_rom.inc TRUE
-- Retrieval info: GEN_FILE: TYPE_NORMAL sys09bug_rom.cmp TRUE
-- Retrieval info: GEN_FILE: TYPE_NORMAL sys09bug_rom.bsf TRUE
-- Retrieval info: GEN_FILE: TYPE_NORMAL sys09bug_rom_inst.vhd TRUE
-- Retrieval info: GEN_FILE: TYPE_NORMAL sys09bug_rom_waveforms.html TRUE
-- Retrieval info: GEN_FILE: TYPE_NORMAL sys09bug_rom_wave*.jpg FALSE
-- Retrieval info: LIB_FILE: altera_mf
/trunk/rtl/Cyclone2/sys09bug_rom_wave0.jpg Cannot display: file marked as a binary type. svn:mime-type = application/octet-stream
/trunk/rtl/Cyclone2/sys09bug_rom_wave0.jpg
trunk/rtl/Cyclone2/sys09bug_rom_wave0.jpg Property changes : Added: svn:mime-type ## -0,0 +1 ## +application/octet-stream \ No newline at end of property Index: trunk/rtl/Cyclone2/sys09bug_rom.inc =================================================================== --- trunk/rtl/Cyclone2/sys09bug_rom.inc (nonexistent) +++ trunk/rtl/Cyclone2/sys09bug_rom.inc (revision 103) @@ -0,0 +1,24 @@ +--Copyright (C) 1991-2009 Altera Corporation +--Your use of Altera Corporation's design tools, logic functions +--and other software and tools, and its AMPP partner logic +--functions, and any output files from any of the foregoing +--(including device programming or simulation files), and any +--associated documentation or information are expressly subject +--to the terms and conditions of the Altera Program License +--Subscription Agreement, Altera MegaCore Function License +--Agreement, or other applicable license agreement, including, +--without limitation, that your use is for the sole purpose of +--programming logic devices manufactured by Altera and sold by +--Altera or its authorized distributors. Please refer to the +--applicable agreement for further details. + + +FUNCTION sys09bug_rom +( + address[11..0], + clock +) + +RETURNS ( + q[7..0] +); Index: trunk/rtl/Cyclone2/sys09bug_rom.qip =================================================================== --- trunk/rtl/Cyclone2/sys09bug_rom.qip (nonexistent) +++ trunk/rtl/Cyclone2/sys09bug_rom.qip (revision 103) @@ -0,0 +1,7 @@ +set_global_assignment -name IP_TOOL_NAME "ROM: 1-PORT" +set_global_assignment -name IP_TOOL_VERSION "9.0" +set_global_assignment -name VHDL_FILE [file join $::quartus(qip_path) "sys09bug_rom.vhd"] +set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "sys09bug_rom.bsf"] +set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "sys09bug_rom_inst.vhd"] +set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "sys09bug_rom.inc"] +set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "sys09bug_rom.cmp"] Index: trunk/rtl/Cyclone2/sys09bug_rom.bsf =================================================================== --- trunk/rtl/Cyclone2/sys09bug_rom.bsf (nonexistent) +++ trunk/rtl/Cyclone2/sys09bug_rom.bsf (revision 103) @@ -0,0 +1,76 @@ +/* +WARNING: Do NOT edit the input and output ports in this file in a text +editor if you plan to continue editing the block that represents it in +the Block Editor! File corruption is VERY likely to occur. +*/ +/* +Copyright (C) 1991-2009 Altera Corporation +Your use of Altera Corporation's design tools, logic functions +and other software and tools, and its AMPP partner logic +functions, and any output files from any of the foregoing +(including device programming or simulation files), and any +associated documentation or information are expressly subject +to the terms and conditions of the Altera Program License +Subscription Agreement, Altera MegaCore Function License +Agreement, or other applicable license agreement, including, +without limitation, that your use is for the sole purpose of +programming logic devices manufactured by Altera and sold by +Altera or its authorized distributors. Please refer to the +applicable agreement for further details. +*/ +(header "symbol" (version "1.1")) +(symbol + (rect 0 0 216 136) + (text "sys09bug_rom" (rect 66 1 166 17)(font "Arial" (font_size 10))) + (text "inst" (rect 8 120 25 132)(font "Arial" )) + (port + (pt 0 32) + (input) + (text "address[11..0]" (rect 0 0 82 14)(font "Arial" (font_size 8))) + (text "address[11..0]" (rect 4 19 69 32)(font "Arial" (font_size 8))) + (line (pt 0 32)(pt 88 32)(line_width 3)) + ) + (port + (pt 0 112) + (input) + (text "clock" (rect 0 0 29 14)(font "Arial" (font_size 8))) + (text "clock" (rect 4 99 27 112)(font "Arial" (font_size 8))) + (line (pt 0 112)(pt 144 112)(line_width 1)) + ) + (port + (pt 216 32) + (output) + (text "q[7..0]" (rect 0 0 35 14)(font "Arial" (font_size 8))) + (text "q[7..0]" (rect 183 19 213 32)(font "Arial" (font_size 8))) + (line (pt 216 32)(pt 160 32)(line_width 3)) + ) + (drawing + (text "8 bits" (rect 108 48 120 71)(font "Arial" )(vertical)) + (text "4096 words" (rect 121 36 133 83)(font "Arial" )(vertical)) + (text "Block type: M4K" (rect 41 116 110 128)(font "Arial" )) + (line (pt 104 24)(pt 136 24)(line_width 1)) + (line (pt 136 24)(pt 136 96)(line_width 1)) + (line (pt 136 96)(pt 104 96)(line_width 1)) + (line (pt 104 96)(pt 104 24)(line_width 1)) + (line (pt 118 58)(pt 123 63)(line_width 1)) + (line (pt 118 62)(pt 123 57)(line_width 1)) + (line (pt 152 27)(pt 160 27)(line_width 1)) + (line (pt 160 27)(pt 160 39)(line_width 1)) + (line (pt 160 39)(pt 152 39)(line_width 1)) + (line (pt 152 39)(pt 152 27)(line_width 1)) + (line (pt 152 34)(pt 154 36)(line_width 1)) + (line (pt 154 36)(pt 152 38)(line_width 1)) + (line (pt 144 36)(pt 152 36)(line_width 1)) + (line (pt 136 32)(pt 152 32)(line_width 3)) + (line (pt 88 27)(pt 96 27)(line_width 1)) + (line (pt 96 27)(pt 96 39)(line_width 1)) + (line (pt 96 39)(pt 88 39)(line_width 1)) + (line (pt 88 39)(pt 88 27)(line_width 1)) + (line (pt 88 34)(pt 90 36)(line_width 1)) + (line (pt 90 36)(pt 88 38)(line_width 1)) + (line (pt 80 36)(pt 88 36)(line_width 1)) + (line (pt 96 32)(pt 104 32)(line_width 3)) + (line (pt 80 112)(pt 80 36)(line_width 1)) + (line (pt 144 112)(pt 144 36)(line_width 1)) + ) +) Index: trunk/rtl/Cyclone2/template.vhd =================================================================== --- trunk/rtl/Cyclone2/template.vhd (nonexistent) +++ trunk/rtl/Cyclone2/template.vhd (revision 103) @@ -0,0 +1,32 @@ +LIBRARY ieee; +USE ieee.std_logic_1164.all; + +ENTITY mon_rom IS + PORT ( + cs : IN STD_LOGIC; + addr : IN STD_LOGIC_VECTOR (7 DOWNTO 0); + data_out : OUT STD_LOGIC_VECTOR (14 DOWNTO 0)); +END mon_rom; + +ARCHITECTURE behavior OF mon_rom IS + +COMPONENT asyn_rom_256x15 +-- pragma translate_off + GENERIC (LPM_FILE : string); + +-- pragma translate_on + PORT ( + Address : IN STD_LOGIC_VECTOR(7 DOWNTO 0); + MemEnab : IN STD_LOGIC; + Q : OUT STD_LOGIC_VECTOR(14 DOWNTO 0) + ); +END COMPONENT; + +BEGIN + + u1: asyn_rom_256x15 +-- pragma translate_off + GENERIC MAP (LPM_FILE => "u1.hex") +-- pragma translate_on + PORT MAP (Address => addr, MemEnab => memenab, Q =>q); +END behavior; Index: trunk/rtl/Cyclone2/sys09bug_rom_waveforms.html =================================================================== --- trunk/rtl/Cyclone2/sys09bug_rom_waveforms.html (nonexistent) +++ trunk/rtl/Cyclone2/sys09bug_rom_waveforms.html (revision 103) @@ -0,0 +1,13 @@ + + +Sample Waveforms for sys09bug_rom.vhd + + +

Sample behavioral waveforms for design file sys09bug_rom.vhd

+

The following waveforms show the behavior of altsyncram megafunction for the chosen set of parameters in design sys09bug_rom.vhd. For the purpose of this simulation, the contents of the memory at the start of the sample waveforms is assumed to be ( F0, F1, F2, F3, ...). The design sys09bug_rom.vhd has one read port. The read port has 4096 words of 8 bits each. The ram block type of the design is M4K. The output of the read port is registered by clock.

+
+

Fig. 1 : Wave showing read operation.

+

The above waveform shows the behavior of the design under normal read conditions. The read happens at the rising edge of the enabled clock cycle. The output from the RAM is undefined until after the first rising edge of the read clock. The clock enable on the read side input registers are disabled. The clock enable on the output registers are disabled.

+

+ +

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