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URL https://opencores.org/ocsvn/System09/System09/trunk

Subversion Repositories System09

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  • This comparison shows the changes necessary to convert path 
    /System09
    from Rev 107 to Rev 108
    ↔ Reverse comparison
  •

Rev 107 → Rev 108

/trunk/rtl/System09_BurchED_B5-X300/System09_BurchED_B5-X300.ucf
1,7 → 1,7
#### UCF file created by Project Navigator
#
NET "reset_n" LOC = "p57" ;
NET "sysclk" LOC = "p77" ;
NET "rst_n" LOC = "p57" ;
NET "clk_in" LOC = "p77" ;
#
# For B5-Compact-Flash:
# Connector A
161,7 → 161,7
#NET "pin7" LOC = "p191"; #pin 7
#NET "pin8" LOC = "p192"; #pin 8
#NET "pin9" LOC = "p193"; #pin 9
NET "timer_out" LOC = "p194"; #pin 10
#NET "pin10" LOC = "p194"; #pin 10
NET "bus_data<0>" LOC = "p198"; #pin 11
NET "bus_data<1>" LOC = "p199"; #pin 12
NET "bus_data<2>" LOC = "p200"; #pin 13
213,15 → 213,15
#
# Timing Constraints
#
#TIMEGRP "gram_cs" OFFSET = OUT 40 ns AFTER "sysclk";
#TIMEGRP "gram_wr" OFFSET = OUT 40 ns AFTER "sysclk";
#TIMEGRP "gram_addr" OFFSET = OUT 40 ns AFTER "sysclk";
#TIMEGRP "gram_data" OFFSET = OUT 40 ns AFTER "sysclk";
#TIMEGRP "gram_data" OFFSET = IN 15 ns BEFORE "sysclk";
#TIMEGRP "gtest_alu" OFFSET = OUT 90 ns AFTER "sysclk";
#TIMEGRP "gtest_cc" OFFSET = OUT 95 ns AFTER "sysclk";
NET "sysclk" TNM_NET = "sysclk";
TIMESPEC "TS_sysclk" = PERIOD "sysclk" 20 ns LOW 50 %;
#TIMEGRP "gram_cs" OFFSET = OUT 40 ns AFTER "clk_in";
#TIMEGRP "gram_wr" OFFSET = OUT 40 ns AFTER "clk_in";
#TIMEGRP "gram_addr" OFFSET = OUT 40 ns AFTER "clk_in";
#TIMEGRP "gram_data" OFFSET = OUT 40 ns AFTER "clk_in";
#TIMEGRP "gram_data" OFFSET = IN 15 ns BEFORE "clk_in";
#TIMEGRP "gtest_alu" OFFSET = OUT 90 ns AFTER "clk_in";
#TIMEGRP "gtest_cc" OFFSET = OUT 95 ns AFTER "clk_in";
NET "clk_in" TNM_NET = "clk_in";
TIMESPEC "TS_clk_in" = PERIOD "clk_in" 20 ns LOW 50 %;
#
# Fast I/O Pins
#
/trunk/rtl/System09_BurchED_B5-X300/System09_BurchED_B5-X300.ise Cannot display: file marked as a binary type. svn:mime-type = application/octet-stream
/trunk/rtl/System09_BurchED_B5-X300/System09_BurchED_B5-X300.vhd
5,7 → 5,7
-- www.OpenCores.Org - September 2003
-- This core adheres to the GNU public license
--
-- File name : System09.vhd
-- File name : System09_BurchED_B5-X300.vhd
--
-- Purpose : Top level file for 6809 compatible system on a chip
-- Designed with Xilinx XC2S300e Spartan 2+ FPGA.
18,32 → 18,44
-- ieee.numeric_std
--
-- Uses :
-- cpu09 (cpu09.vhd) CPU core
-- mon_rom (sys09bug_rom2k_b4.vhd) Monitor ROM
-- dat_ram (datram.vhd) Dynamic Address Translation
-- acia_6850 (ACIA_6850.vhd) ACIA / MiniUART
-- (ACIA_RX.vhd)
-- (ACIA_TX.vhd)
-- ACIA_Clock (ACIA_Clock.vhd) ACIA Baud Clock Divider
-- keyboard (keyboard.vhd) PS/2 Keyboard Interface
-- vdu8 (vdu8.vhd) 80 x 25 Video Display
-- timer (timer.vhd) Timer module
-- trap (trap.vhd) Bus Trap interrupt
-- ioport (ioport.vhd) Parallel I/O port.
-- cpu09 (cpu09.vhd) CPU core
-- SYS09BUG_F800 (sys09b5x_b4.vhd) Monitor ROM
-- dat_ram (datram.vhd) Dynamic Address Translation
-- acia6850 (acia6850.vhd) ACIA / MiniUART
-- ACIA_Clock (ACIA_Clock.vhd) ACIA Baud Clock Divider
-- keyboard (keyboard.vhd) PS/2 Keyboard Interface
-- vdu8 (vdu8.vhd) 80 x 25 Video Display
-- timer (timer.vhd) Timer module
-- trap (trap.vhd) Bus Trap interrupt
-- ioport (ioport.vhd) Parallel I/O port.
--
-- Author : John E. Kent
-- dilbert57@opencores.org
-- Memory Map :
-- $E000 - ACIA (SWTPc)
-- $E010 - Reserved for FD1771 FDC (SWTPc)
-- $E020 - Keyboard
-- $E030 - VDU
-- $E040 - Compact Flash
-- $E050 - Timer
-- $E060 - Bus trap
-- Memory Map :
--
-- $0000 - $DFFF System RAM (256K Mapped via DAT)
-- $E000 - ACIA (SWTPc)
-- $E010 - Reserved for SWTPc FD-01 FD1771 FDC
-- $E020 - Keyboard
-- $E030 - VDU
-- $E040 - Reserved for SWTPc MP-T (was Compact Flash)
-- $E050 - Timer
-- $E060 - Bus Trap (Hardware Breakpoint Interrupt Logic)
-- $E070 - Parallel I/O
-- $E080 - Reserved for 6821 PIA (?) (SWTPc)
-- $E090 - Reserved for 6840 PTM (?) (SWTPc)
-- $E080 - Reserved for SWTPc MP-ID 6821 PIA (?)
-- $E090 - Reserved for SWTPc MP-ID 6840 PTM (?)
-- $E0A0 - Reserved SPP Printer Port
-- $E0B0 - Reserved
-- $E0C0 - Reserved
-- $E100 - $E13F IDE / Compact Flash Card
-- $E140 - $E17F Reserved for Ethernet MAC (XESS)
-- $E180 - $E1BF Reserved for Expansion Slot 0 (XESS)
-- $E1C0 - $E1FF Reserved for Expansion Slot 1 (XESS)
-- $E200 - $EFFF Dual Port RAM interface
-- $F000 - $F7FF Reserved SWTPc DMAF-2
-- $F800 - $FFFF Sys09bug ROM (Read only)
-- $FFF0 - $FFFF DAT - Dynamic Address Translation (Write Only)
--
--===========================================================================----
--
108,6 → 120,16
-- Removed DAT memory map control of ROM & IO
-- to allow for full use of RAM as a RAM disk.
-- Mapped in all 16 bits of the CF data bus.
--
-- Version 1.8 - 23rd February 2009 - John Kent
-- Renamed mon_rom to SYS09BUG_F800
--
-- Version 1.9 - 5th sepember 2010 - John Kent
-- Added Peripheral bus interface
-- Made the clock divider an external module
-- Rearranged VDU generic signals
-- Changed address decoding
-- Made the SRAM an external module
--
--===========================================================================
--
121,8 → 143,8
 
entity System09 is
port(
SysClk : in Std_Logic; -- System Clock input
Reset_n : in Std_logic; -- Master Reset input (active low)
clk_in : in Std_Logic; -- System Clock input
rst_n : in Std_logic; -- Master Reset input (active low)
LED : out std_logic; -- Diagnostic LED Flasher
 
-- Memory Interface signals
178,10 → 200,7
bus_rw : out std_logic;
bus_cs : out std_logic;
bus_addr : out std_logic_vector(15 downto 0);
bus_data : inout std_logic_vector(7 downto 0);
 
-- timer
timer_out : out std_logic
bus_data : inout std_logic_vector(7 downto 0)
);
end System09;
 
192,11 → 211,11
-----------------------------------------------------------------------------
-- constants
-----------------------------------------------------------------------------
constant SYS_Clock_Frequency : integer := 50000000; -- FPGA System Clock
constant PIX_Clock_Frequency : integer := 25000000; -- VGA Pixel Clock
constant CPU_Clock_Frequency : integer := 12500000; -- CPU Clock
constant BAUD_Rate : integer := 57600; -- Baud Rate
constant ACIA_Clock_Frequency : integer := BAUD_Rate * 16;
constant SYS_CLK_FREQ : integer := 50000000; -- FPGA System Clock
constant VGA_CLK_FREQ : integer := 25000000; -- VGA Pixel Clock
constant CPU_CLK_FREQ : integer := 12500000; -- CPU Clock
constant BAUD_RATE : integer := 57600; -- Baud Rate
constant ACIA_CLK_FREQ : integer := BAUD_RATE * 16;
 
type hold_state_type is ( hold_release_state, hold_request_state );
 
203,82 → 222,137
-----------------------------------------------------------------------------
-- Signals
-----------------------------------------------------------------------------
-- Clock signals
signal sys_clk : std_logic;
signal vga_clk : std_logic;
 
-- CPU Interface signals
signal cpu_rst : Std_Logic;
signal cpu_clk : Std_Logic;
signal cpu_vma : std_logic;
signal cpu_addr : std_logic_vector(15 downto 0);
signal cpu_rw : std_logic;
signal cpu_data_in : std_logic_vector(7 downto 0);
signal cpu_data_out : std_logic_vector(7 downto 0);
signal cpu_firq : std_logic;
signal cpu_irq : std_logic;
signal cpu_nmi : std_logic;
signal cpu_halt : std_logic;
signal cpu_hold : std_logic;
 
-- Dynamic address translation
signal dat_cs : std_logic;
signal dat_addr : std_logic_vector(7 downto 0);
 
-- Monitor ROM
signal rom_data_out : Std_Logic_Vector(7 downto 0);
signal rom_cs : std_logic;
 
-- UART Interface signals
-- UART/ACIA Interface signals
signal uart_data_out : Std_Logic_Vector(7 downto 0);
signal uart_cs : Std_Logic;
signal uart_irq : Std_Logic;
signal uart_clk : Std_Logic;
signal uart_clk : Std_Logic;
signal DCD_n : Std_Logic;
 
-- timer
signal timer_data_out : std_logic_vector(7 downto 0);
signal timer_cs : std_logic;
signal timer_irq : std_logic;
-- Keyboard port
signal kbd_data_out : std_logic_vector(7 downto 0);
signal kbd_cs : std_logic;
signal kbd_irq : std_logic;
 
-- Video Display Unit
signal vdu_cs : std_logic;
signal vdu_data_out : std_logic_vector(7 downto 0);
signal vga_red : std_logic;
signal vga_green : std_logic;
signal vga_blue : std_logic;
 
-- trap
signal trap_cs : std_logic;
signal trap_data_out : std_logic_vector(7 downto 0);
signal trap_irq : std_logic;
-- Timer
signal tmr_data_out : std_logic_vector(7 downto 0);
signal tmr_cs : std_logic;
signal tmr_irq : std_logic;
 
-- Trap Hardware break point
signal trap_cs : std_logic;
signal trap_data_out : std_logic_vector(7 downto 0);
signal trap_irq : std_logic;
 
-- Parallel I/O port
signal ioport_data_out : std_logic_vector(7 downto 0);
signal ioport_cs : std_logic;
signal pio_data_out : std_logic_vector(7 downto 0);
signal pio_cs : std_logic;
 
-- compact flash port
signal cf_data_out : std_logic_vector(7 downto 0);
signal cf_cs : std_logic;
signal cf_rd : std_logic;
signal cf_wr : std_logic;
signal cf_hold : std_logic;
signal cf_release : std_logic;
signal cf_count : std_logic_vector(3 downto 0);
signal cf_hold_state : hold_state_type;
-- Peripheral bus
signal pb_data_out : std_logic_vector(7 downto 0);
signal pb_cs : std_logic;
signal pb_hold : std_logic;
 
-- Compact Flash on peripheral bus
signal cf_cs : std_logic;
 
-- keyboard port
signal keyboard_data_out : std_logic_vector(7 downto 0);
signal keyboard_cs : std_logic;
signal keyboard_irq : std_logic;
-- SRAM
signal ram_cs : std_logic; -- memory chip select
signal ram_data_out : std_logic_vector(7 downto 0);
 
-- RAM
signal ram_cs : std_logic; -- memory chip select
signal ram_wrl : std_logic; -- memory write lower
signal ram_wru : std_logic; -- memory write upper
signal ram_data_out : std_logic_vector(7 downto 0);
-----------------------------------------------------------------
--
-- Clock generator
--
-----------------------------------------------------------------
 
component clock_div
port(
clk_in : in std_Logic; -- System Clock input
sys_clk : out std_logic; -- System Clock Out (1/1)
vga_clk : out std_logic; -- VGA Pixel Clock Out (1/2)
cpu_clk : out std_logic -- CPU Clock Out (1/4)
);
end component;
 
 
-----------------------------------------------------------------
--
-- LED Flasher
--
-----------------------------------------------------------------
 
-- CPU Interface signals
signal cpu_reset : Std_Logic;
signal cpu_clk : Std_Logic;
signal cpu_rw : std_logic;
signal cpu_vma : std_logic;
signal cpu_halt : std_logic;
signal cpu_hold : std_logic;
signal cpu_firq : std_logic;
signal cpu_irq : std_logic;
signal cpu_nmi : std_logic;
signal cpu_addr : std_logic_vector(15 downto 0);
signal cpu_data_in : std_logic_vector(7 downto 0);
signal cpu_data_out : std_logic_vector(7 downto 0);
component flasher
port (
clk : in std_logic; -- Clock input
rst : in std_logic; -- Reset input (active high)
LED : out Std_Logic -- LED output
);
end component;
 
------------------------------------------------------------
--
-- B5 SRAM interface ($0000 - $DFFF)
--
------------------------------------------------------------
component BED_SRAM
port (
--
-- CPU Interface signals
--
clk : in std_logic; -- System Clock (twice the CPU clock)
rst : in std_logic; -- Reset input (active high)
cs : in std_logic; -- RAM Chip Select
addr : in std_logic_vector(17 downto 0); -- RAM address bus
rw : in std_logic; -- Read / Not Write
data_in : in std_logic_vector(7 downto 0); -- Data Bus In
data_out : out std_logic_vector(7 downto 0); -- Data Bus Out
--
-- BED_SRAM Interface Signals
--
ram_csn : out Std_Logic;
ram_wrln : out Std_Logic;
ram_wrun : out Std_Logic;
ram_addr : out Std_Logic_Vector(16 downto 0);
ram_data : inout Std_Logic_Vector(15 downto 0)
 
);
end component;
 
 
-- Dynamic address translation
signal dat_cs : std_logic;
signal dat_addr : std_logic_vector(7 downto 0);
 
-- Video Display Unit
signal pix_clk : std_logic;
signal vdu_cs : std_logic;
signal vdu_data_out : std_logic_vector(7 downto 0);
signal vga_red : std_logic;
signal vga_green : std_logic;
signal vga_blue : std_logic;
 
-- Flashing Led test signals
signal countL : std_logic_vector(23 downto 0);
signal clock_div : std_logic_vector(1 downto 0);
 
-----------------------------------------------------------------
--
-- CPU09 CPU core
287,42 → 361,23
 
component cpu09
port (
clk: in std_logic;
rst: in std_logic;
rw: out std_logic; -- Asynchronous memory interface
vma: out std_logic;
address: out std_logic_vector(15 downto 0);
data_in: in std_logic_vector(7 downto 0);
data_out: out std_logic_vector(7 downto 0);
halt: in std_logic;
hold: in std_logic;
irq: in std_logic;
nmi: in std_logic;
firq: in std_logic
clk : in std_logic;
rst : in std_logic;
vma : out std_logic;
addr : out std_logic_vector(15 downto 0);
rw : out std_logic; -- Asynchronous memory interface
data_in : in std_logic_vector(7 downto 0);
data_out : out std_logic_vector(7 downto 0);
halt : in std_logic;
hold : in std_logic;
irq : in std_logic;
nmi : in std_logic;
firq : in std_logic
);
end component;
 
 
----------------------------------------
--
-- SBUG Block RAM Monitor ROM
--
----------------------------------------
component mon_rom
port (
clk : in std_logic;
rst : in std_logic;
cs : in std_logic;
rw : in std_logic;
addr : in std_logic_vector (10 downto 0);
wdata : in std_logic_vector (7 downto 0);
rdata : out std_logic_vector (7 downto 0)
);
end component;
 
 
----------------------------------------
--
-- Dynamic Address Translation Registers
--
----------------------------------------
339,6 → 394,23
);
end component;
 
----------------------------------------
--
-- SBUG Block RAM Monitor ROM
--
----------------------------------------
component SYS09BUG_F800
port (
clk : in std_logic;
rst : in std_logic;
cs : in std_logic;
addr : in std_logic_vector (10 downto 0);
rw : in std_logic;
data_in : in std_logic_vector (7 downto 0);
data_out : out std_logic_vector (7 downto 0)
);
end component;
 
-----------------------------------------------------------------
--
-- 6850 ACIA/UART
345,16 → 417,16
--
-----------------------------------------------------------------
 
component ACIA_6850
component acia6850
port (
clk : in Std_Logic; -- System Clock
rst : in Std_Logic; -- Reset input (active high)
cs : in Std_Logic; -- miniUART Chip Select
addr : in Std_Logic; -- Register Select
rw : in Std_Logic; -- Read / Not Write
data_in : in Std_Logic_Vector(7 downto 0); -- Data Bus In
data_out : out Std_Logic_Vector(7 downto 0); -- Data Bus Out
irq : out Std_Logic; -- Interrupt
Addr : in Std_Logic; -- Register Select
DataIn : in Std_Logic_Vector(7 downto 0); -- Data Bus In
DataOut : out Std_Logic_Vector(7 downto 0); -- Data Bus Out
RxC : in Std_Logic; -- Receive Baud Clock
TxC : in Std_Logic; -- Transmit Baud Clock
RxD : in Std_Logic; -- Receive Data
372,8 → 444,8
 
component ACIA_Clock
generic (
SYS_Clock_Frequency : integer := SYS_Clock_Frequency;
ACIA_Clock_Frequency : integer := ACIA_Clock_Frequency
SYS_CLK_FREQ : integer := SYS_CLK_FREQ;
ACIA_CLK_FREQ : integer := ACIA_CLK_FREQ
);
port (
clk : in Std_Logic; -- System Clock Input
380,9 → 452,72
ACIA_clk : out Std_logic -- ACIA Clock output
);
end component;
 
----------------------------------------
--
-- PS/2 Keyboard
--
----------------------------------------
 
component keyboard
generic(
KBD_CLK_FREQ : integer := CPU_CLK_FREQ
);
port(
clk : in std_logic;
rst : in std_logic;
cs : in std_logic;
rw : in std_logic;
addr : in std_logic;
data_in : in std_logic_vector(7 downto 0);
data_out : out std_logic_vector(7 downto 0);
irq : out std_logic;
kbd_clk : inout std_logic;
kbd_data : inout std_logic
);
end component;
 
----------------------------------------
--
-- Video Display Unit.
--
----------------------------------------
component vdu8
generic(
VGA_CLK_FREQ : integer := VGA_CLK_FREQ; -- 25MHz
VGA_HOR_CHARS : integer := 80; -- CHARACTERS 25.6us
VGA_HOR_CHAR_PIXELS : integer := 8; -- PIXELS 0.32us
VGA_HOR_FRONT_PORCH : integer := 16; -- PIXELS 0.64us (0.94us)
VGA_HOR_SYNC : integer := 96; -- PIXELS 3.84us (3.77us)
VGA_HOR_BACK_PORCH : integer := 48; -- PIXELS 1.92us (1.89us)
VGA_VER_CHARS : integer := 25; -- CHARACTERS 12.8ms
VGA_VER_CHAR_LINES : integer := 16; -- LINES 0.512ms
VGA_VER_FRONT_PORCH : integer := 10; -- LINES 0.320ms
VGA_VER_SYNC : integer := 2; -- LINES 0.064ms
VGA_VER_BACK_PORCH : integer := 34 -- LINES 1.088ms
);
port(
-- control register interface
vdu_clk : in std_logic; -- CPU Clock - 12.5MHz
vdu_rst : in std_logic;
vdu_cs : in std_logic;
vdu_rw : in std_logic;
vdu_addr : in std_logic_vector(2 downto 0);
vdu_data_in : in std_logic_vector(7 downto 0);
vdu_data_out : out std_logic_vector(7 downto 0);
 
-- vga port connections
vga_clk : in std_logic; -- VGA Pixel Clock - 25 MHz
vga_red_o : out std_logic;
vga_green_o : out std_logic;
vga_blue_o : out std_logic;
vga_hsync_o : out std_logic;
vga_vsync_o : out std_logic
);
end component;
 
----------------------------------------
--
-- Timer module
--
----------------------------------------
389,17 → 524,15
 
component timer
port (
clk : in std_logic;
rst : in std_logic;
cs : in std_logic;
rw : in std_logic;
addr : in std_logic;
data_in : in std_logic_vector(7 downto 0);
data_out : out std_logic_vector(7 downto 0);
irq : out std_logic;
timer_in : in std_logic;
timer_out : out std_logic
);
clk : in std_logic;
rst : in std_logic;
cs : in std_logic;
addr : in std_logic;
rw : in std_logic;
data_in : in std_logic_vector(7 downto 0);
data_out : out std_logic_vector(7 downto 0);
irq : out std_logic
);
end component;
 
------------------------------------------------------------
409,8 → 542,8
------------------------------------------------------------
 
component trap
port (
clk : in std_logic;
port (
clk : in std_logic;
rst : in std_logic;
cs : in std_logic;
rw : in std_logic;
417,8 → 550,8
vma : in std_logic;
addr : in std_logic_vector(15 downto 0);
data_in : in std_logic_vector(7 downto 0);
data_out : out std_logic_vector(7 downto 0);
irq : out std_logic
data_out : out std_logic_vector(7 downto 0);
irq : out std_logic
);
end component;
 
428,84 → 561,57
--
----------------------------------------
component ioport
port (
clk : in std_logic;
port (
clk : in std_logic;
rst : in std_logic;
cs : in std_logic;
rw : in std_logic;
addr : in std_logic_vector(1 downto 0);
data_in : in std_logic_vector(7 downto 0);
data_out : out std_logic_vector(7 downto 0);
porta_io : inout std_logic_vector(7 downto 0);
portb_io : inout std_logic_vector(7 downto 0)
);
end component;
 
----------------------------------------
--
-- PS/2 Keyboard
--
----------------------------------------
 
component keyboard
generic(
KBD_Clock_Frequency : integer := CPU_Clock_Frequency
data_out : out std_logic_vector(7 downto 0);
porta_io : inout std_logic_vector(7 downto 0);
portb_io : inout std_logic_vector(7 downto 0)
);
port(
clk : in std_logic;
rst : in std_logic;
cs : in std_logic;
rw : in std_logic;
addr : in std_logic;
data_in : in std_logic_vector(7 downto 0);
data_out : out std_logic_vector(7 downto 0);
irq : out std_logic;
kbd_clk : inout std_logic;
kbd_data : inout std_logic
);
end component;
 
----------------------------------------
--
-- Video Display Unit.
--
----------------------------------------
component vdu8
generic(
VDU_CLOCK_FREQUENCY : integer := CPU_Clock_Frequency; -- HZ
VGA_CLOCK_FREQUENCY : integer := PIX_Clock_Frequency; -- HZ
VGA_HOR_CHARS : integer := 80; -- CHARACTERS
VGA_VER_CHARS : integer := 25; -- CHARACTERS
VGA_PIXELS_PER_CHAR : integer := 8; -- PIXELS
VGA_LINES_PER_CHAR : integer := 16; -- LINES
VGA_HOR_BACK_PORCH : integer := 40; -- PIXELS
VGA_HOR_SYNC : integer := 96; -- PIXELS
VGA_HOR_FRONT_PORCH : integer := 24; -- PIXELS
VGA_VER_BACK_PORCH : integer := 13; -- LINES
VGA_VER_SYNC : integer := 1; -- LINES
VGA_VER_FRONT_PORCH : integer := 36 -- LINES
);
port(
-- control register interface
vdu_clk : in std_logic; -- CPU Clock - 12.5MHz
vdu_rst : in std_logic;
vdu_cs : in std_logic;
vdu_rw : in std_logic;
vdu_addr : in std_logic_vector(2 downto 0);
vdu_data_in : in std_logic_vector(7 downto 0);
vdu_data_out : out std_logic_vector(7 downto 0);
------------------------------------------------------------
--
-- Peripheral Bus interface (IDE CF) ($E100 - $E1FF)
--
------------------------------------------------------------
 
-- vga port connections
vga_clk : in std_logic; -- VGA Pixel Clock - 25 MHz
vga_red_o : out std_logic;
vga_green_o : out std_logic;
vga_blue_o : out std_logic;
vga_hsync_o : out std_logic;
vga_vsync_o : out std_logic
);
end component;
component peripheral_bus is
port (
--
-- CPU Interface signals
--
clk : in std_logic; -- System Clock
rst : in std_logic; -- Reset input (active high)
cs : in std_logic; -- Peripheral Bus Chip Select
addr : in std_logic_vector(7 downto 0); -- Register Select
rw : in std_logic; -- Read / Not Write
data_in : in std_logic_vector(7 downto 0); -- Data Bus In
data_out : out std_logic_vector(7 downto 0); -- Data Bus Out
hold : out std_logic; -- Hold bus cycle output
--
-- Peripheral Bus Interface Signals
-- IO + ($00 - $FF)
-- (for compatibility with XSA-3S1000 / XST 3.0)
--
pb_rd_n : out std_logic; -- ide pin 25
pb_wr_n : out std_logic; -- ide pin 23
pb_addr : out std_logic_vector( 4 downto 0);
pb_data : inout std_logic_vector(15 downto 0);
 
-- Peripheral chip selects on Peripheral Bus
ide_cs : out std_logic; -- IDE / CF interface ($00 - $3F)
eth_cs : out std_logic; -- Ethernet interface ($40 - $7F)
sl1_cs : out std_logic; -- Expansion slot 1 ($80 - $BF)
sl2_cs : out std_logic -- Expansion slot 2 ($C0 - $FF)
);
end component;
 
 
 
component BUFG
port (
i: in std_logic;
514,10 → 620,34
end component;
 
begin
-----------------------------------------------------------------------------
-- Instantiation of internal components
-----------------------------------------------------------------------------
-----------------------------------------------------------------------------
-- Instantiation of internal components
-----------------------------------------------------------------------------
----------------------------------------
--
-- Clock generator
--
----------------------------------------
my_clock_div: clock_div port map (
clk_in => clk_in, -- Clock input
sys_clk => sys_clk, -- System Clock Out (1/1)
vga_clk => vga_clk, -- VGA Pixel Clock Out (1/2)
cpu_clk => cpu_clk -- CPU Clock Out (1/4)
);
 
-----------------------------------------
--
-- LED Flasher
--
-----------------------------------------
 
my_LED_flasher : flasher port map (
clk => cpu_clk,
rst => cpu_rst,
LED => LED
);
 
 
----------------------------------------
--
-- CPU09 CPU Core
525,10 → 655,10
----------------------------------------
my_cpu : cpu09 port map (
clk => cpu_clk,
rst => cpu_reset,
rst => cpu_rst,
vma => cpu_vma,
addr => cpu_addr(15 downto 0),
rw => cpu_rw,
vma => cpu_vma,
address => cpu_addr(15 downto 0),
data_in => cpu_data_in,
data_out => cpu_data_out,
halt => cpu_halt,
540,27 → 670,12
 
----------------------------------------
--
-- SBUG / KBUG / SYS09BUG Monitor ROM
--
----------------------------------------
my_rom : mon_rom port map (
clk => cpu_clk,
rst => cpu_reset,
cs => rom_cs,
rw => '1',
addr => cpu_addr(10 downto 0),
wdata => cpu_data_out,
rdata => rom_data_out
);
 
----------------------------------------
--
-- Dynamic Address Translation Registers
--
----------------------------------------
my_dat : dat_ram port map (
clk => cpu_clk,
rst => cpu_reset,
rst => cpu_rst,
cs => dat_cs,
rw => cpu_rw,
addr_hi => cpu_addr(15 downto 12),
571,18 → 686,33
 
----------------------------------------
--
-- SBUG / KBUG / SYS09BUG Monitor ROM
--
----------------------------------------
my_rom : SYS09BUG_F800 port map (
clk => cpu_clk,
rst => cpu_rst,
cs => rom_cs,
addr => cpu_addr(10 downto 0),
rw => '1',
data_in => cpu_data_out,
data_out => rom_data_out
);
 
----------------------------------------
--
-- ACIA/UART Serial interface
--
----------------------------------------
my_ACIA : ACIA_6850 port map (
my_acia : acia6850 port map (
clk => cpu_clk,
rst => cpu_reset,
rst => cpu_rst,
cs => uart_cs,
addr => cpu_addr(0),
rw => cpu_rw,
data_in => cpu_data_out,
data_out => uart_data_out,
irq => uart_irq,
Addr => cpu_addr(0),
Datain => cpu_data_out,
DataOut => uart_data_out,
RxC => uart_clk,
TxC => uart_clk,
RxD => rxbit,
599,11 → 729,11
----------------------------------------
my_ACIA_Clock : ACIA_Clock
generic map(
SYS_Clock_Frequency => SYS_Clock_Frequency,
ACIA_Clock_Frequency => ACIA_Clock_Frequency
SYS_CLK_FREQ => SYS_CLK_FREQ,
ACIA_CLK_FREQ => ACIA_CLK_FREQ
)
port map(
clk => SysClk,
clk => sys_clk,
acia_clk => uart_clk
);
 
614,77 → 744,75
----------------------------------------
my_keyboard : keyboard
generic map (
KBD_Clock_Frequency => CPU_Clock_frequency
KBD_CLK_FREQ => CPU_CLK_FREQ
)
port map(
clk => cpu_clk,
rst => cpu_reset,
cs => keyboard_cs,
rw => cpu_rw,
addr => cpu_addr(0),
data_in => cpu_data_out(7 downto 0),
data_out => keyboard_data_out(7 downto 0),
irq => keyboard_irq,
kbd_clk => kb_clock,
kbd_data => kb_data
clk => cpu_clk,
rst => cpu_rst,
cs => kbd_cs,
addr => cpu_addr(0),
rw => cpu_rw,
data_in => cpu_data_out(7 downto 0),
data_out => kbd_data_out(7 downto 0),
irq => kbd_irq,
kbd_clk => kb_clock,
kbd_data => kb_data
);
 
 
------------------------------------------------
--
-- Video Display Unit instantiation ($E030-$E03F)
--
-------------------------------------------------
my_vdu : vdu8
generic map(
VGA_CLK_FREQ => VGA_CLK_FREQ, -- 25MHZ
VGA_HOR_CHARS => 80, -- CHARACTERS 25.6us
VGA_HOR_CHAR_PIXELS => 8, -- PIXELS 0.32us
VGA_HOR_FRONT_PORCH => 16, -- PIXELS 0.64us
VGA_HOR_SYNC => 96, -- PIXELS 3.84us
VGA_HOR_BACK_PORCH => 48, -- PIXELS 1.92us
VGA_VER_CHARS => 25, -- CHARACTERS 12.8ms
VGA_VER_CHAR_LINES => 16, -- LINES 0.512ms
VGA_VER_FRONT_PORCH => 10, -- LINES 0.320ms
VGA_VER_SYNC => 2, -- LINES 0.064ms
VGA_VER_BACK_PORCH => 34 -- LINES 1.088ms
)
port map(
 
-- CPU Control Registers interface
vdu_clk => cpu_clk, -- 12.5 MHz System Clock in
vdu_rst => cpu_rst,
vdu_cs => vdu_cs,
vdu_rw => cpu_rw,
vdu_addr => cpu_addr(2 downto 0),
vdu_data_in => cpu_data_out,
vdu_data_out => vdu_data_out,
 
-- vga port connections
vga_clk => vga_clk, -- 25 MHz VDU pixel clock
vga_red_o => vga_red,
vga_green_o => vga_green,
vga_blue_o => vga_blue,
vga_hsync_o => h_drive,
vga_vsync_o => v_drive
);
 
----------------------------------------
--
-- Video Display Unit instantiation
--
----------------------------------------
my_vdu : vdu8
generic map(
VDU_CLOCK_FREQUENCY => CPU_Clock_Frequency, -- HZ
VGA_CLOCK_FREQUENCY => PIX_Clock_Frequency, -- HZ
VGA_HOR_CHARS => 80, -- CHARACTERS
VGA_VER_CHARS => 25, -- CHARACTERS
VGA_PIXELS_PER_CHAR => 8, -- PIXELS
VGA_LINES_PER_CHAR => 16, -- LINES
VGA_HOR_BACK_PORCH => 40, -- PIXELS
VGA_HOR_SYNC => 96, -- PIXELS
VGA_HOR_FRONT_PORCH => 24, -- PIXELS
VGA_VER_BACK_PORCH => 13, -- LINES
VGA_VER_SYNC => 1, -- LINES
VGA_VER_FRONT_PORCH => 36 -- LINES
)
port map(
 
-- Control Registers
vdu_clk => cpu_clk, -- 12.5 MHz System Clock in
vdu_rst => cpu_reset,
vdu_cs => vdu_cs,
vdu_rw => cpu_rw,
vdu_addr => cpu_addr(2 downto 0),
vdu_data_in => cpu_data_out,
vdu_data_out => vdu_data_out,
 
-- vga port connections
vga_clk => pix_clk, -- 25 MHz VDU pixel clock
vga_red_o => vga_red,
vga_green_o => vga_green,
vga_blue_o => vga_blue,
vga_hsync_o => h_drive,
vga_vsync_o => v_drive
);
 
----------------------------------------
--
-- Timer Module
--
----------------------------------------
my_timer : timer port map (
clk => cpu_clk,
rst => cpu_reset,
cs => timer_cs,
rst => cpu_rst,
cs => tmr_cs,
rw => cpu_rw,
addr => cpu_addr(0),
data_in => cpu_data_out,
data_out => timer_data_out,
irq => timer_irq,
timer_in => CountL(5),
timer_out => timer_out
data_out => tmr_data_out,
irq => tmr_irq
);
 
----------------------------------------
694,7 → 822,7
----------------------------------------
my_trap : trap port map (
clk => cpu_clk,
rst => cpu_reset,
rst => cpu_rst,
cs => trap_cs,
rw => cpu_rw,
vma => cpu_vma,
711,31 → 839,77
----------------------------------------
my_ioport : ioport port map (
clk => cpu_clk,
rst => cpu_reset,
cs => ioport_cs,
rst => cpu_rst,
cs => pio_cs,
rw => cpu_rw,
addr => cpu_addr(1 downto 0),
data_in => cpu_data_out,
data_out => ioport_data_out,
data_out => pio_data_out,
porta_io => porta,
portb_io => portb
);
 
 
--
-- 12.5 MHz CPU clock
--
cpu_clk_buffer : BUFG port map(
i => clock_div(1),
o => cpu_clk
------------------------------------------------
--
-- 16 bit Peripheral Bus interface ($E100-$E1FF)
--
------------------------------------------------
my_pb : peripheral_bus port map (
--
-- CPU Interface signals
--
clk => cpu_clk,
rst => cpu_rst,
cs => pb_cs,
addr => cpu_addr(7 downto 0),
rw => cpu_rw,
data_in => cpu_data_out,
data_out => pb_data_out,
hold => pb_hold,
--
-- Peripheral Bus Interface Signals
-- IO + ($00 - $FF)
--
pb_rd_n => cf_rd_n,
pb_wr_n => cf_wr_n,
pb_addr(2 downto 0) => cf_a,
pb_addr(4 downto 3) => open,
pb_data => cf_d,
 
-- Peripheral chip selects on Peripheral Bus
ide_cs => cf_cs,
eth_cs => open,
sl1_cs => open,
sl2_cs => open
);
--
-- 25 MHz VGA Pixel clock
--
vga_clk_buffer : BUFG port map(
i => clock_div(0),
o => pix_clk
);
 
-----------------------------------------------
--
-- BED SRAM interface (256KBytes) ($0000-$DFFF)
--
-----------------------------------------------
my_bed_sram : BED_SRAM port map (
--
-- CPU Interface signals
--
clk => vga_clk, -- VGA Clock (twice the CPU clock)
rst => cpu_rst, -- Reset input (active high)
cs => ram_cs, -- RAM Chip Select
addr(17 downto 12) => dat_addr( 5 downto 0), -- High RAM address goes to the DAT
addr(11 downto 0) => cpu_addr(11 downto 0), -- Low RAM address goes to the CPU
rw => cpu_rw, -- Read / Not Write
data_in => cpu_data_out, -- Data Bus In
data_out => ram_data_out, -- Data Bus Out
--
-- BED_SRAM Interface Signals
--
ram_csn => ram_csn,
ram_wrln => ram_wrln,
ram_wrun => ram_wrun,
ram_addr => ram_addr,
ram_data => ram_data
);
----------------------------------------------------------------------
--
743,62 → 917,72
--
----------------------------------------------------------------------
 
mem_decode: process( cpu_clk, Reset_n, dat_addr,
mem_decode: process( dat_addr,
cpu_addr, cpu_rw, cpu_vma,
rom_data_out,
ram_data_out,
cf_data_out,
timer_data_out,
trap_data_out,
ioport_data_out,
uart_data_out,
keyboard_data_out,
kbd_data_out,
vdu_data_out,
bus_data )
variable decode_addr : std_logic_vector(4 downto 0);
tmr_data_out,
trap_data_out,
pio_data_out,
bus_data,
pb_data_out,
ram_data_out )
begin
decode_addr := dat_addr(3 downto 0) & cpu_addr(11);
-- decode_addr := cpu_addr(15 downto 11);
 
if cpu_addr( 15 downto 8 ) = "11111111" then
cpu_data_in <= rom_data_out;
rom_cs <= cpu_vma; -- read ROM
dat_cs <= cpu_vma; -- write DAT
ram_cs <= '0';
uart_cs <= '0';
cf_cs <= '0';
timer_cs <= '0';
trap_cs <= '0';
ioport_cs <= '0';
keyboard_cs <= '0';
vdu_cs <= '0';
bus_cs <= '0';
else
case decode_addr is
--
-- SBUG/KBUG/SYS09BUG Monitor ROM $F800 - $FFFF
--
when "11111" => -- $F800 - $FFFF
cpu_data_in <= rom_data_out;
rom_cs <= cpu_vma; -- read ROM
dat_cs <= '0';
ram_cs <= '0';
uart_cs <= '0';
cf_cs <= '0';
timer_cs <= '0';
trap_cs <= '0';
ioport_cs <= '0';
keyboard_cs <= '0';
vdu_cs <= '0';
bus_cs <= '0';
 
--
-- IO Devices $E000 - $E7FF
--
when "11100" => -- $E000 - $E7FF
rom_cs <= '0';
dat_cs <= '0';
ram_cs <= '0';
rom_cs <= '0'; -- read ROM
dat_cs <= '0'; -- write DAT
ram_cs <= '0';
uart_cs <= '0';
kbd_cs <= '0';
vdu_cs <= '0';
tmr_cs <= '0';
trap_cs <= '0';
pio_cs <= '0';
bus_cs <= '0';
pb_cs <= '0';
 
--
-- ROM / DAT $FF00 - $FFFF
--
if cpu_addr( 15 downto 8 ) = "11111111" then
cpu_data_in <= rom_data_out;
rom_cs <= cpu_vma; -- read ROM
dat_cs <= cpu_vma; -- write DAT
else
--
-- Decode on 4K Byte boundaries
--
case dat_addr(3 downto 0) is
when "1111" => -- $F000 - $FFFF
if cpu_addr(11) = '1' then
--
-- SBUG/KBUG/SYS09BUG Monitor ROM $F800 - $FFFF
--
cpu_data_in <= rom_data_out;
rom_cs <= cpu_vma;
else
--
-- SRAM $F000 - $F7FF
-- Future use DMAF-2 Floppy Disk controller
--
cpu_data_in <= ram_data_out;
ram_cs <= cpu_vma;
end if;
--
-- IO Devices $EXXX - $EXXX
--
when "1110" =>
--
-- Decode on 256 Byte boundaries
-- IO device $E0XX - $E7XX
--
case cpu_addr(10 downto 8) is
when "000" =>
--
-- Decode I/O Devices on 16 byte boundaries
-- IO device $E00X - $E0FX
--
case cpu_addr(7 downto 4) is
--
-- UART / ACIA $E000
806,13 → 990,6
when "0000" => -- $E000
cpu_data_in <= uart_data_out;
uart_cs <= cpu_vma;
cf_cs <= '0';
timer_cs <= '0';
trap_cs <= '0';
ioport_cs <= '0';
keyboard_cs <= '0';
vdu_cs <= '0';
bus_cs <= '0';
 
--
-- WD1771 FDC sites at $E010-$E01F
822,15 → 999,8
-- Keyboard port $E020 - $E02F
--
when "0010" => -- $E020
cpu_data_in <= keyboard_data_out;
uart_cs <= '0';
cf_cs <= '0';
timer_cs <= '0';
trap_cs <= '0';
ioport_cs <= '0';
keyboard_cs <= cpu_vma;
vdu_cs <= '0';
bus_cs <= '0';
cpu_data_in <= kbd_data_out;
kbd_cs <= cpu_vma;
 
--
-- VDU port $E030 - $E03F
837,42 → 1007,18
--
when "0011" => -- $E030
cpu_data_in <= vdu_data_out;
uart_cs <= '0';
cf_cs <= '0';
timer_cs <= '0';
trap_cs <= '0';
ioport_cs <= '0';
keyboard_cs <= '0';
vdu_cs <= cpu_vma;
bus_cs <= '0';
 
--
-- Compact Flash $E040 - $E04F
--
when "0100" => -- $E040
cpu_data_in <= cf_data_out;
uart_cs <= '0';
cf_cs <= cpu_vma;
timer_cs <= '0';
trap_cs <= '0';
ioport_cs <= '0';
keyboard_cs <= '0';
vdu_cs <= '0';
bus_cs <= '0';
-- Reserved $E040 - $E04F
--
 
--
-- Timer $E050 - $E05F
--
when "0101" => -- $E050
cpu_data_in <= timer_data_out;
uart_cs <= '0';
cf_cs <= '0';
timer_cs <= cpu_vma;
trap_cs <= '0';
ioport_cs <= '0';
keyboard_cs <= '0';
vdu_cs <= '0';
bus_cs <= '0';
cpu_data_in <= tmr_data_out;
tmr_cs <= cpu_vma;
 
--
-- Bus Trap Logic $E060 - $E06F
879,207 → 1025,78
--
when "0110" => -- $E060
cpu_data_in <= trap_data_out;
uart_cs <= '0';
cf_cs <= '0';
timer_cs <= '0';
trap_cs <= cpu_vma;
ioport_cs <= '0';
keyboard_cs <= '0';
vdu_cs <= '0';
bus_cs <= '0';
 
--
-- I/O port $E070 - $E07F
-- Parallel I/O port $E070 - $E07F
--
when "0111" => -- $E070
cpu_data_in <= ioport_data_out;
uart_cs <= '0';
cf_cs <= '0';
timer_cs <= '0';
trap_cs <= '0';
ioport_cs <= cpu_vma;
keyboard_cs <= '0';
vdu_cs <= '0';
bus_cs <= '0';
 
when others => -- $E080 to $E7FF
cpu_data_in <= pio_data_out;
pio_cs <= cpu_vma;
 
--
-- Undefined / Extension Bus $E080 - $E0FF
--
when others => -- $E080 to $E0FF
cpu_data_in <= bus_data;
uart_cs <= '0';
cf_cs <= '0';
timer_cs <= '0';
trap_cs <= '0';
ioport_cs <= '0';
keyboard_cs <= '0';
vdu_cs <= '0';
bus_cs <= cpu_vma;
end case;
--
-- Everything else is RAM
--
when others =>
cpu_data_in <= ram_data_out;
rom_cs <= '0';
dat_cs <= '0';
ram_cs <= cpu_vma;
uart_cs <= '0';
cf_cs <= '0';
timer_cs <= '0';
trap_cs <= '0';
ioport_cs <= '0';
keyboard_cs <= '0';
vdu_cs <= '0';
bus_cs <= '0';
end case;
end if;
bus_cs <= cpu_vma;
end case;
 
--
-- Peripheral Bus $E100 - $E1FF
--
when "001" =>
cpu_data_in <= pb_data_out;
pb_cs <= cpu_vma;
 
--
-- Map RAM at $E200 - $EFFF Just in case we need driver space.
--
when others =>
cpu_data_in <= ram_data_out;
ram_cs <= cpu_vma;
end case;
--
-- Everything else is RAM $0000 - $DFFF
--
when others =>
cpu_data_in <= ram_data_out;
ram_cs <= cpu_vma;
end case;
end if;
end process;
 
 
--
-- B5-SRAM Control
-- Processes to read and write memory based on bus signals
--
ram_process: process( cpu_clk, Reset_n,
cpu_addr, cpu_rw, cpu_vma, cpu_data_out,
dat_addr,
ram_cs, ram_wrl, ram_wru, ram_data_out )
begin
ram_csn <= not( ram_cs and Reset_n );
ram_wrl <= (not cpu_addr(0)) and (not cpu_rw) and cpu_clk;
ram_wrln <= not (ram_wrl);
ram_wru <= cpu_addr(0) and (not cpu_rw) and cpu_clk;
ram_wrun <= not (ram_wru);
ram_addr(16 downto 11) <= dat_addr(5 downto 0);
ram_addr(10 downto 0) <= cpu_addr(11 downto 1);
 
if ram_wrl = '1' then
ram_data(7 downto 0) <= cpu_data_out;
else
ram_data(7 downto 0) <= "ZZZZZZZZ";
end if;
 
if ram_wru = '1' then
ram_data(15 downto 8) <= cpu_data_out;
else
ram_data(15 downto 8) <= "ZZZZZZZZ";
end if;
 
if cpu_addr(0) = '1' then
ram_data_out <= ram_data(15 downto 8);
else
ram_data_out <= ram_data(7 downto 0);
end if;
end process;
 
--
-- Compact Flash Control
--
compact_flash: process( Reset_n,
cpu_addr, cpu_rw, cpu_vma, cpu_data_out,
cf_cs, cf_rd, cf_wr, cf_d )
begin
cf_rst_n <= Reset_n;
cf_cs0_n <= not( cf_cs ) or cpu_addr(3);
cf_cs1_n <= not( cf_cs and cpu_addr(3));
cf_wr <= cf_cs and (not cpu_rw);
cf_rd <= cf_cs and cpu_rw;
cf_wr_n <= not cf_wr;
cf_rd_n <= not cf_rd;
cf_a <= cpu_addr(2 downto 0);
if cf_wr = '1' then
cf_d(7 downto 0) <= cpu_data_out;
cf_d(15 downto 8) <= (others => '0');
else
cf_d(7 downto 0) <= (others => 'Z');
cf_d(15 downto 8) <= (others => 'Z');
end if;
cf_data_out <= cf_d(7 downto 0);
end process;
 
--
-- Hold CF access for a few cycles
--
cf_hold_proc: process( cpu_clk, Reset_n )
begin
if Reset_n = '0' then
cf_release <= '0';
cf_count <= "0000";
cf_hold_state <= hold_release_state;
elsif cpu_clk'event and cpu_clk='0' then
case cf_hold_state is
when hold_release_state =>
cf_release <= '0';
if cf_cs = '1' then
cf_count <= "0011";
cf_hold_state <= hold_request_state;
end if;
 
when hold_request_state =>
cf_count <= cf_count - "0001";
if cf_count = "0000" then
cf_release <= '1';
cf_hold_state <= hold_release_state;
end if;
when others =>
null;
end case;
end if;
end process;
 
--
-- Interrupts and other bus control signals
--
interrupts : process( Reset_n,
cf_cs, cf_hold, cf_release,
uart_irq, trap_irq, timer_irq, keyboard_irq
)
interrupts : process( rst_n, pb_hold,
uart_irq, trap_irq, tmr_irq, kbd_irq )
begin
cf_hold <= cf_cs and (not cf_release);
cpu_reset <= not Reset_n; -- CPU reset is active high
cpu_irq <= uart_irq or keyboard_irq;
cpu_rst <= not rst_n; -- CPU reset is active high
cpu_irq <= uart_irq or kbd_irq;
cpu_nmi <= trap_irq;
cpu_firq <= timer_irq;
cpu_firq <= tmr_irq;
cpu_halt <= '0';
cpu_hold <= cf_hold;
cpu_hold <= pb_hold;
end process;
 
--
-- CPU bus signals
--
my_bus : process( cpu_clk, cpu_reset, cpu_rw, cpu_addr, cpu_data_out )
my_bus : process( cpu_clk, cpu_rst, cpu_rw, cpu_addr, cpu_data_out )
begin
bus_clk <= cpu_clk;
bus_reset <= cpu_reset;
bus_reset <= cpu_rst;
bus_rw <= cpu_rw;
bus_addr <= cpu_addr;
if( cpu_rw = '1' ) then
bus_data <= "ZZZZZZZZ";
bus_data <= (others => 'Z');
else
bus_data <= cpu_data_out;
end if;
end process;
 
--
-- flash led to indicate code is working
--
my_LED_Flasher: process (cpu_clk, CountL )
begin
if(cpu_clk'event and cpu_clk = '0') then
countL <= countL + 1;
end if;
LED <= countL(23);
dcd_n <= '0';
end process;
 
--
-- Clock divider
--
my_clock_divider: process( SysClk )
begin
if SysClk'event and SysClk='0' then
clock_div <= clock_div + "01";
end if;
end process;
--
-- Assign VDU VGA colour output
-- only 8 colours are handled.
--
1092,6 → 1109,19
blue_lo <= vga_blue;
blue_hi <= vga_blue;
end process;
 
--
-- CF card chip selects ($E100 - $E13F)
-- Located on peripheral bus
--
my_cf_decode: process( cpu_rst, cpu_addr, cf_cs )
begin
 
cf_cs0_n <= not( cf_cs and not cpu_addr(4));
cf_cs1_n <= not( cf_cs and cpu_addr(4));
cf_rst_n <= not cpu_rst;
 
end process;
 
end rtl; --===================== End of architecture =======================--
 

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