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URL https://opencores.org/ocsvn/System09/System09/trunk

Subversion Repositories System09

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    /System09
    from Rev 115 to Rev 116
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Rev 115 → Rev 116

/trunk/rtl/Spartan2/sys09b3s.vhd
0,0 → 1,101
--
-- SYS09BUG Monitor Program
-- v1.0 - 21 November 2006 - John Knet
--
-- v1.1 - 22 december 2006 - John Kent
-- made into 4K ROM/RAM.
--
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
library unisim;
use unisim.vcomponents.all;
 
entity mon_rom is
Port (
clk : in std_logic;
rst : in std_logic;
cs : in std_logic;
rw : in std_logic;
addr : in std_logic_vector (11 downto 0);
rdata : out std_logic_vector (7 downto 0);
wdata : in std_logic_vector (7 downto 0)
);
end mon_rom;
 
architecture rtl of mon_rom is
 
signal we : std_logic;
signal cs0 : std_logic;
signal cs1 : std_logic;
signal dp0 : std_logic;
signal dp1 : std_logic;
signal rdata0 : std_logic_vector(7 downto 0);
signal rdata1 : std_logic_vector(7 downto 0);
 
component SYS09BUG_F000
Port (
clk : in std_logic;
rst : in std_logic;
cs : in std_logic;
rw : in std_logic;
addr : in std_logic_vector (10 downto 0);
rdata : out std_logic_vector (7 downto 0);
wdata : in std_logic_vector (7 downto 0)
);
end component;
 
component SYS09BUG_F800
Port (
clk : in std_logic;
rst : in std_logic;
cs : in std_logic;
rw : in std_logic;
addr : in std_logic_vector (10 downto 0);
rdata : out std_logic_vector (7 downto 0);
wdata : in std_logic_vector (7 downto 0)
);
end component;
 
begin
 
addr_f000 : SYS09BUG_F000 port map (
clk => clk,
rst => rst,
cs => cs0,
rw => rw,
addr => addr(10 downto 0),
wdata => wdata,
rdata => rdata0
);
 
addr_f800 : SYS09BUG_F800 port map (
clk => clk,
rst => rst,
cs => cs1,
rw => rw,
addr => addr(10 downto 0),
wdata => wdata,
rdata => rdata1
);
 
my_mon : process ( rw, addr, cs, rdata0, rdata1 )
begin
we <= not rw;
case addr(11) is
when '0' =>
cs0 <= cs;
cs1 <= '0';
rdata <= rdata0;
when '1' =>
cs0 <= '0';
cs1 <= cs;
rdata <= rdata1;
when others =>
null;
end case;
end process;
 
end architecture rtl;
 
/trunk/rtl/Spartan2/sys09bug_b5x_rom2k_b4.vhd
0,0 → 1,218
--
-- sys09bug_rom2k_b4.vhd
--
-- SYS09BUG Monitor ROM for the B5-X300 6809
-- Using 4 x RAMB4_S8 in the XC2S300e
--
-- John Kent
-- 3rd February 2007
-- Has the same entity name as SBUG so
-- it can be easily exchanged.
--
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
library unisim;
use unisim.vcomponents.all;
 
entity mon_rom is
Port (
clk : in std_logic;
rst : in std_logic;
cs : in std_logic;
rw : in std_logic;
addr : in std_logic_vector (10 downto 0);
wdata : in std_logic_vector (7 downto 0);
rdata : out std_logic_vector (7 downto 0)
);
end mon_rom;
 
architecture rtl of mon_rom is
 
signal rdata0 : std_logic_vector (7 downto 0);
signal rdata1 : std_logic_vector (7 downto 0);
signal rdata2 : std_logic_vector (7 downto 0);
signal rdata3 : std_logic_vector (7 downto 0);
 
signal ena0 : std_logic;
signal ena1 : std_logic;
signal ena2 : std_logic;
signal ena3 : std_logic;
 
signal we : std_logic;
 
component RAMB4_S8
generic (
INIT_00, INIT_01, INIT_02, INIT_03,
INIT_04, INIT_05, INIT_06, INIT_07,
INIT_08, INIT_09, INIT_0A, INIT_0B,
INIT_0C, INIT_0D, INIT_0E, INIT_0F : bit_vector (255 downto 0)
);
 
port (
clk, we, en, rst : in std_logic;
addr : in std_logic_vector(8 downto 0);
di : in std_logic_vector(7 downto 0);
do : out std_logic_vector(7 downto 0)
);
end component RAMB4_S8;
 
begin
 
ROM0 : RAMB4_S8
generic map (
INIT_00 => x"A780A610C6C0DF8E106DFE8E2EFA1AFB1EFB8FFBCAFCB5FC97FC9DFC61F814F8",
INIT_01 => x"17431FE4A7D0866AAFDD8C30FB265AE26F0CC65B0117E0DFBF00E08EF9265AA0",
INIT_02 => x"03179FFE8E0C0417F62A5A19048B0327856D0DC64FD0DF8E4703177DFE8E9B04",
INIT_03 => x"17408B981F4F04175E86092C2081891FF1270D817F84330417B30217A6FE8E2E",
INIT_04 => x"20F00217A8FE8EF5266DFE8C02300F2780E137FE8E20C0022F60C14304174804",
INIT_05 => x"17A4A60B0417A50317211F650217AEFE8E121F2D296B03173B341FBC2094ADC0",
INIT_06 => x"27A4A1A4A7390F260D8117275E81DD271881E127088111285E0317030417A503",
INIT_07 => x"0B031705201F30C0DF8E321FA20217BE203F31C2202131E103173F86E4031708",
INIT_08 => x"279603170527E4AC011FF0C4201F0634F0C41000C3101F390124E1AC20340629",
INIT_09 => x"265A8A03172C031780A610C69203172E0317E4AEEE0117AEFE8E103439623203",
INIT_0a => x"29B70217BC20EE265A7303172E8602237E810425208180A610C6E1AE820317F5",
INIT_0b => x"3984A73F86A4AFA0A709273F8184A60F271035558DFFFF8E10341A24C0DF8C1E",
INIT_0c => x"4AAF0427268D1F304AAE431F39FB265A188D08C6E3DF8E104203163F86450317",
INIT_0d => x"A7A0A7A0A7FF8684A7A4A604263F8184A60A24C0DF8C21AEB9FE16480217068D",
INIT_0e => x"0186398D46E0B7E086408D393D3139F7265A0427A1ACA0A608C6E3DF8E1039A0",
INIT_0f => x"178D47E0B7208645E0B744E0B743E0B74F42E0B701862D8D47E0B7EF8641E0B7"
)
 
port map (
clk => clk,
en => ena0,
we => we,
rst => rst,
addr(8 downto 0) => addr(8 downto 0),
di(7 downto 0) => wdata,
do(7 downto 0) => rdata0
);
 
ROM1 : RAMB4_S8
generic map (
INIT_00 => x"E0B6F926808547E0B63B341F4AAF00C08EF42600C28C80A740E0B6218D00C08E",
INIT_01 => x"54545454A6E6D0DF8E104444444462A6363439F927088547E0B639F227408547",
INIT_02 => x"FCBD8435FD265A20C60434B63562E762EA62A70F8462A65858585853A6E6E4E7",
INIT_03 => x"0234A80117F12631813D2739811F0217F9265381260217E2DF7F6402171186DF",
INIT_04 => x"E0EB02340C2904358E01170434E46AE46AE4EBE0EBE0E6103421299101172629",
INIT_05 => x"0117E26F0E02161386E2DF731602173F86BA27FFC102355FEB2080A70527E46A",
INIT_06 => x"2320008310062762A3E4ECF501171286DFFCBDE4AF0130492562AC4D2930344A",
INIT_07 => x"1780A684EB63EB62EB68011762AE750117981F03CB2F0017EFFE8E64E720C602",
INIT_08 => x"10347120028D396532B301171486C326E4AC62AF5B0117981F53F526646A6501",
INIT_09 => x"8D618D394AAF0229F68DF28D910017E50016F800169D01169035690017A0FE8E",
INIT_0a => x"498D3944AF0229D58DD18D5E8D3946AF0229E08DDC8D728D3948AF0229EB8DE7",
INIT_0b => x"8D3941A70229B18DB08D588D3942A70229BC8DBB8D6C8D3943A70229C78DC68D",
INIT_0c => x"BF0016311FF48DB2FE8E39F726048180A63B011739C4A7808A0429A68DA58D5F",
INIT_0d => x"8DC4FE8EE12044AED78DCAFE8EB4001643A6E18DD0FE8EF42048AEEA8DBEFE8E",
INIT_0e => x"D02042A6B38DDBFE8ED92041A6BC8DD6FE8ECF204AAEC58DB8FE8ED82046AECE",
INIT_0f => x"AEFE8EBF8DB88DB08DA98DA18D27FF17AEFE8E900016E7FE8EC4A6AA8DE0FE8E"
)
 
port map (
clk => clk,
en => ena1,
we => we,
rst => rst,
addr(8 downto 0) => addr(8 downto 0),
di(7 downto 0) => wdata,
do(7 downto 0) => rdata1
);
 
ROM2 : RAMB4_S8
generic map (
INIT_00 => x"3C29088D011F42290E8DB400172D86121F4D29098DD520CE8DC78DC08D17FF17",
INIT_01 => x"811D253081578D39E0AB04342829078D891F484848483229118D903561A71034",
INIT_02 => x"3439021A39578003226681072561813937800322468112254181393080032239",
INIT_03 => x"C602344D20078B022F3981308B0F840235048D4444444402340235028D023510",
INIT_04 => x"BE10342D207F84048D0627E2DF7D8235F1265A3B8D3F8D2D860225E46880A608",
INIT_05 => x"B605260185E0DF9FA60234903501A6EE27018584A620E08E0926018584A6E0DF",
INIT_06 => x"BE138D903501A70235FA27028584A6E0DFBE1234458D2086008D8235018520E0",
INIT_07 => x"E703E702A7FBDFFD0000CC30E08E39E2DFB7FF86016D84A7118684A70386E0DF",
INIT_08 => x"810D20748D0427FEDF7D30E08E16345986028D1B86FEDF7F01E702C6FDDFFD04",
INIT_09 => x"8E0027101A816C0027101B814100271008819635C5001784A70520098D042420",
INIT_0a => x"5CFBDFFC51260A81110027100B812C0027100C81990027100D81450027101681",
INIT_0b => x"DFB66800164A3327FBDFB67400165A3C0027105DFBDFFC9900168300261019C1",
INIT_0c => x"54816E002710598116273DC1FEDFF65800160000CC5B00162500271050814CFB",
INIT_0d => x"ED224F812080FEDF7F39FDDFB70426FDDF7D39FEDF7F39FEDFB704263D813127",
INIT_0e => x"26508102A74C84E720C6FBDFB6168D0000CC1B20E12218C120C0FDDF7FFDDFF6",
INIT_0f => x"5AEA2619C15C4FF02650814CFBDFFC3903E702A7FBDFFDFCDFF64F39FEDF7FF7"
)
 
port map (
clk => clk,
en => ena2,
we => we,
rst => rst,
addr(8 downto 0) => addr(8 downto 0),
di(7 downto 0) => wdata,
do(7 downto 0) => rdata2
);
 
ROM3 : RAMB4_S8
generic map (
INIT_00 => x"FCDFF6F42650C15C84A702E7FBDFF72086FBDFF604E75F012519C15C04E6E78D",
INIT_01 => x"7FFB0369FB0274FB0139FEDFF702E7FBDFF75FE4205F03E7FCDFF7082719C15C",
INIT_02 => x"F84DBCFA505EFA4CA5F847FDF8455CF94248FB1953FB183DFB1531FB105EFB04",
INIT_03 => x"000A0DFFFFFFFF94F9A7F8A7F8A7F8A7F894F9D5F94488F958F1F853EDFB52A8",
INIT_04 => x"4B04202D2020303033582D354220524F4620342E312047554239305359530000",
INIT_05 => x"2020043D43502020043D5053202004202D20043F54414857043E040000000A0D",
INIT_06 => x"043D422020043D412020043D50442020043D58492020043D59492020043D5355",
INIT_07 => x"000000000000000000000000000004315343565A4E4948464504203A43432020",
INIT_08 => x"300B2784AC1084AF1084EEAA558E10A0D08E84A7F086FB264A80A70F86F0FF8E",
INIT_09 => x"2DA7D0DF8E10C0DFCE10FDFFB74444444443101F84EFD620ED26A0F08C00F089",
INIT_0a => x"1084AF10AA558E1084EE2227A0F08C00F08930FB2A4AA66F0C862FA7F0862E6F",
INIT_0b => x"2EA7D0DF8E10F186D520A5A70F88891F44444444101FD0DF8E1084EFE92684AC",
INIT_0c => x"8EF32D0C814C80E7A66F0427A6E6211F4F2CE7A66F1420F92A4A0526A6E60C86",
INIT_0d => x"9F6EC6DF9F6EC4DF9F6EC0DF9F6E62F816E2DFF753F9265A80A7A0A610C6F0FF",
INIT_0e => x"0822CEDFBC8B300F27FFFF8CCCDFBE49584F4AAF80E64AAE431FCADF9F6EC8DF",
INIT_0f => x"00FFB2FFC2FFBEFFBAFFB6FFC6FFB2FFC2DF9F6E42EE1F37F16E44AEC4EC1034"
)
 
port map (
clk => clk,
en => ena3,
we => we,
rst => rst,
addr(8 downto 0) => addr(8 downto 0),
di(7 downto 0) => wdata,
do(7 downto 0) => rdata3
);
 
my_sys09bug_b4 : process ( cs, rw, addr, rdata0, rdata1, rdata2, rdata3 )
begin
case addr(10 downto 9) is
when "00" =>
ena0 <= cs;
ena1 <= '0';
ena2 <= '0';
ena3 <= '0';
rdata <= rdata0;
when "01" =>
ena0 <= '0';
ena1 <= cs;
ena2 <= '0';
ena3 <= '0';
rdata <= rdata1;
when "10" =>
ena0 <= '0';
ena1 <= '0';
ena2 <= cs;
ena3 <= '0';
rdata <= rdata2;
when "11" =>
ena0 <= '0';
ena1 <= '0';
ena2 <= '0';
ena3 <= cs;
rdata <= rdata3;
when others =>
null;
end case;
 
we <= not rw;
 
end process;
 
end architecture rtl;
 
/trunk/rtl/Spartan2/sys09b5x.vhd
0,0 → 1,101
--
-- SYS09BUG Monitor Program
-- v1.0 - 21 November 2006 - John Knet
--
-- v1.1 - 22 december 2006 - John Kent
-- made into 4K ROM/RAM.
--
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
library unisim;
use unisim.vcomponents.all;
 
entity mon_rom is
Port (
clk : in std_logic;
rst : in std_logic;
cs : in std_logic;
rw : in std_logic;
addr : in std_logic_vector (11 downto 0);
rdata : out std_logic_vector (7 downto 0);
wdata : in std_logic_vector (7 downto 0)
);
end mon_rom;
 
architecture rtl of mon_rom is
 
signal we : std_logic;
signal cs0 : std_logic;
signal cs1 : std_logic;
signal dp0 : std_logic;
signal dp1 : std_logic;
signal rdata0 : std_logic_vector(7 downto 0);
signal rdata1 : std_logic_vector(7 downto 0);
 
component SYS09BUG_F000
Port (
clk : in std_logic;
rst : in std_logic;
cs : in std_logic;
rw : in std_logic;
addr : in std_logic_vector (10 downto 0);
rdata : out std_logic_vector (7 downto 0);
wdata : in std_logic_vector (7 downto 0)
);
end component;
 
component SYS09BUG_F800
Port (
clk : in std_logic;
rst : in std_logic;
cs : in std_logic;
rw : in std_logic;
addr : in std_logic_vector (10 downto 0);
rdata : out std_logic_vector (7 downto 0);
wdata : in std_logic_vector (7 downto 0)
);
end component;
 
begin
 
addr_f000 : SYS09BUG_F000 port map (
clk => clk,
rst => rst,
cs => cs0,
rw => rw,
addr => addr(10 downto 0),
wdata => wdata,
rdata => rdata0
);
 
addr_f800 : SYS09BUG_F800 port map (
clk => clk,
rst => rst,
cs => cs1,
rw => rw,
addr => addr(10 downto 0),
wdata => wdata,
rdata => rdata1
);
 
my_mon : process ( rw, addr, cs, rdata0, rdata1 )
begin
we <= not rw;
case addr(11) is
when '0' =>
cs0 <= cs;
cs1 <= '0';
rdata <= rdata0;
when '1' =>
cs0 <= '0';
cs1 <= cs;
rdata <= rdata1;
when others =>
null;
end case;
end process;
 
end architecture rtl;
 
/trunk/rtl/Spartan2/sys09b3s_b16.vhd
0,0 → 1,147
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
library unisim;
use unisim.vcomponents.all;
 
entity SYS09BUG_F800 is
port(
clk : in std_logic;
rst : in std_logic;
cs : in std_logic;
rw : in std_logic;
addr : in std_logic_vector(10 downto 0);
rdata : out std_logic_vector(7 downto 0);
wdata : in std_logic_vector(7 downto 0)
);
end SYS09BUG_F800;
 
architecture rtl of SYS09BUG_F800 is
 
type data_array is array(0 to 0) of std_logic_vector(7 downto 0);
signal xdata : data_array;
signal en : std_logic_vector(0 downto 0);
signal dp : std_logic_vector(0 downto 0);
signal we : std_logic;
 
component RAMB16_S9
generic (
INIT_00, INIT_01, INIT_02, INIT_03,
INIT_04, INIT_05, INIT_06, INIT_07,
INIT_08, INIT_09, INIT_0A, INIT_0B,
INIT_0C, INIT_0D, INIT_0E, INIT_0F,
INIT_10, INIT_11, INIT_12, INIT_13,
INIT_14, INIT_15, INIT_16, INIT_17,
INIT_18, INIT_19, INIT_1A, INIT_1B,
INIT_1C, INIT_1D, INIT_1E, INIT_1F,
INIT_20, INIT_21, INIT_22, INIT_23,
INIT_24, INIT_25, INIT_26, INIT_27,
INIT_28, INIT_29, INIT_2A, INIT_2B,
INIT_2C, INIT_2D, INIT_2E, INIT_2F,
INIT_30, INIT_31, INIT_32, INIT_33,
INIT_34, INIT_35, INIT_36, INIT_37,
INIT_38, INIT_39, INIT_3A, INIT_3B,
INIT_3C, INIT_3D, INIT_3E, INIT_3F : bit_vector (255 downto 0)
);
 
port (
clk : in std_logic;
ssr : in std_logic;
en : in std_logic;
we : in std_logic;
addr : in std_logic_vector(10 downto 0);
di : in std_logic_vector( 7 downto 0);
dip : in std_logic_vector( 0 downto 0);
do : out std_logic_vector( 7 downto 0);
dop : out std_logic_vector( 0 downto 0)
);
end component RAMB16_S9;
 
begin
 
ROM00: RAMB16_S9
generic map (
INIT_00 => x"A780A610C6C0DF8E106DFE8E2EFA1AFB1EFB8FFBDCFCC1FC97FC9DFC61F814F8",
INIT_01 => x"17431FE4A7D0866AAFDD8C30FB265AE26F0CC65B0117E0DFBF00E08EF9265AA0",
INIT_02 => x"03179EFE8E0C0417F62A5A19048B0327856D0DC64FD0DF8E4703177DFE8EB104",
INIT_03 => x"17408B981F6104175E86092C2081891FF1270D817F84330417B30217A5FE8E2E",
INIT_04 => x"20F00217A7FE8EF5266DFE8C02300F2780E137FE8E20C0022F60C15504175A04",
INIT_05 => x"17A4A61D0417A50317211F650217ADFE8E121F2D296B03173B341FBC2094ADC0",
INIT_06 => x"27A4A1A4A7390F260D8117275E81DD271881E127088111285E0317150417A503",
INIT_07 => x"0B031705201F30C0DF8E321FA20217BE203F31C2202131F303173F86F6031708",
INIT_08 => x"27A203170527E4AC011FF0C4201F0634F0C41000C3101F390124E1AC20340629",
INIT_09 => x"265A9C03172C031780A610C6A403172E0317E4AEEE0117ADFE8E103439623203",
INIT_0a => x"29B70217BC20EE265A8503172E8602237E810425208180A610C6E1AE940317F5",
INIT_0b => x"3984A73F86A4AFA0A709273F8184A60F271035558DFFFF8E10341A24C0DF8C1E",
INIT_0c => x"4AAF0427268D1F304AAE431F39FB265A188D08C6E3DF8E105403163F86570317",
INIT_0d => x"A7A0A7A0A7FF8684A7A4A604263F8184A60A24C0DF8C21AEB9FE16480217068D",
INIT_0e => x"E1FD0200CC1EE1FD0600CC393D3139F7265A0427A1ACA0A608C6E3DF8E1039A0",
INIT_0f => x"178D0EE1FD20C60AE1FD08E1FD06E1FD5F04E1FD0100CC2E8D0CE1FDE000CC1E",
INIT_10 => x"E1FCF92680C50EE1FC3B341F4AAF00C08EF42600C18C80E700E1FC218D00C08E",
INIT_11 => x"54545454A6E6D0DF8E104444444462A6363439F92708C50EE1FC39F22740C50E",
INIT_12 => x"FCBD8435FD265A20C60434B63562E762EA62A70F8462A65858585853A6E6E4E7",
INIT_13 => x"0234A80117F12631813D2739811F0217F9265381260217E2DF7F7602171186F5",
INIT_14 => x"E0EB02340C2904358E01170434E46AE46AE4EBE0EBE0E6103421299101172629",
INIT_15 => x"0117E26F2002161386E2DF732802173F86BA27FFC102355FEB2080A70527E46A",
INIT_16 => x"2320008310062762A3E4EC0702171286F5FCBDE4AF0130492562AC4D2930344A",
INIT_17 => x"1780A684EB63EB62EB68011762AE750117981F03CB2F0017EEFE8E64E720C602",
INIT_18 => x"10347120028D396532C501171486C326E4AC62AF5B0117981F53F526646A6501",
INIT_19 => x"8D618D394AAF0229F68DF28D910017E50016F80016AF011690356900179FFE8E",
INIT_1a => x"498D3944AF0229D58DD18D5E8D3946AF0229E08DDC8D728D3948AF0229EB8DE7",
INIT_1b => x"8D3941A70229B18DB08D588D3942A70229BC8DBB8D6C8D3943A70229C78DC68D",
INIT_1c => x"BF0016311FF48DB1FE8E39F726048180A64D011739C4A7808A0429A68DA58D5F",
INIT_1d => x"8DC3FE8EE12044AED78DC9FE8EB4001643A6E18DCFFE8EF42048AEEA8DBDFE8E",
INIT_1e => x"D02042A6B38DDAFE8ED92041A6BC8DD5FE8ECF204AAEC58DB7FE8ED82046AECE",
INIT_1f => x"ADFE8EBF8DB88DB08DA98DA18D27FF17ADFE8E900016E6FE8EC4A6AA8DDFFE8E",
INIT_20 => x"3C29088D011F42290E8DC600172D86121F4D29098DD520CE8DC78DC08D17FF17",
INIT_21 => x"811D253081578D39E0AB04342829078D891F484848483229118D903561A71034",
INIT_22 => x"3439021A39578003226681072561813937800322468112254181393080032239",
INIT_23 => x"C602345F20078B022F3981308B0F840235048D4444444402340235028D023510",
INIT_24 => x"8610343F207F84048D0627E2DF7D8235F1265A4D8D518D2D860225E46880A608",
INIT_25 => x"3501A6E0DF9FA75186EE27018584A620E08E0926018584A6E0DFBEE0DF9FA711",
INIT_26 => x"1234498D2086008D8235018520E0B605260185E0DF9FA6E0DF9FA71186023490",
INIT_27 => x"84A7518684A70386E0DFBE138D903501A70235F6260885FA27028584A6E0DFBE",
INIT_28 => x"DF7F01E702C6FDDFFD04E703E702A7FBDFFD0000CC30E08E39E2DFB7FF86016D",
INIT_29 => x"1784A70520098D042420810D20608D0427FEDF7D30E08E16345986028D1B86FE",
INIT_2a => x"24270C81890027100D81382716817C0027101A815A271B81342708819635AF00",
INIT_2b => x"27FBDFB66D205A34275DFBDFFC8F0016792619C15CFBDFFC45260A810F270B81",
INIT_2c => x"54816E27598114273DC1FEDFF656200000CC5820212750814CFBDFB662204A2C",
INIT_2d => x"ED224F812080FEDF7F39FDDFB70426FDDF7D39FEDF7F39FEDFB704263D813127",
INIT_2e => x"26508102A74C84E720C6FBDFB6168D0000CC1B20E12218C120C0FDDF7FFDDFF6",
INIT_2f => x"5AEA2619C15C4FF02650814CFBDFFC3903E702A7FBDFFDFCDFF64F39FEDF7FF7",
INIT_30 => x"FCDFF6F42650C15C84A702E7FBDFF72086FBDFF604E75F012519C15C04E6E78D",
INIT_31 => x"7FFB0369FB0274FB0139FEDFF702E7FBDFF75FE4205F03E7FCDFF7082719C15C",
INIT_32 => x"F84DBCFA505EFA4CA5F847FDF8455CF94248FB1953FB183DFB1531FB105EFB04",
INIT_33 => x"000A0DFFFFFFFF94F9A7F8A7F8A7F8A7F894F9D5F94488F958F1F853EDFB52A8",
INIT_34 => x"0D4B04202D20202B32532D334220524F4620362E312047554239305359530000",
INIT_35 => x"552020043D43502020043D5053202004202D20043F54414857043E040000000A",
INIT_36 => x"20043D422020043D412020043D50442020043D58492020043D59492020043D53",
INIT_37 => x"00000000000000000000000000000004315343565A4E4948464504203A434320",
INIT_38 => x"300B2784AC1084AF1084EEAA558E10A0D08E84A7F086FB264A80A70F86F0FF8E",
INIT_39 => x"2DA7D0DF8E10C0DFCE10FDFFB74444444443101F84EFD620ED26A0F08C00F089",
INIT_3a => x"1084AF10AA558E1084EE2227A0F08C00F08930FB2A4AA66F0C862FA7F0862E6F",
INIT_3b => x"2EA7D0DF8E10F186D520A5A70F88891F44444444101FD0DF8E1084EFE92684AC",
INIT_3c => x"8EF32D0C814C80E7A66F0427A6E6211F4F2CE7A66F1420F92A4A0526A6E60C86",
INIT_3d => x"9F6EC6DF9F6EC4DF9F6EC0DF9F6E62F816E2DFF753F9265A80A7A0A610C6F0FF",
INIT_3e => x"0822CEDFBC8B300F27FFFF8CCCDFBE49584F4AAF80E64AAE431FCADF9F6EC8DF",
INIT_3f => x"00FFB2FFC2FFBEFFBAFFB6FFC6FFB2FFC2DF9F6E42EE1F37F16E44AEC4EC1034"
)
port map (
clk => clk,
ssr => rst,
en => en(0),
we => we,
addr => addr(10 downto 0),
di => wdata,
dip(0) => dp(0),
do => xdata(0),
dop(0) => dp(0)
);
rom_glue: process (cs, rw, addr, xdata)
begin
en(0) <= cs;
rdata <= xdata(0);
we <= not rw;
end process;
end architecture rtl;
 
/trunk/rtl/Spartan2/sys09b5x_b16.vhd
0,0 → 1,147
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
library unisim;
use unisim.vcomponents.all;
 
entity SYS09BUG_F800 is
port(
clk : in std_logic;
rst : in std_logic;
cs : in std_logic;
rw : in std_logic;
addr : in std_logic_vector(10 downto 0);
rdata : out std_logic_vector(7 downto 0);
wdata : in std_logic_vector(7 downto 0)
);
end SYS09BUG_F800;
 
architecture rtl of SYS09BUG_F800 is
 
type data_array is array(0 to 0) of std_logic_vector(7 downto 0);
signal xdata : data_array;
signal en : std_logic_vector(0 downto 0);
signal dp : std_logic_vector(0 downto 0);
signal we : std_logic;
 
component RAMB16_S9
generic (
INIT_00, INIT_01, INIT_02, INIT_03,
INIT_04, INIT_05, INIT_06, INIT_07,
INIT_08, INIT_09, INIT_0A, INIT_0B,
INIT_0C, INIT_0D, INIT_0E, INIT_0F,
INIT_10, INIT_11, INIT_12, INIT_13,
INIT_14, INIT_15, INIT_16, INIT_17,
INIT_18, INIT_19, INIT_1A, INIT_1B,
INIT_1C, INIT_1D, INIT_1E, INIT_1F,
INIT_20, INIT_21, INIT_22, INIT_23,
INIT_24, INIT_25, INIT_26, INIT_27,
INIT_28, INIT_29, INIT_2A, INIT_2B,
INIT_2C, INIT_2D, INIT_2E, INIT_2F,
INIT_30, INIT_31, INIT_32, INIT_33,
INIT_34, INIT_35, INIT_36, INIT_37,
INIT_38, INIT_39, INIT_3A, INIT_3B,
INIT_3C, INIT_3D, INIT_3E, INIT_3F : bit_vector (255 downto 0)
);
 
port (
clk : in std_logic;
ssr : in std_logic;
en : in std_logic;
we : in std_logic;
addr : in std_logic_vector(10 downto 0);
di : in std_logic_vector( 7 downto 0);
dip : in std_logic_vector( 0 downto 0);
do : out std_logic_vector( 7 downto 0);
dop : out std_logic_vector( 0 downto 0)
);
end component RAMB16_S9;
 
begin
 
ROM00: RAMB16_S9
generic map (
INIT_00 => x"A780A610C6C0DF8E106DFE8E2EFA1AFB1EFB8FFBDCFCC1FC97FC9DFC61F814F8",
INIT_01 => x"17431FE4A7D0866AAFDD8C30FB265AE26F0CC65B0117E0DFBF00E08EF9265AA0",
INIT_02 => x"03179FFE8E0C0417F62A5A19048B0327856D0DC64FD0DF8E4703177DFE8EB104",
INIT_03 => x"17408B981F6104175E86092C2081891FF1270D817F84330417B30217A6FE8E2E",
INIT_04 => x"20F00217A8FE8EF5266DFE8C02300F2780E137FE8E20C0022F60C15504175A04",
INIT_05 => x"17A4A61D0417A50317211F650217AEFE8E121F2D296B03173B341FBC2094ADC0",
INIT_06 => x"27A4A1A4A7390F260D8117275E81DD271881E127088111285E0317150417A503",
INIT_07 => x"0B031705201F30C0DF8E321FA20217BE203F31C2202131F303173F86F6031708",
INIT_08 => x"27A203170527E4AC011FF0C4201F0634F0C41000C3101F390124E1AC20340629",
INIT_09 => x"265A9C03172C031780A610C6A403172E0317E4AEEE0117AEFE8E103439623203",
INIT_0a => x"29B70217BC20EE265A8503172E8602237E810425208180A610C6E1AE940317F5",
INIT_0b => x"3984A73F86A4AFA0A709273F8184A60F271035558DFFFF8E10341A24C0DF8C1E",
INIT_0c => x"4AAF0427268D1F304AAE431F39FB265A188D08C6E3DF8E105403163F86570317",
INIT_0d => x"A7A0A7A0A7FF8684A7A4A604263F8184A60A24C0DF8C21AEB9FE16480217068D",
INIT_0e => x"0186398D46E0B7E086408D393D3139F7265A0427A1ACA0A608C6E3DF8E1039A0",
INIT_0f => x"178D47E0B7208645E0B744E0B743E0B74F42E0B701862D8D47E0B7EF8641E0B7",
INIT_10 => x"E0B6F926808547E0B63B341F4AAF00C08EF42600C28C80A740E0B6218D00C08E",
INIT_11 => x"54545454A6E6D0DF8E104444444462A6363439F927088547E0B639F227408547",
INIT_12 => x"FCBD8435FD265A20C60434B63562E762EA62A70F8462A65858585853A6E6E4E7",
INIT_13 => x"0234A80117F12631813D2739811F0217F9265381260217E2DF7F7602171186F5",
INIT_14 => x"E0EB02340C2904358E01170434E46AE46AE4EBE0EBE0E6103421299101172629",
INIT_15 => x"0117E26F2002161386E2DF732802173F86BA27FFC102355FEB2080A70527E46A",
INIT_16 => x"2320008310062762A3E4EC0702171286F5FCBDE4AF0130492562AC4D2930344A",
INIT_17 => x"1780A684EB63EB62EB68011762AE750117981F03CB2F0017EFFE8E64E720C602",
INIT_18 => x"10347120028D396532C501171486C326E4AC62AF5B0117981F53F526646A6501",
INIT_19 => x"8D618D394AAF0229F68DF28D910017E50016F80016AF01169035690017A0FE8E",
INIT_1a => x"498D3944AF0229D58DD18D5E8D3946AF0229E08DDC8D728D3948AF0229EB8DE7",
INIT_1b => x"8D3941A70229B18DB08D588D3942A70229BC8DBB8D6C8D3943A70229C78DC68D",
INIT_1c => x"BF0016311FF48DB2FE8E39F726048180A64D011739C4A7808A0429A68DA58D5F",
INIT_1d => x"8DC4FE8EE12044AED78DCAFE8EB4001643A6E18DD0FE8EF42048AEEA8DBEFE8E",
INIT_1e => x"D02042A6B38DDBFE8ED92041A6BC8DD6FE8ECF204AAEC58DB8FE8ED82046AECE",
INIT_1f => x"AEFE8EBF8DB88DB08DA98DA18D27FF17AEFE8E900016E7FE8EC4A6AA8DE0FE8E",
INIT_20 => x"3C29088D011F42290E8DC600172D86121F4D29098DD520CE8DC78DC08D17FF17",
INIT_21 => x"811D253081578D39E0AB04342829078D891F484848483229118D903561A71034",
INIT_22 => x"3439021A39578003226681072561813937800322468112254181393080032239",
INIT_23 => x"C602345F20078B022F3981308B0F840235048D4444444402340235028D023510",
INIT_24 => x"8610343F207F84048D0627E2DF7D8235F1265A4D8D518D2D860225E46880A608",
INIT_25 => x"3501A6E0DF9FA75186EE27018584A620E08E0926018584A6E0DFBEE0DF9FA711",
INIT_26 => x"1234498D2086008D8235018520E0B605260185E0DF9FA6E0DF9FA71186023490",
INIT_27 => x"84A7518684A70386E0DFBE138D903501A70235F6260885FA27028584A6E0DFBE",
INIT_28 => x"DF7F01E702C6FDDFFD04E703E702A7FBDFFD0000CC30E08E39E2DFB7FF86016D",
INIT_29 => x"1784A70520098D042420810D20608D0427FEDF7D30E08E16345986028D1B86FE",
INIT_2a => x"24270C81890027100D81382716817C0027101A815A271B81342708819635AF00",
INIT_2b => x"27FBDFB66D205A34275DFBDFFC8F0016792619C15CFBDFFC45260A810F270B81",
INIT_2c => x"54816E27598114273DC1FEDFF656200000CC5820212750814CFBDFB662204A2C",
INIT_2d => x"ED224F812080FEDF7F39FDDFB70426FDDF7D39FEDF7F39FEDFB704263D813127",
INIT_2e => x"26508102A74C84E720C6FBDFB6168D0000CC1B20E12218C120C0FDDF7FFDDFF6",
INIT_2f => x"5AEA2619C15C4FF02650814CFBDFFC3903E702A7FBDFFDFCDFF64F39FEDF7FF7",
INIT_30 => x"FCDFF6F42650C15C84A702E7FBDFF72086FBDFF604E75F012519C15C04E6E78D",
INIT_31 => x"7FFB0369FB0274FB0139FEDFF702E7FBDFF75FE4205F03E7FCDFF7082719C15C",
INIT_32 => x"F84DBCFA505EFA4CA5F847FDF8455CF94248FB1953FB183DFB1531FB105EFB04",
INIT_33 => x"000A0DFFFFFFFF94F9A7F8A7F8A7F8A7F894F9D5F94488F958F1F853EDFB52A8",
INIT_34 => x"4B04202D2020303033582D354220524F4620362E312047554239305359530000",
INIT_35 => x"2020043D43502020043D5053202004202D20043F54414857043E040000000A0D",
INIT_36 => x"043D422020043D412020043D50442020043D58492020043D59492020043D5355",
INIT_37 => x"000000000000000000000000000004315343565A4E4948464504203A43432020",
INIT_38 => x"300B2784AC1084AF1084EEAA558E10A0D08E84A7F086FB264A80A70F86F0FF8E",
INIT_39 => x"2DA7D0DF8E10C0DFCE10FDFFB74444444443101F84EFD620ED26A0F08C00F089",
INIT_3a => x"1084AF10AA558E1084EE2227A0F08C00F08930FB2A4AA66F0C862FA7F0862E6F",
INIT_3b => x"2EA7D0DF8E10F186D520A5A70F88891F44444444101FD0DF8E1084EFE92684AC",
INIT_3c => x"8EF32D0C814C80E7A66F0427A6E6211F4F2CE7A66F1420F92A4A0526A6E60C86",
INIT_3d => x"9F6EC6DF9F6EC4DF9F6EC0DF9F6E62F816E2DFF753F9265A80A7A0A610C6F0FF",
INIT_3e => x"0822CEDFBC8B300F27FFFF8CCCDFBE49584F4AAF80E64AAE431FCADF9F6EC8DF",
INIT_3f => x"00FFB2FFC2FFBEFFBAFFB6FFC6FFB2FFC2DF9F6E42EE1F37F16E44AEC4EC1034"
)
port map (
clk => clk,
ssr => rst,
en => en(0),
we => we,
addr => addr(10 downto 0),
di => wdata,
dip(0) => dp(0),
do => xdata(0),
dop(0) => dp(0)
);
rom_glue: process (cs, rw, addr, xdata)
begin
en(0) <= cs;
rdata <= xdata(0);
we <= not rw;
end process;
end architecture rtl;
 
/trunk/rtl/Spartan2/sys09b3s_b4.vhd
0,0 → 1,238
--===========================================================================--
-- --
-- Sys09bug Monitor ROM using 4KBit Block RAMs found in the Spartan 2 --
-- --
--===========================================================================--
--
-- File name : Sys09b3s_b4.vhd
--
-- Entity name : SYS09BUG_F8000
--
-- Purpose : Sys09bug Monitor Program using 4KBit Block RAMs
-- For the System09 6809 compatible System on a Chip
-- Used on the BurchED B3 and B5-X300 Spartan 2 boards.
--
-- Dependencies : ieee.Std_Logic_1164
-- ieee.std_logic_arith
--
-- Author : John E. Kent
-- dilbert57@opencores.org
--
-- Memory Map : Sys09Bug monitor ROM assumes the following memory map
--
-- $0000 - $DFFF System RAM (256K Mapped via DAT)
-- $E000 - $E00F ACIA (SWTPc)
-- $E020 - $E02F Keyboard
-- $E030 - $E03F VDU
-- $E0A0 - $E0AF SPP Printer Port
-- $E100 - $E13F IDE / Compact Flash Card
-- $F800 - $FFFF Sys09bug ROM (Read only)
-- $FFF0 - $FFFF DAT - Dynamic Address Translation (Write Only)
--
-- Copyright (C) 2003 - 2010 John Kent
--
-- This program is free software: you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation, either version 3 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program. If not, see <http://www.gnu.org/licenses/>.
--
--===========================================================================----
--
-- Revision History:
--===========================================================================--
--
-- Version Date Author Comments
--
-- 0.1 2003-??-?? John Kent Initial Version
-- 0.2 2010-08-27 John Kent Added header
--
 
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
library unisim;
use unisim.vcomponents.all;
 
entity SYS09BUG_F800 is
port(
clk : in std_logic;
rst : in std_logic;
cs : in std_logic;
addr : in std_logic_vector(10 downto 0);
rw : in std_logic;
data_in : in std_logic_vector(7 downto 0);
data_out : out std_logic_vector(7 downto 0)
);
end SYS09BUG_F800;
 
architecture rtl of SYS09BUG_F800 is
 
type data_array is array(0 to 3) of std_logic_vector(7 downto 0);
signal xdata : data_array;
signal en : std_logic_vector(3 downto 0);
signal we : std_logic;
 
component RAMB4_S8
generic (
INIT_00, INIT_01, INIT_02, INIT_03,
INIT_04, INIT_05, INIT_06, INIT_07,
INIT_08, INIT_09, INIT_0A, INIT_0B,
INIT_0C, INIT_0D, INIT_0E, INIT_0F : bit_vector (255 downto 0)
);
port (
clk, we, en, rst : in std_logic;
addr : in std_logic_vector(8 downto 0);
di : in std_logic_vector(7 downto 0);
do : out std_logic_vector(7 downto 0)
);
end component RAMB4_S8;
 
begin
 
ROM00: RAMB4_S8
generic map (
INIT_00 => x"A780A610C6C0DF8E106DFE8E2EFA1AFB1EFB8FFBDCFCC1FC97FC9DFC61F814F8",
INIT_01 => x"17431FE4A7D0866AAFDD8C30FB265AE26F0CC65B0117E0DFBF00E08EF9265AA0",
INIT_02 => x"03179EFE8E0C0417F62A5A19048B0327856D0DC64FD0DF8E4703177DFE8EB104",
INIT_03 => x"17408B981F6104175E86092C2081891FF1270D817F84330417B30217A5FE8E2E",
INIT_04 => x"20F00217A7FE8EF5266DFE8C02300F2780E137FE8E20C0022F60C15504175A04",
INIT_05 => x"17A4A61D0417A50317211F650217ADFE8E121F2D296B03173B341FBC2094ADC0",
INIT_06 => x"27A4A1A4A7390F260D8117275E81DD271881E127088111285E0317150417A503",
INIT_07 => x"0B031705201F30C0DF8E321FA20217BE203F31C2202131F303173F86F6031708",
INIT_08 => x"27A203170527E4AC011FF0C4201F0634F0C41000C3101F390124E1AC20340629",
INIT_09 => x"265A9C03172C031780A610C6A403172E0317E4AEEE0117ADFE8E103439623203",
INIT_0a => x"29B70217BC20EE265A8503172E8602237E810425208180A610C6E1AE940317F5",
INIT_0b => x"3984A73F86A4AFA0A709273F8184A60F271035558DFFFF8E10341A24C0DF8C1E",
INIT_0c => x"4AAF0427268D1F304AAE431F39FB265A188D08C6E3DF8E105403163F86570317",
INIT_0d => x"A7A0A7A0A7FF8684A7A4A604263F8184A60A24C0DF8C21AEB9FE16480217068D",
INIT_0e => x"E1FD0200CC1EE1FD0600CC393D3139F7265A0427A1ACA0A608C6E3DF8E1039A0",
INIT_0f => x"178D0EE1FD20C60AE1FD08E1FD06E1FD5F04E1FD0100CC2E8D0CE1FDE000CC1E"
)
port map (
clk => clk,
en => en(0),
we => we,
rst => rst,
addr => addr(8 downto 0),
di => data_in,
do => xdata(0)
);
 
ROM01: RAMB4_S8
generic map (
INIT_00 => x"E1FCF92680C50EE1FC3B341F4AAF00C08EF42600C18C80E700E1FC218D00C08E",
INIT_01 => x"54545454A6E6D0DF8E104444444462A6363439F92708C50EE1FC39F22740C50E",
INIT_02 => x"FCBD8435FD265A20C60434B63562E762EA62A70F8462A65858585853A6E6E4E7",
INIT_03 => x"0234A80117F12631813D2739811F0217F9265381260217E2DF7F7602171186F5",
INIT_04 => x"E0EB02340C2904358E01170434E46AE46AE4EBE0EBE0E6103421299101172629",
INIT_05 => x"0117E26F2002161386E2DF732802173F86BA27FFC102355FEB2080A70527E46A",
INIT_06 => x"2320008310062762A3E4EC0702171286F5FCBDE4AF0130492562AC4D2930344A",
INIT_07 => x"1780A684EB63EB62EB68011762AE750117981F03CB2F0017EEFE8E64E720C602",
INIT_08 => x"10347120028D396532C501171486C326E4AC62AF5B0117981F53F526646A6501",
INIT_09 => x"8D618D394AAF0229F68DF28D910017E50016F80016AF011690356900179FFE8E",
INIT_0a => x"498D3944AF0229D58DD18D5E8D3946AF0229E08DDC8D728D3948AF0229EB8DE7",
INIT_0b => x"8D3941A70229B18DB08D588D3942A70229BC8DBB8D6C8D3943A70229C78DC68D",
INIT_0c => x"BF0016311FF48DB1FE8E39F726048180A64D011739C4A7808A0429A68DA58D5F",
INIT_0d => x"8DC3FE8EE12044AED78DC9FE8EB4001643A6E18DCFFE8EF42048AEEA8DBDFE8E",
INIT_0e => x"D02042A6B38DDAFE8ED92041A6BC8DD5FE8ECF204AAEC58DB7FE8ED82046AECE",
INIT_0f => x"ADFE8EBF8DB88DB08DA98DA18D27FF17ADFE8E900016E6FE8EC4A6AA8DDFFE8E"
)
port map (
clk => clk,
en => en(1),
we => we,
rst => rst,
addr => addr(8 downto 0),
di => data_in,
do => xdata(1)
);
 
ROM02: RAMB4_S8
generic map (
INIT_00 => x"3C29088D011F42290E8DC600172D86121F4D29098DD520CE8DC78DC08D17FF17",
INIT_01 => x"811D253081578D39E0AB04342829078D891F484848483229118D903561A71034",
INIT_02 => x"3439021A39578003226681072561813937800322468112254181393080032239",
INIT_03 => x"C602345F20078B022F3981308B0F840235048D4444444402340235028D023510",
INIT_04 => x"8610343F207F84048D0627E2DF7D8235F1265A4D8D518D2D860225E46880A608",
INIT_05 => x"3501A6E0DF9FA75186EE27018584A620E08E0926018584A6E0DFBEE0DF9FA711",
INIT_06 => x"1234498D2086008D8235018520E0B605260185E0DF9FA6E0DF9FA71186023490",
INIT_07 => x"84A7518684A70386E0DFBE138D903501A70235F6260885FA27028584A6E0DFBE",
INIT_08 => x"DF7F01E702C6FDDFFD04E703E702A7FBDFFD0000CC30E08E39E2DFB7FF86016D",
INIT_09 => x"1784A70520098D042420810D20608D0427FEDF7D30E08E16345986028D1B86FE",
INIT_0a => x"24270C81890027100D81382716817C0027101A815A271B81342708819635AF00",
INIT_0b => x"27FBDFB66D205A34275DFBDFFC8F0016792619C15CFBDFFC45260A810F270B81",
INIT_0c => x"54816E27598114273DC1FEDFF656200000CC5820212750814CFBDFB662204A2C",
INIT_0d => x"ED224F812080FEDF7F39FDDFB70426FDDF7D39FEDF7F39FEDFB704263D813127",
INIT_0e => x"26508102A74C84E720C6FBDFB6168D0000CC1B20E12218C120C0FDDF7FFDDFF6",
INIT_0f => x"5AEA2619C15C4FF02650814CFBDFFC3903E702A7FBDFFDFCDFF64F39FEDF7FF7"
)
port map (
clk => clk,
en => en(2),
we => we,
rst => rst,
addr => addr(8 downto 0),
di => data_in,
do => xdata(2)
);
 
ROM03: RAMB4_S8
generic map (
INIT_00 => x"FCDFF6F42650C15C84A702E7FBDFF72086FBDFF604E75F012519C15C04E6E78D",
INIT_01 => x"7FFB0369FB0274FB0139FEDFF702E7FBDFF75FE4205F03E7FCDFF7082719C15C",
INIT_02 => x"F84DBCFA505EFA4CA5F847FDF8455CF94248FB1953FB183DFB1531FB105EFB04",
INIT_03 => x"000A0DFFFFFFFF94F9A7F8A7F8A7F8A7F894F9D5F94488F958F1F853EDFB52A8",
INIT_04 => x"0D4B04202D20202B32532D334220524F4620362E312047554239305359530000",
INIT_05 => x"552020043D43502020043D5053202004202D20043F54414857043E040000000A",
INIT_06 => x"20043D422020043D412020043D50442020043D58492020043D59492020043D53",
INIT_07 => x"00000000000000000000000000000004315343565A4E4948464504203A434320",
INIT_08 => x"300B2784AC1084AF1084EEAA558E10A0D08E84A7F086FB264A80A70F86F0FF8E",
INIT_09 => x"2DA7D0DF8E10C0DFCE10FDFFB74444444443101F84EFD620ED26A0F08C00F089",
INIT_0a => x"1084AF10AA558E1084EE2227A0F08C00F08930FB2A4AA66F0C862FA7F0862E6F",
INIT_0b => x"2EA7D0DF8E10F186D520A5A70F88891F44444444101FD0DF8E1084EFE92684AC",
INIT_0c => x"8EF32D0C814C80E7A66F0427A6E6211F4F2CE7A66F1420F92A4A0526A6E60C86",
INIT_0d => x"9F6EC6DF9F6EC4DF9F6EC0DF9F6E62F816E2DFF753F9265A80A7A0A610C6F0FF",
INIT_0e => x"0822CEDFBC8B300F27FFFF8CCCDFBE49584F4AAF80E64AAE431FCADF9F6EC8DF",
INIT_0f => x"00FFB2FFC2FFBEFFBAFFB6FFC6FFB2FFC2DF9F6E42EE1F37F16E44AEC4EC1034"
)
port map (
clk => clk,
en => en(3),
we => we,
rst => rst,
addr => addr(8 downto 0),
di => data_in,
do => xdata(3)
);
 
rom_glue: process (cs, rw, addr, xdata)
begin
en <= (others=>'0');
case addr(10 downto 9) is
when "00" =>
en(0) <= cs;
data_out <= xdata(0);
when "01" =>
en(1) <= cs;
data_out <= xdata(1);
when "10" =>
en(2) <= cs;
data_out <= xdata(2);
when "11" =>
en(3) <= cs;
data_out <= xdata(3);
when others =>
null;
end case;
we <= not rw;
end process;
end architecture rtl;
 
/trunk/rtl/Spartan2/sys09bug_b3s_rom2k_b4.vhd
0,0 → 1,218
--
-- sys09b3s_rom2k_b4.vhd
--
-- SYS09BUG Monitor ROM for the B3-S2+ 6809
-- Using 4 x RAMB4_S8 in the XC2S200
--
-- John Kent
-- 3rd February 2007
-- Has the same entity name as SBUG so
-- it can be easily exchanged.
--
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
library unisim;
use unisim.vcomponents.all;
 
entity mon_rom is
Port (
clk : in std_logic;
rst : in std_logic;
cs : in std_logic;
rw : in std_logic;
addr : in std_logic_vector (10 downto 0);
wdata : in std_logic_vector (7 downto 0);
rdata : out std_logic_vector (7 downto 0)
);
end mon_rom;
 
architecture rtl of mon_rom is
 
signal rdata0 : std_logic_vector (7 downto 0);
signal rdata1 : std_logic_vector (7 downto 0);
signal rdata2 : std_logic_vector (7 downto 0);
signal rdata3 : std_logic_vector (7 downto 0);
 
signal ena0 : std_logic;
signal ena1 : std_logic;
signal ena2 : std_logic;
signal ena3 : std_logic;
 
signal we : std_logic;
 
component RAMB4_S8
generic (
INIT_00, INIT_01, INIT_02, INIT_03,
INIT_04, INIT_05, INIT_06, INIT_07,
INIT_08, INIT_09, INIT_0A, INIT_0B,
INIT_0C, INIT_0D, INIT_0E, INIT_0F : bit_vector (255 downto 0)
);
 
port (
clk, we, en, rst : in std_logic;
addr : in std_logic_vector(8 downto 0);
di : in std_logic_vector(7 downto 0);
do : out std_logic_vector(7 downto 0)
);
end component RAMB4_S8;
 
begin
 
ROM0 : RAMB4_S8
generic map (
INIT_00 => x"A780A610C6C0DF8E106DFE8E2EFA1AFB1EFB8FFBCAFCB5FC97FC9DFC61F814F8",
INIT_01 => x"17431FE4A7D0866AAFDD8C30FB265AE26F0CC65B0117E0DFBF00E08EF9265AA0",
INIT_02 => x"03179EFE8E0C0417F62A5A19048B0327856D0DC64FD0DF8E4703177DFE8E9B04",
INIT_03 => x"17408B981F4F04175E86092C2081891FF1270D817F84330417B30217A5FE8E2E",
INIT_04 => x"20F00217A7FE8EF5266DFE8C02300F2780E137FE8E20C0022F60C14304174804",
INIT_05 => x"17A4A60B0417A50317211F650217ADFE8E121F2D296B03173B341FBC2094ADC0",
INIT_06 => x"27A4A1A4A7390F260D8117275E81DD271881E127088111285E0317030417A503",
INIT_07 => x"0B031705201F30C0DF8E321FA20217BE203F31C2202131E103173F86E4031708",
INIT_08 => x"279603170527E4AC011FF0C4201F0634F0C41000C3101F390124E1AC20340629",
INIT_09 => x"265A8A03172C031780A610C69203172E0317E4AEEE0117ADFE8E103439623203",
INIT_0a => x"29B70217BC20EE265A7303172E8602237E810425208180A610C6E1AE820317F5",
INIT_0b => x"3984A73F86A4AFA0A709273F8184A60F271035558DFFFF8E10341A24C0DF8C1E",
INIT_0c => x"4AAF0427268D1F304AAE431F39FB265A188D08C6E3DF8E104203163F86450317",
INIT_0d => x"A7A0A7A0A7FF8684A7A4A604263F8184A60A24C0DF8C21AEB9FE16480217068D",
INIT_0e => x"E1FD0200CC1EE1FD0600CC393D3139F7265A0427A1ACA0A608C6E3DF8E1039A0",
INIT_0f => x"178D0EE1FD20C60AE1FD08E1FD06E1FD5F04E1FD0100CC2E8D0CE1FDE000CC1E"
)
 
port map (
clk => clk,
en => ena0,
we => we,
rst => rst,
addr(8 downto 0) => addr(8 downto 0),
di(7 downto 0) => wdata,
do(7 downto 0) => rdata0
);
 
ROM1 : RAMB4_S8
generic map (
INIT_00 => x"E1FCF92680C50EE1FC3B341F4AAF00C08EF42600C18C80E700E1FC218D00C08E",
INIT_01 => x"54545454A6E6D0DF8E104444444462A6363439F92708C50EE1FC39F22740C50E",
INIT_02 => x"FCBD8435FD265A20C60434B63562E762EA62A70F8462A65858585853A6E6E4E7",
INIT_03 => x"0234A80117F12631813D2739811F0217F9265381260217E2DF7F6402171186DF",
INIT_04 => x"E0EB02340C2904358E01170434E46AE46AE4EBE0EBE0E6103421299101172629",
INIT_05 => x"0117E26F0E02161386E2DF731602173F86BA27FFC102355FEB2080A70527E46A",
INIT_06 => x"2320008310062762A3E4ECF501171286DFFCBDE4AF0130492562AC4D2930344A",
INIT_07 => x"1780A684EB63EB62EB68011762AE750117981F03CB2F0017EEFE8E64E720C602",
INIT_08 => x"10347120028D396532B301171486C326E4AC62AF5B0117981F53F526646A6501",
INIT_09 => x"8D618D394AAF0229F68DF28D910017E50016F800169D011690356900179FFE8E",
INIT_0a => x"498D3944AF0229D58DD18D5E8D3946AF0229E08DDC8D728D3948AF0229EB8DE7",
INIT_0b => x"8D3941A70229B18DB08D588D3942A70229BC8DBB8D6C8D3943A70229C78DC68D",
INIT_0c => x"BF0016311FF48DB1FE8E39F726048180A63B011739C4A7808A0429A68DA58D5F",
INIT_0d => x"8DC3FE8EE12044AED78DC9FE8EB4001643A6E18DCFFE8EF42048AEEA8DBDFE8E",
INIT_0e => x"D02042A6B38DDAFE8ED92041A6BC8DD5FE8ECF204AAEC58DB7FE8ED82046AECE",
INIT_0f => x"ADFE8EBF8DB88DB08DA98DA18D27FF17ADFE8E900016E6FE8EC4A6AA8DDFFE8E"
)
 
port map (
clk => clk,
en => ena1,
we => we,
rst => rst,
addr(8 downto 0) => addr(8 downto 0),
di(7 downto 0) => wdata,
do(7 downto 0) => rdata1
);
 
ROM2 : RAMB4_S8
generic map (
INIT_00 => x"3C29088D011F42290E8DB400172D86121F4D29098DD520CE8DC78DC08D17FF17",
INIT_01 => x"811D253081578D39E0AB04342829078D891F484848483229118D903561A71034",
INIT_02 => x"3439021A39578003226681072561813937800322468112254181393080032239",
INIT_03 => x"C602344D20078B022F3981308B0F840235048D4444444402340235028D023510",
INIT_04 => x"BE10342D207F84048D0627E2DF7D8235F1265A3B8D3F8D2D860225E46880A608",
INIT_05 => x"B605260185E0DF9FA60234903501A6EE27018584A620E08E0926018584A6E0DF",
INIT_06 => x"BE138D903501A70235FA27028584A6E0DFBE1234458D2086008D8235018520E0",
INIT_07 => x"E703E702A7FBDFFD0000CC30E08E39E2DFB7FF86016D84A7118684A70386E0DF",
INIT_08 => x"810D20748D0427FEDF7D30E08E16345986028D1B86FEDF7F01E702C6FDDFFD04",
INIT_09 => x"8E0027101A816C0027101B814100271008819635C5001784A70520098D042420",
INIT_0a => x"5CFBDFFC51260A81110027100B812C0027100C81990027100D81450027101681",
INIT_0b => x"DFB66800164A3327FBDFB67400165A3C0027105DFBDFFC9900168300261019C1",
INIT_0c => x"54816E002710598116273DC1FEDFF65800160000CC5B00162500271050814CFB",
INIT_0d => x"ED224F812080FEDF7F39FDDFB70426FDDF7D39FEDF7F39FEDFB704263D813127",
INIT_0e => x"26508102A74C84E720C6FBDFB6168D0000CC1B20E12218C120C0FDDF7FFDDFF6",
INIT_0f => x"5AEA2619C15C4FF02650814CFBDFFC3903E702A7FBDFFDFCDFF64F39FEDF7FF7"
)
 
port map (
clk => clk,
en => ena2,
we => we,
rst => rst,
addr(8 downto 0) => addr(8 downto 0),
di(7 downto 0) => wdata,
do(7 downto 0) => rdata2
);
 
ROM3 : RAMB4_S8
generic map (
INIT_00 => x"FCDFF6F42650C15C84A702E7FBDFF72086FBDFF604E75F012519C15C04E6E78D",
INIT_01 => x"7FFB0369FB0274FB0139FEDFF702E7FBDFF75FE4205F03E7FCDFF7082719C15C",
INIT_02 => x"F84DBCFA505EFA4CA5F847FDF8455CF94248FB1953FB183DFB1531FB105EFB04",
INIT_03 => x"000A0DFFFFFFFF94F9A7F8A7F8A7F8A7F894F9D5F94488F958F1F853EDFB52A8",
INIT_04 => x"0D4B04202D20202B32532D334220524F4620342E312047554239305359530000",
INIT_05 => x"552020043D43502020043D5053202004202D20043F54414857043E040000000A",
INIT_06 => x"20043D422020043D412020043D50442020043D58492020043D59492020043D53",
INIT_07 => x"00000000000000000000000000000004315343565A4E4948464504203A434320",
INIT_08 => x"300B2784AC1084AF1084EEAA558E10A0D08E84A7F086FB264A80A70F86F0FF8E",
INIT_09 => x"2DA7D0DF8E10C0DFCE10FDFFB74444444443101F84EFD620ED26A0F08C00F089",
INIT_0a => x"1084AF10AA558E1084EE2227A0F08C00F08930FB2A4AA66F0C862FA7F0862E6F",
INIT_0b => x"2EA7D0DF8E10F186D520A5A70F88891F44444444101FD0DF8E1084EFE92684AC",
INIT_0c => x"8EF32D0C814C80E7A66F0427A6E6211F4F2CE7A66F1420F92A4A0526A6E60C86",
INIT_0d => x"9F6EC6DF9F6EC4DF9F6EC0DF9F6E62F816E2DFF753F9265A80A7A0A610C6F0FF",
INIT_0e => x"0822CEDFBC8B300F27FFFF8CCCDFBE49584F4AAF80E64AAE431FCADF9F6EC8DF",
INIT_0f => x"00FFB2FFC2FFBEFFBAFFB6FFC6FFB2FFC2DF9F6E42EE1F37F16E44AEC4EC1034"
)
 
port map (
clk => clk,
en => ena3,
we => we,
rst => rst,
addr(8 downto 0) => addr(8 downto 0),
di(7 downto 0) => wdata,
do(7 downto 0) => rdata3
);
 
my_sys09bug_b4 : process ( cs, rw, addr, rdata0, rdata1, rdata2, rdata3 )
begin
case addr(10 downto 9) is
when "00" =>
ena0 <= cs;
ena1 <= '0';
ena2 <= '0';
ena3 <= '0';
rdata <= rdata0;
when "01" =>
ena0 <= '0';
ena1 <= cs;
ena2 <= '0';
ena3 <= '0';
rdata <= rdata1;
when "10" =>
ena0 <= '0';
ena1 <= '0';
ena2 <= cs;
ena3 <= '0';
rdata <= rdata2;
when "11" =>
ena0 <= '0';
ena1 <= '0';
ena2 <= '0';
ena3 <= cs;
rdata <= rdata3;
when others =>
null;
end case;
 
we <= not rw;
 
end process;
 
end architecture rtl;
 
/trunk/rtl/Spartan2/sys09b5x_b4.vhd
0,0 → 1,238
--===========================================================================--
-- --
-- Sys09bug Monitor ROM using 4KBit Block RAMs found in the Spartan 2 --
-- --
--===========================================================================--
--
-- File name : Sys09b5x_b4.vhd
--
-- Entity name : SYS09BUG_F8000
--
-- Purpose : Sys09bug Monitor Program using 4KBit Block RAMs
-- For the System09 6809 compatible System on a Chip
-- Used on the BurchED B5-X300 Spartan 2 boards.
--
-- Dependencies : ieee.Std_Logic_1164
-- ieee.std_logic_arith
--
-- Author : John E. Kent
-- dilbert57@opencores.org
--
-- Memory Map : Sys09Bug monitor ROM assumes the following memory map
--
-- $0000 - $DFFF System RAM (256K Mapped via DAT)
-- $E000 - $E00F ACIA (SWTPc)
-- $E020 - $E02F Keyboard
-- $E030 - $E03F VDU
-- $E0A0 - $E0AF SPP Printer Port
-- $E100 - $E13F IDE / Compact Flash Card
-- $F800 - $FFFF Sys09bug ROM (Read only)
-- $FFF0 - $FFFF DAT - Dynamic Address Translation (Write Only)
--
-- Copyright (C) 2003 - 2010 John Kent
--
-- This program is free software: you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation, either version 3 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program. If not, see <http://www.gnu.org/licenses/>.
--
--===========================================================================----
--
-- Revision History:
--===========================================================================--
--
-- Version Date Author Comments
--
-- 0.1 2003-??-?? John Kent Initial Version
-- 0.2 2010-09-05 John Kent Added header
--
 
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
library unisim;
use unisim.vcomponents.all;
 
entity SYS09BUG_F800 is
port(
clk : in std_logic;
rst : in std_logic;
cs : in std_logic;
addr : in std_logic_vector(10 downto 0);
rw : in std_logic;
data_in : in std_logic_vector(7 downto 0);
data_out : out std_logic_vector(7 downto 0)
);
end SYS09BUG_F800;
 
architecture rtl of SYS09BUG_F800 is
 
type data_array is array(0 to 3) of std_logic_vector(7 downto 0);
signal xdata : data_array;
signal en : std_logic_vector(3 downto 0);
signal we : std_logic;
 
component RAMB4_S8
generic (
INIT_00, INIT_01, INIT_02, INIT_03,
INIT_04, INIT_05, INIT_06, INIT_07,
INIT_08, INIT_09, INIT_0A, INIT_0B,
INIT_0C, INIT_0D, INIT_0E, INIT_0F : bit_vector (255 downto 0)
);
port (
clk, we, en, rst : in std_logic;
addr : in std_logic_vector(8 downto 0);
di : in std_logic_vector(7 downto 0);
do : out std_logic_vector(7 downto 0)
);
end component RAMB4_S8;
 
begin
 
ROM00: RAMB4_S8
generic map (
INIT_00 => x"A780A610C6C0DF8E106DFE8E2EFA1AFB1EFB8FFBDCFCC1FC97FC9DFC61F814F8",
INIT_01 => x"17431FE4A7D0866AAFDD8C30FB265AE26F0CC65B0117E0DFBF00E08EF9265AA0",
INIT_02 => x"03179FFE8E0C0417F62A5A19048B0327856D0DC64FD0DF8E4703177DFE8EB104",
INIT_03 => x"17408B981F6104175E86092C2081891FF1270D817F84330417B30217A6FE8E2E",
INIT_04 => x"20F00217A8FE8EF5266DFE8C02300F2780E137FE8E20C0022F60C15504175A04",
INIT_05 => x"17A4A61D0417A50317211F650217AEFE8E121F2D296B03173B341FBC2094ADC0",
INIT_06 => x"27A4A1A4A7390F260D8117275E81DD271881E127088111285E0317150417A503",
INIT_07 => x"0B031705201F30C0DF8E321FA20217BE203F31C2202131F303173F86F6031708",
INIT_08 => x"27A203170527E4AC011FF0C4201F0634F0C41000C3101F390124E1AC20340629",
INIT_09 => x"265A9C03172C031780A610C6A403172E0317E4AEEE0117AEFE8E103439623203",
INIT_0a => x"29B70217BC20EE265A8503172E8602237E810425208180A610C6E1AE940317F5",
INIT_0b => x"3984A73F86A4AFA0A709273F8184A60F271035558DFFFF8E10341A24C0DF8C1E",
INIT_0c => x"4AAF0427268D1F304AAE431F39FB265A188D08C6E3DF8E105403163F86570317",
INIT_0d => x"A7A0A7A0A7FF8684A7A4A604263F8184A60A24C0DF8C21AEB9FE16480217068D",
INIT_0e => x"0186398D46E0B7E086408D393D3139F7265A0427A1ACA0A608C6E3DF8E1039A0",
INIT_0f => x"178D47E0B7208645E0B744E0B743E0B74F42E0B701862D8D47E0B7EF8641E0B7"
)
port map (
clk => clk,
en => en(0),
we => we,
rst => rst,
addr => addr(8 downto 0),
di => data_in,
do => xdata(0)
);
 
ROM01: RAMB4_S8
generic map (
INIT_00 => x"E0B6F926808547E0B63B341F4AAF00C08EF42600C28C80A740E0B6218D00C08E",
INIT_01 => x"54545454A6E6D0DF8E104444444462A6363439F927088547E0B639F227408547",
INIT_02 => x"FCBD8435FD265A20C60434B63562E762EA62A70F8462A65858585853A6E6E4E7",
INIT_03 => x"0234A80117F12631813D2739811F0217F9265381260217E2DF7F7602171186F5",
INIT_04 => x"E0EB02340C2904358E01170434E46AE46AE4EBE0EBE0E6103421299101172629",
INIT_05 => x"0117E26F2002161386E2DF732802173F86BA27FFC102355FEB2080A70527E46A",
INIT_06 => x"2320008310062762A3E4EC0702171286F5FCBDE4AF0130492562AC4D2930344A",
INIT_07 => x"1780A684EB63EB62EB68011762AE750117981F03CB2F0017EFFE8E64E720C602",
INIT_08 => x"10347120028D396532C501171486C326E4AC62AF5B0117981F53F526646A6501",
INIT_09 => x"8D618D394AAF0229F68DF28D910017E50016F80016AF01169035690017A0FE8E",
INIT_0a => x"498D3944AF0229D58DD18D5E8D3946AF0229E08DDC8D728D3948AF0229EB8DE7",
INIT_0b => x"8D3941A70229B18DB08D588D3942A70229BC8DBB8D6C8D3943A70229C78DC68D",
INIT_0c => x"BF0016311FF48DB2FE8E39F726048180A64D011739C4A7808A0429A68DA58D5F",
INIT_0d => x"8DC4FE8EE12044AED78DCAFE8EB4001643A6E18DD0FE8EF42048AEEA8DBEFE8E",
INIT_0e => x"D02042A6B38DDBFE8ED92041A6BC8DD6FE8ECF204AAEC58DB8FE8ED82046AECE",
INIT_0f => x"AEFE8EBF8DB88DB08DA98DA18D27FF17AEFE8E900016E7FE8EC4A6AA8DE0FE8E"
)
port map (
clk => clk,
en => en(1),
we => we,
rst => rst,
addr => addr(8 downto 0),
di => data_in,
do => xdata(1)
);
 
ROM02: RAMB4_S8
generic map (
INIT_00 => x"3C29088D011F42290E8DC600172D86121F4D29098DD520CE8DC78DC08D17FF17",
INIT_01 => x"811D253081578D39E0AB04342829078D891F484848483229118D903561A71034",
INIT_02 => x"3439021A39578003226681072561813937800322468112254181393080032239",
INIT_03 => x"C602345F20078B022F3981308B0F840235048D4444444402340235028D023510",
INIT_04 => x"8610343F207F84048D0627E2DF7D8235F1265A4D8D518D2D860225E46880A608",
INIT_05 => x"3501A6E0DF9FA75186EE27018584A620E08E0926018584A6E0DFBEE0DF9FA711",
INIT_06 => x"1234498D2086008D8235018520E0B605260185E0DF9FA6E0DF9FA71186023490",
INIT_07 => x"84A7518684A70386E0DFBE138D903501A70235F6260885FA27028584A6E0DFBE",
INIT_08 => x"DF7F01E702C6FDDFFD04E703E702A7FBDFFD0000CC30E08E39E2DFB7FF86016D",
INIT_09 => x"1784A70520098D042420810D20608D0427FEDF7D30E08E16345986028D1B86FE",
INIT_0a => x"24270C81890027100D81382716817C0027101A815A271B81342708819635AF00",
INIT_0b => x"27FBDFB66D205A34275DFBDFFC8F0016792619C15CFBDFFC45260A810F270B81",
INIT_0c => x"54816E27598114273DC1FEDFF656200000CC5820212750814CFBDFB662204A2C",
INIT_0d => x"ED224F812080FEDF7F39FDDFB70426FDDF7D39FEDF7F39FEDFB704263D813127",
INIT_0e => x"26508102A74C84E720C6FBDFB6168D0000CC1B20E12218C120C0FDDF7FFDDFF6",
INIT_0f => x"5AEA2619C15C4FF02650814CFBDFFC3903E702A7FBDFFDFCDFF64F39FEDF7FF7"
)
port map (
clk => clk,
en => en(2),
we => we,
rst => rst,
addr => addr(8 downto 0),
di => data_in,
do => xdata(2)
);
 
ROM03: RAMB4_S8
generic map (
INIT_00 => x"FCDFF6F42650C15C84A702E7FBDFF72086FBDFF604E75F012519C15C04E6E78D",
INIT_01 => x"7FFB0369FB0274FB0139FEDFF702E7FBDFF75FE4205F03E7FCDFF7082719C15C",
INIT_02 => x"F84DBCFA505EFA4CA5F847FDF8455CF94248FB1953FB183DFB1531FB105EFB04",
INIT_03 => x"000A0DFFFFFFFF94F9A7F8A7F8A7F8A7F894F9D5F94488F958F1F853EDFB52A8",
INIT_04 => x"4B04202D2020303033582D354220524F4620362E312047554239305359530000",
INIT_05 => x"2020043D43502020043D5053202004202D20043F54414857043E040000000A0D",
INIT_06 => x"043D422020043D412020043D50442020043D58492020043D59492020043D5355",
INIT_07 => x"000000000000000000000000000004315343565A4E4948464504203A43432020",
INIT_08 => x"300B2784AC1084AF1084EEAA558E10A0D08E84A7F086FB264A80A70F86F0FF8E",
INIT_09 => x"2DA7D0DF8E10C0DFCE10FDFFB74444444443101F84EFD620ED26A0F08C00F089",
INIT_0a => x"1084AF10AA558E1084EE2227A0F08C00F08930FB2A4AA66F0C862FA7F0862E6F",
INIT_0b => x"2EA7D0DF8E10F186D520A5A70F88891F44444444101FD0DF8E1084EFE92684AC",
INIT_0c => x"8EF32D0C814C80E7A66F0427A6E6211F4F2CE7A66F1420F92A4A0526A6E60C86",
INIT_0d => x"9F6EC6DF9F6EC4DF9F6EC0DF9F6E62F816E2DFF753F9265A80A7A0A610C6F0FF",
INIT_0e => x"0822CEDFBC8B300F27FFFF8CCCDFBE49584F4AAF80E64AAE431FCADF9F6EC8DF",
INIT_0f => x"00FFB2FFC2FFBEFFBAFFB6FFC6FFB2FFC2DF9F6E42EE1F37F16E44AEC4EC1034"
)
port map (
clk => clk,
en => en(3),
we => we,
rst => rst,
addr => addr(8 downto 0),
di => data_in,
do => xdata(3)
);
 
rom_glue: process (cs, rw, addr, xdata)
begin
en <= (others=>'0');
case addr(10 downto 9) is
when "00" =>
en(0) <= cs;
data_out <= xdata(0);
when "01" =>
en(1) <= cs;
data_out <= xdata(1);
when "10" =>
en(2) <= cs;
data_out <= xdata(2);
when "11" =>
en(3) <= cs;
data_out <= xdata(3);
when others =>
null;
end case;
we <= not rw;
end process;
end architecture rtl;
 
/trunk/rtl/System09_Terasic_DE1/system09.qsf File deleted \ No newline at end of file
/trunk/rtl/System09_Terasic_DE1/wrappers.vhd.bak File deleted
/trunk/rtl/System09_Terasic_DE1/xv2bin.cpp File deleted
/trunk/rtl/System09_Terasic_DE1/readme.txt File deleted
/trunk/rtl/System09_Terasic_DE1/system09.qws File deleted
/trunk/rtl/System09_Terasic_DE1/wrappers.vhd File deleted
/trunk/rtl/System09_Terasic_DE1/pace.vhd File deleted
/trunk/rtl/System09_Terasic_DE1/platform_pkg.vhd File deleted
/trunk/rtl/System09_Terasic_DE1/db/system09.sld_design_entry.sci Cannot display: file marked as a binary type. svn:mime-type = application/octet-stream
/trunk/rtl/System09_Terasic_DE1/db/system09.sld_design_entry.sci
trunk/rtl/System09_Terasic_DE1/db/system09.sld_design_entry.sci Property changes : Deleted: svn:mime-type ## -1 +0,0 ## -application/octet-stream \ No newline at end of property Index: trunk/rtl/System09_Terasic_DE1/db/system09.eco.cdb =================================================================== Cannot display: file marked as a binary type. svn:mime-type = application/octet-stream Index: trunk/rtl/System09_Terasic_DE1/db/system09.eco.cdb =================================================================== --- trunk/rtl/System09_Terasic_DE1/db/system09.eco.cdb (revision 115) +++ trunk/rtl/System09_Terasic_DE1/db/system09.eco.cdb (nonexistent)
trunk/rtl/System09_Terasic_DE1/db/system09.eco.cdb Property changes : Deleted: svn:mime-type ## -1 +0,0 ## -application/octet-stream \ No newline at end of property Index: trunk/rtl/System09_Terasic_DE1/db/system09.db_info =================================================================== --- trunk/rtl/System09_Terasic_DE1/db/system09.db_info (revision 115) +++ trunk/rtl/System09_Terasic_DE1/db/system09.db_info (nonexistent) @@ -1,3 +0,0 @@ -Quartus_Version = Version 9.0 Build 235 06/17/2009 Service Pack 2 SJ Full Version -Version_Index = 167832322 -Creation_Time = Wed Mar 10 17:10:05 2010 Index: trunk/rtl/System09_Terasic_DE1/system09_assignment_defaults.qdf =================================================================== --- trunk/rtl/System09_Terasic_DE1/system09_assignment_defaults.qdf (revision 115) +++ trunk/rtl/System09_Terasic_DE1/system09_assignment_defaults.qdf (nonexistent) @@ -1,642 +0,0 @@ -# -------------------------------------------------------------------------- # -# -# Copyright (C) 1991-2009 Altera Corporation -# Your use of Altera Corporation's design tools, logic functions -# and other software and tools, and its AMPP partner logic -# functions, and any output files from any of the foregoing -# (including device programming or simulation files), and any -# associated documentation or information are expressly subject -# to the terms and conditions of the Altera Program License -# Subscription Agreement, Altera MegaCore Function License -# Agreement, or other applicable license agreement, including, -# without limitation, that your use is for the sole purpose of -# programming logic devices manufactured by Altera and sold by -# Altera or its authorized distributors. Please refer to the -# applicable agreement for further details. -# -# -------------------------------------------------------------------------- # -# -# Quartus II -# Version 9.0 Build 235 06/17/2009 Service Pack 2 SJ Full Version -# Date created = 17:10:05 March 10, 2010 -# -# -------------------------------------------------------------------------- # -# -# Note: -# -# 1) Do not modify this file. This file was generated -# automatically by the Quartus II software and is used -# to preserve global assignments across Quartus II versions. -# -# -------------------------------------------------------------------------- # - -set_global_assignment -name PROJECT_SHOW_ENTITY_NAME On -set_global_assignment -name PROJECT_USE_SIMPLIFIED_NAMES Off -set_global_assignment -name ENABLE_REDUCED_MEMORY_MODE Off -set_global_assignment -name VER_COMPATIBLE_DB_DIR export_db -set_global_assignment -name AUTO_EXPORT_VER_COMPATIBLE_DB Off -set_global_assignment -name SMART_RECOMPILE Off -set_global_assignment -name FLOW_DISABLE_ASSEMBLER Off -set_global_assignment -name FLOW_ENABLE_HC_COMPARE Off -set_global_assignment -name HC_OUTPUT_DIR hc_output -set_global_assignment -name SAVE_MIGRATION_INFO_DURING_COMPILATION Off -set_global_assignment -name FLOW_ENABLE_IO_ASSIGNMENT_ANALYSIS Off -set_global_assignment -name RUN_FULL_COMPILE_ON_DEVICE_CHANGE On -set_global_assignment -name FLOW_ENABLE_RTL_VIEWER Off -set_global_assignment -name READ_OR_WRITE_IN_BYTE_ADDRESS "Use global settings" -set_global_assignment -name FLOW_HARDCOPY_DESIGN_READINESS_CHECK On -set_global_assignment -name DEFAULT_HOLD_MULTICYCLE "Same as Multicycle" -set_global_assignment -name CUT_OFF_PATHS_BETWEEN_CLOCK_DOMAINS On -set_global_assignment -name CUT_OFF_READ_DURING_WRITE_PATHS On -set_global_assignment -name CUT_OFF_IO_PIN_FEEDBACK On -set_global_assignment -name DO_COMBINED_ANALYSIS Off -set_global_assignment -name IGNORE_CLOCK_SETTINGS Off -set_global_assignment -name ANALYZE_LATCHES_AS_SYNCHRONOUS_ELEMENTS On -set_global_assignment -name ENABLE_RECOVERY_REMOVAL_ANALYSIS Off -set_global_assignment -name ENABLE_CLOCK_LATENCY Off -set_global_assignment -name USE_TIMEQUEST_TIMING_ANALYZER Off -family ACEX1K -set_global_assignment -name USE_TIMEQUEST_TIMING_ANALYZER Off -family MAX7000B -set_global_assignment -name USE_TIMEQUEST_TIMING_ANALYZER Off -family "HardCopy II" -set_global_assignment -name USE_TIMEQUEST_TIMING_ANALYZER Off -family FLEX10KA -set_global_assignment -name USE_TIMEQUEST_TIMING_ANALYZER On -family "Stratix IV" -set_global_assignment -name USE_TIMEQUEST_TIMING_ANALYZER On -family "Cyclone III" -set_global_assignment -name USE_TIMEQUEST_TIMING_ANALYZER Off -family "HardCopy Stratix" -set_global_assignment -name USE_TIMEQUEST_TIMING_ANALYZER Off -family APEX20KE -set_global_assignment -name USE_TIMEQUEST_TIMING_ANALYZER Off -family MAX7000AE -set_global_assignment -name USE_TIMEQUEST_TIMING_ANALYZER Off -family Cyclone -set_global_assignment -name USE_TIMEQUEST_TIMING_ANALYZER Off -family "Stratix II GX" -set_global_assignment -name USE_TIMEQUEST_TIMING_ANALYZER Off -family FLEX10K -set_global_assignment -name USE_TIMEQUEST_TIMING_ANALYZER Off -family "MAX II" -set_global_assignment -name USE_TIMEQUEST_TIMING_ANALYZER Off -family APEX20KC -set_global_assignment -name USE_TIMEQUEST_TIMING_ANALYZER On -family "Arria II GX" -set_global_assignment -name USE_TIMEQUEST_TIMING_ANALYZER Off -family "Stratix GX" -set_global_assignment -name USE_TIMEQUEST_TIMING_ANALYZER On -family "HardCopy III" -set_global_assignment -name USE_TIMEQUEST_TIMING_ANALYZER Off -family MAX7000S -set_global_assignment -name USE_TIMEQUEST_TIMING_ANALYZER Off -family FLEX6000 -set_global_assignment -name USE_TIMEQUEST_TIMING_ANALYZER Off -family "APEX II" -set_global_assignment -name USE_TIMEQUEST_TIMING_ANALYZER Off -family FLEX10KE -set_global_assignment -name USE_TIMEQUEST_TIMING_ANALYZER Off -family "Cyclone II" -set_global_assignment -name USE_TIMEQUEST_TIMING_ANALYZER On -family "HardCopy IV" -set_global_assignment -name USE_TIMEQUEST_TIMING_ANALYZER On -family "Cyclone III LS" -set_global_assignment -name USE_TIMEQUEST_TIMING_ANALYZER On -family "Stratix III" -set_global_assignment -name USE_TIMEQUEST_TIMING_ANALYZER On -family "Arria GX" -set_global_assignment -name USE_TIMEQUEST_TIMING_ANALYZER Off -family MAX3000A -set_global_assignment -name USE_TIMEQUEST_TIMING_ANALYZER Off -family "Stratix II" -set_global_assignment -name USE_TIMEQUEST_TIMING_ANALYZER Off -family Stratix -set_global_assignment -name NUMBER_OF_SOURCES_PER_DESTINATION_TO_REPORT 10 -set_global_assignment -name NUMBER_OF_DESTINATION_TO_REPORT 10 -set_global_assignment -name NUMBER_OF_PATHS_TO_REPORT 200 -set_global_assignment -name DO_MIN_ANALYSIS Off -set_global_assignment -name DO_MIN_TIMING Off -set_global_assignment -name REPORT_IO_PATHS_SEPARATELY Off -set_global_assignment -name FLOW_ENABLE_TIMING_CONSTRAINT_CHECK Off -set_global_assignment -name TIMEQUEST_MULTICORNER_ANALYSIS Off -family ACEX1K -set_global_assignment -name TIMEQUEST_MULTICORNER_ANALYSIS Off -family MAX7000B -set_global_assignment -name TIMEQUEST_MULTICORNER_ANALYSIS On -family "HardCopy II" -set_global_assignment -name TIMEQUEST_MULTICORNER_ANALYSIS Off -family FLEX10KA -set_global_assignment -name TIMEQUEST_MULTICORNER_ANALYSIS On -family "Stratix IV" -set_global_assignment -name TIMEQUEST_MULTICORNER_ANALYSIS On -family "Cyclone III" -set_global_assignment -name TIMEQUEST_MULTICORNER_ANALYSIS Off -family "HardCopy Stratix" -set_global_assignment -name TIMEQUEST_MULTICORNER_ANALYSIS Off -family APEX20KE -set_global_assignment -name TIMEQUEST_MULTICORNER_ANALYSIS Off -family MAX7000AE -set_global_assignment -name TIMEQUEST_MULTICORNER_ANALYSIS Off -family Cyclone -set_global_assignment -name TIMEQUEST_MULTICORNER_ANALYSIS On -family "Stratix II GX" -set_global_assignment -name TIMEQUEST_MULTICORNER_ANALYSIS Off -family FLEX10K -set_global_assignment -name TIMEQUEST_MULTICORNER_ANALYSIS Off -family "MAX II" -set_global_assignment -name TIMEQUEST_MULTICORNER_ANALYSIS Off -family APEX20KC -set_global_assignment -name TIMEQUEST_MULTICORNER_ANALYSIS On -family "Arria II GX" -set_global_assignment -name TIMEQUEST_MULTICORNER_ANALYSIS Off -family "Stratix GX" -set_global_assignment -name TIMEQUEST_MULTICORNER_ANALYSIS On -family "HardCopy III" -set_global_assignment -name TIMEQUEST_MULTICORNER_ANALYSIS Off -family MAX7000S -set_global_assignment -name TIMEQUEST_MULTICORNER_ANALYSIS Off -family FLEX6000 -set_global_assignment -name TIMEQUEST_MULTICORNER_ANALYSIS Off -family "APEX II" -set_global_assignment -name TIMEQUEST_MULTICORNER_ANALYSIS Off -family FLEX10KE -set_global_assignment -name TIMEQUEST_MULTICORNER_ANALYSIS On -family "Cyclone II" -set_global_assignment -name TIMEQUEST_MULTICORNER_ANALYSIS On -family "HardCopy IV" -set_global_assignment -name TIMEQUEST_MULTICORNER_ANALYSIS On -family "Cyclone III LS" -set_global_assignment -name TIMEQUEST_MULTICORNER_ANALYSIS On -family "Stratix III" -set_global_assignment -name TIMEQUEST_MULTICORNER_ANALYSIS On -family "Arria GX" -set_global_assignment -name TIMEQUEST_MULTICORNER_ANALYSIS Off -family MAX3000A -set_global_assignment -name TIMEQUEST_MULTICORNER_ANALYSIS On -family "Stratix II" -set_global_assignment -name TIMEQUEST_MULTICORNER_ANALYSIS Off -family Stratix -set_global_assignment -name TIMEQUEST_DO_REPORT_TIMING Off -set_global_assignment -name TIMEQUEST_DO_CCPP_REMOVAL Off -family ACEX1K -set_global_assignment -name TIMEQUEST_DO_CCPP_REMOVAL Off -family MAX7000B -set_global_assignment -name TIMEQUEST_DO_CCPP_REMOVAL Off -family "HardCopy II" -set_global_assignment -name TIMEQUEST_DO_CCPP_REMOVAL Off -family FLEX10KA -set_global_assignment -name TIMEQUEST_DO_CCPP_REMOVAL On -family "Stratix IV" -set_global_assignment -name TIMEQUEST_DO_CCPP_REMOVAL On -family "Cyclone III" -set_global_assignment -name TIMEQUEST_DO_CCPP_REMOVAL Off -family "HardCopy Stratix" -set_global_assignment -name TIMEQUEST_DO_CCPP_REMOVAL Off -family APEX20KE -set_global_assignment -name TIMEQUEST_DO_CCPP_REMOVAL Off -family MAX7000AE -set_global_assignment -name TIMEQUEST_DO_CCPP_REMOVAL Off -family Cyclone -set_global_assignment -name TIMEQUEST_DO_CCPP_REMOVAL Off -family "Stratix II GX" -set_global_assignment -name TIMEQUEST_DO_CCPP_REMOVAL Off -family FLEX10K -set_global_assignment -name TIMEQUEST_DO_CCPP_REMOVAL Off -family "MAX II" -set_global_assignment -name TIMEQUEST_DO_CCPP_REMOVAL Off -family APEX20KC -set_global_assignment -name TIMEQUEST_DO_CCPP_REMOVAL On -family "Arria II GX" -set_global_assignment -name TIMEQUEST_DO_CCPP_REMOVAL Off -family "Stratix GX" -set_global_assignment -name TIMEQUEST_DO_CCPP_REMOVAL On -family "HardCopy III" -set_global_assignment -name TIMEQUEST_DO_CCPP_REMOVAL Off -family MAX7000S -set_global_assignment -name TIMEQUEST_DO_CCPP_REMOVAL Off -family FLEX6000 -set_global_assignment -name TIMEQUEST_DO_CCPP_REMOVAL Off -family "APEX II" -set_global_assignment -name TIMEQUEST_DO_CCPP_REMOVAL Off -family FLEX10KE -set_global_assignment -name TIMEQUEST_DO_CCPP_REMOVAL Off -family "Cyclone II" -set_global_assignment -name TIMEQUEST_DO_CCPP_REMOVAL On -family "HardCopy IV" -set_global_assignment -name TIMEQUEST_DO_CCPP_REMOVAL On -family "Cyclone III LS" -set_global_assignment -name TIMEQUEST_DO_CCPP_REMOVAL On -family "Stratix III" -set_global_assignment -name TIMEQUEST_DO_CCPP_REMOVAL Off -family "Arria GX" -set_global_assignment -name TIMEQUEST_DO_CCPP_REMOVAL Off -family MAX3000A -set_global_assignment -name TIMEQUEST_DO_CCPP_REMOVAL Off -family "Stratix II" -set_global_assignment -name TIMEQUEST_DO_CCPP_REMOVAL Off -family Stratix -set_global_assignment -name MUX_RESTRUCTURE Auto -set_global_assignment -name ENABLE_IP_DEBUG Off -set_global_assignment -name SAVE_DISK_SPACE On -set_global_assignment -name DISABLE_OCP_HW_EVAL Off -set_global_assignment -name DEVICE_FILTER_PACKAGE Any -set_global_assignment -name DEVICE_FILTER_PIN_COUNT Any -set_global_assignment -name DEVICE_FILTER_SPEED_GRADE Any -set_global_assignment -name EDA_DESIGN_ENTRY_SYNTHESIS_TOOL "" -set_global_assignment -name VERILOG_INPUT_VERSION Verilog_2001 -set_global_assignment -name VHDL_INPUT_VERSION VHDL93 -set_global_assignment -name FAMILY "Stratix II" -set_global_assignment -name TRUE_WYSIWYG_FLOW Off -set_global_assignment -name SMART_COMPILE_IGNORES_TDC_FOR_STRATIX_PLL_CHANGES Off -set_global_assignment -name STATE_MACHINE_PROCESSING Auto -set_global_assignment -name SAFE_STATE_MACHINE Off -set_global_assignment -name EXTRACT_VERILOG_STATE_MACHINES On -set_global_assignment -name EXTRACT_VHDL_STATE_MACHINES On -set_global_assignment -name IGNORE_VERILOG_INITIAL_CONSTRUCTS Off -set_global_assignment -name VERILOG_CONSTANT_LOOP_LIMIT 5000 -set_global_assignment -name VERILOG_NON_CONSTANT_LOOP_LIMIT 250 -set_global_assignment -name ADD_PASS_THROUGH_LOGIC_TO_INFERRED_RAMS On -set_global_assignment -name PARALLEL_SYNTHESIS Off -set_global_assignment -name DSP_BLOCK_BALANCING Auto -set_global_assignment -name MAX_BALANCING_DSP_BLOCKS "-1 (Unlimited)" -set_global_assignment -name NOT_GATE_PUSH_BACK On -set_global_assignment -name ALLOW_POWER_UP_DONT_CARE On -set_global_assignment -name REMOVE_REDUNDANT_LOGIC_CELLS Off -set_global_assignment -name REMOVE_DUPLICATE_REGISTERS On -set_global_assignment -name IGNORE_CARRY_BUFFERS Off -set_global_assignment -name IGNORE_CASCADE_BUFFERS Off -set_global_assignment -name IGNORE_GLOBAL_BUFFERS Off -set_global_assignment -name IGNORE_ROW_GLOBAL_BUFFERS Off -set_global_assignment -name IGNORE_LCELL_BUFFERS Off -set_global_assignment -name MAX7000_IGNORE_LCELL_BUFFERS AUTO -set_global_assignment -name IGNORE_SOFT_BUFFERS On -set_global_assignment -name MAX7000_IGNORE_SOFT_BUFFERS Off -set_global_assignment -name LIMIT_AHDL_INTEGERS_TO_32_BITS Off -set_global_assignment -name AUTO_GLOBAL_CLOCK_MAX On -set_global_assignment -name AUTO_GLOBAL_OE_MAX On -set_global_assignment -name MAX_AUTO_GLOBAL_REGISTER_CONTROLS On -set_global_assignment -name AUTO_IMPLEMENT_IN_ROM Off -set_global_assignment -name APEX20K_TECHNOLOGY_MAPPER Lut -set_global_assignment -name OPTIMIZATION_TECHNIQUE Balanced -set_global_assignment -name STRATIXII_OPTIMIZATION_TECHNIQUE Balanced -set_global_assignment -name CYCLONE_OPTIMIZATION_TECHNIQUE Balanced -set_global_assignment -name CYCLONEII_OPTIMIZATION_TECHNIQUE Balanced -set_global_assignment -name STRATIX_OPTIMIZATION_TECHNIQUE Balanced -set_global_assignment -name MAXII_OPTIMIZATION_TECHNIQUE Balanced -set_global_assignment -name MAX7000_OPTIMIZATION_TECHNIQUE Speed -set_global_assignment -name APEX20K_OPTIMIZATION_TECHNIQUE Balanced -set_global_assignment -name MERCURY_OPTIMIZATION_TECHNIQUE Area -set_global_assignment -name FLEX6K_OPTIMIZATION_TECHNIQUE Area -set_global_assignment -name FLEX10K_OPTIMIZATION_TECHNIQUE Area -set_global_assignment -name ALLOW_XOR_GATE_USAGE On -set_global_assignment -name AUTO_LCELL_INSERTION On -set_global_assignment -name CARRY_CHAIN_LENGTH 48 -set_global_assignment -name FLEX6K_CARRY_CHAIN_LENGTH 32 -set_global_assignment -name FLEX10K_CARRY_CHAIN_LENGTH 32 -set_global_assignment -name MERCURY_CARRY_CHAIN_LENGTH 48 -set_global_assignment -name STRATIX_CARRY_CHAIN_LENGTH 70 -set_global_assignment -name STRATIXII_CARRY_CHAIN_LENGTH 70 -set_global_assignment -name CASCADE_CHAIN_LENGTH 2 -set_global_assignment -name PARALLEL_EXPANDER_CHAIN_LENGTH 16 -set_global_assignment -name MAX7000_PARALLEL_EXPANDER_CHAIN_LENGTH 4 -set_global_assignment -name AUTO_CARRY_CHAINS On -set_global_assignment -name AUTO_CASCADE_CHAINS On -set_global_assignment -name AUTO_PARALLEL_EXPANDERS On -set_global_assignment -name AUTO_OPEN_DRAIN_PINS On -set_global_assignment -name ADV_NETLIST_OPT_SYNTH_WYSIWYG_REMAP Off -set_global_assignment -name AUTO_ROM_RECOGNITION On -set_global_assignment -name AUTO_RAM_RECOGNITION On -set_global_assignment -name AUTO_DSP_RECOGNITION On -set_global_assignment -name AUTO_SHIFT_REGISTER_RECOGNITION Auto -set_global_assignment -name AUTO_CLOCK_ENABLE_RECOGNITION On -set_global_assignment -name STRICT_RAM_RECOGNITION Off -set_global_assignment -name ALLOW_SYNCH_CTRL_USAGE On -set_global_assignment -name FORCE_SYNCH_CLEAR Off -set_global_assignment -name AUTO_RAM_BLOCK_BALANCING On -set_global_assignment -name AUTO_RAM_TO_LCELL_CONVERSION Off -set_global_assignment -name AUTO_RESOURCE_SHARING Off -set_global_assignment -name ALLOW_ANY_RAM_SIZE_FOR_RECOGNITION Off -set_global_assignment -name ALLOW_ANY_ROM_SIZE_FOR_RECOGNITION Off -set_global_assignment -name ALLOW_ANY_SHIFT_REGISTER_SIZE_FOR_RECOGNITION Off -set_global_assignment -name MAX7000_FANIN_PER_CELL 100 -set_global_assignment -name USE_LOGICLOCK_CONSTRAINTS_IN_BALANCING On -set_global_assignment -name MAX_RAM_BLOCKS_M512 "-1 (Unlimited)" -set_global_assignment -name MAX_RAM_BLOCKS_M4K "-1 (Unlimited)" -set_global_assignment -name MAX_RAM_BLOCKS_MRAM "-1 (Unlimited)" -set_global_assignment -name IGNORE_TRANSLATE_OFF_AND_SYNTHESIS_OFF Off -set_global_assignment -name STRATIXGX_BYPASS_REMAPPING_OF_FORCE_SIGNAL_DETECT_SIGNAL_THRESHOLD_SELECT Off -set_global_assignment -name SYNTH_TIMING_DRIVEN_SYNTHESIS Off -set_global_assignment -name SHOW_PARAMETER_SETTINGS_TABLES_IN_SYNTHESIS_REPORT On -set_global_assignment -name IGNORE_MAX_FANOUT_ASSIGNMENTS Off -set_global_assignment -name SYNCHRONIZATION_REGISTER_CHAIN_LENGTH 2 -set_global_assignment -name OPTIMIZE_POWER_DURING_SYNTHESIS "Normal compilation" -set_global_assignment -name HDL_MESSAGE_LEVEL Level2 -set_global_assignment -name USE_HIGH_SPEED_ADDER Auto -set_global_assignment -name NUMBER_OF_REMOVED_REGISTERS_REPORTED 100 -set_global_assignment -name NUMBER_OF_INVERTED_REGISTERS_REPORTED 100 -set_global_assignment -name SYNTH_CLOCK_MUX_PROTECTION On -set_global_assignment -name SYNTH_GATED_CLOCK_CONVERSION Off -set_global_assignment -name BLOCK_DESIGN_NAMING Auto -set_global_assignment -name SYNTH_PROTECT_SDC_CONSTRAINT Off -set_global_assignment -name SYNTHESIS_EFFORT Auto -set_global_assignment -name SHIFT_REGISTER_RECOGNITION_ACLR_SIGNAL On -set_global_assignment -name PRE_MAPPING_RESYNTHESIS Off -set_global_assignment -name SYNTH_MESSAGE_LEVEL Medium -set_global_assignment -name ROUTER_TIMING_OPTIMIZATION_LEVEL Normal -set_global_assignment -name PLACEMENT_EFFORT_MULTIPLIER 1.0 -set_global_assignment -name ROUTER_EFFORT_MULTIPLIER 1.0 -set_global_assignment -name FIT_ATTEMPTS_TO_SKIP 0.0 -set_global_assignment -name ECO_ALLOW_ROUTING_CHANGES Off -set_global_assignment -name DEVICE AUTO -set_global_assignment -name BASE_PIN_OUT_FILE_ON_SAMEFRAME_DEVICE Off -set_global_assignment -name ENABLE_JTAG_BST_SUPPORT Off -set_global_assignment -name MAX7000_ENABLE_JTAG_BST_SUPPORT On -set_global_assignment -name RESERVE_NCEO_AFTER_CONFIGURATION "Use as regular IO" -set_global_assignment -name CYCLONEII_RESERVE_NCEO_AFTER_CONFIGURATION "Use as programming pin" -set_global_assignment -name STRATIXIII_UPDATE_MODE Standard -set_global_assignment -name STRATIX_UPDATE_MODE Standard -set_global_assignment -name STRATIXIII_CONFIGURATION_SCHEME "Passive Serial" -set_global_assignment -name CYCLONEIII_CONFIGURATION_SCHEME "Active Serial" -set_global_assignment -name STRATIXII_CONFIGURATION_SCHEME "Passive Serial" -set_global_assignment -name CYCLONEII_CONFIGURATION_SCHEME "Active Serial" -set_global_assignment -name APEX20K_CONFIGURATION_SCHEME "Passive Serial" -set_global_assignment -name STRATIX_CONFIGURATION_SCHEME "Passive Serial" -set_global_assignment -name CYCLONE_CONFIGURATION_SCHEME "Active Serial" -set_global_assignment -name MERCURY_CONFIGURATION_SCHEME "Passive Serial" -set_global_assignment -name FLEX6K_CONFIGURATION_SCHEME "Passive Serial" -set_global_assignment -name FLEX10K_CONFIGURATION_SCHEME "Passive Serial" -set_global_assignment -name APEXII_CONFIGURATION_SCHEME "Passive Serial" -set_global_assignment -name USER_START_UP_CLOCK Off -set_global_assignment -name ENABLE_VREFA_PIN Off -set_global_assignment -name ENABLE_VREFB_PIN Off -set_global_assignment -name ALWAYS_ENABLE_INPUT_BUFFERS Off -set_global_assignment -name ENABLE_ASMI_FOR_FLASH_LOADER Off -set_global_assignment -name ENABLE_DEVICE_WIDE_RESET Off -set_global_assignment -name ENABLE_DEVICE_WIDE_OE Off -set_global_assignment -name RESERVE_ALL_UNUSED_PINS "As output driving ground" -set_global_assignment -name FLEX10K_ENABLE_LOCK_OUTPUT Off -set_global_assignment -name ENABLE_INIT_DONE_OUTPUT Off -set_global_assignment -name RESERVE_NWS_NRS_NCS_CS_AFTER_CONFIGURATION "Use as regular IO" -set_global_assignment -name RESERVE_RDYNBUSY_AFTER_CONFIGURATION "Use as regular IO" -set_global_assignment -name RESERVE_DATA7_THROUGH_DATA1_AFTER_CONFIGURATION "Use as regular IO" -set_global_assignment -name RESERVE_DATA0_AFTER_CONFIGURATION "As input tri-stated" -set_global_assignment -name RESERVE_ASDO_AFTER_CONFIGURATION "Use as regular IO" -set_global_assignment -name RESERVE_DATA1_AFTER_CONFIGURATION "As input tri-stated" -set_global_assignment -name RESERVE_DATA7_THROUGH_DATA2_AFTER_CONFIGURATION "Use as regular IO" -set_global_assignment -name RESERVE_FLASH_NCE_AFTER_CONFIGURATION "As input tri-stated" -set_global_assignment -name RESERVE_OTHER_AP_PINS_AFTER_CONFIGURATION "Use as regular IO" -set_global_assignment -name RESERVE_DCLK_AFTER_CONFIGURATION "Use as programming pin" -set_global_assignment -name CRC_ERROR_CHECKING Off -set_global_assignment -name OPTIMIZE_HOLD_TIMING "IO Paths and Minimum TPD Paths" -family "Stratix GX" -set_global_assignment -name OPTIMIZE_HOLD_TIMING -value "ALL PATHS" -family "HardCopy III" -set_global_assignment -name OPTIMIZE_HOLD_TIMING "IO Paths and Minimum TPD Paths" -family "Cyclone II" -set_global_assignment -name OPTIMIZE_HOLD_TIMING "IO Paths and Minimum TPD Paths" -family "HardCopy II" -set_global_assignment -name OPTIMIZE_HOLD_TIMING -value "ALL PATHS" -family "Stratix IV" -set_global_assignment -name OPTIMIZE_HOLD_TIMING -value "ALL PATHS" -family "HardCopy IV" -set_global_assignment -name OPTIMIZE_HOLD_TIMING -value "ALL PATHS" -family "Cyclone III LS" -set_global_assignment -name OPTIMIZE_HOLD_TIMING -value "ALL PATHS" -family "Cyclone III" -set_global_assignment -name OPTIMIZE_HOLD_TIMING -value "ALL PATHS" -family "Stratix III" -set_global_assignment -name OPTIMIZE_HOLD_TIMING "IO Paths and Minimum TPD Paths" -family "HardCopy Stratix" -set_global_assignment -name OPTIMIZE_HOLD_TIMING -value "ALL PATHS" -family "Arria GX" -set_global_assignment -name OPTIMIZE_HOLD_TIMING "IO Paths and Minimum TPD Paths" -family "Stratix II GX" -set_global_assignment -name OPTIMIZE_HOLD_TIMING "IO Paths and Minimum TPD Paths" -family Cyclone -set_global_assignment -name OPTIMIZE_HOLD_TIMING "IO Paths and Minimum TPD Paths" -family "Stratix II" -set_global_assignment -name OPTIMIZE_HOLD_TIMING "IO Paths and Minimum TPD Paths" -family "MAX II" -set_global_assignment -name OPTIMIZE_HOLD_TIMING "IO Paths and Minimum TPD Paths" -family Stratix -set_global_assignment -name OPTIMIZE_HOLD_TIMING -value "ALL PATHS" -family "Arria II GX" -set_global_assignment -name OPTIMIZE_MULTI_CORNER_TIMING Off -set_global_assignment -name BLOCK_RAM_TO_MLAB_CELL_CONVERSION On -set_global_assignment -name BLOCK_RAM_AND_MLAB_EQUIVALENT_POWER_UP_CONDITIONS Auto -set_global_assignment -name BLOCK_RAM_AND_MLAB_EQUIVALENT_PAUSED_READ_CAPABILITIES Care -set_global_assignment -name PROGRAMMABLE_POWER_TECHNOLOGY_SETTING "Force All Tiles with Failing Timing Paths to High Speed" -set_global_assignment -name PROGRAMMABLE_POWER_MAXIMUM_HIGH_SPEED_FRACTION_OF_USED_LAB_TILES 1.0 -set_global_assignment -name GUARANTEE_MIN_DELAY_CORNER_IO_ZERO_HOLD_TIME On -set_global_assignment -name OPTIMIZE_POWER_DURING_FITTING "Normal compilation" -set_global_assignment -name OPTIMIZE_SSN Off -family "Cyclone III LS" -set_global_assignment -name OPTIMIZE_SSN Off -family "Cyclone III" -set_global_assignment -name OPTIMIZE_SSN Off -family "Stratix III" -set_global_assignment -name OPTIMIZE_SSN Off -family "HardCopy III" -set_global_assignment -name OPTIMIZE_SSN Off -family "HardCopy IV" -set_global_assignment -name OPTIMIZE_TIMING "Normal compilation" -set_global_assignment -name ECO_OPTIMIZE_TIMING Off -set_global_assignment -name ECO_REGENERATE_REPORT Off -set_global_assignment -name OPTIMIZE_IOC_REGISTER_PLACEMENT_FOR_TIMING On -set_global_assignment -name FIT_ONLY_ONE_ATTEMPT Off -set_global_assignment -name FINAL_PLACEMENT_OPTIMIZATION Automatically -set_global_assignment -name FITTER_AGGRESSIVE_ROUTABILITY_OPTIMIZATION Automatically -set_global_assignment -name SEED 1 -set_global_assignment -name SLOW_SLEW_RATE Off -set_global_assignment -name PCI_IO Off -set_global_assignment -name TURBO_BIT On -set_global_assignment -name WEAK_PULL_UP_RESISTOR Off -set_global_assignment -name ENABLE_BUS_HOLD_CIRCUITRY Off -set_global_assignment -name AUTO_GLOBAL_MEMORY_CONTROLS Off -set_global_assignment -name MIGRATION_CONSTRAIN_CORE_RESOURCES On -set_global_assignment -name AUTO_PACKED_REGISTERS_STRATIXII AUTO -set_global_assignment -name AUTO_PACKED_REGISTERS_MAXII AUTO -set_global_assignment -name AUTO_PACKED_REGISTERS_CYCLONE Auto -set_global_assignment -name AUTO_PACKED_REGISTERS Off -set_global_assignment -name AUTO_PACKED_REGISTERS_STRATIX AUTO -set_global_assignment -name NORMAL_LCELL_INSERT On -set_global_assignment -name CARRY_OUT_PINS_LCELL_INSERT On -set_global_assignment -name AUTO_DELAY_CHAINS On -set_global_assignment -name XSTL_INPUT_ALLOW_SE_BUFFER Off -set_global_assignment -name TREAT_BIDIR_AS_OUTPUT Off -set_global_assignment -name AUTO_MERGE_PLLS On -set_global_assignment -name IGNORE_MODE_FOR_MERGE Off -set_global_assignment -name AUTO_TURBO_BIT ON -set_global_assignment -name PHYSICAL_SYNTHESIS_COMBO_LOGIC_FOR_AREA Off -set_global_assignment -name PHYSICAL_SYNTHESIS_COMBO_LOGIC Off -set_global_assignment -name PHYSICAL_SYNTHESIS_LOG_FILE Off -set_global_assignment -name PHYSICAL_SYNTHESIS_REGISTER_DUPLICATION Off -set_global_assignment -name PHYSICAL_SYNTHESIS_MAP_LOGIC_TO_MEMORY_FOR_AREA Off -set_global_assignment -name PHYSICAL_SYNTHESIS_REGISTER_RETIMING Off -set_global_assignment -name PHYSICAL_SYNTHESIS_ASYNCHRONOUS_SIGNAL_PIPELINING Off -set_global_assignment -name IO_PLACEMENT_OPTIMIZATION On -set_global_assignment -name ALLOW_LVTTL_LVCMOS_INPUT_LEVELS_TO_OVERDRIVE_INPUT_BUFFER Off -set_global_assignment -name OVERRIDE_DEFAULT_ELECTROMIGRATION_PARAMETERS Off -set_global_assignment -name FITTER_EFFORT "Auto Fit" -set_global_assignment -name FITTER_AUTO_EFFORT_DESIRED_SLACK_MARGIN 0ns -set_global_assignment -name PHYSICAL_SYNTHESIS_EFFORT Normal -set_global_assignment -name ROUTER_LCELL_INSERTION_AND_LOGIC_DUPLICATION AUTO -set_global_assignment -name ROUTER_REGISTER_DUPLICATION AUTO -set_global_assignment -name STRATIXGX_ALLOW_CLOCK_FANOUT_WITH_ANALOG_RESET Off -set_global_assignment -name AUTO_GLOBAL_CLOCK On -set_global_assignment -name AUTO_GLOBAL_OE On -set_global_assignment -name AUTO_GLOBAL_REGISTER_CONTROLS On -set_global_assignment -name FITTER_EARLY_TIMING_ESTIMATE_MODE Realistic -set_global_assignment -name STRATIXGX_ALLOW_GIGE_UNDER_FULL_DATARATE_RANGE Off -set_global_assignment -name STRATIXGX_ALLOW_RX_CORECLK_FROM_NON_RX_CLKOUT_SOURCE_IN_DOUBLE_DATA_WIDTH_MODE Off -set_global_assignment -name STRATIXGX_ALLOW_GIGE_IN_DOUBLE_DATA_WIDTH_MODE Off -set_global_assignment -name STRATIXGX_ALLOW_PARALLEL_LOOPBACK_IN_DOUBLE_DATA_WIDTH_MODE Off -set_global_assignment -name STRATIXGX_ALLOW_XAUI_IN_SINGLE_DATA_WIDTH_MODE Off -set_global_assignment -name STRATIXGX_ALLOW_XAUI_WITH_CORECLK_SELECTED_AT_RATE_MATCHER Off -set_global_assignment -name STRATIXGX_ALLOW_XAUI_WITH_RX_CORECLK_FROM_NON_TXPLL_SOURCE Off -set_global_assignment -name STRATIXGX_ALLOW_GIGE_WITH_CORECLK_SELECTED_AT_RATE_MATCHER Off -set_global_assignment -name STRATIXGX_ALLOW_GIGE_WITHOUT_8B10B Off -set_global_assignment -name STRATIXGX_ALLOW_GIGE_WITH_RX_CORECLK_FROM_NON_TXPLL_SOURCE Off -set_global_assignment -name STRATIXGX_ALLOW_POST8B10B_LOOPBACK Off -set_global_assignment -name STRATIXGX_ALLOW_REVERSE_PARALLEL_LOOPBACK Off -set_global_assignment -name STRATIXGX_ALLOW_USE_OF_GXB_COUPLED_IOS Off -set_global_assignment -name GENERATE_GXB_RECONFIG_MIF Off -set_global_assignment -name GENERATE_GXB_RECONFIG_MIF_WITH_PLL Off -set_global_assignment -name RESERVE_ALL_UNUSED_PINS_WEAK_PULLUP "As input tri-stated with weak pull-up" -set_global_assignment -name STOP_AFTER_CONGESTION_MAP Off -set_global_assignment -name SAVE_INTERMEDIATE_FITTING_RESULTS Off -set_global_assignment -name ENABLE_HOLD_BACK_OFF On -set_global_assignment -name CONFIGURATION_VCCIO_LEVEL Auto -set_global_assignment -name FORCE_CONFIGURATION_VCCIO Off -set_global_assignment -name SYNCHRONIZER_IDENTIFICATION Off -set_global_assignment -name ENABLE_BENEFICIAL_SKEW_OPTIMIZATION -value OFF -set_global_assignment -name OPTIMIZE_FOR_METASTABILITY On -set_global_assignment -name CRC_ERROR_OPEN_DRAIN Off -set_global_assignment -name MAX_GLOBAL_CLOCKS_ALLOWED "-1 (Unlimited)" -set_global_assignment -name MAX_REGIONAL_CLOCKS_ALLOWED "-1 (Unlimited)" -set_global_assignment -name MAX_PERIPHERY_CLOCKS_ALLOWED "-1 (Unlimited)" -set_global_assignment -name MAX_CLOCKS_ALLOWED "-1 (Unlimited)" -set_global_assignment -name ACTIVE_SERIAL_CLOCK FREQ_40MHz -set_global_assignment -name STRATIXIII_MRAM_COMPATIBILITY On -set_global_assignment -name FORCE_FITTER_TO_AVOID_PERIPHERY_PLACEMENT_WARNINGS Off -set_global_assignment -name EDA_SIMULATION_TOOL "" -set_global_assignment -name EDA_TIMING_ANALYSIS_TOOL "" -set_global_assignment -name EDA_BOARD_DESIGN_TIMING_TOOL "" -set_global_assignment -name EDA_BOARD_DESIGN_SYMBOL_TOOL "" -set_global_assignment -name EDA_BOARD_DESIGN_SIGNAL_INTEGRITY_TOOL "" -set_global_assignment -name EDA_BOARD_DESIGN_BOUNDARY_SCAN_TOOL "" -set_global_assignment -name EDA_BOARD_DESIGN_TOOL "" -set_global_assignment -name EDA_FORMAL_VERIFICATION_TOOL "" -set_global_assignment -name EDA_RESYNTHESIS_TOOL "" -set_global_assignment -name ON_CHIP_BITSTREAM_DECOMPRESSION On -set_global_assignment -name COMPRESSION_MODE Off -set_global_assignment -name CLOCK_SOURCE Internal -set_global_assignment -name CONFIGURATION_CLOCK_FREQUENCY "10 MHz" -set_global_assignment -name CONFIGURATION_CLOCK_DIVISOR 1 -set_global_assignment -name ENABLE_LOW_VOLTAGE_MODE_ON_CONFIG_DEVICE On -set_global_assignment -name FLEX6K_ENABLE_LOW_VOLTAGE_MODE_ON_CONFIG_DEVICE Off -set_global_assignment -name FLEX10K_ENABLE_LOW_VOLTAGE_MODE_ON_CONFIG_DEVICE On -set_global_assignment -name MAX7000S_JTAG_USER_CODE FFFF -set_global_assignment -name STRATIX_JTAG_USER_CODE FFFFFFFF -set_global_assignment -name APEX20K_JTAG_USER_CODE FFFFFFFF -set_global_assignment -name MERCURY_JTAG_USER_CODE FFFFFFFF -set_global_assignment -name FLEX10K_JTAG_USER_CODE 7F -set_global_assignment -name MAX7000_JTAG_USER_CODE FFFFFFFF -set_global_assignment -name MAX7000_USE_CHECKSUM_AS_USERCODE Off -set_global_assignment -name USE_CHECKSUM_AS_USERCODE Off -set_global_assignment -name SECURITY_BIT Off -set_global_assignment -name USE_CONFIGURATION_DEVICE On -family ACEX1K -set_global_assignment -name USE_CONFIGURATION_DEVICE On -family MAX7000B -set_global_assignment -name USE_CONFIGURATION_DEVICE On -family "HardCopy II" -set_global_assignment -name USE_CONFIGURATION_DEVICE On -family FLEX10KA -set_global_assignment -name USE_CONFIGURATION_DEVICE Off -family "Stratix IV" -set_global_assignment -name USE_CONFIGURATION_DEVICE Off -family "Cyclone III" -set_global_assignment -name USE_CONFIGURATION_DEVICE On -family "HardCopy Stratix" -set_global_assignment -name USE_CONFIGURATION_DEVICE On -family APEX20KE -set_global_assignment -name USE_CONFIGURATION_DEVICE On -family MAX7000AE -set_global_assignment -name USE_CONFIGURATION_DEVICE On -family Cyclone -set_global_assignment -name USE_CONFIGURATION_DEVICE On -family "Stratix II GX" -set_global_assignment -name USE_CONFIGURATION_DEVICE On -family FLEX10K -set_global_assignment -name USE_CONFIGURATION_DEVICE On -family "MAX II" -set_global_assignment -name USE_CONFIGURATION_DEVICE On -family APEX20KC -set_global_assignment -name USE_CONFIGURATION_DEVICE Off -family "Arria II GX" -set_global_assignment -name USE_CONFIGURATION_DEVICE On -family "Stratix GX" -set_global_assignment -name USE_CONFIGURATION_DEVICE Off -family "HardCopy III" -set_global_assignment -name USE_CONFIGURATION_DEVICE On -family MAX7000S -set_global_assignment -name USE_CONFIGURATION_DEVICE On -family FLEX6000 -set_global_assignment -name USE_CONFIGURATION_DEVICE On -family "APEX II" -set_global_assignment -name USE_CONFIGURATION_DEVICE On -family FLEX10KE -set_global_assignment -name USE_CONFIGURATION_DEVICE On -family "Cyclone II" -set_global_assignment -name USE_CONFIGURATION_DEVICE Off -family "HardCopy IV" -set_global_assignment -name USE_CONFIGURATION_DEVICE Off -family "Cyclone III LS" -set_global_assignment -name USE_CONFIGURATION_DEVICE Off -family "Stratix III" -set_global_assignment -name USE_CONFIGURATION_DEVICE On -family "Arria GX" -set_global_assignment -name USE_CONFIGURATION_DEVICE On -family MAX3000A -set_global_assignment -name USE_CONFIGURATION_DEVICE On -family "Stratix II" -set_global_assignment -name USE_CONFIGURATION_DEVICE On -family Stratix -set_global_assignment -name CYCLONEIII_CONFIGURATION_DEVICE Auto -set_global_assignment -name STRATIXII_CONFIGURATION_DEVICE Auto -set_global_assignment -name APEX20K_CONFIGURATION_DEVICE Auto -set_global_assignment -name MERCURY_CONFIGURATION_DEVICE Auto -set_global_assignment -name FLEX6K_CONFIGURATION_DEVICE Auto -set_global_assignment -name FLEX10K_CONFIGURATION_DEVICE Auto -set_global_assignment -name CYCLONE_CONFIGURATION_DEVICE Auto -set_global_assignment -name STRATIX_CONFIGURATION_DEVICE Auto -set_global_assignment -name APEX20K_CONFIG_DEVICE_JTAG_USER_CODE FFFFFFFF -set_global_assignment -name STRATIX_CONFIG_DEVICE_JTAG_USER_CODE FFFFFFFF -set_global_assignment -name MERCURY_CONFIG_DEVICE_JTAG_USER_CODE FFFFFFFF -set_global_assignment -name FLEX10K_CONFIG_DEVICE_JTAG_USER_CODE FFFFFFFF -set_global_assignment -name EPROM_USE_CHECKSUM_AS_USERCODE Off -set_global_assignment -name AUTO_INCREMENT_CONFIG_DEVICE_JTAG_USER_CODE On -set_global_assignment -name DISABLE_NCS_AND_OE_PULLUPS_ON_CONFIG_DEVICE Off -set_global_assignment -name GENERATE_TTF_FILE Off -set_global_assignment -name GENERATE_RBF_FILE Off -set_global_assignment -name GENERATE_HEX_FILE Off -set_global_assignment -name HEXOUT_FILE_START_ADDRESS 0 -set_global_assignment -name HEXOUT_FILE_COUNT_DIRECTION Up -set_global_assignment -name RESERVE_ALL_UNUSED_PINS_NO_OUTPUT_GND "As output driving an unspecified signal" -set_global_assignment -name RELEASE_CLEARS_BEFORE_TRI_STATES Off -set_global_assignment -name AUTO_RESTART_CONFIGURATION On -set_global_assignment -name HARDCOPYII_POWER_ON_EXTRA_DELAY Off -set_global_assignment -name STRATIXII_MRAM_COMPATIBILITY Off -set_global_assignment -name CYCLONEII_M4K_COMPATIBILITY On -set_global_assignment -name ENABLE_OCT_DONE Off -set_global_assignment -name USE_CHECKERED_PATTERN_AS_UNINITIALIZED_RAM_CONTENT Off -set_global_assignment -name START_TIME 0ns -set_global_assignment -name SIMULATION_MODE TIMING -set_global_assignment -name AUTO_USE_SIMULATION_PDB_NETLIST Off -set_global_assignment -name ADD_DEFAULT_PINS_TO_SIMULATION_OUTPUT_WAVEFORMS On -set_global_assignment -name SETUP_HOLD_DETECTION Off -set_global_assignment -name SETUP_HOLD_DETECTION_INPUT_REGISTERS_BIDIR_PINS_DISABLED Off -set_global_assignment -name CHECK_OUTPUTS Off -set_global_assignment -name SIMULATION_COVERAGE On -set_global_assignment -name SIMULATION_COMPLETE_COVERAGE_REPORT_PANEL On -set_global_assignment -name SIMULATION_MISSING_1_VALUE_COVERAGE_REPORT_PANEL On -set_global_assignment -name SIMULATION_MISSING_0_VALUE_COVERAGE_REPORT_PANEL On -set_global_assignment -name GLITCH_DETECTION Off -set_global_assignment -name GLITCH_INTERVAL 1ns -set_global_assignment -name SIMULATOR_GENERATE_SIGNAL_ACTIVITY_FILE Off -set_global_assignment -name SIMULATION_WITH_GLITCH_FILTERING_WHEN_GENERATING_SAF On -set_global_assignment -name SIMULATION_BUS_CHANNEL_GROUPING Off -set_global_assignment -name SIMULATION_VDB_RESULT_FLUSH On -set_global_assignment -name VECTOR_COMPARE_TRIGGER_MODE INPUT_EDGE -set_global_assignment -name SIMULATION_NETLIST_VIEWER Off -set_global_assignment -name SIMULATION_INTERCONNECT_DELAY_MODEL_TYPE TRANSPORT -set_global_assignment -name SIMULATION_CELL_DELAY_MODEL_TYPE TRANSPORT -set_global_assignment -name SIMULATOR_GENERATE_POWERPLAY_VCD_FILE Off -set_global_assignment -name SIMULATOR_PVT_TIMING_MODEL_TYPE AUTO -set_global_assignment -name SIMULATION_WITH_AUTO_GLITCH_FILTERING AUTO -set_global_assignment -name DRC_TOP_FANOUT 50 -set_global_assignment -name DRC_FANOUT_EXCEEDING 30 -set_global_assignment -name DRC_GATED_CLOCK_FEED 30 -set_global_assignment -name HARDCOPY_FLOW_AUTOMATION MIGRATION_ONLY -set_global_assignment -name ENABLE_DRC_SETTINGS Off -set_global_assignment -name CLK_RULE_CLKNET_CLKSPINES_THRESHOLD 25 -set_global_assignment -name DRC_DETAIL_MESSAGE_LIMIT 10 -set_global_assignment -name DRC_VIOLATION_MESSAGE_LIMIT 30 -set_global_assignment -name DRC_DEADLOCK_STATE_LIMIT 2 -set_global_assignment -name MERGE_HEX_FILE Off -set_global_assignment -name GENERATE_SVF_FILE Off -set_global_assignment -name GENERATE_ISC_FILE Off -set_global_assignment -name GENERATE_JAM_FILE Off -set_global_assignment -name GENERATE_JBC_FILE Off -set_global_assignment -name GENERATE_JBC_FILE_COMPRESSED On -set_global_assignment -name GENERATE_CONFIG_SVF_FILE Off -set_global_assignment -name GENERATE_CONFIG_ISC_FILE Off -set_global_assignment -name GENERATE_CONFIG_JAM_FILE Off -set_global_assignment -name GENERATE_CONFIG_JBC_FILE Off -set_global_assignment -name GENERATE_CONFIG_JBC_FILE_COMPRESSED On -set_global_assignment -name GENERATE_CONFIG_HEXOUT_FILE Off -set_global_assignment -name ISP_CLAMP_STATE_DEFAULT "Tri-state" -set_global_assignment -name SIGNALPROBE_ALLOW_OVERUSE Off -set_global_assignment -name SIGNALPROBE_DURING_NORMAL_COMPILATION Off -set_global_assignment -name LOGICLOCK_INCREMENTAL_COMPILE_ASSIGNMENT Off -set_global_assignment -name POWER_DEFAULT_TOGGLE_RATE 12.5% -set_global_assignment -name POWER_DEFAULT_INPUT_IO_TOGGLE_RATE 12.5% -set_global_assignment -name POWER_USE_PVA On -set_global_assignment -name POWER_USE_INPUT_FILE "No File" -set_global_assignment -name POWER_USE_INPUT_FILES Off -set_global_assignment -name POWER_VCD_FILTER_GLITCHES On -set_global_assignment -name POWER_REPORT_SIGNAL_ACTIVITY Off -set_global_assignment -name POWER_REPORT_POWER_DISSIPATION Off -set_global_assignment -name POWER_USE_DEVICE_CHARACTERISTICS TYPICAL -set_global_assignment -name POWER_AUTO_COMPUTE_TJ On -set_global_assignment -name POWER_TJ_VALUE 25 -set_global_assignment -name POWER_USE_TA_VALUE 25 -set_global_assignment -name POWER_USE_CUSTOM_COOLING_SOLUTION Off -set_global_assignment -name POWER_BOARD_TEMPERATURE 25 -set_global_assignment -name INCREMENTAL_COMPILATION FULL_INCREMENTAL_COMPILATION -set_global_assignment -name AUTO_EXPORT_INCREMENTAL_COMPILATION Off -set_global_assignment -name INCREMENTAL_COMPILATION_EXPORT_NETLIST_TYPE POST_FIT -set_global_assignment -name OUTPUT_IO_TIMING_ENDPOINT "Near End" -set_global_assignment -name RTLV_REMOVE_FANOUT_FREE_REGISTERS On -set_global_assignment -name RTLV_SIMPLIFIED_LOGIC On -set_global_assignment -name RTLV_GROUP_RELATED_NODES On -set_global_assignment -name RTLV_GROUP_COMB_LOGIC_IN_CLOUD Off -set_global_assignment -name RTLV_GROUP_COMB_LOGIC_IN_CLOUD_TMV Off -set_global_assignment -name RTLV_GROUP_RELATED_NODES_TMV On -set_global_assignment -name EQC_CONSTANT_DFF_DETECTION On -set_global_assignment -name EQC_DUPLICATE_DFF_DETECTION On -set_global_assignment -name EQC_BBOX_MERGE On -set_global_assignment -name EQC_LVDS_MERGE On -set_global_assignment -name EQC_RAM_UNMERGING On -set_global_assignment -name EQC_DFF_SS_EMULATION On -set_global_assignment -name EQC_RAM_REGISTER_UNPACK On -set_global_assignment -name EQC_MAC_REGISTER_UNPACK On -set_global_assignment -name EQC_SET_PARTITION_BB_TO_VCC_GND On -set_global_assignment -name EQC_STRUCTURE_MATCHING On -set_global_assignment -name EQC_AUTO_BREAK_CONE On -set_global_assignment -name EQC_POWER_UP_COMPARE Off -set_global_assignment -name EQC_AUTO_COMP_LOOP_CUT On -set_global_assignment -name EQC_AUTO_INVERSION On -set_global_assignment -name EQC_AUTO_TERMINATE On -set_global_assignment -name EQC_SUB_CONE_REPORT Off -set_global_assignment -name EQC_RENAMING_RULES On -set_global_assignment -name EQC_PARAMETER_CHECK On -set_global_assignment -name EQC_AUTO_PORTSWAP On -set_global_assignment -name EQC_DETECT_DONT_CARES On -set_global_assignment -name EQC_SHOW_ALL_MAPPED_POINTS Off -set_global_assignment -name DUTY_CYCLE 50 -section_id ? -set_global_assignment -name INVERT_BASE_CLOCK Off -section_id ? -set_global_assignment -name MULTIPLY_BASE_CLOCK_PERIOD_BY 1 -section_id ? -set_global_assignment -name DIVIDE_BASE_CLOCK_PERIOD_BY 1 -section_id ? -set_global_assignment -name EDA_INPUT_GND_NAME GND -section_id ? -set_global_assignment -name EDA_INPUT_VCC_NAME VCC -section_id ? -set_global_assignment -name EDA_INPUT_DATA_FORMAT NONE -section_id ? -set_global_assignment -name EDA_SHOW_LMF_MAPPING_MESSAGES Off -section_id ? -set_global_assignment -name EDA_RUN_TOOL_AUTOMATICALLY Off -section_id ? -set_global_assignment -name RESYNTHESIS_RETIMING FULL -section_id ? -set_global_assignment -name RESYNTHESIS_OPTIMIZATION_EFFORT Normal -section_id ? -set_global_assignment -name RESYNTHESIS_PHYSICAL_SYNTHESIS Normal -section_id ? -set_global_assignment -name USE_GENERATED_PHYSICAL_CONSTRAINTS On -section_id ? -set_global_assignment -name VCCPD_VOLTAGE 3.3V -section_id ? -set_global_assignment -name EDA_USER_COMPILED_SIMULATION_LIBRARY_DIRECTORY "" -section_id ? -set_global_assignment -name EDA_LAUNCH_CMD_LINE_TOOL Off -section_id ? -set_global_assignment -name EDA_NATIVELINK_GENERATE_SCRIPT_ONLY Off -section_id ? -set_global_assignment -name EDA_WAIT_FOR_GUI_TOOL_COMPLETION Off -section_id ? -set_global_assignment -name EDA_TRUNCATE_LONG_HIERARCHY_PATHS Off -section_id ? -set_global_assignment -name EDA_FLATTEN_BUSES Off -section_id ? -set_global_assignment -name EDA_MAP_ILLEGAL_CHARACTERS Off -section_id ? -set_global_assignment -name EDA_GENERATE_TIMING_CLOSURE_DATA Off -section_id ? -set_global_assignment -name EDA_GENERATE_POWER_INPUT_FILE Off -section_id ? -set_global_assignment -name EDA_TEST_BENCH_ENABLE_STATUS NOT_USED -section_id ? -set_global_assignment -name EDA_RTL_SIM_MODE NOT_USED -section_id ? -set_global_assignment -name EDA_MAINTAIN_DESIGN_HIERARCHY Off -section_id ? -set_global_assignment -name EDA_GENERATE_FUNCTIONAL_NETLIST Off -section_id ? -set_global_assignment -name EDA_WRITE_DEVICE_CONTROL_PORTS Off -section_id ? -set_global_assignment -name EDA_SIMULATION_VCD_OUTPUT_TCL_FILE Off -section_id ? -set_global_assignment -name EDA_SIMULATION_VCD_OUTPUT_SIGNALS_TO_TCL_FILE "All Except Combinational Logic Element Outputs" -section_id ? -set_global_assignment -name EDA_ENABLE_GLITCH_FILTERING Off -section_id ? -set_global_assignment -name EDA_WRITE_NODES_FOR_POWER_ESTIMATION OFF -section_id ? -set_global_assignment -name EDA_SETUP_HOLD_DETECTION_INPUT_REGISTERS_BIDIR_PINS_DISABLED Off -section_id ? -set_global_assignment -name EDA_WRITER_DONT_WRITE_TOP_ENTITY Off -section_id ? -set_global_assignment -name EDA_VHDL_ARCH_NAME structure -section_id ? -set_global_assignment -name EDA_IBIS_MODEL_SELECTOR Off -section_id ? -set_global_assignment -name EDA_IBIS_MUTUAL_COUPLING Off -section_id ? -set_global_assignment -name EDA_FORMAL_VERIFICATION_ALLOW_RETIMING Off -section_id ? -set_global_assignment -name EDA_BOARD_BOUNDARY_SCAN_OPERATION PRE_CONFIG -section_id ? -set_global_assignment -name EDA_GENERATE_RTL_SIMULATION_COMMAND_SCRIPT Off -section_id ? -set_global_assignment -name EDA_GENERATE_GATE_LEVEL_SIMULATION_COMMAND_SCRIPT Off -section_id ? -set_global_assignment -name SIM_VECTOR_COMPARED_CLOCK_OFFSET 0ns -section_id ? -set_global_assignment -name SIM_VECTOR_COMPARED_CLOCK_DUTY_CYCLE 50 -section_id ? -set_global_assignment -name APEX20K_CLIQUE_TYPE LAB -section_id ? -entity ? -set_global_assignment -name MAX7K_CLIQUE_TYPE LAB -section_id ? -entity ? -set_global_assignment -name MERCURY_CLIQUE_TYPE LAB -section_id ? -entity ? -set_global_assignment -name FLEX6K_CLIQUE_TYPE LAB -section_id ? -entity ? -set_global_assignment -name FLEX10K_CLIQUE_TYPE LAB -section_id ? -entity ? -set_global_assignment -name PARTITION_IMPORT_ASSIGNMENTS On -section_id ? -entity ? -set_global_assignment -name PARTITION_IMPORT_EXISTING_ASSIGNMENTS REPLACE_CONFLICTING -section_id ? -entity ? -set_global_assignment -name PARTITION_IMPORT_EXISTING_LOGICLOCK_REGIONS REPLACE_CONFLICTING -section_id ? -entity ? -set_global_assignment -name PARTITION_IMPORT_PROMOTE_ASSIGNMENTS On -section_id ? -entity ? Index: trunk/rtl/System09_Terasic_DE1/roms/kbug_rom.mif =================================================================== --- trunk/rtl/System09_Terasic_DE1/roms/kbug_rom.mif (revision 115) +++ trunk/rtl/System09_Terasic_DE1/roms/kbug_rom.mif (nonexistent) @@ -1,2054 +0,0 @@ -WIDTH=8; -DEPTH=2048; -ADDRESS_RADIX=UNS; -DATA_RADIX=HEX; -CONTENT BEGIN - 0 : F8; - 1 : 38; - 2 : F8; - 3 : 7C; - 4 : FC; - 5 : 80; - 6 : FC; - 7 : A9; - 8 : FC; - 9 : 65; - 10 : FC; - 11 : AB; - 12 : FC; - 13 : 5E; - 14 : FC; - 15 : 53; - 16 : FC; - 17 : 4F; - 18 : FA; - 19 : 18; - 20 : FA; - 21 : 18; - 22 : FA; - 23 : 18; - 24 : FA; - 25 : 18; - 26 : FA; - 27 : 18; - 28 : FD; - 29 : 1B; - 30 : FC; - 31 : FB; - 32 : FD; - 33 : 04; - 34 : FD; - 35 : 3A; - 36 : FC; - 37 : BF; - 38 : FC; - 39 : D2; - 40 : FC; - 41 : DC; - 42 : FC; - 43 : EB; - 44 : FC; - 45 : FA; - 46 : FC; - 47 : FB; - 48 : FD; - 49 : 04; - 50 : FD; - 51 : 0C; - 52 : 10; - 53 : CE; - 54 : F0; - 55 : C0; - 56 : 8E; - 57 : FE; - 58 : B9; - 59 : 10; - 60 : 8E; - 61 : F0; - 62 : C0; - 63 : C6; - 64 : 10; - 65 : A6; - 66 : 80; - 67 : A7; - 68 : A0; - 69 : 5A; - 70 : 26; - 71 : F9; - 72 : 8E; - 73 : E0; - 74 : 00; - 75 : BF; - 76 : F0; - 77 : D0; - 78 : 17; - 79 : 01; - 80 : 8E; - 81 : C6; - 82 : 0C; - 83 : 6F; - 84 : E2; - 85 : 5A; - 86 : 26; - 87 : FB; - 88 : 30; - 89 : 8C; - 90 : DD; - 91 : AF; - 92 : 6A; - 93 : 86; - 94 : D0; - 95 : A7; - 96 : E4; - 97 : 1F; - 98 : 43; - 99 : 86; - 100 : 03; - 101 : B7; - 102 : F0; - 103 : D7; - 104 : 86; - 105 : 0A; - 106 : B7; - 107 : F0; - 108 : D8; - 109 : 17; - 110 : 04; - 111 : 4F; - 112 : 17; - 113 : 04; - 114 : 87; - 115 : 17; - 116 : 04; - 117 : A5; - 118 : 8E; - 119 : FE; - 120 : C9; - 121 : 17; - 122 : 03; - 123 : E2; - 124 : 8E; - 125 : FE; - 126 : E5; - 127 : 17; - 128 : 03; - 129 : CD; - 130 : 17; - 131 : 03; - 132 : FB; - 133 : 84; - 134 : 7F; - 135 : 81; - 136 : 0D; - 137 : 27; - 138 : F1; - 139 : 1F; - 140 : 89; - 141 : 81; - 142 : 20; - 143 : 2C; - 144 : 09; - 145 : 86; - 146 : 5E; - 147 : 17; - 148 : 04; - 149 : 15; - 150 : 1F; - 151 : 98; - 152 : 8B; - 153 : 40; - 154 : 17; - 155 : 04; - 156 : 0E; - 157 : 17; - 158 : 02; - 159 : A3; - 160 : 8E; - 161 : FE; - 162 : 7A; - 163 : E1; - 164 : 80; - 165 : 27; - 166 : 0F; - 167 : 30; - 168 : 02; - 169 : 8C; - 170 : FE; - 171 : B9; - 172 : 26; - 173 : F5; - 174 : 8E; - 175 : FE; - 176 : E7; - 177 : 17; - 178 : 03; - 179 : AA; - 180 : 20; - 181 : C6; - 182 : AD; - 183 : 94; - 184 : 20; - 185 : C2; - 186 : 17; - 187 : 02; - 188 : 45; - 189 : 29; - 190 : 2D; - 191 : 1F; - 192 : 12; - 193 : 8E; - 194 : FE; - 195 : ED; - 196 : 17; - 197 : 03; - 198 : 88; - 199 : 1F; - 200 : 21; - 201 : 17; - 202 : 03; - 203 : 65; - 204 : 17; - 205 : 02; - 206 : 74; - 207 : A6; - 208 : A4; - 209 : 17; - 210 : 03; - 211 : 65; - 212 : 17; - 213 : 02; - 214 : 6C; - 215 : 17; - 216 : 02; - 217 : 38; - 218 : 28; - 219 : 11; - 220 : 81; - 221 : 08; - 222 : 27; - 223 : E1; - 224 : 81; - 225 : 18; - 226 : 27; - 227 : DD; - 228 : 81; - 229 : 5E; - 230 : 27; - 231 : 17; - 232 : 81; - 233 : 0D; - 234 : 26; - 235 : 0F; - 236 : 39; - 237 : A7; - 238 : A4; - 239 : A1; - 240 : A4; - 241 : 27; - 242 : 08; - 243 : 17; - 244 : 02; - 245 : 4D; - 246 : 86; - 247 : 3F; - 248 : 17; - 249 : 03; - 250 : B0; - 251 : 31; - 252 : 21; - 253 : 20; - 254 : C2; - 255 : 31; - 256 : 3F; - 257 : 20; - 258 : BE; - 259 : 17; - 260 : 02; - 261 : C0; - 262 : 1F; - 263 : 32; - 264 : 8E; - 265 : F0; - 266 : C0; - 267 : 30; - 268 : 1F; - 269 : 20; - 270 : 05; - 271 : 17; - 272 : 01; - 273 : E6; - 274 : 29; - 275 : 06; - 276 : 34; - 277 : 20; - 278 : AC; - 279 : E1; - 280 : 24; - 281 : 01; - 282 : 39; - 283 : 1F; - 284 : 10; - 285 : C3; - 286 : 00; - 287 : 10; - 288 : C4; - 289 : F0; - 290 : 34; - 291 : 06; - 292 : 1F; - 293 : 20; - 294 : C4; - 295 : F0; - 296 : 1F; - 297 : 01; - 298 : AC; - 299 : E4; - 300 : 27; - 301 : 05; - 302 : 17; - 303 : 03; - 304 : 34; - 305 : 27; - 306 : 03; - 307 : 32; - 308 : 62; - 309 : 39; - 310 : 34; - 311 : 10; - 312 : 8E; - 313 : FE; - 314 : ED; - 315 : 17; - 316 : 03; - 317 : 11; - 318 : AE; - 319 : E4; - 320 : 17; - 321 : 02; - 322 : EE; - 323 : 17; - 324 : 01; - 325 : FB; - 326 : C6; - 327 : 10; - 328 : A6; - 329 : 80; - 330 : 17; - 331 : 02; - 332 : EC; - 333 : 17; - 334 : 01; - 335 : F3; - 336 : 5A; - 337 : 26; - 338 : F5; - 339 : 17; - 340 : 01; - 341 : EB; - 342 : AE; - 343 : E1; - 344 : C6; - 345 : 10; - 346 : A6; - 347 : 80; - 348 : 81; - 349 : 20; - 350 : 25; - 351 : 04; - 352 : 81; - 353 : 7E; - 354 : 23; - 355 : 02; - 356 : 86; - 357 : 2E; - 358 : 17; - 359 : 03; - 360 : 42; - 361 : 5A; - 362 : 26; - 363 : EE; - 364 : 20; - 365 : BC; - 366 : 17; - 367 : 01; - 368 : FD; - 369 : 28; - 370 : 01; - 371 : 39; - 372 : 1F; - 373 : 34; - 374 : 3B; - 375 : 5F; - 376 : 17; - 377 : 03; - 378 : 05; - 379 : 81; - 380 : 53; - 381 : 26; - 382 : 07; - 383 : 17; - 384 : 03; - 385 : 3D; - 386 : D8; - 387 : 02; - 388 : 20; - 389 : F2; - 390 : 81; - 391 : 56; - 392 : 26; - 393 : 07; - 394 : 17; - 395 : 03; - 396 : 8E; - 397 : C8; - 398 : 01; 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- 2030 : 3C; - 2031 : 00; - 2032 : 00; - 2033 : 08; - 2034 : 1C; - 2035 : 2A; - 2036 : 08; - 2037 : 08; - 2038 : 08; - 2039 : 08; - 2040 : 00; - 2041 : 00; - 2042 : 10; - 2043 : 20; - 2044 : 7F; - 2045 : 20; - 2046 : 10; - 2047 : 00; -END; Index: trunk/rtl/System09_Terasic_DE1/ps2_keyboard.vhd =================================================================== --- trunk/rtl/System09_Terasic_DE1/ps2_keyboard.vhd (revision 115) +++ trunk/rtl/System09_Terasic_DE1/ps2_keyboard.vhd (nonexistent) @@ -1,850 +0,0 @@ ---------------------------------------------------------------------------------------- --- --- Author: John Clayton --- Date : April 30, 2001 --- Update: 4/30/01 copied this file from lcd_2.v (pared down). --- Update: 5/24/01 changed the first module from "ps2_keyboard_receiver" --- to "ps2_keyboard_interface" --- Update: 5/29/01 Added input synchronizing flip-flops. Changed state --- encoding (m1) for good operation after part config. --- Update: 5/31/01 Added low drive strength and slow transitions to ps2_clk --- and ps2_data in the constraints file. Added the signal --- "tx_shifting_done" as distinguished from "rx_shifting_done." --- Debugged the transmitter portion in the lab. --- Update: 6/01/01 Added horizontal tab to the ascii output. --- Update: 6/01/01 Added parameter TRAP_SHIFT_KEYS. --- Update: 6/05/01 Debugged the "debounce" timer functionality. --- Used 60usec timer as a "watchdog" timeout during --- receive from the keyboard. This means that a keyboard --- can now be "hot plugged" into the interface, without --- messing up the bit_count, since the bit_count is reset --- to zero during periods of inactivity anyway. This was --- difficult to debug. I ended up using the logic analyzer, --- and had to scratch my head quite a bit. --- Update: 6/06/01 Removed extra comments before the input synchronizing --- flip-flops. Used the correct parameter to size the --- 5usec_timer_count. Changed the name of this file from --- ps2.v to ps2_keyboard.v --- Update: 6/06/01 Removed "&& q[7:0]" in output_strobe logic. Removed extra --- commented out "else" condition in the shift register and --- bit counter. --- Update: 6/07/01 Changed default values for 60usec timer parameters so that --- they correspond to 60usec for a 49.152MHz clock. --- --- Converted to VHDL: 10 February 2004 - John Kent --- 11 Sept 04 added ctrl key --- changed undefined key codes to x"ff" --- reversed clock polarity --- --- 18th Oct 04 added ctrl keys to ASCII ROM --- added CAPS Lock toggle. --- --- Description ---------------------------------------------------------------------------------------- --- This is a state-machine driven serial-to-parallel and parallel-to-serial --- interface to the ps2 style keyboard interface. The details of the operation --- of the keyboard interface were obtained from the following website: --- --- http:--www.beyondlogic.org/keyboard/keybrd.htm --- --- Some aspects of the keyboard interface are not implemented (e.g, parity --- checking for the receive side, and recognition of the various commands --- which the keyboard sends out, such as "power on selt test passed," "Error" --- and "Resend.") However, if the user wishes to recognize these reply --- messages, the scan code output can always be used to extend functionality --- as desired. --- --- Note that the "Extended" (0xE0) and "Released" (0xF0) codes are recognized. --- The rx interface provides separate indicator flags for these two conditions --- with every valid character scan code which it provides. The shift keys are --- also trapped by the interface, in order to provide correct uppercase ASCII --- characters at the ascii output, although the scan codes for the shift keys --- are still provided at the scan code output. So, the left/right ALT keys --- can be differentiated by the presence of the rx_entended signal, while the --- left/right shift keys are differentiable by the different scan codes --- received. --- --- The interface to the ps2 keyboard uses ps2_clk clock rates of --- 30-40 kHz, dependent upon the keyboard itself. The rate at which the state --- machine runs should be at least twice the rate of the ps2_clk, so that the --- states can accurately follow the clock signal itself. Four times --- oversampling is better. Say 200kHz at least. The upper limit for clocking --- the state machine will undoubtedly be determined by delays in the logic --- which decodes the scan codes into ASCII equivalents. The maximum speed --- will be most likely many megahertz, depending upon target technology. --- In order to run the state machine extremely fast, synchronizing flip-flops --- have been added to the ps2_clk and ps2_data inputs of the state machine. --- This avoids poor performance related to slow transitions of the inputs. --- --- Because this is a bi-directional interface, while reading from the keyboard --- the ps2_clk and ps2_data lines are used as inputs. While writing to the --- keyboard, however (which may be done at any time. If writing interrupts a --- read from the keyboard, the keyboard will buffer up its data, and send --- it later) both the ps2_clk and ps2_data lines are occasionally pulled low, --- and pullup resistors are used to bring the lines high again, by setting --- the drivers to high impedance state. --- --- The tx interface, for writing to the keyboard, does not provide any special --- pre-processing. It simply transmits the 8-bit command value to the --- keyboard. --- --- Pullups MUST BE USED on the ps2_clk and ps2_data lines for this design, --- whether they be internal to an FPGA I/O pad, or externally placed. --- If internal pullups are used, they may be fairly weak, causing bounces --- due to crosstalk, etc. There is a "debounce timer" implemented in order --- to eliminate erroneous state transitions which would occur based on bounce. --- --- Parameters are provided in order to configure and appropriately size the --- counter of a 60 microsecond timer used in the transmitter, depending on --- the clock frequency used. The 60 microsecond period is guaranteed to be --- more than one period of the ps2_clk_s signal. --- --- Also, a smaller 5 microsecond timer has been included for "debounce". --- This is used because, with internal pullups on the ps2_clk and ps2_data --- lines, there is some bouncing around which occurs --- --- A parameter TRAP_SHIFT_KEYS allows the user to eliminate shift keypresses --- from producing scan codes (along with their "undefined" ASCII equivalents) --- at the output of the interface. If TRAP_SHIFT_KEYS is non-zero, the shift --- key status will only be reported by rx_shift_key_on. No ascii or scan --- codes will be reported for the shift keys. This is useful for those who --- wish to use the ASCII data stream, and who don't want to have to "filter --- out" the shift key codes. --- ---------------------------------------------------------------------------------------- - -library ieee; - use ieee.std_logic_1164.all; - use IEEE.STD_LOGIC_ARITH.ALL; - use IEEE.STD_LOGIC_UNSIGNED.ALL; - use ieee.numeric_std.all; - -entity ps2_keyboard_interface is - port( - clk : in std_logic; - reset : in std_logic; - ps2_clk : in std_logic; - ps2_data : in std_logic; - rx_extended : out std_logic; - rx_released : out std_logic; - rx_shift_key_on : out std_logic; --- rx_scan_code : out std_logic_vector(7 downto 0); - rx_ascii : out std_logic_vector(7 downto 0); - rx_data_ready : out std_logic; -- rx_read_o - rx_read : in std_logic; -- rx_read_ack_i - tx_data : in std_logic_vector(7 downto 0); - tx_write : in std_logic; - tx_write_ack : out std_logic; - tx_error_no_keyboard_ack : out std_logic - ); -end ps2_keyboard_interface; - -------------------------------------------------------------------------------- --- Architecture for ps2 keyboard interface -------------------------------------------------------------------------------- -architecture my_ps2_keyboard of ps2_keyboard_interface is - ----------------------------------------------------------------------------- - - -constant TOTAL_BITS : integer := 11; -constant EXTEND_CODE : integer := 16#E0#; -constant RELEASE_CODE : integer := 16#F0#; -constant LEFT_SHIFT : integer := 16#12#; -constant RIGHT_SHIFT : integer := 16#59#; -constant CTRL_CODE : integer := 16#14#; -constant CAPS_CODE : integer := 16#58#; - - --- constants - --- The timer value can be up to (2^bits) inclusive. --- Values for 49.152 MHz clock ---constant TIMER_60USEC_VALUE_PP : integer := 2950; -- Number of sys_clks for 60usec. ---constant TIMER_60USEC_BITS_PP : integer := 12; -- Number of bits needed for timer ---constant TIMER_5USEC_VALUE_PP : integer := 186; -- Number of sys_clks for debounce ---constant TIMER_5USEC_BITS_PP : integer := 8; -- Number of bits needed for timer - --- Values for 12.5 MHz Clock -constant TIMER_60USEC_VALUE_PP : integer := 750; -- Number of sys_clks for 60usec. -constant TIMER_60USEC_BITS_PP : integer := 10; -- Number of bits needed for timer -constant TIMER_5USEC_VALUE_PP : integer := 62; -- Number of sys_clks for debounce -constant TIMER_5USEC_BITS_PP : integer := 6; -- Number of bits needed for timer - -constant TRAP_SHIFT_KEYS_PP : integer := 1; -- Default: No shift key trap. - --- State encodings, provided as constants --- for flexibility to the one instantiating the module. --- In general, the default values need not be changed. - --- State "m1_rx_clk_l" has been chosen on purpose. Since the input --- synchronizing flip-flops initially contain zero, it takes one clk --- for them to update to reflect the actual (idle = high) status of --- the I/O lines from the keyboard. Therefore, choosing 0 for m1_rx_clk_l --- allows the state machine to transition to m1_rx_clk_h when the true --- values of the input signals become present at the outputs of the --- synchronizing flip-flops. This initial transition is harmless, and it --- eliminates the need for a "reset" pulse before the interface can operate. - -type m1_type is ( m1_rx_clk_h, m1_rx_clk_l, - m1_tx_wait_clk_h, m1_tx_force_clk_l, - m1_tx_clk_h, m1_tx_clk_l, - m1_tx_wait_keyboard_ack, m1_tx_done_recovery, - m1_tx_error_no_keyboard_ack, m1_tx_rising_edge_marker, - m1_tx_first_wait_clk_h, m1_tx_first_wait_clk_l, m1_tx_reset_timer, - m1_rx_falling_edge_marker, m1_rx_rising_edge_marker ); - --- Internal signal declarations -signal timer_60usec_done : std_logic; -signal timer_5usec_done : std_logic; -signal extended : std_logic; -signal released : std_logic; -signal shift_key_on : std_logic; -signal ctrl_key_on : std_logic; -signal caps_key_on : std_logic; - - -- NOTE: These two signals used to be one. They - -- were split into two signals because of - -- shift key trapping. With shift key - -- trapping, no event is generated externally, - -- but the "hold" data must still be cleared - -- anyway regardless, in preparation for the - -- next scan codes. -signal rx_output_event : std_logic; -- Used only to clear: hold_released, hold_extended -signal rx_output_strobe : std_logic; -- Used to produce the actual output. - -signal tx_parity_bit : std_logic; -signal rx_shifting_done : std_logic; -signal tx_shifting_done : std_logic; -signal shift_key_plus_code: std_logic_vector(8 downto 0); - -signal q : std_logic_vector(TOTAL_BITS-1 downto 0); -signal m1_state : m1_type; -signal m1_next_state : m1_type; -signal bit_count : std_logic_vector(3 downto 0); -signal enable_timer_60usec: std_logic; -signal enable_timer_5usec : std_logic; -signal timer_60usec_count : std_logic_vector(TIMER_60USEC_BITS_PP-1 downto 0); -signal timer_5usec_count : std_logic_vector(TIMER_5USEC_BITS_PP-1 downto 0); -signal ascii : std_logic_vector(7 downto 0); -- "REG" type only because a case statement is used. -signal left_shift_key : std_logic; -signal right_shift_key : std_logic; -signal hold_extended : std_logic; -- Holds prior value, cleared at rx_output_strobe -signal hold_released : std_logic; -- Holds prior value, cleared at rx_output_strobe -signal ps2_clk_s : std_logic; -- Synchronous version of this input -signal ps2_data_s : std_logic; -- Synchronous version of this input -signal ps2_clk_hi_z : std_logic; -- Without keyboard, high Z equals 1 due to pullups. -signal ps2_data_hi_z : std_logic; -- Without keyboard, high Z equals 1 due to pullups. -signal tx_write_ack_o : std_logic; - --- --- key lookup table --- -component key_slice - Port ( - addr : in std_logic_vector (8 downto 0); - data : out std_logic_vector (7 downto 0) - ); -end component; - ---component key_b4 --- Port ( --- clk : in std_logic; --- rst : in std_logic; --- cs : in std_logic; --- rw : in std_logic; --- addr : in std_logic_vector (8 downto 0); --- rdata : out std_logic_vector (7 downto 0); --- wdata : in std_logic_vector (7 downto 0) --- ); ---end component; - -begin - -my_key_map : key_slice - Port map ( - addr => shift_key_plus_code, - data => ascii - ); - ---my_key_map : key_b4 --- Port map ( --- clk => clk, --- rst => reset, --- cs => '1', --- rw => '1', --- addr => shift_key_plus_code, --- rdata => ascii, --- wdata => "00000000" --- ); - ----------------------------------------------------------------------------- --- Module code --- assign ps2_clk = ps2_clk_hi_z?1'bZ:1'b0; --- assign ps2_data = ps2_data_hi_z?1'bZ:1'b0; --- -ps2_direction : process( ps2_clk_hi_z, ps2_data_hi_z ) -begin - if( ps2_clk_hi_z = '1' ) then - --ps2_clk <= 'Z'; - else - --ps2_clk <= '0'; - end if; - if( ps2_data_hi_z = '1' ) then - --ps2_data <= 'Z'; - else - --ps2_data <= '0'; - end if; -end process; - --- Input "synchronizing" logic -- synchronizes the inputs to the state --- machine clock, thus avoiding errors related to --- spurious state machine transitions. -ps2_synch : process(clk, ps2_clk, ps2_data) -begin - if clk'event and clk='0' then - ps2_clk_s <= ps2_clk; - ps2_data_s <= ps2_data; - end if; -end process; - --- State register -m1_state_register : process( clk, reset, m1_state ) -begin - if clk'event and clk='0' then - if (reset = '1') then - m1_state <= m1_rx_clk_h; - else - m1_state <= m1_next_state; - end if; - end if; -end process; - -m1_state_logic : process( m1_state, q, - tx_shifting_done, tx_write, - ps2_clk_s, ps2_data_s, - timer_60usec_done, timer_5usec_done ) -begin - -- Output signals default to this value, unless changed in a state condition. - ps2_clk_hi_z <= '1'; - ps2_data_hi_z <= '1'; - tx_error_no_keyboard_ack <= '0'; - enable_timer_60usec <= '0'; - enable_timer_5usec <= '0'; - - case (m1_state) is - when m1_rx_clk_h => - enable_timer_60usec <= '1'; - if (tx_write = '1') then - m1_next_state <= m1_tx_reset_timer; - elsif (ps2_clk_s = '0') then - m1_next_state <= m1_rx_falling_edge_marker; - else - m1_next_state <= m1_rx_clk_h; - end if; - - when m1_rx_falling_edge_marker => - enable_timer_60usec <= '0'; - m1_next_state <= m1_rx_clk_l; - - when m1_rx_clk_l => - enable_timer_60usec <= '1'; - if (tx_write = '1') then - m1_next_state <= m1_tx_reset_timer; - elsif (ps2_clk_s = '1') then - m1_next_state <= m1_rx_rising_edge_marker; - else - m1_next_state <= m1_rx_clk_l; - end if; - - when m1_rx_rising_edge_marker => - enable_timer_60usec <= '0'; - m1_next_state <= m1_rx_clk_h; - - when m1_tx_reset_timer => - enable_timer_60usec <= '0'; - m1_next_state <= m1_tx_force_clk_l; - - when m1_tx_force_clk_l => - enable_timer_60usec <= '1'; - ps2_clk_hi_z <= '0'; -- Force the ps2_clk line low. - if (timer_60usec_done = '1') then - m1_next_state <= m1_tx_first_wait_clk_h; - else - m1_next_state <= m1_tx_force_clk_l; - end if; - - when m1_tx_first_wait_clk_h => - enable_timer_5usec <= '1'; - ps2_data_hi_z <= '0'; -- Start bit. - if (ps2_clk_s = '0') and (timer_5usec_done = '1') then - m1_next_state <= m1_tx_clk_l; - else - m1_next_state <= m1_tx_first_wait_clk_h; - end if; - - -- This state must be included because the device might possibly - -- delay for up to 10 milliseconds before beginning its clock pulses. - -- During that waiting time, we cannot drive the data (q[0]) because it - -- is possibly 1, which would cause the keyboard to abort its receive - -- and the expected clocks would then never be generated. - when m1_tx_first_wait_clk_l => - ps2_data_hi_z <= '0'; - if (ps2_clk_s = '0') then - m1_next_state <= m1_tx_clk_l; - else - m1_next_state <= m1_tx_first_wait_clk_l; - end if; - - when m1_tx_wait_clk_h => - enable_timer_5usec <= '1'; - ps2_data_hi_z <= q(0); - if (ps2_clk_s = '1') and (timer_5usec_done = '1') then - m1_next_state <= m1_tx_rising_edge_marker; - else - m1_next_state <= m1_tx_wait_clk_h; - end if; - - when m1_tx_rising_edge_marker => - ps2_data_hi_z <= q(0); - m1_next_state <= m1_tx_clk_h; - - when m1_tx_clk_h => - ps2_data_hi_z <= q(0); - if (tx_shifting_done = '1') then - m1_next_state <= m1_tx_wait_keyboard_ack; - elsif (ps2_clk_s = '0') then - m1_next_state <= m1_tx_clk_l; - else - m1_next_state <= m1_tx_clk_h; - end if; - - when m1_tx_clk_l => - ps2_data_hi_z <= q(0); - if (ps2_clk_s = '1') then - m1_next_state <= m1_tx_wait_clk_h; - else - m1_next_state <= m1_tx_clk_l; - end if; - - when m1_tx_wait_keyboard_ack => - if (ps2_clk_s = '0') and (ps2_data_s = '1') then - m1_next_state <= m1_tx_error_no_keyboard_ack; - elsif (ps2_clk_s = '0') and (ps2_data_s = '0') then - m1_next_state <= m1_tx_done_recovery; - else - m1_next_state <= m1_tx_wait_keyboard_ack; - end if; - - when m1_tx_done_recovery => - if (ps2_clk_s = '1') and (ps2_data_s = '1') then - m1_next_state <= m1_rx_clk_h; - else - m1_next_state <= m1_tx_done_recovery; - end if; - - when m1_tx_error_no_keyboard_ack => - tx_error_no_keyboard_ack <= '1'; - if (ps2_clk_s = '1') and (ps2_data_s ='1') then - m1_next_state <= m1_rx_clk_h; - else - m1_next_state <= m1_tx_error_no_keyboard_ack; - end if; - - when others => - m1_next_state <= m1_rx_clk_h; - end case; -end process; - --- This is the bit counter -bit_counter: process(clk, reset, m1_state, bit_count ) -begin - if clk'event and clk = '0' then - if ( reset = '1' ) or - ( rx_shifting_done = '1' ) or - (m1_state = m1_tx_wait_keyboard_ack) then -- After tx is done. - bit_count <= "0000"; -- normal reset - elsif (timer_60usec_done = '1' ) and - (m1_state = m1_rx_clk_h) and - (ps2_clk_s = '1') then - bit_count <= "0000"; -- rx watchdog timer reset - elsif (m1_state = m1_rx_falling_edge_marker) or -- increment for rx - (m1_state = m1_tx_rising_edge_marker) then -- increment for tx - bit_count <= bit_count + 1; - end if; - end if; -end process; - -assign: process( bit_count, tx_write, tx_write_ack_o, m1_state ) -begin - if (bit_count = TOTAL_BITS) then - rx_shifting_done <= '1'; - else - rx_shifting_done <= '0'; - end if; - - if (bit_count = (TOTAL_BITS-1)) then - tx_shifting_done <= '1'; - else - tx_shifting_done <= '0'; - end if; - --- This is the signal which enables loading of the shift register. --- It also indicates "ack" to the device writing to the transmitter. - if ((tx_write = '1') and (m1_state = m1_rx_clk_h)) or - ((tx_write = '1') and (m1_state = m1_rx_clk_l)) then - tx_write_ack_o <= '1'; - else - tx_write_ack_o <= '0'; - end if; - tx_write_ack <= tx_write_ack_o; -end process; - --- This is the ODD parity bit for the transmitted word. --- assign tx_parity_bit = ~^tx_data; --- -tx_parity_bit <= not( tx_data(7) xor tx_data(6) xor tx_data(5) xor tx_data(4) xor - tx_data(3) xor tx_data(2) xor tx_data(1) xor tx_data(0) ); - --- This is the shift register -q_shift : process(clk, tx_write_ack_o, tx_parity_bit, tx_data, - m1_state, q, ps2_data_s, rx_shifting_done ) -begin - if clk'event and clk='0' then - if (reset = '1') then - q <= "00000000000"; - elsif (tx_write_ack_o = '1') then - q <= "1" & tx_parity_bit & tx_data & "0"; - elsif ( (m1_state = m1_rx_falling_edge_marker) or - (m1_state = m1_tx_rising_edge_marker) ) then - q <= ps2_data_s & q((TOTAL_BITS-1) downto 1); - end if; - end if; - --- Create the signals which indicate special scan codes received. --- These are the "unlatched versions." - if (q(8 downto 1) = EXTEND_CODE) and (rx_shifting_done = '1') then - extended <= '1'; - else - extended <= '0'; - end if; - if (q(8 downto 1) = RELEASE_CODE) and (rx_shifting_done = '1') then - released <= '1'; - else - released <= '0'; - end if; -end process; - --- This is the 60usec timer counter -timer60usec: process(clk, enable_timer_60usec, timer_60usec_count) -begin - if clk'event and clk = '0' then - if (enable_timer_60usec = '0') then - timer_60usec_count <= "0000000000"; - elsif (timer_60usec_done = '0') then - timer_60usec_count <= timer_60usec_count + 1; - end if; - end if; - - if (timer_60usec_count = (TIMER_60USEC_VALUE_PP - 1)) then - timer_60usec_done <= '1'; - else - timer_60usec_done <= '0'; - end if; -end process; - --- This is the 5usec timer counter -timer5usec : process(clk, enable_timer_5usec, timer_5usec_count ) -begin - if clk'event and clk = '0' then - if (enable_timer_5usec = '0') then - timer_5usec_count <= "000000"; - elsif (timer_5usec_done = '0') then - timer_5usec_count <= timer_5usec_count + 1; - end if; - end if; - - if( timer_5usec_count = (TIMER_5USEC_VALUE_PP - 1)) then - timer_5usec_done <= '1'; - else - timer_5usec_done <= '0'; - end if; -end process; - - --- Store the special scan code status bits --- Not the final output, but an intermediate storage place, --- until the entire set of output data can be assembled. -special_scan : process(clk, reset, rx_output_event, rx_shifting_done, extended, released ) -begin - if clk'event and clk='0' then - if (reset = '1') or (rx_output_event = '1') then - hold_extended <= '0'; - hold_released <= '0'; - else - if (rx_shifting_done = '1') and (extended = '1') then - hold_extended <= '1'; - end if; - if (rx_shifting_done = '1') and (released = '1') then - hold_released <= '1'; - end if; - end if; - end if; -end process; - - --- These bits contain the status of the two shift keys -left_shift_proc : process(clk, reset, q, rx_shifting_done, hold_released ) -begin - if clk'event and clk = '0' then - if (reset = '1') then - left_shift_key <= '0'; - elsif (q(8 downto 1) = LEFT_SHIFT) and - (rx_shifting_done = '1') and - (hold_released = '0') then - left_shift_key <= '1'; - elsif (q(8 downto 1) = LEFT_SHIFT) and - (rx_shifting_done = '1') and - (hold_released = '1') then - left_shift_key <= '0'; - end if; - end if; -end process; - -right_shift_proc : process(clk, reset, q, rx_shifting_done, hold_released ) -begin - if clk'event and clk = '0' then - if (reset = '1') then - right_shift_key <= '0'; - elsif (q(8 downto 1) = RIGHT_SHIFT) and - (rx_shifting_done = '1') and - (hold_released = '0') then - right_shift_key <= '1'; - elsif (q(8 downto 1) = RIGHT_SHIFT) and - (rx_shifting_done = '1') and - (hold_released = '1') then - right_shift_key <= '0'; - end if; - end if; -end process; - -shift_key_on <= left_shift_key or right_shift_key; -rx_shift_key_on <= shift_key_on; - --- --- Control keys --- -ctrl_proc : process(clk, reset, q, rx_shifting_done, hold_released ) -begin - if clk'event and clk = '0' then - if (reset = '1') then - ctrl_key_on <= '0'; - elsif (q(8 downto 1) = CTRL_CODE) and - (rx_shifting_done = '1') and - (hold_released = '0') then - ctrl_key_on <= '1'; - elsif (q(8 downto 1) = CTRL_CODE) and - (rx_shifting_done = '1') and - (hold_released = '1') then - ctrl_key_on <= '0'; - end if; - end if; -end process; - --- --- Caps lock --- -caps_proc : process(clk, reset, q, rx_shifting_done, hold_released, caps_key_on ) -begin - if clk'event and clk = '0' then - if (reset = '1') then - caps_key_on <= '0'; - elsif (q(8 downto 1) = CAPS_CODE) and - (rx_shifting_done = '1') and - (hold_released = '0') then - caps_key_on <= not caps_key_on; - end if; - end if; -end process; - --- Output the special scan code flags, the scan code and the ascii -special_scan_proc : process(clk, reset, - hold_extended, hold_released, - q, ascii, ctrl_key_on ) -begin - if clk'event and clk = '0' then - if (reset = '1') then - rx_extended <= '0'; - rx_released <= '0'; --- rx_scan_code <= "00000000"; - rx_ascii <= "00000000"; - elsif (rx_output_strobe = '1') then - rx_extended <= hold_extended; - rx_released <= hold_released; --- rx_scan_code <= q(8 downto 1); - elsif ctrl_key_on = '1' then - rx_ascii <= ascii and x"1f"; - else - rx_ascii <= ascii; - end if; - end if; -end process; - --- Store the final rx output data only when all extend and release codes --- are received and the next (actual key) scan code is also ready. --- (the presence of rx_extended or rx_released refers to the --- the current latest scan code received, not the previously latched flags.) - -rx_output_proc : process( clk, reset, - rx_shifting_done, rx_output_strobe, - extended, released, - q, ascii, rx_read ) -begin - if (rx_shifting_done = '1') and (extended = '0') and (released = '0') then - rx_output_event <= '1'; - else - rx_output_event <= '0'; - end if; - - if clk'event and clk = '0' then - if reset = '1' then - rx_output_strobe <= '0'; - elsif (rx_shifting_done = '1') and - (rx_output_strobe = '0') and - (extended = '0') and - (released = '0') and - (hold_released = '0' ) and - (ascii /= x"00" ) then --- ((TRAP_SHIFT_KEYS_PP = 0) or --- ( (q(8 downto 1) /= RIGHT_SHIFT) and --- (q(8 downto 1) /= LEFT_SHIFT) and --- (q(8 downto 1) /= CTRL_CODE) ) )then - rx_output_strobe <= '1'; - elsif rx_read = '1' then - rx_output_strobe <= '0'; - end if; - end if; - rx_data_ready <= rx_output_strobe; -end process; - - --- This part translates the scan code into an ASCII value... --- Only the ASCII codes which I considered important have been included. --- if you want more, just add the appropriate case statement lines... --- (You will need to know the keyboard scan codes you wish to assign.) --- The entries are listed in ascending order of ASCII value. -shift_key_plus_code <= shift_key_on & caps_key_on & q(7 downto 1); - ---shift_map : process( shift_key_plus_code ) ---begin --- case shift_key_plus_code is --- when x"066" => ascii <= x"08"; -- Backspace ("backspace" key) --- when x"166" => ascii <= x"08"; -- Backspace ("backspace" key) --- when x"00d" => ascii <= x"09"; -- Horizontal Tab --- when x"10d" => ascii <= x"09"; -- Horizontal Tab --- when x"05a" => ascii <= x"0d"; -- Carriage return ("enter" key) --- when x"15a" => ascii <= x"0d"; -- Carriage return ("enter" key) --- when x"076" => ascii <= x"1b"; -- Escape ("esc" key) --- when x"176" => ascii <= x"1b"; -- Escape ("esc" key) --- when x"029" => ascii <= x"20"; -- Space --- when x"129" => ascii <= x"20"; -- Space --- when x"116" => ascii <= x"21"; -- ! --- when x"152" => ascii <= x"22"; -- " --- when x"126" => ascii <= x"23"; -- # --- when x"125" => ascii <= x"24"; -- $ --- when x"12e" => ascii <= x"25"; -- --- when x"13d" => ascii <= x"26"; -- --- when x"052" => ascii <= x"27"; -- --- when x"146" => ascii <= x"28"; -- --- when x"145" => ascii <= x"29"; -- --- when x"13e" => ascii <= x"2a"; -- * --- when x"155" => ascii <= x"2b"; -- + --- when x"041" => ascii <= x"2c"; -- , --- when x"04e" => ascii <= x"2d"; -- - --- when x"049" => ascii <= x"2e"; -- . --- when x"04a" => ascii <= x"2f"; -- / --- when x"045" => ascii <= x"30"; -- 0 --- when x"016" => ascii <= x"31"; -- 1 --- when x"01e" => ascii <= x"32"; -- 2 --- when x"026" => ascii <= x"33"; -- 3 --- when x"025" => ascii <= x"34"; -- 4 --- when x"02e" => ascii <= x"35"; -- 5 --- when x"036" => ascii <= x"36"; -- 6 --- when x"03d" => ascii <= x"37"; -- 7 --- when x"03e" => ascii <= x"38"; -- 8 --- when x"046" => ascii <= x"39"; -- 9 --- when x"14c" => ascii <= x"3a"; -- : --- when x"04c" => ascii <= x"3b"; -- ; --- when x"141" => ascii <= x"3c"; -- < --- when x"055" => ascii <= x"3d"; -- = --- when x"149" => ascii <= x"3e"; -- > --- when x"14a" => ascii <= x"3f"; -- ? --- when x"11e" => ascii <= x"40"; -- @ --- when x"11c" => ascii <= x"41"; -- A --- when x"132" => ascii <= x"42"; -- B --- when x"121" => ascii <= x"43"; -- C --- when x"123" => ascii <= x"44"; -- D --- when x"124" => ascii <= x"45"; -- E --- when x"12b" => ascii <= x"46"; -- F --- when x"134" => ascii <= x"47"; -- G --- when x"133" => ascii <= x"48"; -- H --- when x"143" => ascii <= x"49"; -- I --- when x"13b" => ascii <= x"4a"; -- J --- when x"142" => ascii <= x"4b"; -- K --- when x"14b" => ascii <= x"4c"; -- L --- when x"13a" => ascii <= x"4d"; -- M --- when x"131" => ascii <= x"4e"; -- N --- when x"144" => ascii <= x"4f"; -- O --- when x"14d" => ascii <= x"50"; -- P --- when x"115" => ascii <= x"51"; -- Q --- when x"12d" => ascii <= x"52"; -- R --- when x"11b" => ascii <= x"53"; -- S --- when x"12c" => ascii <= x"54"; -- T --- when x"13c" => ascii <= x"55"; -- U --- when x"12a" => ascii <= x"56"; -- V --- when x"11d" => ascii <= x"57"; -- W --- when x"122" => ascii <= x"58"; -- X --- when x"135" => ascii <= x"59"; -- Y --- when x"11a" => ascii <= x"5a"; -- Z --- when x"054" => ascii <= x"5b"; -- [ --- when x"05d" => ascii <= x"5c"; -- \ --- when x"05b" => ascii <= x"5d"; -- ] --- when x"136" => ascii <= x"5e"; -- ^ --- when x"14e" => ascii <= x"5f"; -- _ --- when x"00e" => ascii <= x"60"; -- ` --- when x"01c" => ascii <= x"61"; -- a --- when x"032" => ascii <= x"62"; -- b --- when x"021" => ascii <= x"63"; -- c --- when x"023" => ascii <= x"64"; -- d --- when x"024" => ascii <= x"65"; -- e --- when x"02b" => ascii <= x"66"; -- f --- when x"034" => ascii <= x"67"; -- g --- when x"033" => ascii <= x"68"; -- h --- when x"043" => ascii <= x"69"; -- i --- when x"03b" => ascii <= x"6a"; -- j --- when x"042" => ascii <= x"6b"; -- k --- when x"04b" => ascii <= x"6c"; -- l --- when x"03a" => ascii <= x"6d"; -- m --- when x"031" => ascii <= x"6e"; -- n --- when x"044" => ascii <= x"6f"; -- o --- when x"04d" => ascii <= x"70"; -- p --- when x"015" => ascii <= x"71"; -- q --- when x"02d" => ascii <= x"72"; -- r --- when x"01b" => ascii <= x"73"; -- s --- when x"02c" => ascii <= x"74"; -- t --- when x"03c" => ascii <= x"75"; -- u --- when x"02a" => ascii <= x"76"; -- v --- when x"01d" => ascii <= x"77"; -- w --- when x"022" => ascii <= x"78"; -- x --- when x"035" => ascii <= x"79"; -- y --- when x"01a" => ascii <= x"7a"; -- z --- when x"154" => ascii <= x"7b"; -- { --- when x"15d" => ascii <= x"7c"; -- | --- when x"15b" => ascii <= x"7d"; -- } --- when x"10e" => ascii <= x"7e"; -- ~ --- when x"071" => ascii <= x"7f"; -- (Delete OR DEL on numeric keypad) --- when x"171" => ascii <= x"7f"; -- (Delete OR DEL on numeric keypad) --- when others => ascii <= x"ff"; -- 0xff used for unlisted characters. --- end case; ---end process; - -end my_ps2_keyboard; Index: trunk/rtl/System09_Terasic_DE1/System09.vhd =================================================================== --- trunk/rtl/System09_Terasic_DE1/System09.vhd (revision 115) +++ trunk/rtl/System09_Terasic_DE1/System09.vhd (nonexistent) @@ -1,939 +0,0 @@ ---===========================================================================---- --- --- S Y N T H E Z I A B L E System09 - SOC. --- --- www.OpenCores.Org - September 2003 --- This core adheres to the GNU public license --- --- File name : System09.vhd --- --- Purpose : Top level file for 6809 compatible system on a chip --- Designed with Xilinx XC2S300e Spartan 2+ FPGA. --- Implemented With BurchED B5-X300 FPGA board, --- B5-SRAM module, B5-CF module and B5-FPGA-CPU-IO module --- --- Dependencies : ieee.Std_Logic_1164 --- ieee.std_logic_unsigned --- ieee.std_logic_arith --- ieee.numeric_std --- --- Uses : --- cpu09 (cpu09.vhd) CPU core --- mon_rom (kbug_rom_b4.vhd) Monitor ROM --- dat_ram (datram.vhd) Dynamic Address Translation --- miniuart (minitUART3.vhd) ACIA / MiniUART --- (rxunit3.vhd) --- (tx_unit3.vhd) --- keyboard (keyboard.vhd) PS/2 Keyboard Interface --- vdu (vdu8.vhd) 80 x 25 Video Display --- timer (timer.vhd) Timer module --- trap (trap.vhd) Bus Trap interrupt --- ioport (ioport.vhd) Parallel I/O port. --- --- Author : John E. Kent --- dilbert57@opencores.org --- ---===========================================================================---- --- --- Revision History: ---===========================================================================-- --- Version 0.1 - 20 March 2003 --- Version 0.2 - 30 March 2003 --- Version 0.3 - 29 April 2003 --- Version 0.4 - 29 June 2003 --- --- Version 0.5 - 19 July 2003 --- prints out "Hello World" --- --- Version 0.6 - 5 September 2003 --- Runs SBUG --- --- Version 1.0- 6 Sep 2003 - John Kent --- Inverted SysClk --- Initial release to Open Cores --- --- Version 1.1 - 17 Jan 2004 - John Kent --- Updated miniUart. --- --- Version 1.2 - 25 Jan 2004 - John Kent --- removed signals "test_alu" and "test_cc" --- Trap hardware re-instated. --- --- Version 1.3 - 11 Feb 2004 - John Kent --- Designed forked off to produce System09_VDU --- Added VDU component --- VDU runs at 25MHz and divides the clock by 2 for the CPU --- UART Runs at 57.6 Kbps --- --- Version 1.4 - 21 Nov 2004 - John Kent --- Changes to make compatible with Spartan3 starter kit version --- Designed to run with a 50MHz clock input. --- the VDU divides 50 MHz to generate a --- 25 MHz VDU Pixel Clock and a 12.5 MHz CPU clock --- Changed Monitor ROM signals to make it look like --- a standard 2K memory block --- Re-assigned I/O port assignments so it is possible to run KBUG9 --- $E000 - ACIA --- $E010 - Keyboard --- $E020 - VDU --- $E030 - Compact Flash --- $E040 - Timer --- $E050 - Bus trap --- $E060 - Parallel I/O --- ---===========================================================================-- -library ieee; - use ieee.std_logic_1164.all; - use IEEE.STD_LOGIC_UNSIGNED.ALL; - use ieee.numeric_std.all; - -entity My_System09 is - port( - SysClk : in Std_Logic; -- System Clock input - Reset_n : in Std_logic; -- Master Reset input (active low) - LED : out std_logic; -- Diagnostic LED Flasher - - -- Memory Interface signals - ram_csn : out Std_Logic; - ram_wrln : out Std_Logic; - ram_wrun : out Std_Logic; - ram_addr : out Std_Logic_Vector(16 downto 0); - ram_data_i : in std_logic_vector(15 downto 0); - ram_data_o : out std_logic_vector(15 downto 0); - - -- Stuff on the peripheral board - - -- PS/2 Keyboard - kb_clock : inout Std_logic; - kb_data : inout Std_Logic; - - -- PS/2 Mouse interface --- mouse_clock : in Std_Logic; --- mouse_data : in Std_Logic; - - -- Uart Interface - rxbit : in Std_Logic; - txbit : out Std_Logic; - rts_n : out Std_Logic; - cts_n : in Std_Logic; - - -- CRTC output signals - v_drive : out Std_Logic; - h_drive : out Std_Logic; - blue_lo : out std_logic; - blue_hi : out std_logic; - green_lo : out std_logic; - green_hi : out std_logic; - red_lo : out std_logic; - red_hi : out std_logic; --- buzzer : out std_logic; - --- Compact Flash - cf_rst_n : out std_logic; - cf_cs0_n : out std_logic; - cf_cs1_n : out std_logic; - cf_rd_n : out std_logic; - cf_wr_n : out std_logic; - cf_cs16_n : out std_logic; - cf_a : out std_logic_vector(2 downto 0); - cf_d : inout std_logic_vector(15 downto 0); - --- Parallel I/O port - porta : inout std_logic_vector(7 downto 0); - portb : inout std_logic_vector(7 downto 0); - --- CPU bus - bus_clk : out std_logic; - bus_reset : out std_logic; - bus_rw : out std_logic; - bus_cs : out std_logic; - bus_addr : out std_logic_vector(15 downto 0); - bus_data : inout std_logic_vector(7 downto 0); - --- timer - timer_out : out std_logic - ); -end My_System09; - -------------------------------------------------------------------------------- --- Architecture for System09 -------------------------------------------------------------------------------- -architecture my_computer of My_System09 is - ----------------------------------------------------------------------------- - -- Signals - ----------------------------------------------------------------------------- - -- Monitor ROM - signal rom_data_out : Std_Logic_Vector(7 downto 0); - signal rom_cs : std_logic; - - -- UART Interface signals - signal uart_data_out : Std_Logic_Vector(7 downto 0); - signal uart_cs : Std_Logic; - signal uart_irq : Std_Logic; - signal baudclk : Std_Logic; - signal DCD_n : Std_Logic; - - -- timer - signal timer_data_out : std_logic_vector(7 downto 0); - signal timer_cs : std_logic; - signal timer_irq : std_logic; - - -- trap - signal trap_cs : std_logic; - signal trap_data_out : std_logic_vector(7 downto 0); - signal trap_irq : std_logic; - - -- Parallel I/O port - signal ioport_data_out : std_logic_vector(7 downto 0); - signal ioport_cs : std_logic; - - -- compact flash port - signal cf_data_out : std_logic_vector(7 downto 0); - signal cf_cs : std_logic; - signal cf_rd : std_logic; - signal cf_wr : std_logic; - - -- keyboard port - signal keyboard_data_out : std_logic_vector(7 downto 0); - signal keyboard_cs : std_logic; - signal keyboard_irq : std_logic; - - -- RAM - signal ram_cs : std_logic; -- memory chip select - signal ram_wrl : std_logic; -- memory write lower - signal ram_wru : std_logic; -- memory write upper - signal ram_data_out : std_logic_vector(7 downto 0); - - -- CPU Interface signals - signal cpu_reset : Std_Logic; - signal cpu_clk : Std_Logic; - signal cpu_rw : std_logic; - signal cpu_vma : std_logic; - signal cpu_halt : std_logic; - signal cpu_hold : std_logic; - signal cpu_firq : std_logic; - signal cpu_irq : std_logic; - signal cpu_nmi : std_logic; - signal cpu_addr : std_logic_vector(15 downto 0); - signal cpu_data_in : std_logic_vector(7 downto 0); - signal cpu_data_out : std_logic_vector(7 downto 0); - - -- Dynamic address translation - signal dat_cs : std_logic; - signal dat_addr : std_logic_vector(7 downto 0); - - -- Video Display Unit - signal vdu_cs : std_logic; - signal vdu_data_out : std_logic_vector(7 downto 0); - signal vga_red : std_logic; - signal vga_green : std_logic; - signal vga_blue : std_logic; - - -- Flashing Led test signals - signal countL : std_logic_vector(23 downto 0); - signal BaudCount : std_logic_vector(5 downto 0); - ------------------------------------------------------------------ --- --- CPU09 CPU core --- ------------------------------------------------------------------ - -component cpu09 - port ( - clk: in std_logic; - rst: in std_logic; - rw: out std_logic; -- Asynchronous memory interface - vma: out std_logic; - address: out std_logic_vector(15 downto 0); - data_in: in std_logic_vector(7 downto 0); - data_out: out std_logic_vector(7 downto 0); - halt: in std_logic; - hold: in std_logic; - irq: in std_logic; - nmi: in std_logic; - firq: in std_logic - ); -end component; - - ----------------------------------------- --- --- SBUG Block RAM Monitor ROM --- ----------------------------------------- -component mon_rom - port ( - clk : in std_logic; - rst : in std_logic; - cs : in std_logic; - rw : in std_logic; - addr : in std_logic_vector (10 downto 0); - wdata : in std_logic_vector (7 downto 0); - rdata : out std_logic_vector (7 downto 0) - ); -end component; - - ----------------------------------------- --- --- Dynamic Address Translation Registers --- ----------------------------------------- -component dat_ram - port ( - clk: in std_logic; - rst: in std_logic; - cs: in std_logic; - rw: in std_logic; - addr_lo: in std_logic_vector(3 downto 0); - addr_hi: in std_logic_vector(3 downto 0); - data_in: in std_logic_vector(7 downto 0); - data_out: out std_logic_vector(7 downto 0) - ); -end component; - ------------------------------------------------------------------ --- --- Open Cores Mini UART --- ------------------------------------------------------------------ - -component miniUART - port ( - clk : in Std_Logic; -- System Clock - rst : in Std_Logic; -- Reset input (active high) - cs : in Std_Logic; -- miniUART Chip Select - rw : in Std_Logic; -- Read / Not Write - irq : out Std_Logic; -- Interrupt - Addr : in Std_Logic; -- Register Select - DataIn : in Std_Logic_Vector(7 downto 0); -- Data Bus In - DataOut : out Std_Logic_Vector(7 downto 0); -- Data Bus Out - RxC : in Std_Logic; -- Receive Baud Clock - TxC : in Std_Logic; -- Transmit Baud Clock - RxD : in Std_Logic; -- Receive Data - TxD : out Std_Logic; -- Transmit Data - DCD_n : in Std_Logic; -- Data Carrier Detect - CTS_n : in Std_Logic; -- Clear To Send - RTS_n : out Std_Logic ); -- Request To send -end component; - - ----------------------------------------- --- --- Timer module --- ----------------------------------------- - -component timer - port ( - clk : in std_logic; - rst : in std_logic; - cs : in std_logic; - rw : in std_logic; - addr : in std_logic; - data_in : in std_logic_vector(7 downto 0); - data_out : out std_logic_vector(7 downto 0); - irq : out std_logic; - timer_in : in std_logic; - timer_out : out std_logic - ); -end component; - ------------------------------------------------------------- --- --- Bus Trap logic --- ------------------------------------------------------------- - -component trap - port ( - clk : in std_logic; - rst : in std_logic; - cs : in std_logic; - rw : in std_logic; - vma : in std_logic; - addr : in std_logic_vector(15 downto 0); - data_in : in std_logic_vector(7 downto 0); - data_out : out std_logic_vector(7 downto 0); - irq : out std_logic - ); -end component; - ----------------------------------------- --- --- Dual 8 bit Parallel I/O module --- ----------------------------------------- -component ioport - port ( - clk : in std_logic; - rst : in std_logic; - cs : in std_logic; - rw : in std_logic; - addr : in std_logic_vector(1 downto 0); - data_in : in std_logic_vector(7 downto 0); - data_out : out std_logic_vector(7 downto 0); - porta_io : inout std_logic_vector(7 downto 0); - portb_io : inout std_logic_vector(7 downto 0) - ); -end component; - ----------------------------------------- --- --- PS/2 Keyboard --- ----------------------------------------- - -component keyboard - port( - clk : in std_logic; - rst : in std_logic; - cs : in std_logic; - rw : in std_logic; - addr : in std_logic; - data_in : in std_logic_vector(7 downto 0); - data_out : out std_logic_vector(7 downto 0); - irq : out std_logic; - kbd_clk : inout std_logic; - kbd_data : inout std_logic - ); -end component; - ----------------------------------------- --- --- Video Display Unit. --- ----------------------------------------- -component vdu - port( - -- control register interface - vdu_clk_in : in std_logic; - cpu_clk_out : out std_logic; - vdu_rst : in std_logic; - vdu_cs : in std_logic; - vdu_rw : in std_logic; - vdu_addr : in std_logic_vector(2 downto 0); - vdu_data_in : in std_logic_vector(7 downto 0); - vdu_data_out : out std_logic_vector(7 downto 0); - - -- vga port connections - vga_red_o : out std_logic; - vga_green_o : out std_logic; - vga_blue_o : out std_logic; - vga_hsync_o : out std_logic; - vga_vsync_o : out std_logic - ); -end component; - - --- component BUFG --- port ( --- i: in std_logic; --- o: out std_logic --- ); --- end component; - -begin - ----------------------------------------------------------------------------- - -- Instantiation of internal components - ----------------------------------------------------------------------------- - ----------------------------------------- --- --- CPU09 CPU Core --- ----------------------------------------- -my_cpu : cpu09 port map ( - clk => cpu_clk, - rst => cpu_reset, - rw => cpu_rw, - vma => cpu_vma, - address => cpu_addr(15 downto 0), - data_in => cpu_data_in, - data_out => cpu_data_out, - halt => cpu_halt, - hold => cpu_hold, - irq => cpu_irq, - nmi => cpu_nmi, - firq => cpu_firq - ); - ----------------------------------------- --- --- SBUG / KBUG Monitor ROM --- ----------------------------------------- -my_rom : mon_rom port map ( - clk => cpu_clk, - rst => cpu_reset, - cs => rom_cs, - rw => '1', - addr => cpu_addr(10 downto 0), - wdata => cpu_data_out, - rdata => rom_data_out - ); - ----------------------------------------- --- --- Dynamic Address Translation Registers --- ----------------------------------------- -my_dat : dat_ram port map ( - clk => cpu_clk, - rst => cpu_reset, - cs => dat_cs, - rw => cpu_rw, - addr_hi => cpu_addr(15 downto 12), - addr_lo => cpu_addr(3 downto 0), - data_in => cpu_data_out, - data_out => dat_addr(7 downto 0) - ); - ----------------------------------------- --- --- ACIA/UART Serial interface --- ----------------------------------------- -my_uart : miniUART port map ( - clk => cpu_clk, - rst => cpu_reset, - cs => uart_cs, - rw => cpu_rw, - irq => uart_irq, - Addr => cpu_addr(0), - Datain => cpu_data_out, - DataOut => uart_data_out, - RxC => baudclk, - TxC => baudclk, - RxD => rxbit, - TxD => txbit, - DCD_n => dcd_n, - CTS_n => cts_n, - RTS_n => rts_n - ); - ----------------------------------------- --- --- PS/2 Keyboard Interface --- ----------------------------------------- -my_keyboard : keyboard port map( - clk => cpu_clk, - rst => cpu_reset, - cs => keyboard_cs, - rw => cpu_rw, - addr => cpu_addr(0), - data_in => cpu_data_out(7 downto 0), - data_out => keyboard_data_out(7 downto 0), - irq => keyboard_irq, - kbd_clk => kb_clock, - kbd_data => kb_data - ); - ----------------------------------------- --- --- Video Display Unit instantiation --- ----------------------------------------- -my_vdu : vdu port map( - - -- Control Registers - vdu_clk_in => SysClk, -- 50MHz System Clock in - cpu_clk_out => cpu_clk, -- 12.5 MHz CPU clock out - vdu_rst => cpu_reset, - vdu_cs => vdu_cs, - vdu_rw => cpu_rw, - vdu_addr => cpu_addr(2 downto 0), - vdu_data_in => cpu_data_out, - vdu_data_out => vdu_data_out, - - -- vga port connections - vga_red_o => vga_red, - vga_green_o => vga_green, - vga_blue_o => vga_blue, - vga_hsync_o => h_drive, - vga_vsync_o => v_drive - ); - ----------------------------------------- --- --- Timer Module --- ----------------------------------------- -my_timer : timer port map ( - clk => cpu_clk, - rst => cpu_reset, - cs => timer_cs, - rw => cpu_rw, - addr => cpu_addr(0), - data_in => cpu_data_out, - data_out => timer_data_out, - irq => timer_irq, - timer_in => CountL(5), - timer_out => timer_out - ); - ----------------------------------------- --- --- Bus Trap Interrupt logic --- ----------------------------------------- -my_trap : trap port map ( - clk => cpu_clk, - rst => cpu_reset, - cs => trap_cs, - rw => cpu_rw, - vma => cpu_vma, - addr => cpu_addr, - data_in => cpu_data_out, - data_out => trap_data_out, - irq => trap_irq - ); - ----------------------------------------- --- --- Parallel I/O Port --- ----------------------------------------- -my_ioport : ioport port map ( - clk => cpu_clk, - rst => cpu_reset, - cs => ioport_cs, - rw => cpu_rw, - addr => cpu_addr(1 downto 0), - data_in => cpu_data_out, - data_out => ioport_data_out, - porta_io => porta, - portb_io => portb - ); - - --- clk_buffer : BUFG port map( --- i => e_clk, --- o => cpu_clk --- ); - ----------------------------------------------------------------------- --- --- Process to decode memory map --- ----------------------------------------------------------------------- - -mem_decode: process( cpu_clk, Reset_n, - cpu_addr, cpu_rw, cpu_vma, - rom_data_out, - ram_data_out, - cf_data_out, - timer_data_out, - trap_data_out, - ioport_data_out, - uart_data_out, - keyboard_data_out, - vdu_data_out, - bus_data ) -begin - case cpu_addr(15 downto 11) is - -- - -- SBUG/KBUG Monitor ROM $F800 - $FFFF - -- - when "11111" => -- $F800 - $FFFF - cpu_data_in <= rom_data_out; - rom_cs <= cpu_vma; -- read ROM - dat_cs <= cpu_vma; -- write DAT - ram_cs <= '0'; - uart_cs <= '0'; - cf_cs <= '0'; - timer_cs <= '0'; - trap_cs <= '0'; - ioport_cs <= '0'; - keyboard_cs <= '0'; - vdu_cs <= '0'; - bus_cs <= '0'; - - -- - -- IO Devices $E000 - $E7FF - -- - when "11100" => -- $E000 - $E7FF - rom_cs <= '0'; - dat_cs <= '0'; - ram_cs <= '0'; - case cpu_addr(7 downto 4) is - -- - -- UART / ACIA $E000 - -- - when "0000" => -- $E000 - cpu_data_in <= uart_data_out; - uart_cs <= cpu_vma; - cf_cs <= '0'; - timer_cs <= '0'; - trap_cs <= '0'; - ioport_cs <= '0'; - keyboard_cs <= '0'; - vdu_cs <= '0'; - bus_cs <= '0'; - - -- - -- Keyboard port $E010 - $E01F - -- - when "0001" => -- $E010 - cpu_data_in <= keyboard_data_out; - uart_cs <= '0'; - cf_cs <= '0'; - timer_cs <= '0'; - trap_cs <= '0'; - ioport_cs <= '0'; - keyboard_cs <= cpu_vma; - vdu_cs <= '0'; - bus_cs <= '0'; - - -- - -- VDU port $E020 - $E02F - -- - when "0010" => -- $E020 - cpu_data_in <= vdu_data_out; - uart_cs <= '0'; - cf_cs <= '0'; - timer_cs <= '0'; - trap_cs <= '0'; - ioport_cs <= '0'; - keyboard_cs <= '0'; - vdu_cs <= cpu_vma; - bus_cs <= '0'; - - - -- - -- Compact Flash $E030 - $E03F - -- - when "0011" => -- $E030 - cpu_data_in <= cf_data_out; - uart_cs <= '0'; - cf_cs <= cpu_vma; - timer_cs <= '0'; - trap_cs <= '0'; - ioport_cs <= '0'; - keyboard_cs <= '0'; - vdu_cs <= '0'; - bus_cs <= '0'; - - -- - -- Timer $E040 - $E04F - -- - when "0100" => -- $E040 - cpu_data_in <= timer_data_out; - uart_cs <= '0'; - cf_cs <= '0'; - timer_cs <= cpu_vma; - trap_cs <= '0'; - ioport_cs <= '0'; - keyboard_cs <= '0'; - vdu_cs <= '0'; - bus_cs <= '0'; - - -- - -- Bus Trap Logic $E050 - $E05F - -- - when "0101" => -- $E050 - cpu_data_in <= trap_data_out; - uart_cs <= '0'; - cf_cs <= '0'; - timer_cs <= '0'; - trap_cs <= cpu_vma; - ioport_cs <= '0'; - keyboard_cs <= '0'; - vdu_cs <= '0'; - bus_cs <= '0'; - - -- - -- I/O port $E060 - $E06F - -- - when "0110" => -- $E060 - cpu_data_in <= ioport_data_out; - uart_cs <= '0'; - cf_cs <= '0'; - timer_cs <= '0'; - trap_cs <= '0'; - ioport_cs <= cpu_vma; - keyboard_cs <= '0'; - vdu_cs <= '0'; - bus_cs <= '0'; - - when others => -- $E070 to $E7FF - cpu_data_in <= bus_data; - uart_cs <= '0'; - cf_cs <= '0'; - timer_cs <= '0'; - trap_cs <= '0'; - ioport_cs <= '0'; - keyboard_cs <= '0'; - vdu_cs <= '0'; - bus_cs <= cpu_vma; - end case; - -- - -- Everything else is RAM - -- - when others => - cpu_data_in <= ram_data_out; - rom_cs <= '0'; - dat_cs <= '0'; - ram_cs <= cpu_vma; - uart_cs <= '0'; - cf_cs <= '0'; - timer_cs <= '0'; - trap_cs <= '0'; - ioport_cs <= '0'; - keyboard_cs <= '0'; - vdu_cs <= '0'; - bus_cs <= '0'; - end case; -end process; - - --- --- B5-SRAM Control --- Processes to read and write memory based on bus signals --- -ram_process: process( cpu_clk, Reset_n, - cpu_addr, cpu_rw, cpu_vma, cpu_data_out, - dat_addr, - ram_cs, ram_wrl, ram_wru, ram_data_out ) -begin - ram_csn <= not( ram_cs and Reset_n ); - -- use ram_wrl *ONLY* for 8-bit SRAM read/write - --ram_wrl <= (not cpu_addr(0)) and (not cpu_rw) and cpu_clk; - ram_wrl <= (not cpu_rw) and cpu_clk; - ram_wrln <= not (ram_wrl); - --ram_wru <= cpu_addr(0) and (not cpu_rw) and cpu_clk; - --ram_wrun <= not (ram_wru); - ram_wrun <= '1'; - --ram_addr(16 downto 11) <= dat_addr(5 downto 0); - --ram_addr(10 downto 0) <= cpu_addr(11 downto 1); - ram_addr(16 downto 12) <= dat_addr(4 downto 0); - ram_addr(11 downto 0) <= cpu_addr(11 downto 0); - - --if ram_wrl = '1' then - ram_data_o <= std_logic_vector(resize(unsigned(cpu_data_out), ram_data_o'length)); - --else - -- ram_data(7 downto 0) <= "ZZZZZZZZ"; - --end if; - - --if ram_wru = '1' then - -- ram_data(15 downto 8) <= cpu_data_out; - --else - -- ram_data(15 downto 8) <= "ZZZZZZZZ"; - -- end if; - - --if cpu_addr(0) = '1' then - -- ram_data_out <= ram_data(15 downto 8); - --else - ram_data_out <= ram_data_i(7 downto 0); - --end if; -end process; - --- --- Compact Flash Control --- -compact_flash: process( cpu_clk, Reset_n, - cpu_addr, cpu_rw, cpu_vma, cpu_data_out, - cf_cs, cf_rd, cf_wr, cf_data_out ) -begin - cf_rst_n <= Reset_n; - cf_cs0_n <= not( cf_cs ) or cpu_addr(3); - cf_cs1_n <= not( cf_cs and cpu_addr(3)); - cf_cs16_n <= '1'; - cf_wr <= cf_cs and (not cpu_rw); - cf_rd <= cf_cs and cpu_rw; - cf_wr_n <= not cf_wr; - cf_rd_n <= not cf_rd; - cf_a <= cpu_addr(2 downto 0); - if cf_wr = '1' then - cf_d(7 downto 0) <= cpu_data_out; - else - cf_d(7 downto 0) <= "ZZZZZZZZ"; - end if; - cf_data_out <= cf_d(7 downto 0); - cf_d(15 downto 8) <= "ZZZZZZZZ"; -end process; - --- --- Interrupts and other bus control signals --- -interrupts : process( Reset_n, uart_irq, - trap_irq, timer_irq, keyboard_irq - ) -begin - cpu_reset <= not Reset_n; -- CPU reset is active high - cpu_irq <= uart_irq or keyboard_irq; - cpu_nmi <= trap_irq; - cpu_firq <= timer_irq; - cpu_halt <= '0'; - cpu_hold <= '0'; -end process; - --- --- CPU bus signals --- -my_bus : process( cpu_clk, cpu_reset, cpu_rw, cpu_addr, cpu_data_out ) -begin - bus_clk <= cpu_clk; - bus_reset <= cpu_reset; - bus_rw <= cpu_rw; - bus_addr <= cpu_addr; - if( cpu_rw = '1' ) then - bus_data <= "ZZZZZZZZ"; - else - bus_data <= cpu_data_out; - end if; -end process; - - -- - -- flash led to indicate code is working - -- -increment: process (SysClk, CountL ) -begin - if(SysClk'event and SysClk = '0') then - countL <= countL + 1; - end if; - LED <= countL(23); - dcd_n <= '0'; -end process; - --- --- Baud Rate Clock Divider --- --- 25MHz / 27 = 926,000 KHz = 57,870Bd * 16 --- 50MHz / 54 = 926,000 KHz = 57,870Bd * 16 --- -my_clock: process( SysClk ) -begin - if(SysClk'event and SysClk = '0') then - if( BaudCount = 53 ) then - baudclk <= '0'; - BaudCount <= "000000"; - else - if( BaudCount = 26 ) then - baudclk <='1'; - else - baudclk <=baudclk; - end if; - BaudCount <= BaudCount + 1; - end if; - end if; -end process; - --- --- Assign VDU VGA colour output --- only 8 colours are handled. --- -my_vga_out: process( vga_red, vga_green, vga_blue ) -begin - red_lo <= vga_red; - red_hi <= vga_red; - green_lo <= vga_green; - green_hi <= vga_green; - blue_lo <= vga_blue; - blue_hi <= vga_blue; -end process; - -end my_computer; --===================== End of architecture =======================-- - Index: trunk/rtl/System09_Terasic_DE1/project_pkg.vhd =================================================================== --- trunk/rtl/System09_Terasic_DE1/project_pkg.vhd (revision 115) +++ trunk/rtl/System09_Terasic_DE1/project_pkg.vhd (nonexistent) @@ -1,39 +0,0 @@ -library ieee; -use ieee.std_logic_1164.all; -use ieee.std_logic_unsigned.all; - -library work; -use work.pace_pkg.all; -use work.video_controller_pkg.all; -use work.target_pkg.all; - -package project_pkg is - - -- - -- PACE constants which *MUST* be defined - -- - - constant PACE_HAS_PLL : boolean := true; - constant PACE_HAS_FLASH : boolean := false; - constant PACE_HAS_SRAM : boolean := true; - constant PACE_HAS_SDRAM : boolean := false; - constant PACE_HAS_SERIAL : boolean := false; - - constant PACE_JAMMA : PACEJamma_t := PACE_JAMMA_NONE; - - constant PACE_VIDEO_CONTROLLER_TYPE : PACEVideoController_t := PACE_VIDEO_NONE; - - -- Reference clock is 50MHz - constant PACE_CLK0_DIVIDE_BY : natural := 1; - constant PACE_CLK0_MULTIPLY_BY : natural := 1; -- 50*1/1 = 50MHz - constant PACE_CLK1_DIVIDE_BY : natural := 1; - constant PACE_CLK1_MULTIPLY_BY : natural := 1; -- 24MHz (not used) - - -- System09-specific constants - - --constant SYSTEM09_CPU_CLK_ENA_DIVIDE_BY : natural := 10; - --constant SYSTEM09_1MHz_CLK0_COUNTS : natural := 30; - - --constant USE_VIDEO_VBLANK_INTERRUPT : boolean := true; - -end; Index: trunk/rtl/System09_Terasic_DE1/system09.qpf =================================================================== --- trunk/rtl/System09_Terasic_DE1/system09.qpf (revision 115) +++ trunk/rtl/System09_Terasic_DE1/system09.qpf (nonexistent) @@ -1,23 +0,0 @@ -# Copyright (C) 1991-2005 Altera Corporation -# Your use of Altera Corporation's design tools, logic functions -# and other software and tools, and its AMPP partner logic -# functions, and any output files any of the foregoing -# (including device programming or simulation files), and any -# associated documentation or information are expressly subject -# to the terms and conditions of the Altera Program License -# Subscription Agreement, Altera MegaCore Function License -# Agreement, or other applicable license agreement, including, -# without limitation, that your use is for the sole purpose of -# programming logic devices manufactured by Altera and sold by -# Altera or its authorized distributors. Please refer to the -# applicable agreement for further details. - - - -QUARTUS_VERSION = "5.0" -DATE = "19:21:54 August 25, 2005" - - -# Revisions - -PROJECT_REVISION = "system09" Index: trunk/rtl/Cyclone2/sys09bug_rom_waveforms.html =================================================================== --- trunk/rtl/Cyclone2/sys09bug_rom_waveforms.html (revision 115) +++ trunk/rtl/Cyclone2/sys09bug_rom_waveforms.html (nonexistent) @@ -1,13 +0,0 @@ - - -Sample Waveforms for sys09bug_rom.vhd - - -

Sample behavioral waveforms for design file sys09bug_rom.vhd

-

The following waveforms show the behavior of altsyncram megafunction for the chosen set of parameters in design sys09bug_rom.vhd. For the purpose of this simulation, the contents of the memory at the start of the sample waveforms is assumed to be ( F0, F1, F2, F3, ...). The design sys09bug_rom.vhd has one read port. The read port has 4096 words of 8 bits each. The ram block type of the design is M4K. The output of the read port is registered by clock.

-
-

Fig. 1 : Wave showing read operation.

-

The above waveform shows the behavior of the design under normal read conditions. The read happens at the rising edge of the enabled clock cycle. The output from the RAM is undefined until after the first rising edge of the read clock. The clock enable on the read side input registers are disabled. The clock enable on the output registers are disabled.

-

- - Index: trunk/rtl/Cyclone2/template.vhd =================================================================== --- trunk/rtl/Cyclone2/template.vhd (revision 115) +++ trunk/rtl/Cyclone2/template.vhd (nonexistent) @@ -1,32 +0,0 @@ -LIBRARY ieee; -USE ieee.std_logic_1164.all; - -ENTITY mon_rom IS - PORT ( - cs : IN STD_LOGIC; - addr : IN STD_LOGIC_VECTOR (7 DOWNTO 0); - data_out : OUT STD_LOGIC_VECTOR (14 DOWNTO 0)); -END mon_rom; - -ARCHITECTURE behavior OF mon_rom IS - -COMPONENT asyn_rom_256x15 --- pragma translate_off - GENERIC (LPM_FILE : string); - --- pragma translate_on - PORT ( - Address : IN STD_LOGIC_VECTOR(7 DOWNTO 0); - MemEnab : IN STD_LOGIC; - Q : OUT STD_LOGIC_VECTOR(14 DOWNTO 0) - ); -END COMPONENT; - -BEGIN - - u1: asyn_rom_256x15 --- pragma translate_off - GENERIC MAP (LPM_FILE => "u1.hex") --- pragma translate_on - PORT MAP (Address => addr, MemEnab => memenab, Q =>q); -END behavior; Index: trunk/rtl/Cyclone2/sys09bug_rom.qip =================================================================== --- trunk/rtl/Cyclone2/sys09bug_rom.qip (revision 115) +++ trunk/rtl/Cyclone2/sys09bug_rom.qip (nonexistent) @@ -1,7 +0,0 @@ -set_global_assignment -name IP_TOOL_NAME "ROM: 1-PORT" -set_global_assignment -name IP_TOOL_VERSION "9.0" -set_global_assignment -name VHDL_FILE [file join $::quartus(qip_path) "sys09bug_rom.vhd"] -set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "sys09bug_rom.bsf"] -set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "sys09bug_rom_inst.vhd"] -set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "sys09bug_rom.inc"] -set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "sys09bug_rom.cmp"] Index: trunk/rtl/Cyclone2/sys09bug_rom.vhd =================================================================== --- trunk/rtl/Cyclone2/sys09bug_rom.vhd (revision 115) +++ trunk/rtl/Cyclone2/sys09bug_rom.vhd (nonexistent) @@ -1,171 +0,0 @@ --- megafunction wizard: %ROM: 1-PORT% --- GENERATION: STANDARD --- VERSION: WM1.0 --- MODULE: altsyncram - --- ============================================================ --- File Name: sys09bug_rom.vhd --- Megafunction Name(s): --- altsyncram --- --- Simulation Library Files(s): --- altera_mf --- ============================================================ --- ************************************************************ --- THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE! --- --- 9.0 Build 235 06/17/2009 SP 2 SJ Full Version --- ************************************************************ - - ---Copyright (C) 1991-2009 Altera Corporation ---Your use of Altera Corporation's design tools, logic functions ---and other software and tools, and its AMPP partner logic ---functions, and any output files from any of the foregoing ---(including device programming or simulation files), and any ---associated documentation or information are expressly subject ---to the terms and conditions of the Altera Program License ---Subscription Agreement, Altera MegaCore Function License ---Agreement, or other applicable license agreement, including, ---without limitation, that your use is for the sole purpose of ---programming logic devices manufactured by Altera and sold by ---Altera or its authorized distributors. Please refer to the ---applicable agreement for further details. - - -LIBRARY ieee; -USE ieee.std_logic_1164.all; - -LIBRARY altera_mf; -USE altera_mf.all; - -ENTITY sys09bug_rom IS - PORT - ( - address : IN STD_LOGIC_VECTOR (11 DOWNTO 0); - clock : IN STD_LOGIC := '1'; - q : OUT STD_LOGIC_VECTOR (7 DOWNTO 0) - ); -END sys09bug_rom; - - -ARCHITECTURE SYN OF sys09bug_rom IS - - SIGNAL sub_wire0 : STD_LOGIC_VECTOR (7 DOWNTO 0); - - - - COMPONENT altsyncram - GENERIC ( - clock_enable_input_a : STRING; - clock_enable_output_a : STRING; - init_file : STRING; - intended_device_family : STRING; - lpm_hint : STRING; - lpm_type : STRING; - numwords_a : NATURAL; - operation_mode : STRING; - outdata_aclr_a : STRING; - outdata_reg_a : STRING; - ram_block_type : STRING; - widthad_a : NATURAL; - width_a : NATURAL; - width_byteena_a : NATURAL - ); - PORT ( - clock0 : IN STD_LOGIC ; - address_a : IN STD_LOGIC_VECTOR (11 DOWNTO 0); - q_a : OUT STD_LOGIC_VECTOR (7 DOWNTO 0) - ); - END COMPONENT; - -BEGIN - q <= sub_wire0(7 DOWNTO 0); - - altsyncram_component : altsyncram - GENERIC MAP ( - clock_enable_input_a => "BYPASS", - clock_enable_output_a => "BYPASS", - init_file => "sys09bug_c27.hex", - intended_device_family => "Cyclone II", - lpm_hint => "ENABLE_RUNTIME_MOD=NO", - lpm_type => "altsyncram", - numwords_a => 4096, - operation_mode => "ROM", - outdata_aclr_a => "NONE", - outdata_reg_a => "CLOCK0", - ram_block_type => "M4K", - widthad_a => 12, - width_a => 8, - width_byteena_a => 1 - ) - PORT MAP ( - clock0 => clock, - address_a => address, - q_a => sub_wire0 - ); - - - -END SYN; - --- ============================================================ --- CNX file retrieval info --- ============================================================ --- Retrieval info: PRIVATE: ADDRESSSTALL_A NUMERIC "0" --- Retrieval info: PRIVATE: AclrAddr NUMERIC "0" --- Retrieval info: PRIVATE: AclrByte NUMERIC "0" --- Retrieval info: PRIVATE: AclrOutput NUMERIC "0" --- Retrieval info: PRIVATE: BYTE_ENABLE NUMERIC "0" --- Retrieval info: PRIVATE: BYTE_SIZE NUMERIC "8" --- Retrieval info: PRIVATE: BlankMemory NUMERIC "0" --- Retrieval info: PRIVATE: CLOCK_ENABLE_INPUT_A NUMERIC "0" --- Retrieval info: PRIVATE: CLOCK_ENABLE_OUTPUT_A NUMERIC "0" --- Retrieval info: PRIVATE: Clken NUMERIC "0" --- Retrieval info: PRIVATE: IMPLEMENT_IN_LES NUMERIC "0" --- Retrieval info: PRIVATE: INIT_FILE_LAYOUT STRING "PORT_A" --- Retrieval info: PRIVATE: INIT_TO_SIM_X NUMERIC "0" --- Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone II" --- Retrieval info: PRIVATE: JTAG_ENABLED NUMERIC "0" --- Retrieval info: PRIVATE: JTAG_ID STRING "NONE" --- Retrieval info: PRIVATE: MAXIMUM_DEPTH NUMERIC "0" --- Retrieval info: PRIVATE: MIFfilename STRING "sys09bug_c27.hex" --- Retrieval info: PRIVATE: NUMWORDS_A NUMERIC "4096" --- Retrieval info: PRIVATE: RAM_BLOCK_TYPE NUMERIC "2" --- Retrieval info: PRIVATE: RegAddr NUMERIC "1" --- Retrieval info: PRIVATE: RegOutput NUMERIC "1" --- Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0" --- Retrieval info: PRIVATE: SingleClock NUMERIC "1" --- Retrieval info: PRIVATE: UseDQRAM NUMERIC "0" --- Retrieval info: PRIVATE: WidthAddr NUMERIC "12" --- Retrieval info: PRIVATE: WidthData NUMERIC "8" --- Retrieval info: PRIVATE: rden NUMERIC "0" --- Retrieval info: CONSTANT: CLOCK_ENABLE_INPUT_A STRING "BYPASS" --- Retrieval info: CONSTANT: CLOCK_ENABLE_OUTPUT_A STRING "BYPASS" --- Retrieval info: CONSTANT: INIT_FILE STRING "sys09bug_c27.hex" --- Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone II" --- Retrieval info: CONSTANT: LPM_HINT STRING "ENABLE_RUNTIME_MOD=NO" --- Retrieval info: CONSTANT: LPM_TYPE STRING "altsyncram" --- Retrieval info: CONSTANT: NUMWORDS_A NUMERIC "4096" --- Retrieval info: CONSTANT: OPERATION_MODE STRING "ROM" --- Retrieval info: CONSTANT: OUTDATA_ACLR_A STRING "NONE" --- Retrieval info: CONSTANT: OUTDATA_REG_A STRING "CLOCK0" --- Retrieval info: CONSTANT: RAM_BLOCK_TYPE STRING "M4K" --- Retrieval info: CONSTANT: WIDTHAD_A NUMERIC "12" --- Retrieval info: CONSTANT: WIDTH_A NUMERIC "8" --- Retrieval info: CONSTANT: WIDTH_BYTEENA_A NUMERIC "1" --- Retrieval info: USED_PORT: address 0 0 12 0 INPUT NODEFVAL address[11..0] --- Retrieval info: USED_PORT: clock 0 0 0 0 INPUT VCC clock --- Retrieval info: USED_PORT: q 0 0 8 0 OUTPUT NODEFVAL q[7..0] --- Retrieval info: CONNECT: @address_a 0 0 12 0 address 0 0 12 0 --- Retrieval info: CONNECT: q 0 0 8 0 @q_a 0 0 8 0 --- Retrieval info: CONNECT: @clock0 0 0 0 0 clock 0 0 0 0 --- Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all --- Retrieval info: GEN_FILE: TYPE_NORMAL sys09bug_rom.vhd TRUE --- Retrieval info: GEN_FILE: TYPE_NORMAL sys09bug_rom.inc TRUE --- Retrieval info: GEN_FILE: TYPE_NORMAL sys09bug_rom.cmp TRUE --- Retrieval info: GEN_FILE: TYPE_NORMAL sys09bug_rom.bsf TRUE --- Retrieval info: GEN_FILE: TYPE_NORMAL sys09bug_rom_inst.vhd TRUE --- Retrieval info: GEN_FILE: TYPE_NORMAL sys09bug_rom_waveforms.html TRUE --- Retrieval info: GEN_FILE: TYPE_NORMAL sys09bug_rom_wave*.jpg FALSE --- Retrieval info: LIB_FILE: altera_mf Index: trunk/rtl/Cyclone2/sys09bug_rom_wave0.jpg =================================================================== Cannot display: file marked as a binary type. svn:mime-type = application/octet-stream Index: trunk/rtl/Cyclone2/sys09bug_rom_wave0.jpg =================================================================== --- trunk/rtl/Cyclone2/sys09bug_rom_wave0.jpg (revision 115) +++ trunk/rtl/Cyclone2/sys09bug_rom_wave0.jpg (nonexistent)
trunk/rtl/Cyclone2/sys09bug_rom_wave0.jpg Property changes : Deleted: svn:mime-type ## -1 +0,0 ## -application/octet-stream \ No newline at end of property Index: trunk/rtl/Cyclone2/sys09bug_rom.cmp =================================================================== --- trunk/rtl/Cyclone2/sys09bug_rom.cmp (revision 115) +++ trunk/rtl/Cyclone2/sys09bug_rom.cmp (nonexistent) @@ -1,23 +0,0 @@ ---Copyright (C) 1991-2009 Altera Corporation ---Your use of Altera Corporation's design tools, logic functions ---and other software and tools, and its AMPP partner logic ---functions, and any output files from any of the foregoing ---(including device programming or simulation files), and any ---associated documentation or information are expressly subject ---to the terms and conditions of the Altera Program License ---Subscription Agreement, Altera MegaCore Function License ---Agreement, or other applicable license agreement, including, ---without limitation, that your use is for the sole purpose of ---programming logic devices manufactured by Altera and sold by ---Altera or its authorized distributors. Please refer to the ---applicable agreement for further details. - - -component sys09bug_rom - PORT - ( - address : IN STD_LOGIC_VECTOR (11 DOWNTO 0); - clock : IN STD_LOGIC := '1'; - q : OUT STD_LOGIC_VECTOR (7 DOWNTO 0) - ); -end component; Index: trunk/rtl/Cyclone2/sys09bug_rom.inc =================================================================== --- trunk/rtl/Cyclone2/sys09bug_rom.inc (revision 115) +++ trunk/rtl/Cyclone2/sys09bug_rom.inc (nonexistent) @@ -1,24 +0,0 @@ ---Copyright (C) 1991-2009 Altera Corporation ---Your use of Altera Corporation's design tools, logic functions ---and other software and tools, and its AMPP partner logic ---functions, and any output files from any of the foregoing ---(including device programming or simulation files), and any ---associated documentation or information are expressly subject ---to the terms and conditions of the Altera Program License ---Subscription Agreement, Altera MegaCore Function License ---Agreement, or other applicable license agreement, including, ---without limitation, that your use is for the sole purpose of ---programming logic devices manufactured by Altera and sold by ---Altera or its authorized distributors. Please refer to the ---applicable agreement for further details. - - -FUNCTION sys09bug_rom -( - address[11..0], - clock -) - -RETURNS ( - q[7..0] -); Index: trunk/rtl/Cyclone2/sys09bug_rom.bsf =================================================================== --- trunk/rtl/Cyclone2/sys09bug_rom.bsf (revision 115) +++ trunk/rtl/Cyclone2/sys09bug_rom.bsf (nonexistent) @@ -1,76 +0,0 @@ -/* -WARNING: Do NOT edit the input and output ports in this file in a text -editor if you plan to continue editing the block that represents it in -the Block Editor! File corruption is VERY likely to occur. -*/ -/* -Copyright (C) 1991-2009 Altera Corporation -Your use of Altera Corporation's design tools, logic functions -and other software and tools, and its AMPP partner logic -functions, and any output files from any of the foregoing -(including device programming or simulation files), and any -associated documentation or information are expressly subject -to the terms and conditions of the Altera Program License -Subscription Agreement, Altera MegaCore Function License -Agreement, or other applicable license agreement, including, -without limitation, that your use is for the sole purpose of -programming logic devices manufactured by Altera and sold by -Altera or its authorized distributors. Please refer to the -applicable agreement for further details. -*/ -(header "symbol" (version "1.1")) -(symbol - (rect 0 0 216 136) - (text "sys09bug_rom" (rect 66 1 166 17)(font "Arial" (font_size 10))) - (text "inst" (rect 8 120 25 132)(font "Arial" )) - (port - (pt 0 32) - (input) - (text "address[11..0]" (rect 0 0 82 14)(font "Arial" (font_size 8))) - (text "address[11..0]" (rect 4 19 69 32)(font "Arial" (font_size 8))) - (line (pt 0 32)(pt 88 32)(line_width 3)) - ) - (port - (pt 0 112) - (input) - (text "clock" (rect 0 0 29 14)(font "Arial" (font_size 8))) - (text "clock" (rect 4 99 27 112)(font "Arial" (font_size 8))) - (line (pt 0 112)(pt 144 112)(line_width 1)) - ) - (port - (pt 216 32) - (output) - (text "q[7..0]" (rect 0 0 35 14)(font "Arial" (font_size 8))) - (text "q[7..0]" (rect 183 19 213 32)(font "Arial" (font_size 8))) - (line (pt 216 32)(pt 160 32)(line_width 3)) - ) - (drawing - (text "8 bits" (rect 108 48 120 71)(font "Arial" )(vertical)) - (text "4096 words" (rect 121 36 133 83)(font "Arial" )(vertical)) - (text "Block type: M4K" (rect 41 116 110 128)(font "Arial" )) - (line (pt 104 24)(pt 136 24)(line_width 1)) - (line (pt 136 24)(pt 136 96)(line_width 1)) - (line (pt 136 96)(pt 104 96)(line_width 1)) - (line (pt 104 96)(pt 104 24)(line_width 1)) - (line (pt 118 58)(pt 123 63)(line_width 1)) - (line (pt 118 62)(pt 123 57)(line_width 1)) - (line (pt 152 27)(pt 160 27)(line_width 1)) - (line (pt 160 27)(pt 160 39)(line_width 1)) - (line (pt 160 39)(pt 152 39)(line_width 1)) - (line (pt 152 39)(pt 152 27)(line_width 1)) - (line (pt 152 34)(pt 154 36)(line_width 1)) - (line (pt 154 36)(pt 152 38)(line_width 1)) - (line (pt 144 36)(pt 152 36)(line_width 1)) - (line (pt 136 32)(pt 152 32)(line_width 3)) - (line (pt 88 27)(pt 96 27)(line_width 1)) - (line (pt 96 27)(pt 96 39)(line_width 1)) - (line (pt 96 39)(pt 88 39)(line_width 1)) - (line (pt 88 39)(pt 88 27)(line_width 1)) - (line (pt 88 34)(pt 90 36)(line_width 1)) - (line (pt 90 36)(pt 88 38)(line_width 1)) - (line (pt 80 36)(pt 88 36)(line_width 1)) - (line (pt 96 32)(pt 104 32)(line_width 3)) - (line (pt 80 112)(pt 80 36)(line_width 1)) - (line (pt 144 112)(pt 144 36)(line_width 1)) - ) -) Index: trunk/rtl/Cyclone2/sys09bug_rom_inst.vhd =================================================================== --- trunk/rtl/Cyclone2/sys09bug_rom_inst.vhd (revision 115) +++ trunk/rtl/Cyclone2/sys09bug_rom_inst.vhd (nonexistent) @@ -1,5 +0,0 @@ -sys09bug_rom_inst : sys09bug_rom PORT MAP ( - address => address_sig, - clock => clock_sig, - q => q_sig - ); Index: trunk/rtl/Cyclone2/pll.qip =================================================================== --- trunk/rtl/Cyclone2/pll.qip (nonexistent) +++ trunk/rtl/Cyclone2/pll.qip (revision 116) @@ -0,0 +1,8 @@ +set_global_assignment -name IP_TOOL_NAME "ALTPLL" +set_global_assignment -name IP_TOOL_VERSION "9.1" +set_global_assignment -name VHDL_FILE [file join $::quartus(qip_path) "pll.vhd"] +set_global_assignment -name MISC_FILE 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2033 : B2; + 2034 : FF; + 2035 : C6; + 2036 : FF; + 2037 : B6; + 2038 : FF; + 2039 : BA; + 2040 : FF; + 2041 : BE; + 2042 : FF; + 2043 : C2; + 2044 : F8; + 2045 : 34; + 2046 : F8; + 2047 : 34; +END; Index: trunk/rtl/Cyclone2/sprom.vhd =================================================================== --- trunk/rtl/Cyclone2/sprom.vhd (nonexistent) +++ trunk/rtl/Cyclone2/sprom.vhd (revision 116) @@ -0,0 +1,79 @@ +LIBRARY ieee; +USE ieee.std_logic_1164.all; + +LIBRARY altera_mf; +USE altera_mf.all; + +ENTITY sprom IS + GENERIC + ( + INIT_FILE : string := ""; + WORD_COUNT : natural := 2048; + ADDR_WIDTH : natural := 11; + DATA_WIDTH : natural := 8; + REG_OUT : string := "UNREGISTERED" + ); + PORT + ( + clk : IN STD_LOGIC ; + addr : IN STD_LOGIC_VECTOR (ADDR_WIDTH-1 DOWNTO 0); + data_in : IN STD_LOGIC_VECTOR (DATA_WIDTH-1 DOWNTO 0); + data_out : OUT STD_LOGIC_VECTOR (DATA_WIDTH-1 DOWNTO 0) + ); +END sprom; + +ARCHITECTURE SYN OF sprom IS + + COMPONENT altsyncram + GENERIC ( + clock_enable_input_a : STRING; + clock_enable_output_a : STRING; + init_file : STRING; + intended_device_family : STRING; + lpm_hint : STRING; + lpm_type : STRING; + numwords_a : NATURAL; + operation_mode : STRING; + outdata_aclr_a : STRING; + outdata_reg_a : STRING; + power_up_uninitialized : STRING; + widthad_a : NATURAL; + width_a : NATURAL; + width_byteena_a : NATURAL + ); + PORT ( + clock0 : IN STD_LOGIC ; + wren_a : IN STD_LOGIC ; + address_a : IN STD_LOGIC_VECTOR (ADDR_WIDTH-1 DOWNTO 0); + data_a : IN STD_LOGIC_VECTOR (DATA_WIDTH-1 DOWNTO 0); + q_a : OUT STD_LOGIC_VECTOR (DATA_WIDTH-1 DOWNTO 0) + ); + END COMPONENT; + +BEGIN + + altsyncram_component : altsyncram + GENERIC MAP ( + clock_enable_input_a => "BYPASS", + clock_enable_output_a => "BYPASS", + init_file => INIT_FILE, + intended_device_family => "Cyclone II", + lpm_hint => "ENABLE_RUNTIME_MOD=NO", + lpm_type => "altsyncram", + numwords_a => WORD_COUNT, + operation_mode => "ROM", + outdata_aclr_a => "NONE", + outdata_reg_a => REG_OUT, + power_up_uninitialized => "FALSE", + widthad_a => ADDR_WIDTH, + width_a => DATA_WIDTH, + width_byteena_a => 1 + ) + PORT MAP ( + clock0 => clk, + address_a => addr, + data_a => data_in, + q_a => data_out + ); + +END SYN; Index: trunk/rtl/Cyclone2/keymap_rom.vhd =================================================================== --- trunk/rtl/Cyclone2/keymap_rom.vhd (nonexistent) +++ trunk/rtl/Cyclone2/keymap_rom.vhd (revision 116) @@ -0,0 +1,36 @@ +library ieee; +use ieee.std_logic_1164.all; +use ieee.numeric_std.all; + +entity keymap_rom is + Port ( + clk : in std_logic; + rst : in std_logic; + cs : in std_logic; + rw : in std_logic; + addr : in std_logic_vector (8 downto 0); + data_in : in std_logic_vector (7 downto 0); + data_out : out std_logic_vector (7 downto 0) + ); +end keymap_rom; + +architecture SYN of keymap_rom is +begin + + rom_inst : entity work.sprom + generic map + ( + INIT_FILE => "keymap_rom.mif", + WORD_COUNT => 512, + ADDR_WIDTH => 9 + ) + port map + ( + clk => clk, + addr => addr, + data_in => data_in, + data_out => data_out + ); + +end SYN; + Index: trunk/rtl/Cyclone2/sys09bug_de2-70.hex =================================================================== --- trunk/rtl/Cyclone2/sys09bug_de2-70.hex (nonexistent) +++ trunk/rtl/Cyclone2/sys09bug_de2-70.hex (revision 116) @@ -0,0 +1,129 @@ +:10000000F814F861FCA1FC9BFCC5FCE0FB8FFB1E17 +:10001000FB1AFA2E8EFE74108EDFC0C610A680A7C3 +:10002000A05A26F98EE000BFDFE017015BC60C6F17 +:10003000E25A26FB308CDDAF6A86D0A7E41F431757 +:1000400004B58EFE841703478EDFD04FC60D6D8535 +:1000500027038B04195A2AF617040C8EFEA41703E3 +:100060002E8EFEAB1702B3170437847F810D27F164 +:100070001F8981202C09865E1704651F988B401705 +:10008000045E170459C1602F02C0208EFE3BE18040 +:10009000270F30028CFE7426F58EFEAD1702F0207D +:1000A000C0AD9420BC1F343B17036B292D1F128E4B +:1000B000FEB31702651F211703A5170421A6A41775 +:1000C00003A517041917035E2811810827E1811879 +:1000D00027DD815E2717810D260F39A7A4A1A4274C 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+:1007C000DFC86E9FDFCA1F43AE4AE680AF4A4F586C +:1007D00049BEDFCC8CFFFF270F308BBCDFCE220859 +:1007E0003410ECC4AE446EF1371FEE426E9FDFC290 +:1007F000FFB2FFC6FFB6FFBAFFBEFFC2FFB2FF00E7 +:00000001FF \ No newline at end of file Index: trunk/rtl/Cyclone2/mon_rom.vhd =================================================================== --- trunk/rtl/Cyclone2/mon_rom.vhd (nonexistent) +++ trunk/rtl/Cyclone2/mon_rom.vhd (revision 116) @@ -0,0 +1,35 @@ +library ieee; +use ieee.std_logic_1164.all; +use ieee.numeric_std.all; + +entity mon_rom is + Port ( + clk : in std_logic; + rst : in std_logic; + cs : in std_logic; + rw : in std_logic; + addr : in std_logic_vector (10 downto 0); + data_in : in std_logic_vector (7 downto 0); + data_out : out std_logic_vector (7 downto 0) + ); +end mon_rom; + +architecture SYN of mon_rom is +begin + + rom_inst : entity work.sprom + generic map + ( + INIT_FILE => "sys09bug_de2-70.hex", + WORD_COUNT => 2048, + ADDR_WIDTH => 11 + ) + port map + ( + clk => clk, + addr => addr, + data_in => data_in, + data_out => data_out + ); + +end SYN; Index: trunk/rtl/Cyclone2/ram_2k.vhd =================================================================== --- trunk/rtl/Cyclone2/ram_2k.vhd (nonexistent) +++ trunk/rtl/Cyclone2/ram_2k.vhd (revision 116) @@ -0,0 +1,40 @@ +library ieee; +use ieee.std_logic_1164.all; +use ieee.numeric_std.all; + +entity ram_2k is + Port ( + clk : in std_logic; + rst : in std_logic; + cs : in std_logic; + rw : in std_logic; + addr : in std_logic_vector (10 downto 0); + data_in : in std_logic_vector (7 downto 0); + data_out : out std_logic_vector (7 downto 0) + ); +end ram_2k; + +architecture SYN of ram_2k is +signal we : std_logic; + +begin + + we <= cs and (not rw) and (not rst); + + ram_inst : entity work.spram + generic map + ( + INIT_FILE => "char_rom.mif", + WORD_COUNT => 2048, + ADDR_WIDTH => 11 + ) + port map + ( + clk => clk, + addr => addr, + wren => we, + data_in => data_in, + data_out => data_out + ); + +end SYN; Index: trunk/rtl/Cyclone2/ram2k.vhd =================================================================== --- trunk/rtl/Cyclone2/ram2k.vhd (nonexistent) +++ trunk/rtl/Cyclone2/ram2k.vhd (revision 116) @@ -0,0 +1,83 @@ +LIBRARY ieee; +USE ieee.std_logic_1164.all; + +LIBRARY altera_mf; +USE altera_mf.all; + +ENTITY spram IS + GENERIC + ( + INIT_FILE : string := ""; + WORD_COUNT : natural := 2048; + ADDR_WIDTH : natural := 11; + DATA_WIDTH : natural := 8; + REG_OUT : string := "UNREGISTERED" + ); + PORT + ( + clk : IN STD_LOGIC ; + rst : IN STD_LOGIC ; + cs : IN STD_LOGIC ; + addr : IN STD_LOGIC_VECTOR (ADDR_WIDTH-1 DOWNTO 0); + rw : IN STD_LOGIC ; + data_in : IN STD_LOGIC_VECTOR (DATA_WIDTH-1 DOWNTO 0); + data_out : OUT STD_LOGIC_VECTOR (DATA_WIDTH-1 DOWNTO 0) + ); +END spram; + +ARCHITECTURE SYN OF spram IS + + COMPONENT altsyncram + GENERIC ( + clock_enable_input_a : STRING; + clock_enable_output_a : STRING; + init_file : STRING; + intended_device_family : STRING; + lpm_hint : STRING; + lpm_type : STRING; + numwords_a : NATURAL; + operation_mode : STRING; + outdata_aclr_a : STRING; + outdata_reg_a : STRING; + power_up_uninitialized : STRING; + widthad_a : NATURAL; + width_a : NATURAL; + width_byteena_a : NATURAL + ); + PORT ( + clock0 : IN STD_LOGIC ; + wren_a : IN STD_LOGIC ; + address_a : IN STD_LOGIC_VECTOR (ADDR_WIDTH-1 DOWNTO 0); + data_a : IN STD_LOGIC_VECTOR (DATA_WIDTH-1 DOWNTO 0); + q_a : OUT STD_LOGIC_VECTOR (DATA_WIDTH-1 DOWNTO 0) + ); + END COMPONENT; + +BEGIN + + altsyncram_component : altsyncram + GENERIC MAP ( + clock_enable_input_a => "BYPASS", + clock_enable_output_a => "BYPASS", + init_file => INIT_FILE, + intended_device_family => "Cyclone II", + lpm_hint => "ENABLE_RUNTIME_MOD=NO", + lpm_type => "altsyncram", + numwords_a => WORD_COUNT, + operation_mode => "SINGLE_PORT", + outdata_aclr_a => "NONE", + outdata_reg_a => REG_OUT, + power_up_uninitialized => "FALSE", + widthad_a => ADDR_WIDTH, + width_a => DATA_WIDTH, + width_byteena_a => 1 + ) + PORT MAP ( + wren_a => wren, + clock0 => clk, + address_a => addr, + data_a => data_in, + q_a => data_out + ); + +END SYN; Index: trunk/rtl/Cyclone2/pll.inc =================================================================== --- trunk/rtl/Cyclone2/pll.inc (nonexistent) +++ trunk/rtl/Cyclone2/pll.inc (revision 116) @@ -0,0 +1,27 @@ +--Copyright (C) 1991-2010 Altera Corporation +--Your use of Altera Corporation's design tools, logic functions +--and other software and tools, and its AMPP partner logic +--functions, and any output files from any of the foregoing +--(including device programming or simulation files), and any +--associated documentation or information are expressly subject +--to the terms and conditions of the Altera Program License +--Subscription Agreement, Altera MegaCore Function License +--Agreement, or other applicable license agreement, including, +--without limitation, that your use is for the sole purpose of +--programming logic devices manufactured by Altera and sold by +--Altera or its authorized distributors. Please refer to the +--applicable agreement for further details. + + +FUNCTION pll +( + areset, + inclk0 +) + +RETURNS ( + c0, + c1, + c2, + locked +); Index: trunk/rtl/Cyclone2/wb_lpm_ram.vhd =================================================================== --- trunk/rtl/Cyclone2/wb_lpm_ram.vhd (nonexistent) +++ trunk/rtl/Cyclone2/wb_lpm_ram.vhd (revision 116) @@ -0,0 +1,115 @@ +--===========================================================================-- +-- +-- S Y N T H E Z I A B L E Altera LPM_RAM / WISHBONE interface +-- +-- www.OpenCores.Org - August 2003 +-- This core adheres to the GNU public license +-- +-- File name : wb_lpm_ram.vhd +-- +-- Purpose : Implements a WISHBONE compatble interface +-- for the Altera LPM_ROM +-- +-- Dependencies : ieee.Std_Logic_1164 +-- ieee.std_logic_unsigned +-- work.lpm_components (Altera's 220PACK.vhd) +-- +-- Author : Michael L. Hasenfratz Sr. +-- +--===========================================================================---- +-- +-- Revision History: +-- +-- Date: Revision Author +--===========================================================================-- +-- 4 Aug 2003 0.1 Michael L. Hasenfratz Sr. +-- Created +-- 5 Aug 2003 0.2 Michael L. Hasenfratz Sr. +-- Added Cache check +-- + +library ieee; +use ieee.std_logic_1164.all; +use ieee.std_logic_unsigned.all; + +library lpm; +use lpm.lpm_components.all; + +entity wb_lpm_ram is + generic ( + LPM_WIDTH : positive range 1 to 64 := 8; -- data bits WIDE + LPM_WIDTHAD : positive range 1 to 32 := 8 -- address bits; + ); + port ( + DAT_I : in std_logic_vector(LPM_WIDTH-1 downto 0); + DAT_O : out std_logic_vector(LPM_WIDTH-1 downto 0); + ADR_I : in std_logic_vector(LPM_WIDTHAD-1 downto 0); + SEL_I : in std_logic_vector((LPM_WIDTH/8)-1 downto 0); + WE_I : in std_logic; + STB_I : in std_logic; -- VMA (Valid Memory Access) + CYC_I : in std_logic; -- CYC in progress + ACK_O : out std_logic; -- Data ready + CLK_I : in std_logic; -- System Clock + RST_I : in std_logic -- Reset + ); +end; + +architecture bhv_wb_lpm_ram of wb_lpm_ram is + + signal iwe : std_logic_vector(SEL_I'RANGE); -- Internal Write Enables + signal iack : std_logic; -- Internal ACK + signal sel : std_logic; -- device selected + +begin + +--------------------------------------------------------- +-- Instantiate the RAM interface +--------------------------------------------------------- +gen : for idx in SEL_I'RANGE generate +ram : LPM_RAM_DQ + generic map ( + LPM_WIDTH => 8, + LPM_WIDTHAD => LPM_WIDTHAD, + USE_EAB => "ON", + LPM_OUTDATA => "UNREGISTERED" + ) + port map ( + DATA => DAT_I((idx*8)+7 downto (idx*8)), + Q => DAT_O((idx*8)+7 downto (idx*8)), + WE => iwe(idx), + ADDRESS => ADR_I, + INCLOCK => CLK_I + ); + end generate; + +--------------------------------------------------------- +-- Interconnections +--------------------------------------------------------- + ACK_O <= (iack or WE_I) and sel; + +-- find SEL_(x) +selx : process(SEL_I, CYC_I, STB_I, WE_I) + variable isel : std_logic ; + begin + isel := '0'; + for ndx in SEL_I'RANGE loop + isel := isel or SEL_I(ndx); + iwe(ndx) <= SEL_I(ndx) and WE_I; + end loop; + sel <= isel and CYC_I and STB_I; + end process; + +-- ACK / HOLD +intc0 : process(CLK_I) + begin + if CLK_I'EVENT and CLK_I = '1' then + if RST_I = '1' then + iack <= '0'; + else + iack <= sel and not(iack); + end if; + end if; + end process; + +end bhv_wb_lpm_ram; + Index: trunk/rtl/Cyclone2/pll.bsf =================================================================== --- trunk/rtl/Cyclone2/pll.bsf (nonexistent) +++ trunk/rtl/Cyclone2/pll.bsf (revision 116) @@ -0,0 +1,107 @@ +/* +WARNING: Do NOT edit the input and output ports in this file in a text +editor if you plan to continue editing the block that represents it in +the Block Editor! File corruption is VERY likely to occur. +*/ +/* +Copyright (C) 1991-2010 Altera Corporation +Your use of Altera Corporation's design tools, logic functions +and other software and tools, and its AMPP partner logic +functions, and any output files from any of the foregoing +(including device programming or simulation files), and any +associated documentation or information are expressly subject +to the terms and conditions of the Altera Program License +Subscription Agreement, Altera MegaCore Function License +Agreement, or other applicable license agreement, including, +without limitation, that your use is for the sole purpose of +programming logic devices manufactured by Altera and sold by +Altera or its authorized distributors. Please refer to the +applicable agreement for further details. +*/ +(header "symbol" (version "1.1")) +(symbol + (rect 0 0 264 184) + (text "pll" (rect 126 0 141 16)(font "Arial" (font_size 10))) + (text "inst" (rect 8 168 25 180)(font "Arial" )) + (port + (pt 0 64) + (input) + (text "inclk0" (rect 0 0 31 14)(font "Arial" (font_size 8))) + (text "inclk0" (rect 4 51 31 64)(font "Arial" (font_size 8))) + (line (pt 0 64)(pt 48 64)(line_width 1)) + ) + (port + (pt 0 80) + (input) + (text "areset" (rect 0 0 36 14)(font "Arial" (font_size 8))) + (text "areset" (rect 4 67 32 80)(font "Arial" (font_size 8))) + (line (pt 0 80)(pt 48 80)(line_width 1)) + ) + (port + (pt 264 64) + (output) + (text "c0" (rect 0 0 14 14)(font "Arial" (font_size 8))) + (text "c0" (rect 249 51 260 64)(font "Arial" (font_size 8))) + (line (pt 264 64)(pt 216 64)(line_width 1)) + ) + (port + (pt 264 80) + (output) + (text "c1" (rect 0 0 14 14)(font "Arial" (font_size 8))) + (text "c1" (rect 249 67 260 80)(font "Arial" (font_size 8))) + (line (pt 264 80)(pt 216 80)(line_width 1)) + ) + (port + (pt 264 96) + (output) + (text "c2" (rect 0 0 14 14)(font "Arial" (font_size 8))) + (text "c2" (rect 249 83 260 96)(font "Arial" (font_size 8))) + (line (pt 264 96)(pt 216 96)(line_width 1)) + ) + (port + (pt 264 112) + (output) + (text "locked" (rect 0 0 36 14)(font "Arial" (font_size 8))) + (text "locked" (rect 230 99 260 112)(font "Arial" (font_size 8))) + (line (pt 264 112)(pt 216 112)(line_width 1)) + ) + (drawing + (text "Cyclone II" (rect 207 169 251 181)(font "Arial" )) + (text "inclk0 frequency: 50.000 MHz" (rect 58 59 183 71)(font "Arial" )) + (text "Operation Mode: Normal" (rect 58 73 159 85)(font "Arial" )) + (text "Clk " (rect 59 96 76 108)(font "Arial" )) + (text "Ratio" (rect 81 96 103 108)(font "Arial" )) + (text "Ph (dg)" (rect 108 96 138 108)(font "Arial" )) + (text "DC (%)" (rect 143 96 174 108)(font "Arial" )) + (text "c0" (rect 62 111 72 123)(font "Arial" )) + (text "1/1" (rect 86 111 99 123)(font "Arial" )) + (text "0.00" (rect 114 111 132 123)(font "Arial" )) + (text "50.00" (rect 147 111 170 123)(font "Arial" )) + (text "c1" (rect 62 126 72 138)(font "Arial" )) + (text "1/2" (rect 86 126 99 138)(font "Arial" )) + (text "0.00" (rect 114 126 132 138)(font "Arial" )) + (text "50.00" (rect 147 126 170 138)(font "Arial" )) + (text "c2" (rect 62 141 72 153)(font "Arial" )) + (text "1/2" (rect 86 141 99 153)(font "Arial" )) + (text "0.00" (rect 114 141 132 153)(font "Arial" )) + (text "50.00" (rect 147 141 170 153)(font "Arial" )) + (line (pt 0 0)(pt 265 0)(line_width 1)) + (line (pt 265 0)(pt 265 185)(line_width 1)) + (line (pt 0 185)(pt 265 185)(line_width 1)) + (line (pt 0 0)(pt 0 185)(line_width 1)) + (line (pt 56 94)(pt 176 94)(line_width 1)) + (line (pt 56 108)(pt 176 108)(line_width 1)) + (line (pt 56 123)(pt 176 123)(line_width 1)) + (line (pt 56 138)(pt 176 138)(line_width 1)) + (line (pt 56 153)(pt 176 153)(line_width 1)) + (line (pt 56 94)(pt 56 153)(line_width 1)) + (line (pt 78 94)(pt 78 153)(line_width 3)) + (line (pt 105 94)(pt 105 153)(line_width 3)) + (line (pt 140 94)(pt 140 153)(line_width 3)) + (line (pt 175 94)(pt 175 153)(line_width 1)) + (line (pt 48 48)(pt 216 48)(line_width 1)) + (line (pt 216 48)(pt 216 168)(line_width 1)) + (line (pt 48 168)(pt 216 168)(line_width 1)) + (line (pt 48 48)(pt 48 168)(line_width 1)) + ) +) Index: trunk/rtl/Cyclone2/spram.vhd =================================================================== --- trunk/rtl/Cyclone2/spram.vhd (nonexistent) +++ trunk/rtl/Cyclone2/spram.vhd (revision 116) @@ -0,0 +1,81 @@ +LIBRARY ieee; +USE ieee.std_logic_1164.all; + +LIBRARY altera_mf; +USE altera_mf.all; + +ENTITY spram IS + GENERIC + ( + INIT_FILE : string := ""; + WORD_COUNT : natural := 2048; + ADDR_WIDTH : natural := 11; + DATA_WIDTH : natural := 8; + REG_OUT : string := "UNREGISTERED" + ); + PORT + ( + clk : IN STD_LOGIC ; + addr : IN STD_LOGIC_VECTOR (ADDR_WIDTH-1 DOWNTO 0); + wren : IN STD_LOGIC ; + data_in : IN STD_LOGIC_VECTOR (DATA_WIDTH-1 DOWNTO 0); + data_out : OUT STD_LOGIC_VECTOR (DATA_WIDTH-1 DOWNTO 0) + ); +END spram; + +ARCHITECTURE SYN OF spram IS + + COMPONENT altsyncram + GENERIC ( + clock_enable_input_a : STRING; + clock_enable_output_a : STRING; + init_file : STRING; + intended_device_family : STRING; + lpm_hint : STRING; + lpm_type : STRING; + numwords_a : NATURAL; + operation_mode : STRING; + outdata_aclr_a : STRING; + outdata_reg_a : STRING; + power_up_uninitialized : STRING; + widthad_a : NATURAL; + width_a : NATURAL; + width_byteena_a : NATURAL + ); + PORT ( + clock0 : IN STD_LOGIC ; + wren_a : IN STD_LOGIC ; + address_a : IN STD_LOGIC_VECTOR (ADDR_WIDTH-1 DOWNTO 0); + data_a : IN STD_LOGIC_VECTOR (DATA_WIDTH-1 DOWNTO 0); + q_a : OUT STD_LOGIC_VECTOR (DATA_WIDTH-1 DOWNTO 0) + ); + END COMPONENT; + +BEGIN + + altsyncram_component : altsyncram + GENERIC MAP ( + clock_enable_input_a => "BYPASS", + clock_enable_output_a => "BYPASS", + init_file => INIT_FILE, + intended_device_family => "Cyclone II", + lpm_hint => "ENABLE_RUNTIME_MOD=NO", + lpm_type => "altsyncram", + numwords_a => WORD_COUNT, + operation_mode => "SINGLE_PORT", + outdata_aclr_a => "NONE", + outdata_reg_a => REG_OUT, + power_up_uninitialized => "FALSE", + widthad_a => ADDR_WIDTH, + width_a => DATA_WIDTH, + width_byteena_a => 1 + ) + PORT MAP ( + wren_a => wren, + clock0 => clk, + address_a => addr, + data_a => data_in, + q_a => data_out + ); + +END SYN; Index: trunk/rtl/Cyclone2/char_rom.mif =================================================================== --- trunk/rtl/Cyclone2/char_rom.mif (nonexistent) +++ trunk/rtl/Cyclone2/char_rom.mif (revision 116) @@ -0,0 +1,2054 @@ +WIDTH=8; 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+ 2011 : 70; + 2012 : 00; + 2013 : 00; + 2014 : 00; + 2015 : 00; + 2016 : 00; + 2017 : 31; + 2018 : 49; + 2019 : 46; + 2020 : 00; + 2021 : 00; + 2022 : 00; + 2023 : 00; + 2024 : 00; + 2025 : 00; + 2026 : 00; + 2027 : 00; + 2028 : 00; + 2029 : 00; + 2030 : 00; + 2031 : 00; + 2032 : 00; + 2033 : 49; + 2034 : 22; + 2035 : 49; + 2036 : 22; + 2037 : 49; + 2038 : 22; + 2039 : 49; + 2040 : 22; + 2041 : 49; + 2042 : 22; + 2043 : 49; + 2044 : 00; + 2045 : 00; + 2046 : 00; + 2047 : 00; +END; Index: trunk/rtl/Cyclone2/pll_inst.vhd =================================================================== --- trunk/rtl/Cyclone2/pll_inst.vhd (nonexistent) +++ trunk/rtl/Cyclone2/pll_inst.vhd (revision 116) @@ -0,0 +1,8 @@ +pll_inst : pll PORT MAP ( + areset => areset_sig, + inclk0 => inclk0_sig, + c0 => c0_sig, + c1 => c1_sig, + c2 => c2_sig, + locked => locked_sig + ); Index: trunk/rtl/Cyclone2/wb_rom.vhd =================================================================== --- trunk/rtl/Cyclone2/wb_rom.vhd (nonexistent) +++ trunk/rtl/Cyclone2/wb_rom.vhd (revision 116) @@ -0,0 +1,82 @@ +--===========================================================================-- +-- +-- S Y N T H E Z I A B L E ROM / WISHBONE interface +-- +-- www.OpenCores.Org - August 2003 +-- This core adheres to the GNU public license +-- +-- File name : wb_rom.vhd +-- +-- Purpose : Implements a WISHBONE compatble interface +-- for an External ROM +-- +-- Dependencies : ieee.Std_Logic_1164 +-- ieee.std_logic_unsigned +-- work.std_logic_arith (MTI's mti_std_logic_arith.vhd) +-- +-- Author : Michael L. Hasenfratz Sr. +-- +--===========================================================================---- +-- +-- Revision History: +-- +-- Date: Revision Author +--===========================================================================-- +-- 5 Aug 2003 0.1 Michael L. Hasenfratz Sr. +-- Created +-- + +library ieee; +use ieee.std_logic_1164.all; +use ieee.std_logic_unsigned.all; +use ieee.std_logic_arith.all; + +entity wb_rom is + generic ( + ROM_WIDTH : positive range 1 to 64 := 8; -- data bits WIDE + ROM_WIDTHAD : positive range 1 to 32 := 8 -- address bits; + ); + port ( + DAT_O : out std_logic_vector(ROM_WIDTH-1 downto 0); + ADR_I : in std_logic_vector(ROM_WIDTHAD-1 downto 0); + SEL_I : in std_logic_vector((ROM_WIDTH/8)-1 downto 0); + STB_I : in std_logic; -- VMA (Valid Memory Access) + CYC_I : in std_logic; -- CYC in progress + ACK_O : out std_logic; -- Data ready + + rom_adr : out std_logic_vector(ROM_WIDTHAD-1 downto 0); + rom_dat : in std_logic_vector(ROM_WIDTH-1 downto 0); + rom_csn : out std_logic; -- ROM Chip Select + rom_oen : out std_logic -- ROM Output Enable + ); +end; + +architecture bhv_wb_rom of wb_rom is + + signal sel : std_logic; -- internal SELECT + +begin + +--------------------------------------------------------- +-- Interconnections +--------------------------------------------------------- +sel0 : process(SEL_I, CYC_I, STB_I) + variable isel : std_logic; + begin + isel := '0'; -- reset 'or' + -- look for ANY selects + for idx in SEL_I'RANGE loop + isel := isel or SEL_I(idx); + end loop; + sel <= isel and CYC_I; + end process; + + rom_adr <= ADR_I; + rom_csn <= not(sel); + rom_oen <= not(sel) and STB_I; + + DAT_O <= rom_dat; + ACK_O <= sel and STB_I; + +end bhv_wb_rom; + Index: trunk/rtl/Cyclone2/pll.cmp =================================================================== --- trunk/rtl/Cyclone2/pll.cmp (nonexistent) +++ trunk/rtl/Cyclone2/pll.cmp (revision 116) @@ -0,0 +1,26 @@ +--Copyright (C) 1991-2010 Altera Corporation +--Your use of Altera Corporation's design tools, logic functions +--and other software and tools, and its AMPP partner logic +--functions, and any output files from any of the foregoing +--(including device programming or simulation files), and any +--associated documentation or information are expressly subject +--to the terms and conditions of the Altera Program License +--Subscription Agreement, Altera MegaCore Function License +--Agreement, or other applicable license agreement, including, +--without limitation, that your use is for the sole purpose of +--programming logic devices manufactured by Altera and sold by +--Altera or its authorized distributors. Please refer to the +--applicable agreement for further details. + + +component pll + PORT + ( + areset : IN STD_LOGIC := '0'; + inclk0 : IN STD_LOGIC := '0'; + c0 : OUT STD_LOGIC ; + c1 : OUT STD_LOGIC ; + c2 : OUT STD_LOGIC ; + locked : OUT STD_LOGIC + ); +end component; Index: trunk/rtl/Cyclone2/pll.vhd =================================================================== --- trunk/rtl/Cyclone2/pll.vhd (nonexistent) +++ trunk/rtl/Cyclone2/pll.vhd (revision 116) @@ -0,0 +1,429 @@ +-- megafunction wizard: %ALTPLL% +-- GENERATION: STANDARD +-- VERSION: WM1.0 +-- MODULE: altpll + +-- ============================================================ +-- File Name: pll.vhd +-- Megafunction Name(s): +-- altpll +-- +-- Simulation Library Files(s): +-- altera_mf +-- ============================================================ +-- ************************************************************ +-- THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE! +-- +-- 9.1 Build 304 01/25/2010 SP 1 SJ Web Edition +-- ************************************************************ + + +--Copyright (C) 1991-2010 Altera Corporation +--Your use of Altera Corporation's design tools, logic functions +--and other software and tools, and its AMPP partner logic +--functions, and any output files from any of the foregoing +--(including device programming or simulation files), and any +--associated documentation or information are expressly subject +--to the terms and conditions of the Altera Program License +--Subscription Agreement, Altera MegaCore Function License +--Agreement, or other applicable license agreement, including, +--without limitation, that your use is for the sole purpose of +--programming logic devices manufactured by Altera and sold by +--Altera or its authorized distributors. Please refer to the +--applicable agreement for further details. + + +LIBRARY ieee; +USE ieee.std_logic_1164.all; + +LIBRARY altera_mf; +USE altera_mf.all; + +ENTITY pll IS + PORT + ( + areset : IN STD_LOGIC := '0'; + inclk0 : IN STD_LOGIC := '0'; + c0 : OUT STD_LOGIC ; + c1 : OUT STD_LOGIC ; + c2 : OUT STD_LOGIC ; + locked : OUT STD_LOGIC + ); +END pll; + + +ARCHITECTURE SYN OF pll IS + + SIGNAL sub_wire0 : STD_LOGIC_VECTOR (5 DOWNTO 0); + SIGNAL sub_wire1 : STD_LOGIC ; + SIGNAL sub_wire2 : STD_LOGIC ; + SIGNAL sub_wire3 : STD_LOGIC ; + SIGNAL sub_wire4 : STD_LOGIC ; + SIGNAL sub_wire5 : STD_LOGIC ; + SIGNAL sub_wire6 : STD_LOGIC_VECTOR (1 DOWNTO 0); + SIGNAL sub_wire7_bv : BIT_VECTOR (0 DOWNTO 0); + SIGNAL sub_wire7 : STD_LOGIC_VECTOR (0 DOWNTO 0); + + + + COMPONENT altpll + GENERIC ( + clk0_divide_by : NATURAL; + clk0_duty_cycle : NATURAL; + clk0_multiply_by : NATURAL; + clk0_phase_shift : STRING; + clk1_divide_by : NATURAL; + clk1_duty_cycle : NATURAL; + clk1_multiply_by : NATURAL; + clk1_phase_shift : STRING; + clk2_divide_by : NATURAL; + clk2_duty_cycle : NATURAL; + clk2_multiply_by : NATURAL; + clk2_phase_shift : STRING; + compensate_clock : STRING; + gate_lock_signal : STRING; + inclk0_input_frequency : NATURAL; + intended_device_family : STRING; + invalid_lock_multiplier : NATURAL; + lpm_hint : STRING; + lpm_type : STRING; + operation_mode : STRING; + port_activeclock : STRING; + port_areset : STRING; + port_clkbad0 : STRING; + port_clkbad1 : STRING; + port_clkloss : STRING; + port_clkswitch : STRING; + port_configupdate : STRING; + port_fbin : STRING; + port_inclk0 : STRING; + port_inclk1 : STRING; + port_locked : STRING; + port_pfdena : STRING; + port_phasecounterselect : STRING; + port_phasedone : STRING; + port_phasestep : STRING; + port_phaseupdown : STRING; + port_pllena : STRING; + port_scanaclr : STRING; + port_scanclk : STRING; + port_scanclkena : STRING; + port_scandata : STRING; + port_scandataout : STRING; + port_scandone : STRING; + port_scanread : STRING; + port_scanwrite : STRING; + port_clk0 : STRING; + port_clk1 : STRING; + port_clk2 : STRING; + port_clk3 : STRING; + port_clk4 : STRING; + port_clk5 : STRING; + port_clkena0 : STRING; + port_clkena1 : STRING; + port_clkena2 : STRING; + port_clkena3 : STRING; + port_clkena4 : STRING; + port_clkena5 : STRING; + port_extclk0 : STRING; + port_extclk1 : STRING; + port_extclk2 : STRING; + port_extclk3 : STRING; + valid_lock_multiplier : NATURAL + ); + PORT ( + inclk : IN STD_LOGIC_VECTOR (1 DOWNTO 0); + locked : OUT STD_LOGIC ; + areset : IN STD_LOGIC ; + clk : OUT STD_LOGIC_VECTOR (5 DOWNTO 0) + ); + END COMPONENT; + +BEGIN + sub_wire7_bv(0 DOWNTO 0) <= "0"; + sub_wire7 <= To_stdlogicvector(sub_wire7_bv); + sub_wire3 <= sub_wire0(2); + sub_wire2 <= sub_wire0(1); + sub_wire1 <= sub_wire0(0); + c0 <= sub_wire1; + c1 <= sub_wire2; + c2 <= sub_wire3; + locked <= sub_wire4; + sub_wire5 <= inclk0; + sub_wire6 <= sub_wire7(0 DOWNTO 0) & sub_wire5; + + altpll_component : altpll + GENERIC MAP ( + clk0_divide_by => 1, + clk0_duty_cycle => 50, + clk0_multiply_by => 1, + clk0_phase_shift => "0", + clk1_divide_by => 2, + clk1_duty_cycle => 50, + clk1_multiply_by => 1, + clk1_phase_shift => "0", + clk2_divide_by => 2, + clk2_duty_cycle => 50, + clk2_multiply_by => 1, + clk2_phase_shift => "0", + compensate_clock => "CLK0", + gate_lock_signal => "NO", + inclk0_input_frequency => 20000, + intended_device_family => "Cyclone II", + invalid_lock_multiplier => 5, + lpm_hint => "CBX_MODULE_PREFIX=pll", + lpm_type => "altpll", + operation_mode => "NORMAL", + port_activeclock => "PORT_UNUSED", + port_areset => "PORT_USED", + port_clkbad0 => "PORT_UNUSED", + port_clkbad1 => "PORT_UNUSED", + port_clkloss => "PORT_UNUSED", + port_clkswitch => "PORT_UNUSED", + port_configupdate => "PORT_UNUSED", + port_fbin => "PORT_UNUSED", + port_inclk0 => "PORT_USED", + port_inclk1 => "PORT_UNUSED", + port_locked => "PORT_USED", + port_pfdena => "PORT_UNUSED", + port_phasecounterselect => "PORT_UNUSED", + port_phasedone => "PORT_UNUSED", + port_phasestep => "PORT_UNUSED", + port_phaseupdown => "PORT_UNUSED", + port_pllena => "PORT_UNUSED", + port_scanaclr => "PORT_UNUSED", + port_scanclk => "PORT_UNUSED", + port_scanclkena => "PORT_UNUSED", + port_scandata => "PORT_UNUSED", + port_scandataout => "PORT_UNUSED", + port_scandone => "PORT_UNUSED", + port_scanread => "PORT_UNUSED", + port_scanwrite => "PORT_UNUSED", + port_clk0 => "PORT_USED", + port_clk1 => "PORT_USED", + port_clk2 => "PORT_USED", + port_clk3 => "PORT_UNUSED", + port_clk4 => "PORT_UNUSED", + port_clk5 => "PORT_UNUSED", + port_clkena0 => "PORT_UNUSED", + port_clkena1 => "PORT_UNUSED", + port_clkena2 => "PORT_UNUSED", + port_clkena3 => "PORT_UNUSED", + port_clkena4 => "PORT_UNUSED", + port_clkena5 => "PORT_UNUSED", + port_extclk0 => "PORT_UNUSED", + port_extclk1 => "PORT_UNUSED", + port_extclk2 => "PORT_UNUSED", + port_extclk3 => "PORT_UNUSED", + valid_lock_multiplier => 1 + ) + PORT MAP ( + inclk => sub_wire6, + areset => areset, + clk => sub_wire0, + locked => sub_wire4 + ); + + + +END SYN; + +-- ============================================================ +-- CNX file retrieval info +-- ============================================================ +-- Retrieval info: PRIVATE: ACTIVECLK_CHECK STRING "0" +-- Retrieval info: PRIVATE: BANDWIDTH STRING "1.000" +-- Retrieval info: PRIVATE: BANDWIDTH_FEATURE_ENABLED STRING "0" +-- Retrieval info: PRIVATE: BANDWIDTH_FREQ_UNIT STRING "MHz" +-- Retrieval info: PRIVATE: BANDWIDTH_PRESET STRING "Low" +-- Retrieval info: PRIVATE: BANDWIDTH_USE_AUTO STRING "1" +-- Retrieval info: PRIVATE: BANDWIDTH_USE_CUSTOM STRING "0" +-- Retrieval info: PRIVATE: BANDWIDTH_USE_PRESET STRING "0" +-- Retrieval info: PRIVATE: CLKBAD_SWITCHOVER_CHECK STRING "0" +-- Retrieval info: PRIVATE: CLKLOSS_CHECK STRING "0" +-- Retrieval info: PRIVATE: CLKSWITCH_CHECK STRING "1" +-- Retrieval info: PRIVATE: CNX_NO_COMPENSATE_RADIO STRING "0" +-- Retrieval info: PRIVATE: CREATE_CLKBAD_CHECK STRING "0" +-- Retrieval info: PRIVATE: CREATE_INCLK1_CHECK STRING "0" +-- Retrieval info: PRIVATE: CUR_DEDICATED_CLK STRING "c0" +-- Retrieval info: PRIVATE: CUR_FBIN_CLK STRING "e0" +-- Retrieval info: PRIVATE: DEVICE_SPEED_GRADE STRING "Any" +-- Retrieval info: PRIVATE: DIV_FACTOR0 NUMERIC "1" +-- Retrieval info: PRIVATE: DIV_FACTOR1 NUMERIC "1" +-- Retrieval info: PRIVATE: DIV_FACTOR2 NUMERIC "1" +-- Retrieval info: PRIVATE: DUTY_CYCLE0 STRING "50.00000000" +-- Retrieval info: PRIVATE: DUTY_CYCLE1 STRING "50.00000000" +-- Retrieval info: PRIVATE: DUTY_CYCLE2 STRING "50.00000000" +-- Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE0 STRING "50.000000" +-- Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE1 STRING "25.000000" +-- Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE2 STRING "25.000000" +-- Retrieval info: PRIVATE: EXPLICIT_SWITCHOVER_COUNTER STRING "0" +-- Retrieval info: PRIVATE: EXT_FEEDBACK_RADIO STRING "0" +-- Retrieval info: PRIVATE: GLOCKED_COUNTER_EDIT_CHANGED STRING "1" +-- Retrieval info: PRIVATE: GLOCKED_FEATURE_ENABLED STRING "1" +-- Retrieval info: PRIVATE: GLOCKED_MODE_CHECK STRING "0" +-- Retrieval info: PRIVATE: GLOCK_COUNTER_EDIT NUMERIC "1048575" +-- Retrieval info: PRIVATE: HAS_MANUAL_SWITCHOVER STRING "1" +-- Retrieval info: PRIVATE: INCLK0_FREQ_EDIT STRING "50.000" +-- Retrieval info: PRIVATE: INCLK0_FREQ_UNIT_COMBO STRING "MHz" +-- Retrieval info: PRIVATE: INCLK1_FREQ_EDIT STRING "100.000" +-- Retrieval info: PRIVATE: INCLK1_FREQ_EDIT_CHANGED STRING "1" +-- Retrieval info: PRIVATE: INCLK1_FREQ_UNIT_CHANGED STRING "1" +-- Retrieval info: PRIVATE: INCLK1_FREQ_UNIT_COMBO STRING "MHz" +-- Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone II" +-- Retrieval info: PRIVATE: INT_FEEDBACK__MODE_RADIO STRING "1" +-- Retrieval info: PRIVATE: LOCKED_OUTPUT_CHECK STRING "1" +-- Retrieval info: PRIVATE: LONG_SCAN_RADIO STRING "1" +-- Retrieval info: PRIVATE: LVDS_MODE_DATA_RATE STRING "300.000" +-- Retrieval info: PRIVATE: LVDS_MODE_DATA_RATE_DIRTY NUMERIC "0" +-- Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT0 STRING "deg" +-- Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT1 STRING "deg" +-- Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT2 STRING "deg" +-- Retrieval info: PRIVATE: MIG_DEVICE_SPEED_GRADE STRING "Any" +-- Retrieval info: PRIVATE: MIRROR_CLK0 STRING "0" +-- Retrieval info: PRIVATE: MIRROR_CLK1 STRING "0" +-- Retrieval info: PRIVATE: MIRROR_CLK2 STRING "0" +-- Retrieval info: PRIVATE: MULT_FACTOR0 NUMERIC "1" +-- Retrieval info: PRIVATE: MULT_FACTOR1 NUMERIC "1" +-- Retrieval info: PRIVATE: MULT_FACTOR2 NUMERIC "1" +-- Retrieval info: PRIVATE: NORMAL_MODE_RADIO STRING "1" +-- Retrieval info: PRIVATE: OUTPUT_FREQ0 STRING "50.00000000" +-- Retrieval info: PRIVATE: OUTPUT_FREQ1 STRING "25.00000000" +-- Retrieval info: PRIVATE: OUTPUT_FREQ2 STRING "25.00000000" +-- Retrieval info: PRIVATE: OUTPUT_FREQ_MODE0 STRING "1" +-- Retrieval info: PRIVATE: OUTPUT_FREQ_MODE1 STRING "1" +-- Retrieval info: PRIVATE: OUTPUT_FREQ_MODE2 STRING "1" +-- Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT0 STRING "MHz" +-- Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT1 STRING "MHz" +-- Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT2 STRING "MHz" +-- Retrieval info: PRIVATE: PHASE_RECONFIG_FEATURE_ENABLED STRING "0" +-- Retrieval info: PRIVATE: PHASE_RECONFIG_INPUTS_CHECK STRING "0" +-- Retrieval info: PRIVATE: PHASE_SHIFT0 STRING "0.00000000" +-- Retrieval info: PRIVATE: PHASE_SHIFT1 STRING "0.00000000" +-- Retrieval info: PRIVATE: PHASE_SHIFT2 STRING "0.00000000" +-- Retrieval info: PRIVATE: PHASE_SHIFT_STEP_ENABLED_CHECK STRING "0" +-- Retrieval info: PRIVATE: PHASE_SHIFT_UNIT0 STRING "deg" +-- Retrieval info: PRIVATE: PHASE_SHIFT_UNIT1 STRING "deg" +-- Retrieval info: PRIVATE: PHASE_SHIFT_UNIT2 STRING "deg" +-- Retrieval info: PRIVATE: PLL_ADVANCED_PARAM_CHECK STRING "0" +-- Retrieval info: PRIVATE: PLL_ARESET_CHECK STRING "1" +-- Retrieval info: PRIVATE: PLL_AUTOPLL_CHECK NUMERIC "1" +-- Retrieval info: PRIVATE: PLL_ENA_CHECK STRING "0" +-- Retrieval info: PRIVATE: PLL_ENHPLL_CHECK NUMERIC "0" +-- Retrieval info: PRIVATE: PLL_FASTPLL_CHECK NUMERIC "0" +-- Retrieval info: PRIVATE: PLL_FBMIMIC_CHECK STRING "0" +-- Retrieval info: PRIVATE: PLL_LVDS_PLL_CHECK NUMERIC "0" +-- Retrieval info: PRIVATE: PLL_PFDENA_CHECK STRING "0" +-- Retrieval info: PRIVATE: PLL_TARGET_HARCOPY_CHECK NUMERIC "0" +-- Retrieval info: PRIVATE: PRIMARY_CLK_COMBO STRING "inclk0" +-- Retrieval info: PRIVATE: RECONFIG_FILE STRING "pll.mif" +-- Retrieval info: PRIVATE: SACN_INPUTS_CHECK STRING "0" +-- Retrieval info: PRIVATE: SCAN_FEATURE_ENABLED STRING "0" +-- Retrieval info: PRIVATE: SELF_RESET_LOCK_LOSS STRING "0" +-- Retrieval info: PRIVATE: SHORT_SCAN_RADIO STRING "0" +-- Retrieval info: PRIVATE: SPREAD_FEATURE_ENABLED STRING "0" +-- Retrieval info: PRIVATE: SPREAD_FREQ STRING "50.000" +-- Retrieval info: PRIVATE: SPREAD_FREQ_UNIT STRING "KHz" +-- Retrieval info: PRIVATE: SPREAD_PERCENT STRING "0.500" +-- Retrieval info: PRIVATE: SPREAD_USE STRING "0" +-- Retrieval info: PRIVATE: SRC_SYNCH_COMP_RADIO STRING "0" +-- Retrieval info: PRIVATE: STICKY_CLK0 STRING "1" +-- Retrieval info: PRIVATE: STICKY_CLK1 STRING "1" +-- Retrieval info: PRIVATE: STICKY_CLK2 STRING "1" +-- Retrieval info: PRIVATE: SWITCHOVER_COUNT_EDIT NUMERIC "1" +-- Retrieval info: PRIVATE: SWITCHOVER_FEATURE_ENABLED STRING "1" +-- Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0" +-- Retrieval info: PRIVATE: USE_CLK0 STRING "1" +-- Retrieval info: PRIVATE: USE_CLK1 STRING "1" +-- Retrieval info: PRIVATE: USE_CLK2 STRING "1" +-- Retrieval info: PRIVATE: USE_CLKENA0 STRING "0" +-- Retrieval info: PRIVATE: USE_CLKENA1 STRING "0" +-- Retrieval info: PRIVATE: USE_CLKENA2 STRING "0" +-- Retrieval info: PRIVATE: USE_MIL_SPEED_GRADE NUMERIC "0" +-- Retrieval info: PRIVATE: ZERO_DELAY_RADIO STRING "0" +-- Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all +-- Retrieval info: CONSTANT: CLK0_DIVIDE_BY NUMERIC "1" +-- Retrieval info: CONSTANT: CLK0_DUTY_CYCLE NUMERIC "50" +-- Retrieval info: CONSTANT: CLK0_MULTIPLY_BY NUMERIC "1" +-- Retrieval info: CONSTANT: CLK0_PHASE_SHIFT STRING "0" +-- Retrieval info: CONSTANT: CLK1_DIVIDE_BY NUMERIC "2" +-- Retrieval info: CONSTANT: CLK1_DUTY_CYCLE NUMERIC "50" +-- Retrieval info: CONSTANT: CLK1_MULTIPLY_BY NUMERIC "1" +-- Retrieval info: CONSTANT: CLK1_PHASE_SHIFT STRING "0" +-- Retrieval info: CONSTANT: CLK2_DIVIDE_BY NUMERIC "2" +-- Retrieval info: CONSTANT: CLK2_DUTY_CYCLE NUMERIC "50" +-- Retrieval info: CONSTANT: CLK2_MULTIPLY_BY NUMERIC "1" +-- Retrieval info: CONSTANT: CLK2_PHASE_SHIFT STRING "0" +-- Retrieval info: CONSTANT: COMPENSATE_CLOCK STRING "CLK0" +-- Retrieval info: CONSTANT: GATE_LOCK_SIGNAL STRING "NO" +-- Retrieval info: CONSTANT: INCLK0_INPUT_FREQUENCY NUMERIC "20000" +-- Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone II" +-- Retrieval info: CONSTANT: INVALID_LOCK_MULTIPLIER NUMERIC "5" +-- Retrieval info: CONSTANT: LPM_TYPE STRING "altpll" +-- Retrieval info: CONSTANT: OPERATION_MODE STRING "NORMAL" +-- Retrieval info: CONSTANT: PORT_ACTIVECLOCK STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_ARESET STRING "PORT_USED" +-- Retrieval info: CONSTANT: PORT_CLKBAD0 STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_CLKBAD1 STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_CLKLOSS STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_CLKSWITCH STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_CONFIGUPDATE STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_FBIN STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_INCLK0 STRING "PORT_USED" +-- Retrieval info: CONSTANT: PORT_INCLK1 STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_LOCKED STRING "PORT_USED" +-- Retrieval info: CONSTANT: PORT_PFDENA STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_PHASECOUNTERSELECT STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_PHASEDONE STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_PHASESTEP STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_PHASEUPDOWN STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_PLLENA STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_SCANACLR STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_SCANCLK STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_SCANCLKENA STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_SCANDATA STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_SCANDATAOUT STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_SCANDONE STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_SCANREAD STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_SCANWRITE STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_clk0 STRING "PORT_USED" +-- Retrieval info: CONSTANT: PORT_clk1 STRING "PORT_USED" +-- Retrieval info: CONSTANT: PORT_clk2 STRING "PORT_USED" +-- Retrieval info: CONSTANT: PORT_clk3 STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_clk4 STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_clk5 STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_clkena0 STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_clkena1 STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_clkena2 STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_clkena3 STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_clkena4 STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_clkena5 STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_extclk0 STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_extclk1 STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_extclk2 STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_extclk3 STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: VALID_LOCK_MULTIPLIER NUMERIC "1" +-- Retrieval info: USED_PORT: @clk 0 0 6 0 OUTPUT_CLK_EXT VCC "@clk[5..0]" +-- Retrieval info: USED_PORT: @extclk 0 0 4 0 OUTPUT_CLK_EXT VCC "@extclk[3..0]" +-- Retrieval info: USED_PORT: @inclk 0 0 2 0 INPUT_CLK_EXT VCC "@inclk[1..0]" +-- Retrieval info: USED_PORT: areset 0 0 0 0 INPUT GND "areset" +-- Retrieval info: USED_PORT: c0 0 0 0 0 OUTPUT_CLK_EXT VCC "c0" +-- Retrieval info: USED_PORT: c1 0 0 0 0 OUTPUT_CLK_EXT VCC "c1" +-- Retrieval info: USED_PORT: c2 0 0 0 0 OUTPUT_CLK_EXT VCC "c2" +-- Retrieval info: USED_PORT: inclk0 0 0 0 0 INPUT_CLK_EXT GND "inclk0" +-- Retrieval info: USED_PORT: locked 0 0 0 0 OUTPUT GND "locked" +-- Retrieval info: CONNECT: locked 0 0 0 0 @locked 0 0 0 0 +-- Retrieval info: CONNECT: @inclk 0 0 1 0 inclk0 0 0 0 0 +-- Retrieval info: CONNECT: c0 0 0 0 0 @clk 0 0 1 0 +-- Retrieval info: CONNECT: c1 0 0 0 0 @clk 0 0 1 1 +-- Retrieval info: CONNECT: c2 0 0 0 0 @clk 0 0 1 2 +-- Retrieval info: CONNECT: @inclk 0 0 1 1 GND 0 0 0 0 +-- Retrieval info: CONNECT: @areset 0 0 0 0 areset 0 0 0 0 +-- Retrieval info: GEN_FILE: TYPE_NORMAL pll.vhd TRUE +-- Retrieval info: GEN_FILE: TYPE_NORMAL pll.ppf TRUE +-- Retrieval info: GEN_FILE: TYPE_NORMAL pll.inc TRUE +-- Retrieval info: GEN_FILE: TYPE_NORMAL pll.cmp TRUE +-- Retrieval info: GEN_FILE: TYPE_NORMAL pll.bsf TRUE +-- Retrieval info: GEN_FILE: TYPE_NORMAL pll_inst.vhd TRUE +-- Retrieval info: LIB_FILE: altera_mf +-- Retrieval info: CBX_MODULE_PREFIX: ON Index: trunk/rtl/Cyclone2/char_rom.vhd =================================================================== --- trunk/rtl/Cyclone2/char_rom.vhd (nonexistent) +++ trunk/rtl/Cyclone2/char_rom.vhd (revision 116) @@ -0,0 +1,36 @@ +library ieee; +use ieee.std_logic_1164.all; +use ieee.numeric_std.all; + +entity char_rom is + Port ( + clk : in std_logic; + rst : in std_logic; + cs : in std_logic; + rw : in std_logic; + addr : in std_logic_vector (10 downto 0); + data_in : in std_logic_vector (7 downto 0); + data_out : out std_logic_vector (7 downto 0) + ); +end char_rom; + +architecture SYN of char_rom is +begin + + rom_inst : entity work.sprom + generic map + ( + INIT_FILE => "char_rom.mif", + WORD_COUNT => 2048, + ADDR_WIDTH => 11 + ) + port map + ( + clk => clk, + addr => addr, + data_in => data_in, + data_out => data_out + ); + +end SYN; + Index: trunk/rtl/Cyclone2/rom2k.vhd =================================================================== --- trunk/rtl/Cyclone2/rom2k.vhd (nonexistent) +++ trunk/rtl/Cyclone2/rom2k.vhd (revision 116) @@ -0,0 +1,83 @@ +LIBRARY ieee; +USE ieee.std_logic_1164.all; + +LIBRARY altera_mf; +USE altera_mf.all; + +ENTITY sprom IS + GENERIC + ( + INIT_FILE : string := ""; + WORD_COUNT : natural := 2048; + ADDR_WIDTH : natural := 11; + DATA_WIDTH : natural := 8; + REG_OUT : string := "UNREGISTERED" + ); + PORT + ( + clk : IN STD_LOGIC ; + addr : IN STD_LOGIC_VECTOR (ADDR_WIDTH-1 DOWNTO 0); + wren : IN STD_LOGIC ; + data_in : IN STD_LOGIC_VECTOR (DATA_WIDTH-1 DOWNTO 0); + data_out : OUT STD_LOGIC_VECTOR (DATA_WIDTH-1 DOWNTO 0) + ); +END sprom; + +ARCHITECTURE SYN OF sprom IS + + COMPONENT altsyncram + GENERIC ( + clock_enable_input_a : STRING; + clock_enable_output_a : STRING; + init_file : STRING; + intended_device_family : STRING; + lpm_hint : STRING; + lpm_type : STRING; + numwords_a : NATURAL; + operation_mode : STRING; + outdata_aclr_a : STRING; + outdata_reg_a : STRING; + power_up_uninitialized : STRING; + widthad_a : NATURAL; + width_a : NATURAL; + width_byteena_a : NATURAL + ); + PORT ( + clock0 : IN STD_LOGIC ; + wren_a : IN STD_LOGIC ; + address_a : IN STD_LOGIC_VECTOR (ADDR_WIDTH-1 DOWNTO 0); + data_a : IN STD_LOGIC_VECTOR (DATA_WIDTH-1 DOWNTO 0); + q_a : OUT STD_LOGIC_VECTOR (DATA_WIDTH-1 DOWNTO 0) + ); + END COMPONENT; + +BEGIN + + wren <= cs and not rw; + + altsyncram_component : altsyncram + GENERIC MAP ( + clock_enable_input_a => "BYPASS", + clock_enable_output_a => "BYPASS", + init_file => INIT_FILE, + intended_device_family => "Cyclone II", + lpm_hint => "ENABLE_RUNTIME_MOD=NO", + lpm_type => "altsyncram", + numwords_a => WORD_COUNT, + operation_mode => "ROM", + outdata_aclr_a => "NONE", + outdata_reg_a => REG_OUT, + power_up_uninitialized => "FALSE", + widthad_a => ADDR_WIDTH, + width_a => DATA_WIDTH, + width_byteena_a => 1 + ) + PORT MAP ( + wren_a => wren, + clock0 => clk, + address_a => addr, + data_a => data_in, + q_a => data_out + ); + +END SYN; Index: trunk/rtl/Cyclone2/kemap.txt =================================================================== --- trunk/rtl/Cyclone2/kemap.txt (nonexistent) +++ trunk/rtl/Cyclone2/kemap.txt (revision 116) @@ -0,0 +1,107 @@ +-- when x"00d" => ascii <= x"09"; -- Horizontal Tab +-- when x"00e" => ascii <= x"60"; -- ` +-- when x"015" => ascii <= x"71"; -- q +-- when x"016" => ascii <= x"31"; -- 1 +-- when x"01a" => ascii <= x"7a"; -- z +-- when x"01b" => ascii <= x"73"; -- s +-- when x"01c" => ascii <= x"61"; -- a +-- when x"01d" => ascii <= x"77"; -- w +-- when x"01e" => ascii <= x"32"; -- 2 +-- when x"021" => ascii <= x"63"; -- c +-- when x"022" => ascii <= x"78"; -- x +-- when x"023" => ascii <= x"64"; -- d +-- when x"024" => ascii <= x"65"; -- e +-- when x"025" => ascii <= x"34"; -- 4 +-- when x"026" => ascii <= x"33"; -- 3 +-- when x"029" => ascii <= x"20"; -- Space +-- when x"02a" => ascii <= x"76"; -- v +-- when x"02b" => ascii <= x"66"; -- f +-- when x"02c" => ascii <= x"74"; -- t +-- when x"02d" => ascii <= x"72"; -- r +-- when x"02e" => ascii <= x"35"; -- 5 +-- when x"031" => ascii <= x"6e"; -- n +-- when x"032" => ascii <= x"62"; -- b +-- when x"033" => ascii <= x"68"; -- h +-- when x"034" => ascii <= x"67"; -- g +-- when x"035" => ascii <= x"79"; -- y +-- when x"036" => ascii <= x"36"; -- 6 +-- when x"03a" => ascii <= x"6d"; -- m +-- when x"03b" => ascii <= x"6a"; -- j +-- when x"03c" => ascii <= x"75"; -- u +-- when x"03d" => ascii <= x"37"; -- 7 +-- when x"03e" => ascii <= x"38"; -- 8 +-- when x"041" => ascii <= x"2c"; -- , +-- when x"042" => ascii <= x"6b"; -- k +-- when x"043" => ascii <= x"69"; -- i +-- when x"044" => ascii <= x"6f"; -- o +-- when x"045" => ascii <= x"30"; -- 0 +-- when x"046" => ascii <= x"39"; -- 9 +-- when x"04e" => ascii <= x"2d"; -- - +-- when x"049" => ascii <= x"2e"; -- . +-- when x"04a" => ascii <= x"2f"; -- / +-- when x"04b" => ascii <= x"6c"; -- l +-- when x"04c" => ascii <= x"3b"; -- ; +-- when x"04d" => ascii <= x"70"; -- p +-- when x"052" => ascii <= x"27"; -- +-- when x"054" => ascii <= x"5b"; -- [ +-- when x"055" => ascii <= x"3d"; -- = +-- when x"05a" => ascii <= x"0d"; -- Carriage return ("enter" key) +-- when x"05b" => ascii <= x"5d"; -- ] +-- when x"05d" => ascii <= x"5c"; -- \ +-- when x"066" => ascii <= x"08"; -- Backspace ("backspace" key) +-- when x"071" => ascii <= x"7f"; -- (Delete OR DEL on numeric keypad) +-- when x"076" => ascii <= x"1b"; -- Escape ("esc" key) +-- when x"10d" => ascii <= x"09"; -- Horizontal Tab +-- when x"10e" => ascii <= x"7e"; -- ~ +-- when x"115" => ascii <= x"51"; -- Q +-- when x"116" => ascii <= x"21"; -- ! +-- when x"11a" => ascii <= x"5a"; -- Z +-- when x"11b" => ascii <= x"53"; -- S +-- when x"11c" => ascii <= x"41"; -- A +-- when x"11d" => ascii <= x"57"; -- W +-- when x"11e" => ascii <= x"40"; -- @ +-- when x"121" => ascii <= x"43"; -- C +-- when x"122" => ascii <= x"58"; -- X +-- when x"123" => ascii <= x"44"; -- D +-- when x"124" => ascii <= x"45"; -- E +-- when x"125" => ascii <= x"24"; -- $ +-- when x"126" => ascii <= x"23"; -- # +-- when x"129" => ascii <= x"20"; -- Space +-- when x"12a" => ascii <= x"56"; -- V +-- when x"12b" => ascii <= x"46"; -- F +-- when x"12c" => ascii <= x"54"; -- T +-- when x"12d" => ascii <= x"52"; -- R +-- when x"12e" => ascii <= x"25"; -- +-- when x"131" => ascii <= x"4e"; -- N +-- when x"132" => ascii <= x"42"; -- B +-- when x"133" => ascii <= x"48"; -- H +-- when x"134" => ascii <= x"47"; -- G +-- when x"135" => ascii <= x"59"; -- Y +-- when x"136" => ascii <= x"5e"; -- ^ +-- when x"13a" => ascii <= x"4d"; -- M +-- when x"13b" => ascii <= x"4a"; -- J +-- when x"13c" => ascii <= x"55"; -- U +-- when x"13d" => ascii <= x"26"; -- +-- when x"13e" => ascii <= x"2a"; -- * +-- when x"141" => ascii <= x"3c"; -- < +-- when x"142" => ascii <= x"4b"; -- K +-- when x"143" => ascii <= x"49"; -- I +-- when x"144" => ascii <= x"4f"; -- O +-- when x"145" => ascii <= x"29"; -- +-- when x"146" => ascii <= x"28"; -- +-- when x"149" => ascii <= x"3e"; -- > +-- when x"14a" => ascii <= x"3f"; -- ? +-- when x"14b" => ascii <= x"4c"; -- L +-- when x"14c" => ascii <= x"3a"; -- : +-- when x"14d" => ascii <= x"50"; -- P +-- when x"14e" => ascii <= x"5f"; -- _ +-- when x"152" => ascii <= x"22"; -- " +-- when x"154" => ascii <= x"7b"; -- { +-- when x"155" => ascii <= x"2b"; -- + +-- when x"15a" => ascii <= x"0d"; -- Carriage return ("enter" key) +-- when x"15b" => ascii <= x"7d"; -- } +-- when x"15d" => ascii <= x"7c"; -- | +-- when x"166" => ascii <= x"08"; -- Backspace ("backspace" key) +-- when x"171" => ascii <= x"7f"; -- (Delete OR DEL on numeric keypad) +-- when x"176" => ascii <= x"1b"; -- Escape ("esc" key) +-- when others => ascii <= x"ff"; -- 0xff used for unlisted characters. \ No newline at end of file Index: trunk/rtl/Cyclone2/pll.ppf =================================================================== --- trunk/rtl/Cyclone2/pll.ppf (nonexistent) +++ trunk/rtl/Cyclone2/pll.ppf (revision 116) @@ -0,0 +1,13 @@ + + + + + + + + + + + + + Index: trunk/rtl/Cyclone2/keymap_rom.mif =================================================================== --- trunk/rtl/Cyclone2/keymap_rom.mif (nonexistent) +++ trunk/rtl/Cyclone2/keymap_rom.mif (revision 116) @@ -0,0 +1,301 @@ +-- Copyright (C) 1991-2010 Altera Corporation +-- Your use of Altera Corporation's design tools, logic functions +-- and other software and tools, and its AMPP partner logic +-- functions, and any output files from any of the foregoing +-- (including device programming or simulation files), and any +-- associated documentation or information are expressly subject +-- to the terms and conditions of the Altera Program License +-- Subscription Agreement, Altera MegaCore Function License +-- Agreement, or other applicable license agreement, including, +-- without limitation, that your use is for the sole purpose of +-- programming logic devices manufactured by Altera and sold by +-- Altera or its authorized distributors. Please refer to the +-- applicable agreement for further details. + +-- Quartus II generated Memory Initialization File (.mif) + +WIDTH=8; +DEPTH=512; + +ADDRESS_RADIX=UNS; +DATA_RADIX=HEX; + +CONTENT BEGIN + [0..12] : 00; + 13 : 09; + 14 : 60; + [15..20] : 00; + 21 : 71; + 22 : 31; + [23..25] : 00; + 26 : 7A; + 27 : 73; + 28 : 61; + 29 : 77; + 30 : 32; + [31..32] : 00; + 33 : 63; + 34 : 78; + 35 : 64; + 36 : 65; + 37 : 34; + 38 : 33; + [39..40] : 00; + 41 : 20; + 42 : 76; + 43 : 66; + 44 : 74; + 45 : 72; + 46 : 35; + [47..48] : 00; + 49 : 6E; + 50 : 62; + 51 : 68; + 52 : 67; + 53 : 79; + 54 : 36; + [55..57] : 00; + 58 : 6D; + 59 : 6A; + 60 : 75; + 61 : 37; + 62 : 38; + [63..64] : 00; + 65 : 2C; + 66 : 6B; + 67 : 69; + 68 : 6F; + 69 : 30; + 70 : 39; + [71..72] : 00; + 73 : 2E; + 74 : 2F; + 75 : 6C; + 76 : 3B; + 77 : 70; + 78 : 2D; + [79..81] : 00; + 82 : 27; + 83 : 00; + 84 : 5B; + 85 : 3D; + [86..89] : 00; + 90 : 0D; + 91 : 5D; + 92 : 00; + 93 : 5C; + [94..101] : 00; + 102 : 08; + [103..112] : 00; + 113 : 7F; + [114..117] : 00; + 118 : 1B; + [119..140] : 00; + 141 : 09; + 142 : 7E; + [143..148] : 00; + 149 : 51; + 150 : 31; + [151..153] : 00; + 154 : 5A; + 155 : 53; + 156 : 41; + 157 : 57; + 158 : 32; + [159..160] : 00; + 161 : 43; + 162 : 58; + 163 : 44; + 164 : 45; + 165 : 34; + 166 : 33; + [167..168] : 00; + 169 : 20; + 170 : 56; + 171 : 46; + 172 : 54; + 173 : 52; + 174 : 35; + [175..176] : 00; + 177 : 4E; + 178 : 42; + 179 : 48; + 180 : 47; + 181 : 59; + 182 : 36; + [183..185] : 00; + 186 : 4D; + 187 : 4A; + 188 : 55; + 189 : 37; + 190 : 38; + [191..192] : 00; + 193 : 2C; + 194 : 4B; + 195 : 49; + 196 : 4F; + 197 : 30; + 198 : 39; + [199..200] : 00; + 201 : 2E; + 202 : 2F; + 203 : 4C; + 204 : 3B; + 205 : 50; + 206 : 2D; + [207..209] : 00; + 210 : 27; + 211 : 00; + 212 : 5B; + 213 : 3D; + [214..217] : 00; + 218 : 0D; + 219 : 5D; + 220 : 00; + 221 : 5C; + [222..229] : 00; + 230 : 08; + [231..240] : 00; + 241 : 7F; + [242..245] : 00; + 246 : 1B; + [247..268] : 00; + 269 : 09; + 270 : 7E; + [271..276] : 00; + 277 : 51; + 278 : 21; + [279..281] : 00; + 282 : 5A; + 283 : 53; + 284 : 41; + 285 : 57; + 286 : 40; + [287..288] : 00; + 289 : 43; + 290 : 58; + 291 : 44; + 292 : 45; + 293 : 24; + 294 : 23; + [295..296] : 00; + 297 : 20; + 298 : 56; + 299 : 46; + 300 : 54; + 301 : 52; + 302 : 25; + [303..304] : 00; + 305 : 4E; + 306 : 42; + 307 : 48; + 308 : 47; + 309 : 59; + 310 : 5E; + [311..313] : 00; + 314 : 4D; + 315 : 4A; + 316 : 55; + 317 : 26; + 318 : 2A; + [319..320] : 00; + 321 : 3C; + 322 : 4B; + 323 : 49; + 324 : 4F; + 325 : 29; + 326 : 28; + [327..328] : 00; + 329 : 3E; + 330 : 3F; + 331 : 4C; + 332 : 3A; + 333 : 50; + 334 : 5F; + [335..337] : 00; + 338 : 22; + 339 : 00; + 340 : 7B; + 341 : 2B; + [342..345] : 00; + 346 : 0D; + 347 : 7D; + 348 : 00; + 349 : 7C; + [350..357] : 00; + 358 : 08; + [359..368] : 00; + 369 : 7F; + [370..373] : 00; + 374 : 1B; + [375..396] : 00; + 397 : 09; + 398 : 60; + [399..404] : 00; + 405 : 71; + 406 : 21; + [407..409] : 00; + 410 : 7A; + 411 : 73; + 412 : 61; + 413 : 77; + 414 : 40; + [415..416] : 00; + 417 : 63; + 418 : 78; + 419 : 64; + 420 : 65; + 421 : 24; + 422 : 23; + [423..424] : 00; + 425 : 20; + 426 : 76; + 427 : 66; + 428 : 74; + 429 : 72; + 430 : 25; + [431..432] : 00; + 433 : 6E; + 434 : 62; + 435 : 68; + 436 : 67; + 437 : 79; + 438 : 5E; + [439..441] : 00; + 442 : 6D; + 443 : 6A; + 444 : 75; + 445 : 26; + 446 : 2A; + [447..448] : 00; + 449 : 3C; + 450 : 6B; + 451 : 69; + 452 : 6F; + 453 : 29; + 454 : 28; + [455..456] : 00; + 457 : 3E; + 458 : 3F; + 459 : 6C; + 460 : 3A; + 461 : 70; + 462 : 5F; + [463..465] : 00; + 466 : 22; + 467 : 00; + 468 : 7B; + 469 : 2B; + [470..473] : 00; + 474 : 0D; + 475 : 7D; + 476 : 00; + 477 : 7C; + [478..485] : 00; + 486 : 08; + [487..496] : 00; + 497 : 7F; + [498..501] : 00; + 502 : 1B; + [503..511] : 00; +END; Index: trunk/rtl/Cyclone2/wb_lpm_rom.vhd =================================================================== --- trunk/rtl/Cyclone2/wb_lpm_rom.vhd (nonexistent) +++ trunk/rtl/Cyclone2/wb_lpm_rom.vhd (revision 116) @@ -0,0 +1,109 @@ +--===========================================================================-- +-- +-- S Y N T H E Z I A B L E Altera LPM_ROM / WISHBONE interface +-- +-- www.OpenCores.Org - August 2003 +-- This core adheres to the GNU public license +-- +-- File name : wb_lpm_rom.vhd +-- +-- Purpose : Implements a WISHBONE compatble interface +-- for the Altera LPM_ROM +-- +-- Dependencies : ieee.Std_Logic_1164 +-- ieee.std_logic_unsigned +-- work.lpm_components (Altera's 220PACK.vhd) +-- +-- Author : Michael L. Hasenfratz Sr. +-- +--===========================================================================---- +-- +-- Revision History: +-- +-- Date: Revision Author +--===========================================================================-- +-- 1 Aug 2003 0.1 Michael L. Hasenfratz Sr. +-- Created +-- + +library ieee; +use ieee.std_logic_1164.all; +use ieee.std_logic_unsigned.all; + +library lpm; +use lpm.lpm_components.all; + +entity wb_lpm_rom is + generic ( + LPM_WIDTH : positive range 1 to 64 := 8; -- data bits WIDE + LPM_WIDTHAD : positive range 1 to 32 := 8; -- address bits; + LPM_FILE : string := "my_rom" -- ROM Data File + ); + port ( + DAT_O : out std_logic_vector(LPM_WIDTH-1 downto 0); + ADR_I : in std_logic_vector(LPM_WIDTHAD-1 downto 0); + SEL_I : in std_logic_vector((LPM_WIDTH/8)-1 downto 0); + STB_I : in std_logic; -- VMA (Valid Memory Access) + CYC_I : in std_logic; -- CYC in progress + ACK_O : out std_logic; -- Data ready + CLK_I : in std_logic; -- System Clock + RST_I : in std_logic -- Reset + ); +end; + +architecture bhv_wb_lpm_rom of wb_lpm_rom is + + signal iack : std_logic; -- Internal ACK + signal isel : std_logic; -- device selected + +begin + +--------------------------------------------------------- +-- Instantiate the ROM interface +--------------------------------------------------------- +rom0 : LPM_ROM + generic map ( + LPM_WIDTH => LPM_WIDTH, + LPM_WIDTHAD => LPM_WIDTHAD, + LPM_OUTDATA => "UNREGISTERED", + LPM_FILE => LPM_FILE + ) + port map ( + Q => DAT_O, + ADDRESS => ADR_I, + INCLOCK => CLK_I + ); + +--------------------------------------------------------- +-- Interconnections +--------------------------------------------------------- + + ACK_O <= isel and iack; + +-- Selection +romsel : process(SEL_I, CYC_I, STB_I) + variable vsel : std_logic; + begin + vsel := '0'; + for ndx in SEL_I'RANGE loop + vsel := vsel or SEL_I(ndx); + end loop; + isel <= vsel and CYC_I and STB_I; + end process; + +-- Read Acknowledge +rdack : process(RST_I, CLK_I) + begin + if CLK_I'EVENT and CLK_I = '1' then + if RST_I = '1' then + iack <= '0'; + elsif iack = '1' then + iack <= '0'; + else + iack <= isel; + end if; + end if; + end process; + +end bhv_wb_lpm_rom; + Index: trunk/doc/Booting_Flex9_Digilent_S3Starter.doc =================================================================== Cannot display: file marked as a binary type. svn:mime-type = application/octet-stream Index: trunk/doc/Booting_Flex9_Digilent_S3Starter.doc =================================================================== --- trunk/doc/Booting_Flex9_Digilent_S3Starter.doc (revision 115) +++ trunk/doc/Booting_Flex9_Digilent_S3Starter.doc (nonexistent)
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