URL
https://opencores.org/ocsvn/System09/System09/trunk
Subversion Repositories System09
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- This comparison shows the changes necessary to convert path
/System09
- from Rev 138 to Rev 139
- ↔ Reverse comparison
Rev 138 → Rev 139
/trunk/rtl/VHDL/acia6850.vhd
205,7 → 205,7
-- IO address + 0 Write |
-- |
-----------+--------+--------+--------+--------+--------+--------+--------+ |
-- RxIE |TxCtl(1)|TxCtl(0)|WdFmt(2)|WdFmt(1)|WdFmt(0)|BdCtl(1)|BdCtl(0)| |
-- RXIEnb |TxCtl(1)|TxCtl(0)|WdFmt(2)|WdFmt(1)|WdFmt(0)|BdCtl(1)|BdCtl(0)| |
-----------+--------+--------+--------+--------+--------+--------+--------+ |
-- RxIEnb - Bit[7] |
-- 0 - Rx Interrupt disabled |
248,7 → 248,7
signal TxDat : std_logic := '1'; -- Transmit data bit |
signal TxRdy : std_logic := '0'; -- Transmit buffer empty |
signal RxRdy : std_logic := '0'; -- Receive Data ready |
-- |
-- |
signal FErr : std_logic := '0'; -- Frame error |
signal OErr : std_logic := '0'; -- Output error |
signal PErr : std_logic := '0'; -- Parity Error |
316,9 → 316,10
|
begin |
|
--------------------------------------------------------------- |
-- ACIA Reset may be hardware or software |
--------------------------------------------------------------- |
--------------------------------------------------------------- |
-- ACIA Reset may be hardware or software |
--------------------------------------------------------------- |
|
acia_reset : process( clk, rst, ac_rst, dcd_n ) |
begin |
-- |
335,10 → 336,9
|
end process; |
|
|
----------------------------------------------------------------------------- |
-- Generate Read / Write strobes. |
----------------------------------------------------------------------------- |
----------------------------------------------------------------------------- |
-- Generate Read / Write strobes. |
----------------------------------------------------------------------------- |
|
acia_read_write : process(clk, ac_rst) |
begin |
394,11 → 394,10
end if; |
end process; |
|
----------------------------------------------------------------------------- |
-- ACIA Transmit Control |
----------------------------------------------------------------------------- |
|
----------------------------------------------------------------------------- |
-- ACIA Transmit Control |
----------------------------------------------------------------------------- |
|
acia_control : process(CtrlReg, TxDat) |
begin |
case CtrlReg(6 downto 5) is |
427,9 → 426,9
BdFmt <= CtrlReg(1 downto 0); |
end process; |
|
--------------------------------------------------------------- |
-- Set Data Output Multiplexer |
-------------------------------------------------------------- |
--------------------------------------------------------------- |
-- Set Data Output Multiplexer |
-------------------------------------------------------------- |
|
acia_data_mux : process(Addr, RxReg, StatReg) |
begin |
442,9 → 441,10
|
irq <= StatReg(7); |
|
--------------------------------------------------------------- |
-- Data Carrier Detect Edge rising edge detect |
--------------------------------------------------------------- |
--------------------------------------------------------------- |
-- Data Carrier Detect Edge rising edge detect |
--------------------------------------------------------------- |
|
acia_dcd_edge : process( clk, ac_rst ) |
begin |
if falling_edge(clk) then |
458,14 → 458,13
end if; |
end process; |
|
--------------------------------------------------------------- |
-- Data Carrier Detect Interrupt |
--------------------------------------------------------------- |
-- If Data Carrier is lost, an interrupt is generated |
-- To clear the interrupt, first read the status register |
-- then read the data receive register |
|
--------------------------------------------------------------- |
-- Data Carrier Detect Interrupt |
--------------------------------------------------------------- |
-- If Data Carrier is lost, an interrupt is generated |
-- To clear the interrupt, first read the status register |
-- then read the data receive register |
|
acia_dcd_int : process( clk, ac_rst ) |
begin |
if falling_edge(clk) then |
499,12 → 498,11
end if; |
end process; |
|
|
--------------------------------------------------------------------- |
-- Receiver Clock Edge Detection |
--------------------------------------------------------------------- |
-- A rising edge will produce a one clock cycle pulse |
-- |
|
acia_rx_clock_edge : process( clk, rx_rst ) |
begin |
if falling_edge(clk) then |
522,7 → 520,7
-- Receiver Data Edge Detection |
--------------------------------------------------------------------- |
-- A falling edge will produce a pulse on RxClk wide |
-- |
|
acia_rx_data_edge : process( clk, rx_rst ) |
begin |
if falling_edge(clk) then |
545,7 → 543,7
--------------------------------------------------------------------- |
-- Enable the receive clock on detection of a start bit |
-- Disable the receive clock after a byte is received. |
-- |
|
acia_rx_start_stop : process( clk, rx_rst ) |
begin |
if falling_edge(clk) then |
571,7 → 569,7
--------------------------------------------------------------------- |
-- Hold the Rx Clock divider in reset when the receiver is disabled |
-- Advance the count only on a rising Rx clock edge |
-- |
|
acia_rx_clock_divide : process( clk, rx_rst ) |
begin |
if falling_edge(clk) then |
622,6 → 620,7
-- 1 0 1 - 8 data, no parity, 1 stop |
-- 1 1 0 - 8 data, even parity, 1 stop |
-- 1 1 1 - 8 data, odd parity, 1 stop |
|
acia_rx_receive : process( clk, rst ) |
begin |
if falling_edge( clk ) then |
706,6 → 705,7
--------------------------------------------------------------------- |
-- Receiver Read process |
--------------------------------------------------------------------- |
|
acia_rx_read : process( clk, rst, RxRdy ) |
begin |
if falling_edge(clk) then |
726,7 → 726,6
end if; |
end process; |
|
|
--------------------------------------------------------------------- |
-- Transmit Clock Edge Detection |
-- A falling edge will produce a one clock cycle pulse |
764,6 → 763,7
--------------------------------------------------------------------- |
-- Transmit Baud Clock Selector |
--------------------------------------------------------------------- |
|
acia_tx_baud_clock_select : process( BdFmt, TxClkCnt, TxC ) |
begin |
-- BdFmt |
795,6 → 795,7
-- 1 0 1 - 8 data, no parity, 1 stop |
-- 1 1 0 - 8 data, even parity, 1 stop |
-- 1 1 1 - 8 data, odd parity, 1 stop |
|
acia_tx_transmit : process( clk, tx_rst) |
begin |
if falling_edge(clk) then |