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/tags/arelease/vhdl/testbench1.vhd
0,0 → 1,148
--===========================================================================--
--
-- CPU68 Microprocessor Test Bench 1
-- Print out "Hello World" on the Uart
--
--
-- John Kent 21st October 2002
--
--
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
use ieee.numeric_std.all;
library work;
-- use work.UART_Def.all;
-- use work.typedefines.all;
-- use work.memory.all;
 
entity my_testbench is
end my_testbench;
 
-------------------------------------------------------------------------------
-- Architecture for memio Controller Unit
-------------------------------------------------------------------------------
architecture behavior of my_testbench is
-----------------------------------------------------------------------------
-- Signals
-----------------------------------------------------------------------------
signal uart_irq : Std_Logic;
signal timer_irq : std_logic;
 
-- CPU Interface signals
signal SysClk : Std_Logic;
signal cpu_reset : Std_Logic;
signal cpu_rw : Std_Logic;
signal cpu_vma : Std_Logic;
signal cpu_addr : Std_Logic_Vector(15 downto 0);
signal cpu_data_in : Std_Logic_Vector(7 downto 0);
signal cpu_data_out: Std_Logic_Vector(7 downto 0);
signal cpu_alu : Std_Logic_Vector(15 downto 0);
signal cpu_cc : Std_Logic_Vector(7 downto 0);
 
constant width : integer := 8;
constant memsize : integer := 64;
 
type rom_array is array(0 to memsize-1) of std_logic_vector(width-1 downto 0);
 
constant rom_data : rom_array :=
(
"11001110", "11111111", "11101000", -- E000 - CE E028 RESET LDX #MSG
"10000110", "00010001", -- E003 - 86 11 LDAA #$11
"10110111", "10000000", "00000100", -- E005 - B7 8004 STAA UARTCR
"10110110", "10000000", "00000100", -- E008 - B6 8004 POLL1 LDAA UARTCR
"10000101", "00000010", -- E00B - 85 02 BITA #TXBE
-- "00100111", "11111001", -- E00D - 27 F9 BEQ POLL1
"00100110", "11111001", -- E00D - 26 F9 BNE POLL1
"10100110", "00000000", -- E00F - A6 00 LDAA 0,X
"00100111", "00000110", -- E011 - 27 06 BEQ POLL2
"00001000", -- E013 - 08 INX
"10110111", "10000000", "00000101", -- E014 - B7 8005 STA UARTDR
"00100110", "11101111", -- E017 - 26 EF BNE POLL1
"00001000", "10000000", "00000100", -- E019 - B6 8004 POLL2 LDAA UARTCR
"10000101", "00000001", -- E01C - 85 01 BITA #RXBF
"00100111", "11111001", -- E01E - 27 F9 BEQ POLL2
-- "00100110", "11111001", -- E01E - 26 F9 BEQ POLL2
"10110110", "10000000", "00000101", -- E020 - B6 8005 LDAA UARTDR
"00100000", "11100000", "00000000", -- E023 - 7E E000 JMP RESET
"00000000", "00000000", -- E026 - 00 00 fcb $00,$00
"01001000", "01100101", "01101100", -- E028 - 48 65 6c MSG FCC "Hel"
"01101100", "01101111", "00100000", -- E02B - 6c 6f 20 FCC "lo "
"01010111", "01101111", "01110010", -- E02E - 57 6f 72 FCC "Wor"
"01101100", "01100100", -- E031 - 6c 64 FCC "ld"
"00001010", "00001101", "00000000", -- E033 - 0a 0d 00 FCB LF,CR,NULL
"00000000", "00000000", -- E036 - 00 00 fcb null,null
"11100000", "00000000", -- E038 - E0 00 fdb $E000 ; Timer irq
"11100000", "00000000", -- E03A - E0 00 fdb $E000 ; Ext IRQ
"11100000", "00000000", -- E03C - E0 00 fcb $E000 ; SWI
"11100000", "00000000" -- E03E - E0 00 fdb $E000 ; Reset
);
 
component cpu68
port (
clk: in std_logic;
rst: in std_logic;
rw: out std_logic; -- Asynchronous memory interface
vma: out std_logic;
address: out std_logic_vector(15 downto 0);
data_in: in std_logic_vector(7 downto 0);
data_out: out std_logic_vector(7 downto 0);
irq: in std_logic;
nmi: in std_logic;
test_alu: out std_logic_vector(15 downto 0);
test_cc: out std_logic_vector(7 downto 0)
);
end component cpu68;
 
 
begin
cpu : cpu68 port map (
clk => SysClk,
rst => cpu_reset,
rw => cpu_rw,
vma => cpu_vma,
address => cpu_addr(15 downto 0),
data_in => cpu_data_in,
data_out => cpu_data_out,
irq => uart_irq,
nmi => timer_irq,
test_alu => cpu_alu,
test_cc => cpu_cc
);
 
-- *** Test Bench - User Defined Section ***
tb : PROCESS
variable count : integer;
BEGIN
 
cpu_reset <= '0';
SysClk <= '0';
uart_irq <= '0';
timer_irq <= '0';
 
for count in 0 to 256 loop
SysClk <= '0';
if count = 0 then
cpu_reset <= '1';
elsif count = 1 then
cpu_reset <= '0';
end if;
wait for 100 ns;
SysClk <= '1';
wait for 100 ns;
end loop;
 
wait; -- will wait forever
END PROCESS;
-- *** End Test Bench - User Defined Section ***
 
 
rom : PROCESS( cpu_addr )
begin
cpu_data_in <= rom_data(conv_integer(cpu_addr(5 downto 0)));
end process;
 
end behavior; --===================== End of architecture =======================--
 
/tags/arelease/vhdl/uart_lib.vhd
0,0 → 1,62
--===========================================================================--
--
-- S Y N T H E Z I A B L E miniUART C O R E
--
-- www.OpenCores.Org - January 2000
-- This core adheres to the GNU public license
--
-- Design units : UART_Def
--
-- File name : uart_lib.vhd
--
-- Purpose : Implements an miniUART device for communication purposes
-- between the OR1K processor and the Host computer through
-- an RS-232 communication protocol.
--
-- Library : uart_lib.vhd
--
-- Dependencies : IEEE.Std_Logic_1164
--
--===========================================================================--
-------------------------------------------------------------------------------
-- Revision list
-- Version Author Date Changes
--
-- 0.1 Ovidiu Lupas 15 January 2000 New model
-- olupas@opencores.org
-------------------------------------------------------------------------------
--------------------------------------------------------------------------------
-- package UART_Def
--------------------------------------------------------------------------------
library IEEE;
use IEEE.Std_Logic_1164.all;
use IEEE.Numeric_Std.all;
--**--
package UART_Def is
-----------------------------------------------------------------------------
-- Converts unsigned Std_LOGIC_Vector to Integer, leftmost bit is MSB
-- Error message for unknowns (U, X, W, Z, -), converted to 0
-- Verifies whether vector is too long (> 16 bits)
-----------------------------------------------------------------------------
function ToInteger (
Invector : in Unsigned(3 downto 0))
return Integer;
end UART_Def; --==================== End of package header ======================--
package body UART_Def is
function ToInteger (
InVector : in Unsigned(3 downto 0))
return Integer is
variable Result : Integer := 0;
constant HeaderMsg : String := "To_Integer:";
constant MsgSeverity : Severity_Level := Warning;
begin
for i in 0 to 3 loop
if (InVector(i) = '1') then
Result := Result + (2**I);
end if;
end loop;
return Result;
end ToInteger;
end UART_Def; --================ End of package body ================--
 
 
/tags/arelease/vhdl/testbench2.vhd
0,0 → 1,138
--===========================================================================--
--
-- CPU68 Microprocessor Test Bench 2
--
--
-- John Kent 21st October 2002
--
--
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
use ieee.numeric_std.all;
 
entity my_testbench is
end my_testbench;
 
-------------------------------------------------------------------------------
-- Architecture for memio Controller Unit
-------------------------------------------------------------------------------
architecture behavior of my_testbench is
-----------------------------------------------------------------------------
-- Signals
-----------------------------------------------------------------------------
signal uart_irq : Std_Logic;
signal timer_irq : std_logic;
 
-- Sequencer Interface signals
signal SysClk : Std_Logic;
signal cpu_reset : Std_Logic;
signal cpu_rw : std_logic;
signal cpu_vma : std_logic;
signal cpu_addr : Std_Logic_Vector(15 downto 0);
signal cpu_data_in : Std_Logic_Vector(7 downto 0);
signal cpu_data_out: Std_Logic_Vector(7 downto 0);
 
constant width : integer := 8;
constant memsize : integer := 64;
 
type rom_array is array(0 to memsize-1) of std_logic_vector(width-1 downto 0);
 
constant rom_data : rom_array :=
(
"10001110", "11111111", "11011101", -- FFC0 - 8E FFDD RESET LDS #$FFDD
"11001110", "00010010", "00110100", -- FFC3 - CE 1234 LDX #$1234
"10001101", "00000100", -- FFC6 - 8D 04 BSR SAVGET
"00100111", "11110110", -- FFC8 - 27 F6 REENT BEQ RESET
"00100000", "11111110", -- FFCA - 20 FF BRA *
"11111111", "11111111", "11110000", -- FFCC - FF FFF0 SAVGET STX $FFF0
"11111110", "11111111", "11011001", -- FFCF - FE FFD9 LDX $FFD9
"00110111", -- FFD2 - 37 PSHB
"11100110", "00000001", -- FFD3 - E6 01 LDAB 1,X
"11100001", "00000011", -- FFD5 - E1 03 CMPB 3,X
"00110011", -- FFD7 - 33 PULB
"00111001", -- FFD8 - 39 RTS
"11111111", "11100000", -- FFD9 - FF E0 FDB $FFE0
"01010101", -- FFDB - 55 FCB $55
"11111111", "11001000", -- FFDC - FFC8 FDB REENT
"00100000", "11100000", -- FFDE - 20 E0 BRA RESET
"00000000", "00000000", -- FFE0 - 00 00 fcb $00,$00
"00000000", "00000000", -- FFE2 - 00 00 fcb $00,$00
"00000000", "00000000", -- FFE4 - 00 00 fcb $00,$00
"00000000", "00000000", -- FFE6 - 00 00 fcb $00,$00
"01001000", "01100101", "01101100", -- FFE8 - 48 65 6c MSG FCC "Hel"
"01101100", "01101111", "00100000", -- FFEB - 6c 6f 20 FCC "lo "
"01010111", "01101111", "01110010", -- FFEE - 57 6f 72 FCC "Wor"
"01101100", "01100100", -- FFF1 - 6c 64 FCC "ld"
"00001010", "00001101", "00000000", -- FFF3 - 0a 0d 00 FCB LF,CR,NULL
"00000000", "00000000", -- FFF6 - 00 00 fcb null,null
"11111111", "11000000", -- FFF8 - FF C0 fdb $FFC0 ; Timer irq
"11111111", "11000000", -- FFFA - FF C0 fdb $FFC0 ; Ext IRQ
"11111111", "11000000", -- FFFC - FF C0 fcb $FFC0 ; SWI
"11111111", "11000000" -- FFFE - FF C0 fdb $FFC0 ; Reset
);
 
component cpu68
port (
data_in: in std_logic_vector(7 downto 0);
data_out: out std_logic_vector(7 downto 0);
address: out std_logic_vector(15 downto 0);
vma: out std_logic;
rw: out std_logic; -- Asynchronous memory interface
rst: in std_logic;
clk: in std_logic;
irq: in std_logic;
nmi: in std_logic
);
end component cpu68;
 
 
begin
cpu : cpu68 port map (
data_in => cpu_data_in,
data_out => cpu_data_out,
address => cpu_addr(15 downto 0),
vma => cpu_vma,
rw => cpu_rw,
rst => cpu_reset,
clk => SysClk,
irq => uart_irq,
nmi => timer_irq
);
 
-- *** Test Bench - User Defined Section ***
tb : PROCESS
variable count : integer;
BEGIN
 
cpu_reset <= '0';
SysClk <= '0';
uart_irq <= '0';
timer_irq <= '0';
 
for count in 0 to 256 loop
SysClk <= '0';
if count = 0 then
cpu_reset <= '1';
elsif count = 1 then
cpu_reset <= '0';
end if;
wait for 100 ns;
SysClk <= '1';
wait for 100 ns;
end loop;
 
wait; -- will wait forever
END PROCESS;
-- *** End Test Bench - User Defined Section ***
 
 
rom : PROCESS( cpu_addr )
begin
cpu_data_in <= rom_data(conv_integer(cpu_addr(5 downto 0)));
end process;
 
end behavior; --===================== End of architecture =======================--
 
/tags/arelease/vhdl/System68.vhd
0,0 → 1,476
--===========================================================================--
--
-- S Y N T H E Z I A B L E System68 System On a Chip
--
-- www.OpenCores.Org - December 2002
-- This core adheres to the GNU public license
--
-- File name : system68.vhd
--
-- Purpose : Top level file for a 6800 compatible system on a chip
-- Designed for the Burch ED B3-Spartan II board with
-- X2S200 FPGA, 128 x 16 Word SRAM module and CPU I/O module
-- Using mimiUart from open cores modified to look like a 6850
--
-- Dependencies : ieee.Std_Logic_1164
-- ieee.std_logic_unsigned
-- ieee.std_logic_arith
-- ieee.numeric_std
--
-- Uses : miniuart.vhd, rxunit.vhd, tx_unit.vhd, clkunit.vhd
-- swtbug.vhd (6800 SWTBUG ROM)
-- datram.vhd (Dynamic address translation registers)
-- ioport.vhd (4 x 8 port parallel I/O )
-- cpu68.vhd (6800 compatible CPU core)
-- timer.vhd (timer module)
--
-- Author : John E. Kent
--
--===========================================================================----
--
-- Revision History:
--===========================================================================--
--
-- Date: Revision Author
-- 22 September 2002 0.1 John Kent
-- Initial design.
--
-------------------------------------------------------------------------------
--
-- Memory Map:
--
-- $0000 - $7FFF RAM
-- $8000 - $9FFF IO
-- $8000 - $8003 Timer
-- $8004 - $8007 MiniUart / Acia
-- $8008 - $800F IO Port
-- $A000 - $DFFF RAM
-- $E000 - $FFFF ROM (read) & DAT (write)
--
library ieee;
use ieee.std_logic_1164.all;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
use ieee.numeric_std.all;
 
entity System68 is
port(
SysClk : in Std_Logic; -- System Clock input
Reset_n : in Std_logic; -- Master Reset input (active low)
LED : out std_logic; -- Diagnostic LED Flasher
 
-- Memory Interface signals
ram_csn : out Std_Logic; -- RAM Chip select (active low)
ram_wrln : out Std_Logic; -- lower byte write strobe (active low)
ram_wrun : out Std_Logic; -- upper byte write strobe (active low)
ram_addr : out Std_Logic_Vector(16 downto 0); -- RAM Address bus
ram_data : inout Std_Logic_Vector(15 downto 0); -- RAM Data bus
 
-- Stuff on the peripheral board
-- aux_clock : in Std_Logic; -- FPGA-CPU-IO clock
 
-- PS/2 Mouse interface
-- mouse_clock : in Std_Logic;
-- mouse_data : in Std_Logic;
 
-- Uart Interface
rxbit : in Std_Logic; -- UART receive data
txbit : out Std_Logic; -- UART transmit data
rts_n : out Std_Logic; -- Request to send (active low)
cts_n : in Std_Logic; -- Clear to send (active low)
 
-- CRTC output signals
-- Signal defined on B3-CPU-IO Module
-- Not currently used.
v_drive : out Std_Logic;
h_drive : out Std_Logic;
blue_lo : out std_logic;
blue_hi : out std_logic;
green_lo : out std_logic;
green_hi : out std_logic;
red_lo : out std_logic;
red_hi : out std_logic;
buzzer : out std_logic;
 
-- I/O Ports
PortA : inout std_logic_vector(7 downto 0);
PortB : inout std_logic_vector(7 downto 0);
PortC : inout std_logic_vector(7 downto 0);
PortD : inout std_logic_vector(7 downto 0);
 
-- Timer I/O
timer_out : out std_logic;
 
-- Test Pins
uart_csn : out std_logic; -- Uart chip select out (active low)
test_rw : out std_logic; -- Read / Write signal
test_d0 : out std_logic; -- Uart Chip select ANDed with Receive Data Ready bit
test_d1 : out std_logic; -- Uart Chip select ANDed with Transmit Data Ready bit
 
test_alu : out std_logic_vector(15 downto 0); -- ALU output for timing constraints
test_cc : out std_logic_vector(7 downto 0) -- Condition Code Outputs for timing constraints
);
end System68;
 
-------------------------------------------------------------------------------
-- Architecture for memio Controller Unit
-------------------------------------------------------------------------------
architecture my_computer of System68 is
-----------------------------------------------------------------------------
-- Signals
-----------------------------------------------------------------------------
-- BOOT ROM
signal rom_data_out : Std_Logic_Vector(7 downto 0);
 
-- UART Interface signals
signal uart_data_out : Std_Logic_Vector(7 downto 0);
signal uart_cs : Std_Logic;
signal uart_irq : Std_Logic;
 
-- timer
signal timer_data_out : std_logic_vector(7 downto 0);
signal timer_cs : std_logic;
signal timer_irq : std_logic;
 
-- i/o port
signal ioport_data_out : std_logic_vector(7 downto 0);
signal ioport_cs : std_logic;
 
-- RAM
signal ram_cs : std_logic; -- memory chip select
signal ram_wrl : std_logic; -- memory write lower
signal ram_wru : std_logic; -- memory write upper
signal ram_data_out : std_logic_vector(7 downto 0);
 
-- CPU Interface signals
signal cpu_reset : Std_Logic;
signal cpu_clk : Std_Logic;
signal cpu_rw : std_logic;
signal cpu_vma : std_logic;
signal cpu_irq : std_logic;
signal cpu_nmi : std_logic;
signal cpu_addr : Std_Logic_Vector(15 downto 0);
signal cpu_data_in : Std_Logic_Vector(7 downto 0);
signal cpu_data_out: Std_Logic_Vector(7 downto 0);
 
-- Dynamic Address Translation RAM
signal dat_cs : std_logic;
signal dat_addr : std_logic_vector(7 downto 0);
 
-- Flashing Led test signals
signal countL : std_logic_vector(23 downto 0);
 
 
-----------------------------------------------------------------
--
-- Open Cores Mini UART
--
-----------------------------------------------------------------
 
component miniUART is
port (
SysClk : in Std_Logic; -- System Clock
rst : in Std_Logic; -- Reset input
cs : in Std_Logic;
rw : in Std_Logic;
RxD : in Std_Logic;
TxD : out Std_Logic;
CTS_n : in Std_Logic;
RTS_n : out Std_Logic;
Irq : out Std_logic;
Addr : in Std_Logic;
DataIn : in Std_Logic_Vector(7 downto 0); --
DataOut : out Std_Logic_Vector(7 downto 0)); --
end component;
 
--------------------------------------
--
-- Three port parallel I/O
--
---------------------------------------
 
component ioport is
port (
clk : in std_logic;
rst : in std_logic;
cs : in std_logic;
rw : in std_logic;
addr : in std_logic_vector(2 downto 0);
data_in : in std_logic_vector(7 downto 0);
data_out : out std_logic_vector(7 downto 0);
porta_io : inout std_logic_vector(7 downto 0);
portb_io : inout std_logic_vector(7 downto 0);
portc_io : inout std_logic_vector(7 downto 0);
portd_io : inout std_logic_vector(7 downto 0)
);
end component;
 
----------------------------------------
--
-- Timer module
--
----------------------------------------
 
component timer is
port (
clk : in std_logic;
rst : in std_logic;
cs : in std_logic;
rw : in std_logic;
addr : in std_logic;
data_in : in std_logic_vector(7 downto 0);
data_out : out std_logic_vector(7 downto 0);
irq : out std_logic;
timer_in : in std_logic;
timer_out : out std_logic
);
end component timer;
 
component cpu68 is
port (
clk: in std_logic;
rst: in std_logic;
rw: out std_logic; -- Asynchronous memory interface
vma: out std_logic;
address: out std_logic_vector(15 downto 0);
data_in: in std_logic_vector(7 downto 0);
data_out: out std_logic_vector(7 downto 0);
irq: in std_logic;
nmi: in std_logic;
test_alu: out std_logic_vector(15 downto 0);
test_cc: out std_logic_vector(7 downto 0)
);
end component cpu68;
 
component dat_ram is
port (
clk: in std_logic;
rst: in std_logic;
cs: in std_logic;
rw: in std_logic;
addr_lo: in std_logic_vector(3 downto 0);
addr_hi: in std_logic_vector(3 downto 0);
data_in: in std_logic_vector(7 downto 0);
data_out: out std_logic_vector(7 downto 0)
);
end component dat_ram;
 
component boot_rom is
port (
addr : in Std_Logic_Vector(9 downto 0); -- 1K byte boot rom
data : out Std_Logic_Vector(7 downto 0)
);
end component boot_rom;
 
begin
-----------------------------------------------------------------------------
-- Instantiation of internal components
-----------------------------------------------------------------------------
 
my_uart : miniUART port map (
SysClk => SysClk,
rst => cpu_reset,
cs => uart_cs,
rw => cpu_rw,
RxD => rxbit,
TxD => txbit,
CTS_n => cts_n,
RTS_n => rts_n,
Irq => uart_irq,
Addr => cpu_addr(0),
Datain => cpu_data_out,
DataOut => uart_data_out
);
 
my_ioport : ioport port map (
clk => SysClk,
rst => cpu_reset,
cs => ioport_cs,
rw => cpu_rw,
addr => cpu_addr(2 downto 0),
data_in => cpu_data_out,
data_out => ioport_data_out,
porta_io => porta,
portb_io => portb,
portc_io => portc,
portd_io => portd
);
 
my_timer : timer port map (
clk => SysClk,
rst => cpu_reset,
cs => timer_cs,
rw => cpu_rw,
addr => cpu_addr(0),
data_in => cpu_data_out,
data_out => timer_data_out,
irq => timer_irq,
timer_in => CountL(5),
timer_out => timer_out
);
 
my_cpu : cpu68 port map (
clk => SysClk,
rst => cpu_reset,
rw => cpu_rw,
vma => cpu_vma,
address => cpu_addr(15 downto 0),
data_in => cpu_data_in,
data_out => cpu_data_out,
irq => cpu_irq,
nmi => cpu_nmi,
test_alu => test_alu,
test_cc => test_cc
);
 
 
my_dat : dat_ram port map (
clk => SysClk,
rst => cpu_reset,
cs => dat_cs,
rw => cpu_rw,
addr_hi => cpu_addr(15 downto 12),
addr_lo => cpu_addr(3 downto 0),
data_in => cpu_data_out,
data_out => dat_addr(7 downto 0)
);
 
my_rom : boot_rom port map (
addr => cpu_addr(9 downto 0),
data => rom_data_out
);
----------------------------------------------------------------------
--
-- Processes to read and write memory based on bus signals
--
----------------------------------------------------------------------
 
memory: process( SysClk, Reset_n,
cpu_addr, cpu_rw, cpu_vma, cpu_data_out,
ram_cs, ram_wrl, ram_wru, dat_addr,
rom_data_out, ram_data_out,
ioport_data_out, timer_data_out, uart_data_out )
begin
case cpu_addr(15 downto 13) is
when "111" => -- $E000 - $FFFF
cpu_data_in <= rom_data_out;
dat_cs <= cpu_vma;
ram_cs <= '0';
uart_cs <= '0';
ioport_cs <= '0';
timer_cs <= '0';
when "100" => -- $8000 - $9FFF
dat_cs <= '0';
ram_cs <= '0';
case cpu_addr(5 downto 2) is
when "0000" => -- $8000
cpu_data_in <= timer_data_out;
uart_cs <= '0';
ioport_cs <= '0';
timer_cs <= cpu_vma;
when "0001" => -- $8004
cpu_data_in <= uart_data_out;
uart_cs <= cpu_vma;
ioport_cs <= '0';
timer_cs <= '0';
when "0010" | "0011" => -- $8008/$800C
cpu_data_in <= ioport_data_out;
uart_cs <= '0';
ioport_cs <= cpu_vma;
timer_cs <= '0';
when others => -- $8010 to $9FFF
cpu_data_in <= "00000000";
uart_cs <= '0';
ioport_cs <= '0';
timer_cs <= '0';
end case;
when others =>
cpu_data_in <= ram_data_out;
ram_cs <= cpu_vma;
dat_cs <= '0';
uart_cs <= '0';
ioport_cs <= '0';
timer_cs <= '0';
end case;
cpu_reset <= not Reset_n; -- CPU reset is active high
ram_csn <= not( ram_cs and Reset_n );
ram_wrl <= (not dat_addr(5)) and (not cpu_rw) and SysClk;
ram_wrln <= not ram_wrl;
ram_wru <= dat_addr(5) and (not cpu_rw) and SysClk;
ram_wrun <= not ram_wru;
ram_addr(16 downto 12) <= dat_addr(4 downto 0);
ram_addr(11 downto 0) <= cpu_addr(11 downto 0);
 
if ram_wrl = '1' then
ram_data(7 downto 0) <= cpu_data_out;
else
ram_data(7 downto 0) <= "ZZZZZZZZ";
end if;
 
if ram_wru = '1' then
ram_data(15 downto 8) <= cpu_data_out;
else
ram_data(15 downto 8) <= "ZZZZZZZZ";
end if;
 
if dat_addr(5) = '1' then
ram_data_out <= ram_data(15 downto 8);
else
ram_data_out <= ram_data(7 downto 0);
end if;
-- test pins
uart_csn <= not uart_cs;
test_rw <= cpu_rw;
test_d0 <= uart_data_out(0) and uart_cs;
test_d1 <= uart_data_out(1) and uart_cs;
end process;
 
--
-- tie together interrupts
--
interrupts : process( timer_irq, uart_irq )
begin
cpu_irq <= uart_irq;
cpu_nmi <= timer_irq;
end process;
 
--
--
--clock_gen : process( SysClk, e_clk )
--begin
-- if SysClk'event and SysClk='1' then
-- e_clk <= not e_clk;
-- end if;
--end process;
 
--
-- flash led to indicate code is working
--
increment: process (SysClk, CountL )
begin
if(SysClk'event and SysClk = '1') then
countL <= countL + 1;
end if;
LED <= countL(21);
end process;
 
uncommitted: process( SysClk )
begin
--
-- CRTC output signals
--
v_drive <= '0';
h_drive <= '0';
blue_lo <= '0';
blue_hi <= '0';
green_lo <= '0';
green_hi <= '0';
red_lo <= '0';
red_hi <= '0';
buzzer <= '0';
end process;
 
end my_computer; --===================== End of architecture =======================--
 
/tags/arelease/vhdl/testbench3.vhd
0,0 → 1,141
--===========================================================================--
--
-- CPU68 Microprocessor Test Bench 3
--
-- 16 bit compare test (CPX)
--
-- John Kent 21st October 2002
--
--
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
use ieee.numeric_std.all;
 
entity my_testbench is
end my_testbench;
 
-------------------------------------------------------------------------------
-- Architecture for memio Controller Unit
-------------------------------------------------------------------------------
architecture behavior of my_testbench is
-----------------------------------------------------------------------------
-- Signals
-----------------------------------------------------------------------------
signal uart_irq : Std_Logic;
signal timer_irq : std_logic;
 
-- Sequencer Interface signals
signal SysClk : Std_Logic;
signal cpu_reset : Std_Logic;
signal cpu_rw : std_logic;
signal cpu_vma : std_logic;
signal cpu_addr : Std_Logic_Vector(15 downto 0);
signal cpu_data_in : Std_Logic_Vector(7 downto 0);
signal cpu_data_out: Std_Logic_Vector(7 downto 0);
 
constant width : integer := 8;
constant memsize : integer := 64;
 
type rom_array is array(0 to memsize-1) of std_logic_vector(width-1 downto 0);
 
constant rom_data : rom_array :=
(
"10001110", "11111111", "11011101", -- FFC0 - 8E FFDD RESET LDS #$FFDD
"11111110", "11111111", "11001110", -- FFC3 - FE FFCE LDX BEGA
"00001000", -- FFC6 - 08 LOOP INX
"10111100", "11111111", "11010000", -- FFC7 - BC FFD0 CPX ENDA
"00100011", "11111010", -- FFCA - 23 FA REENT BLS LOOP
"00100000", "11110010", -- FFCC - 20 F2 BRA RESET
"00010010", "00110100", -- FFCE - 12 34 FDB $1234
"00010010", "00110110", -- FFD0 - 12 36 FDB $1236
-- the rest is junk
"00110111", -- FFD2 - 37 PSHB
"11100110", "00000001", -- FFD3 - E6 01 LDAB 1,X
"11100001", "00000011", -- FFD5 - E1 03 CMPB 3,X
"00110011", -- FFD7 - 33 PULB
"00111001", -- FFD8 - 39 RTS
"11111111", "11100000", -- FFD9 - FF E0 FDB $FFE0
"01010101", -- FFDB - 55 FCB $55
"11111111", "11001000", -- FFDC - FFC8 FDB REENT
"00100000", "11100000", -- FFDE - 20 E0 BRA RESET
"00000000", "00000000", -- FFE0 - 00 00 fcb $00,$00
"00000000", "00000000", -- FFE2 - 00 00 fcb $00,$00
"00000000", "00000000", -- FFE4 - 00 00 fcb $00,$00
"00000000", "00000000", -- FFE6 - 00 00 fcb $00,$00
"01001000", "01100101", "01101100", -- FFE8 - 48 65 6c MSG FCC "Hel"
"01101100", "01101111", "00100000", -- FFEB - 6c 6f 20 FCC "lo "
"01010111", "01101111", "01110010", -- FFEE - 57 6f 72 FCC "Wor"
"01101100", "01100100", -- FFF1 - 6c 64 FCC "ld"
"00001010", "00001101", "00000000", -- FFF3 - 0a 0d 00 FCB LF,CR,NULL
"00000000", "00000000", -- FFF6 - 00 00 fcb null,null
"11111111", "11000000", -- FFF8 - FF C0 fdb $FFC0 ; Timer irq
"11111111", "11000000", -- FFFA - FF C0 fdb $FFC0 ; Ext IRQ
"11111111", "11000000", -- FFFC - FF C0 fcb $FFC0 ; SWI
"11111111", "11000000" -- FFFE - FF C0 fdb $FFC0 ; Reset
);
 
component cpu68
port (
data_in: in std_logic_vector(7 downto 0);
data_out: out std_logic_vector(7 downto 0);
address: out std_logic_vector(15 downto 0);
vma: out std_logic;
rw: out std_logic; -- Asynchronous memory interface
rst: in std_logic;
clk: in std_logic;
irq: in std_logic;
nmi: in std_logic
);
end component cpu68;
 
 
begin
cpu : cpu68 port map (
data_in => cpu_data_in,
data_out => cpu_data_out,
address => cpu_addr(15 downto 0),
vma => cpu_vma,
rw => cpu_rw,
rst => cpu_reset,
clk => SysClk,
irq => uart_irq,
nmi => timer_irq
);
 
-- *** Test Bench - User Defined Section ***
tb : PROCESS
variable count : integer;
BEGIN
 
cpu_reset <= '0';
SysClk <= '0';
uart_irq <= '0';
timer_irq <= '0';
 
for count in 0 to 256 loop
SysClk <= '0';
if count = 0 then
cpu_reset <= '1';
elsif count = 1 then
cpu_reset <= '0';
end if;
wait for 100 ns;
SysClk <= '1';
wait for 100 ns;
end loop;
 
wait; -- will wait forever
END PROCESS;
-- *** End Test Bench - User Defined Section ***
 
 
rom : PROCESS( cpu_addr )
begin
cpu_data_in <= rom_data(conv_integer(cpu_addr(5 downto 0)));
end process;
 
end behavior; --===================== End of architecture =======================--
 
/tags/arelease/vhdl/cpu68.vhd
0,0 → 1,3747
--===========================================================================--
--
-- S Y N T H E Z I A B L E CPU68 C O R E
--
-- www.OpenCores.Org - December 2002
-- This core adheres to the GNU public license
--
-- File name : cpu68.vhd
--
-- Purpose : Implements a 6800 compatible CPU core with some
-- additional instructions found in the 6801
--
-- Dependencies : ieee.Std_Logic_1164
-- ieee.std_logic_unsigned
--
-- Author : John E. Kent
--
--===========================================================================----
--
-- Revision History:
--
-- Date: Revision Author
-- 22 Sep 2002 0.1 John Kent
--
-- 30 Oct 2002 0.2 John Kent
-- made NMI edge triggered
--
-- 30 Oct 2002 0.3 John Kent
-- more corrections to NMI
-- added wai_wait_state to prevent stack overflow on wai.
--
-- 1 Nov 2002 0.4 John Kent
-- removed WAI states and integrated WAI with the interrupt service routine
-- replace Data out (do) and Data in (di) register with a single Memory Data (md) reg.
-- Added Multiply instruction states.
-- run ALU and CC out of CPU module for timing measurements.
--
-- 3 Nov 2002 0.5 John Kent
-- Memory Data Register was not loaded on Store instructions
-- SEV and CLV were not defined in the ALU
-- Overflow Flag on NEG was incorrect
--
 
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
 
entity cpu68 is
port (
clk: in std_logic;
rst: in std_logic;
rw: out std_logic;
vma: out std_logic;
address: out std_logic_vector(15 downto 0);
data_in: in std_logic_vector(7 downto 0);
data_out: out std_logic_vector(7 downto 0);
irq: in std_logic;
nmi: in std_logic;
test_alu: out std_logic_vector(15 downto 0);
test_cc: out std_logic_vector(7 downto 0)
);
end;
 
architecture CPU_ARCH of cpu68 is
 
constant SBIT : integer := 7;
constant XBIT : integer := 6;
constant HBIT : integer := 5;
constant IBIT : integer := 4;
constant NBIT : integer := 3;
constant ZBIT : integer := 2;
constant VBIT : integer := 1;
constant CBIT : integer := 0;
 
type state_type is (reset_state, fetch_state, decode_state,
extended_state, indexed_state, direct_state, direct16_state, immediate16_state,
write8_state, write16_state,
execute_state, halt_state,
mul_state, mulea_state, muld_state,
mul0_state, mul1_state, mul2_state, mul3_state,
mul4_state, mul5_state, mul6_state, mul7_state,
jmp_state, jsr_state, jsr1_state,
branch_state, bsr_state, bsr1_state,
rts_hi_state, rts_lo_state,
int_pcl_state, int_pch_state,
int_ixl_state, int_ixh_state,
int_cc_state, int_acca_state, int_accb_state,
int_wai_state, int_mask_state,
rti_state, rti_cc_state, rti_acca_state, rti_accb_state,
rti_ixl_state, rti_ixh_state,
rti_pcl_state, rti_pch_state,
pula_state, psha_state, pulb_state, pshb_state,
pulx_lo_state, pulx_hi_state, pshx_lo_state, pshx_hi_state,
vect_lo_state, vect_hi_state );
type addr_type is (idle_ad, fetch_ad, read_ad, write_ad, push_ad, pull_ad, int_hi_ad, int_lo_ad );
type dout_type is (md_lo_dout, md_hi_dout, acca_dout, accb_dout, ix_lo_dout, ix_hi_dout, cc_dout, pc_lo_dout, pc_hi_dout );
type op_type is (reset_op, fetch_op, latch_op );
type acca_type is (reset_acca, load_acca, load_hi_acca, pull_acca, latch_acca );
type accb_type is (reset_accb, load_accb, pull_accb, latch_accb );
type cc_type is (reset_cc, load_cc, pull_cc, latch_cc );
type ix_type is (reset_ix, load_ix, pull_lo_ix, pull_hi_ix, latch_ix );
type sp_type is (reset_sp, latch_sp, load_sp );
type pc_type is (reset_pc, latch_pc, load_pc, pull_lo_pc, pull_hi_pc );
type md_type is (reset_md, latch_md, load_md, fetch_first_md, fetch_next_md, shiftl_md );
type ea_type is (reset_ea, latch_ea, load_ea, fetch_first_ea, fetch_next_ea );
type iv_type is (reset_iv, latch_iv, swi_iv, nmi_iv, irq_iv );
type nmi_type is (reset_nmi, set_nmi, latch_nmi );
type left_type is (acca_left, accb_left, accd_left, md_left, ix_left, pc_left, sp_left, ea_left );
type right_type is (md_right, zero_right, plus_one_right, accb_right, ea_right, sexea_right );
type alu_type is (alu_add8, alu_sub8, alu_add16, alu_sub16, alu_adc, alu_sbc,
alu_and, alu_ora, alu_eor,
alu_tst, alu_inc, alu_dec, alu_clr, alu_neg, alu_com,
alu_inx, alu_dex, alu_cpx,
alu_lsr16, alu_lsl16,
alu_ror8, alu_rol8,
alu_asr8, alu_asl8, alu_lsr8,
alu_sei, alu_cli, alu_sec, alu_clc, alu_sev, alu_clv, alu_tpa, alu_tap,
alu_ld8, alu_st8, alu_ld16, alu_st16, alu_nop, alu_daa );
 
signal op_code: std_logic_vector(7 downto 0);
signal acca: std_logic_vector(7 downto 0);
signal accb: std_logic_vector(7 downto 0);
signal cc: std_logic_vector(7 downto 0);
signal cc_out: std_logic_vector(7 downto 0);
signal xreg: std_logic_vector(15 downto 0);
signal sp: std_logic_vector(15 downto 0);
signal ea: std_logic_vector(15 downto 0);
signal pc: std_logic_vector(15 downto 0);
signal md: std_logic_vector(15 downto 0);
signal left: std_logic_vector(15 downto 0);
signal right: std_logic_vector(15 downto 0);
signal out_alu: std_logic_vector(15 downto 0);
signal iv: std_logic_vector(1 downto 0);
signal nmi_req: std_logic;
signal nmi_ack: std_logic;
 
signal state: state_type;
signal next_state: state_type;
signal pc_ctrl: pc_type;
signal ea_ctrl: ea_type;
signal op_ctrl: op_type;
signal md_ctrl: md_type;
signal acca_ctrl: acca_type;
signal accb_ctrl: accb_type;
signal ix_ctrl: ix_type;
signal cc_ctrl: cc_type;
signal sp_ctrl: sp_type;
signal iv_ctrl: iv_type;
signal left_ctrl: left_type;
signal right_ctrl: right_type;
signal alu_ctrl: alu_type;
signal addr_ctrl: addr_type;
signal dout_ctrl: dout_type;
signal nmi_ctrl: nmi_type;
 
 
begin
 
----------------------------------
--
-- Address output multiplexer
--
----------------------------------
 
addr_mux: process( clk, addr_ctrl, pc, ea, sp, iv )
begin
case addr_ctrl is
when idle_ad =>
address <= "1111111111111111";
vma <= '0';
rw <= '1';
when fetch_ad =>
address <= pc;
vma <= '1';
rw <= '1';
when read_ad =>
address <= ea;
vma <= '1';
rw <= '1';
when write_ad =>
address <= ea;
vma <= '1';
rw <= '0';
when push_ad =>
address <= sp;
vma <= '1';
rw <= '0';
when pull_ad =>
address <= sp;
vma <= '1';
rw <= '1';
when int_hi_ad =>
address <= "1111111111111" & iv & "0";
vma <= '1';
rw <= '1';
when int_lo_ad =>
address <= "1111111111111" & iv & "1";
vma <= '1';
rw <= '1';
when others =>
address <= "1111111111111111";
vma <= '0';
rw <= '1';
end case;
end process;
 
----------------------------------
--
-- Program Counter Control
--
----------------------------------
 
pc_mux: process( clk, pc_ctrl, pc, out_alu, data_in )
begin
if clk'event and clk = '1' then
case pc_ctrl is
when reset_pc =>
pc <= "0000000000000000";
when load_pc =>
pc <= out_alu(15 downto 0);
when pull_lo_pc =>
pc(7 downto 0) <= data_in;
when pull_hi_pc =>
pc(15 downto 8) <= data_in;
when others =>
-- when latch_pc =>
pc <= pc;
end case;
end if;
end process;
 
----------------------------------
--
-- Effective Address Control
--
----------------------------------
 
ea_mux: process( clk, ea_ctrl, ea, out_alu, data_in )
begin
 
if clk'event and clk = '1' then
case ea_ctrl is
when reset_ea =>
ea <= "0000000000000000";
when fetch_first_ea =>
ea(7 downto 0) <= data_in;
ea(15 downto 8) <= "00000000";
when fetch_next_ea =>
ea(15 downto 8) <= ea(7 downto 0);
ea(7 downto 0) <= data_in;
when load_ea =>
ea <= out_alu(15 downto 0);
when others =>
-- when latch_ea =>
ea <= ea;
end case;
end if;
end process;
 
--------------------------------
--
-- Accumulator A
--
--------------------------------
acca_mux : process( clk, acca_ctrl, out_alu, acca, data_in )
begin
if clk'event and clk = '1' then
case acca_ctrl is
when reset_acca =>
acca <= "00000000";
when load_acca =>
acca <= out_alu(7 downto 0);
when load_hi_acca =>
acca <= out_alu(15 downto 8);
when pull_acca =>
acca <= data_in;
when others =>
-- when latch_acca =>
acca <= acca;
end case;
end if;
end process;
 
--------------------------------
--
-- Accumulator B
--
--------------------------------
accb_mux : process( clk, accb_ctrl, out_alu, accb, data_in )
begin
if clk'event and clk = '1' then
case accb_ctrl is
when reset_accb =>
accb <= "00000000";
when load_accb =>
accb <= out_alu(7 downto 0);
when pull_accb =>
accb <= data_in;
when others =>
-- when latch_accb =>
accb <= accb;
end case;
end if;
end process;
 
--------------------------------
--
-- X Index register
--
--------------------------------
ix_mux : process( clk, ix_ctrl, out_alu, xreg, data_in )
begin
if clk'event and clk = '1' then
case ix_ctrl is
when reset_ix =>
xreg <= "0000000000000000";
when load_ix =>
xreg <= out_alu(15 downto 0);
when pull_hi_ix =>
xreg(15 downto 8) <= data_in;
when pull_lo_ix =>
xreg(7 downto 0) <= data_in;
when others =>
-- when latch_ix =>
xreg <= xreg;
end case;
end if;
end process;
 
--------------------------------
--
-- stack pointer
--
--------------------------------
sp_mux : process( clk, sp_ctrl, out_alu )
begin
if clk'event and clk = '1' then
case sp_ctrl is
when reset_sp =>
sp <= "0000000000000000";
when load_sp =>
sp <= out_alu(15 downto 0);
when others =>
-- when latch_sp =>
sp <= sp;
end case;
end if;
end process;
 
--------------------------------
--
-- Memory Data
--
--------------------------------
md_mux : process( clk, md_ctrl, out_alu, data_in, md )
begin
if clk'event and clk = '1' then
case md_ctrl is
when reset_md =>
md <= "0000000000000000";
when load_md =>
md <= out_alu(15 downto 0);
when fetch_first_md =>
md(15 downto 8) <= "00000000";
md(7 downto 0) <= data_in;
when fetch_next_md =>
md(15 downto 8) <= md(7 downto 0);
md(7 downto 0) <= data_in;
when shiftl_md =>
md(15 downto 1) <= md(14 downto 0);
md(0) <= '0';
when others =>
-- when latch_md =>
md <= md;
end case;
end if;
end process;
 
 
----------------------------------
--
-- Condition Codes
--
----------------------------------
 
cc_mux: process( clk, cc_ctrl, cc_out, cc, data_in )
begin
if clk'event and clk = '1' then
case cc_ctrl is
when reset_cc =>
cc <= "11000000";
when load_cc =>
cc <= cc_out;
when pull_cc =>
cc <= data_in;
when others =>
-- when latch_cc =>
cc <= cc;
end case;
end if;
end process;
 
----------------------------------
--
-- interrupt vector
--
----------------------------------
 
iv_mux: process( clk, iv_ctrl )
begin
if clk'event and clk = '1' then
case iv_ctrl is
when reset_iv =>
iv <= "11";
when nmi_iv =>
iv <= "10";
when swi_iv =>
iv <= "01";
when irq_iv =>
iv <= "00";
when others =>
iv <= iv;
end case;
end if;
end process;
 
 
--------------------------------
--
-- Data Bus output
--
--------------------------------
dout_mux : process( clk, dout_ctrl, md, acca, accb, xreg, pc, cc )
begin
case dout_ctrl is
when md_hi_dout => -- alu output
data_out <= md(15 downto 8);
when md_lo_dout =>
data_out <= md(7 downto 0);
when acca_dout => -- accumulator a
data_out <= acca;
when accb_dout => -- accumulator b
data_out <= accb;
when ix_lo_dout => -- index reg
data_out <= xreg(7 downto 0);
when ix_hi_dout => -- index reg
data_out <= xreg(15 downto 8);
when cc_dout => -- condition codes
data_out <= cc;
when pc_lo_dout => -- low order pc
data_out <= pc(7 downto 0);
when pc_hi_dout => -- high order pc
data_out <= pc(15 downto 8);
when others =>
data_out <= "00000000";
end case;
end process;
 
 
----------------------------------
--
-- op code fetch
--
----------------------------------
 
op_fetch: process( clk, data_in, op_ctrl, op_code )
begin
if clk'event and clk = '1' then
case op_ctrl is
when reset_op =>
op_code <= "00000001";
when fetch_op =>
op_code <= data_in;
when others =>
-- when latch_op =>
op_code <= op_code;
end case;
end if;
end process;
 
----------------------------------
--
-- Left Mux
--
----------------------------------
 
left_mux: process( left_ctrl, acca, accb, xreg, sp, pc, ea, md )
begin
case left_ctrl is
when acca_left =>
left(15 downto 8) <= "00000000";
left(7 downto 0) <= acca;
when accb_left =>
left(15 downto 8) <= "00000000";
left(7 downto 0) <= accb;
when accd_left =>
left(15 downto 8) <= acca;
left(7 downto 0) <= accb;
when md_left =>
left <= md;
when ix_left =>
left <= xreg;
when sp_left =>
left <= sp;
when pc_left =>
left <= pc;
when others =>
-- when ea_left =>
left <= ea;
end case;
end process;
----------------------------------
--
-- Right Mux
--
----------------------------------
 
right_mux: process( right_ctrl, data_in, md, accb, ea )
begin
case right_ctrl is
when zero_right =>
right <= "0000000000000000";
when plus_one_right =>
right <= "0000000000000001";
when accb_right =>
right <= "00000000" & accb;
when ea_right =>
right <= ea;
when sexea_right =>
if ea(7) = '0' then
right <= "00000000" & ea(7 downto 0);
else
right <= "11111111" & ea(7 downto 0);
end if;
when others =>
-- when md_right =>
right <= md;
end case;
end process;
 
----------------------------------
--
-- Arithmetic Logic Unit
--
----------------------------------
 
mux_alu: process( alu_ctrl, cc, left, right, out_alu, cc_out )
variable valid_lo, valid_hi : boolean;
variable carry_in : std_logic;
variable daa_reg : std_logic_vector(7 downto 0);
begin
 
case alu_ctrl is
when alu_adc | alu_sbc |
alu_rol8 | alu_ror8 =>
carry_in := cc(CBIT);
when others =>
carry_in := '0';
end case;
 
valid_lo := left(3 downto 0) <= 9;
valid_hi := left(7 downto 4) <= 9;
 
if (cc(CBIT) = '0') then
if( cc(HBIT) = '1' ) then
if valid_hi then
daa_reg := "00000110";
else
daa_reg := "01100110";
end if;
else
if valid_lo then
if valid_hi then
daa_reg := "00000000";
else
daa_reg := "01100000";
end if;
else
if( left(7 downto 4) <= 8 ) then
daa_reg := "00000110";
else
daa_reg := "01100110";
end if;
end if;
end if;
else
if ( cc(HBIT) = '1' )then
daa_reg := "01100110";
else
if valid_lo then
daa_reg := "01100000";
else
daa_reg := "01100110";
end if;
end if;
end if;
 
case alu_ctrl is
when alu_add8 | alu_inc |
alu_add16 | alu_inx |
alu_adc =>
out_alu <= left + right + ("000000000000000" & carry_in);
when alu_sub8 | alu_dec |
alu_sub16 | alu_dex |
alu_sbc | alu_cpx =>
out_alu <= left - right - ("000000000000000" & carry_in);
when alu_and =>
out_alu <= left and right; -- and/bit
when alu_ora =>
out_alu <= left or right; -- or
when alu_eor =>
out_alu <= left xor right; -- eor/xor
when alu_lsl16 | alu_asl8 | alu_rol8 =>
out_alu <= left(14 downto 0) & carry_in; -- rol8/asl8/lsl16
when alu_lsr16 | alu_lsr8 =>
out_alu <= carry_in & left(15 downto 1); -- lsr
when alu_ror8 =>
out_alu <= "00000000" & carry_in & left(7 downto 1); -- ror
when alu_asr8 =>
out_alu <= "00000000" & left(7) & left(7 downto 1); -- asr
when alu_neg =>
out_alu <= right - left; -- neg (right=0)
when alu_com =>
out_alu <= not left;
when alu_clr | alu_ld8 | alu_ld16 =>
out_alu <= right; -- clr, ld
when alu_st8 | alu_st16 =>
out_alu <= left;
when alu_daa =>
out_alu <= left + ("00000000" & daa_reg);
when alu_tpa =>
out_alu <= "00000000" & cc;
when others =>
out_alu <= left; -- nop
end case;
 
--
-- carry bit
--
case alu_ctrl is
when alu_add8 | alu_adc =>
cc_out(CBIT) <= (left(7) and right(7)) or
(left(7) and not out_alu(7)) or
(right(7) and not out_alu(7));
when alu_sub8 | alu_sbc =>
cc_out(CBIT) <= ((not left(7)) and right(7)) or
((not left(7)) and out_alu(7)) or
(right(7) and out_alu(7));
when alu_add16 =>
cc_out(CBIT) <= (left(15) and right(15)) or
(left(15) and not out_alu(15)) or
(right(15) and not out_alu(15));
when alu_sub16 =>
cc_out(CBIT) <= ((not left(15)) and right(15)) or
((not left(15)) and out_alu(15)) or
(right(15) and out_alu(15));
when alu_ror8 | alu_lsr16 | alu_lsr8 | alu_asr8 =>
cc_out(CBIT) <= left(0);
when alu_rol8 | alu_asl8 =>
cc_out(CBIT) <= left(7);
when alu_lsl16 =>
cc_out(CBIT) <= left(15);
when alu_com =>
cc_out(CBIT) <= '1';
when alu_neg | alu_clr =>
cc_out(CBIT) <= out_alu(7) or out_alu(6) or out_alu(5) or out_alu(4) or
out_alu(3) or out_alu(2) or out_alu(1) or out_alu(0);
when alu_daa =>
if ( daa_reg(7 downto 4) = "0110" ) then
cc_out(CBIT) <= '1';
else
cc_out(CBIT) <= '0';
end if;
when alu_sec =>
cc_out(CBIT) <= '1';
when alu_clc =>
cc_out(CBIT) <= '0';
when alu_tap =>
cc_out(CBIT) <= left(CBIT);
when others => -- carry is not affected by cpx
cc_out(CBIT) <= cc(CBIT);
end case;
--
-- Zero flag
--
case alu_ctrl is
when alu_add8 | alu_sub8 |
alu_adc | alu_sbc |
alu_and | alu_ora | alu_eor |
alu_inc | alu_dec |
alu_neg | alu_com | alu_clr |
alu_rol8 | alu_ror8 | alu_asr8 | alu_asl8 | alu_lsr8 |
alu_ld8 | alu_st8 =>
cc_out(ZBIT) <= not( out_alu(7) or out_alu(6) or out_alu(5) or out_alu(4) or
out_alu(3) or out_alu(2) or out_alu(1) or out_alu(0) );
when alu_add16 | alu_sub16 |
alu_lsl16 | alu_lsr16 |
alu_inx | alu_dex |
alu_ld16 | alu_st16 | alu_cpx =>
cc_out(ZBIT) <= not( out_alu(15) or out_alu(14) or out_alu(13) or out_alu(12) or
out_alu(11) or out_alu(10) or out_alu(9) or out_alu(8) or
out_alu(7) or out_alu(6) or out_alu(5) or out_alu(4) or
out_alu(3) or out_alu(2) or out_alu(1) or out_alu(0) );
when alu_tap =>
cc_out(ZBIT) <= left(ZBIT);
when others =>
cc_out(ZBIT) <= cc(ZBIT);
end case;
 
--
-- negative flag
--
case alu_ctrl is
when alu_add8 | alu_sub8 |
alu_adc | alu_sbc |
alu_and | alu_ora | alu_eor |
alu_rol8 | alu_ror8 | alu_asr8 | alu_asl8 | alu_lsr8 |
alu_inc | alu_dec | alu_neg | alu_com | alu_clr |
alu_ld8 | alu_st8 =>
cc_out(NBIT) <= out_alu(7);
when alu_add16 | alu_sub16 |
alu_lsl16 | alu_lsr16 |
alu_ld16 | alu_st16 | alu_cpx =>
cc_out(NBIT) <= out_alu(15);
when alu_tap =>
cc_out(NBIT) <= left(NBIT);
when others =>
cc_out(NBIT) <= cc(NBIT);
end case;
 
--
-- Interrupt mask flag
--
case alu_ctrl is
when alu_sei =>
cc_out(IBIT) <= '1'; -- set interrupt mask
when alu_cli =>
cc_out(IBIT) <= '0'; -- clear interrupt mask
when alu_tap =>
cc_out(IBIT) <= left(IBIT);
when others =>
cc_out(IBIT) <= cc(IBIT); -- interrupt mask
end case;
 
--
-- Half Carry flag
--
case alu_ctrl is
when alu_add8 | alu_adc =>
cc_out(HBIT) <= (left(3) and right(3)) or
(right(3) and not out_alu(3)) or
(left(3) and not out_alu(3));
when alu_tap =>
cc_out(HBIT) <= left(HBIT);
when others =>
cc_out(HBIT) <= cc(HBIT);
end case;
 
--
-- Overflow flag
--
case alu_ctrl is
when alu_add8 | alu_adc =>
cc_out(VBIT) <= (left(7) and right(7) and (not out_alu(7))) or
((not left(7)) and (not right(7)) and out_alu(7));
when alu_sub8 | alu_sbc =>
cc_out(VBIT) <= (left(7) and (not right(7)) and (not out_alu(7))) or
((not left(7)) and right(7) and out_alu(7));
when alu_add16 =>
cc_out(VBIT) <= (left(15) and right(15) and (not out_alu(15))) or
((not left(15)) and (not right(15)) and out_alu(15));
when alu_sub16 | alu_cpx =>
cc_out(VBIT) <= (left(15) and (not right(15)) and (not out_alu(15))) or
((not left(15)) and right(15) and out_alu(15));
when alu_inc =>
cc_out(VBIT) <= ((not left(7)) and left(6) and left(5) and left(4) and
left(3) and left(2) and left(1) and left(0));
when alu_dec | alu_neg =>
cc_out(VBIT) <= (left(7) and (not left(6)) and (not left(5)) and (not left(4)) and
(not left(3)) and (not left(2)) and (not left(1)) and (not left(0)));
when alu_asr8 =>
cc_out(VBIT) <= left(0) xor left(7);
when alu_lsr8 | alu_lsr16 =>
cc_out(VBIT) <= left(0);
when alu_ror8 =>
cc_out(VBIT) <= left(0) xor cc(CBIT);
when alu_lsl16 =>
cc_out(VBIT) <= left(15) xor left(14);
when alu_rol8 | alu_asl8 =>
cc_out(VBIT) <= left(7) xor left(6);
when alu_tap =>
cc_out(VBIT) <= left(VBIT);
when alu_and | alu_ora | alu_eor | alu_com |
alu_st8 | alu_st16 | alu_ld8 | alu_ld16 |
alu_clv =>
cc_out(VBIT) <= '0';
when alu_sev =>
cc_out(VBIT) <= '1';
when others =>
cc_out(VBIT) <= cc(VBIT);
end case;
 
case alu_ctrl is
when alu_tap =>
cc_out(XBIT) <= cc(XBIT) and left(XBIT);
cc_out(SBIT) <= left(SBIT);
when others =>
cc_out(XBIT) <= cc(XBIT) and left(XBIT);
cc_out(SBIT) <= cc(SBIT);
end case;
 
test_alu <= out_alu;
test_cc <= cc_out;
end process;
 
------------------------------------
--
-- Detect Edge of NMI interrupt
--
------------------------------------
 
nmi_handler : process( clk, rst, nmi, nmi_ack )
begin
if clk'event and clk='1' then
if rst='1' then
nmi_req <= '0';
else
if (nmi='1') and (nmi_ack='0') then
nmi_req <= '1';
else
if (nmi='0') and (nmi_ack='1') then
nmi_req <= '0';
else
nmi_req <= nmi_req;
end if;
end if;
end if;
end if;
end process;
 
------------------------------------
--
-- Nmi mux
--
------------------------------------
 
nmi_mux: process( clk, nmi_ctrl, nmi_ack )
begin
if clk'event and clk='1' then
case nmi_ctrl is
when set_nmi =>
nmi_ack <= '1';
when reset_nmi =>
nmi_ack <= '0';
when others =>
-- when latch_nmi =>
nmi_ack <= nmi_ack;
end case;
end if;
end process;
 
------------------------------------
--
-- state sequencer
--
------------------------------------
process( state, op_code, cc, ea, irq, nmi_req, nmi_ack )
begin
case state is
when reset_state => -- released from reset
-- reset the registers
op_ctrl <= reset_op;
acca_ctrl <= reset_acca;
accb_ctrl <= reset_accb;
ix_ctrl <= reset_ix;
sp_ctrl <= reset_sp;
pc_ctrl <= reset_pc;
ea_ctrl <= reset_ea;
md_ctrl <= reset_md;
iv_ctrl <= reset_iv;
nmi_ctrl <= reset_nmi;
sp_ctrl <= reset_sp;
-- idle the ALU
left_ctrl <= pc_left;
right_ctrl <= zero_right;
alu_ctrl <= alu_nop;
cc_ctrl <= reset_cc;
-- idle the bus
dout_ctrl <= md_lo_dout;
addr_ctrl <= idle_ad;
next_state <= vect_hi_state;
 
--
-- Jump via interrupt vector
-- iv holds interrupt type
-- fetch PC hi from vector location
--
when vect_hi_state =>
-- default the registers
op_ctrl <= latch_op;
nmi_ctrl <= latch_nmi;
acca_ctrl <= latch_acca;
accb_ctrl <= latch_accb;
ix_ctrl <= latch_ix;
sp_ctrl <= latch_sp;
md_ctrl <= latch_md;
ea_ctrl <= latch_ea;
iv_ctrl <= latch_iv;
-- idle the ALU
left_ctrl <= pc_left;
right_ctrl <= zero_right;
alu_ctrl <= alu_nop;
cc_ctrl <= latch_cc;
-- fetch pc low interrupt vector
pc_ctrl <= pull_hi_pc;
addr_ctrl <= int_hi_ad;
dout_ctrl <= pc_hi_dout;
next_state <= vect_lo_state;
--
-- jump via interrupt vector
-- iv holds vector type
-- fetch PC lo from vector location
--
when vect_lo_state =>
-- default the registers
op_ctrl <= latch_op;
nmi_ctrl <= latch_nmi;
acca_ctrl <= latch_acca;
accb_ctrl <= latch_accb;
ix_ctrl <= latch_ix;
sp_ctrl <= latch_sp;
md_ctrl <= latch_md;
ea_ctrl <= latch_ea;
iv_ctrl <= latch_iv;
-- idle the ALU
left_ctrl <= pc_left;
right_ctrl <= zero_right;
alu_ctrl <= alu_nop;
cc_ctrl <= latch_cc;
-- fetch the vector low byte
pc_ctrl <= pull_lo_pc;
addr_ctrl <= int_lo_ad;
dout_ctrl <= pc_lo_dout;
next_state <= fetch_state;
 
--
-- Here to fetch an instruction
-- PC points to opcode
-- Should service interrupt requests at this point
-- either from the timer
-- or from the external input.
--
when fetch_state =>
acca_ctrl <= latch_acca;
accb_ctrl <= latch_accb;
ix_ctrl <= latch_ix;
sp_ctrl <= latch_sp;
md_ctrl <= latch_md;
-- fetch the op code
op_ctrl <= fetch_op;
ea_ctrl <= reset_ea;
addr_ctrl <= fetch_ad;
dout_ctrl <= md_lo_dout;
iv_ctrl <= latch_iv;
-- service non maskable interrupts
if (nmi_req = '1') and (nmi_ack = '0') then
left_ctrl <= acca_left;
right_ctrl <= zero_right;
alu_ctrl <= alu_nop;
cc_ctrl <= latch_cc;
pc_ctrl <= latch_pc;
nmi_ctrl <= set_nmi;
next_state <= int_pcl_state;
-- service maskable interrupts
else
--
-- nmi request is not cleared until nmi input goes low
--
if(nmi_req = '0') and (nmi_ack='1') then
nmi_ctrl <= reset_nmi;
else
nmi_ctrl <= latch_nmi;
end if;
--
-- IRQ is level sensitive
--
if (irq = '1') and (cc(IBIT) = '0') then
left_ctrl <= acca_left;
right_ctrl <= zero_right;
alu_ctrl <= alu_nop;
cc_ctrl <= latch_cc;
pc_ctrl <= latch_pc;
next_state <= int_pcl_state;
else
-- Advance the PC to fetch next instruction byte
left_ctrl <= pc_left;
right_ctrl <= plus_one_right;
alu_ctrl <= alu_add16;
cc_ctrl <= latch_cc;
pc_ctrl <= load_pc;
next_state <= decode_state;
end if;
end if;
--
-- Here to decode instruction
-- and fetch next byte of intruction
-- whether it be necessary or not
--
when decode_state =>
-- fetch first byte of address or immediate data
md_ctrl <= fetch_first_md;
ea_ctrl <= fetch_first_ea;
addr_ctrl <= fetch_ad;
dout_ctrl <= md_lo_dout;
op_ctrl <= latch_op;
nmi_ctrl <= latch_nmi;
iv_ctrl <= latch_iv;
case op_code(7 downto 4) is
when "0000" =>
sp_ctrl <= latch_sp;
pc_ctrl <= latch_pc;
case op_code(3 downto 0) is
when "0001" => -- nop
left_ctrl <= accd_left;
right_ctrl <= zero_right;
alu_ctrl <= alu_nop;
cc_ctrl <= latch_cc;
acca_ctrl <= latch_acca;
accb_ctrl <= latch_accb;
ix_ctrl <= latch_ix;
when "0100" => -- lsrd
left_ctrl <= accd_left;
right_ctrl <= zero_right;
alu_ctrl <= alu_lsr16;
cc_ctrl <= load_cc;
acca_ctrl <= load_hi_acca;
accb_ctrl <= load_accb;
ix_ctrl <= latch_ix;
when "0101" => -- lsld
left_ctrl <= accd_left;
right_ctrl <= zero_right;
alu_ctrl <= alu_lsl16;
cc_ctrl <= load_cc;
acca_ctrl <= load_hi_acca;
accb_ctrl <= load_accb;
ix_ctrl <= latch_ix;
when "0110" => -- tap
left_ctrl <= acca_left;
right_ctrl <= zero_right;
alu_ctrl <= alu_tap;
cc_ctrl <= load_cc;
acca_ctrl <= latch_acca;
accb_ctrl <= latch_accb;
ix_ctrl <= latch_ix;
when "0111" => -- tpa
left_ctrl <= acca_left;
right_ctrl <= zero_right;
alu_ctrl <= alu_tpa;
cc_ctrl <= latch_cc;
acca_ctrl <= load_acca;
accb_ctrl <= latch_accb;
ix_ctrl <= latch_ix;
when "1000" => -- inx
left_ctrl <= ix_left;
right_ctrl <= plus_one_right;
alu_ctrl <= alu_inx;
cc_ctrl <= load_cc;
acca_ctrl <= latch_acca;
accb_ctrl <= latch_accb;
ix_ctrl <= load_ix;
when "1001" => -- dex
left_ctrl <= ix_left;
right_ctrl <= plus_one_right;
alu_ctrl <= alu_dex;
cc_ctrl <= load_cc;
acca_ctrl <= latch_acca;
accb_ctrl <= latch_accb;
ix_ctrl <= load_ix;
when "1010" => -- clv
left_ctrl <= acca_left;
right_ctrl <= zero_right;
alu_ctrl <= alu_clv;
cc_ctrl <= load_cc;
acca_ctrl <= latch_acca;
accb_ctrl <= latch_accb;
ix_ctrl <= latch_ix;
when "1011" => -- sev
left_ctrl <= acca_left;
right_ctrl <= zero_right;
alu_ctrl <= alu_sev;
cc_ctrl <= load_cc;
acca_ctrl <= latch_acca;
accb_ctrl <= latch_accb;
ix_ctrl <= latch_ix;
when "1100" => -- clc
left_ctrl <= acca_left;
right_ctrl <= zero_right;
alu_ctrl <= alu_clc;
cc_ctrl <= load_cc;
acca_ctrl <= latch_acca;
accb_ctrl <= latch_accb;
ix_ctrl <= latch_ix;
when "1101" => -- sec
left_ctrl <= acca_left;
right_ctrl <= zero_right;
alu_ctrl <= alu_sec;
cc_ctrl <= load_cc;
acca_ctrl <= latch_acca;
accb_ctrl <= latch_accb;
ix_ctrl <= latch_ix;
when "1110" => -- cli
left_ctrl <= acca_left;
right_ctrl <= zero_right;
alu_ctrl <= alu_cli;
cc_ctrl <= load_cc;
acca_ctrl <= latch_acca;
accb_ctrl <= latch_accb;
ix_ctrl <= latch_ix;
when "1111" => -- sei
left_ctrl <= acca_left;
right_ctrl <= zero_right;
alu_ctrl <= alu_sei;
cc_ctrl <= load_cc;
acca_ctrl <= latch_acca;
accb_ctrl <= latch_accb;
ix_ctrl <= latch_ix;
when others =>
left_ctrl <= acca_left;
right_ctrl <= zero_right;
alu_ctrl <= alu_nop;
cc_ctrl <= latch_cc;
acca_ctrl <= latch_acca;
accb_ctrl <= latch_accb;
ix_ctrl <= latch_ix;
end case;
next_state <= fetch_state;
-- acca / accb inherent instructions
when "0001" =>
ix_ctrl <= latch_ix;
sp_ctrl <= latch_sp;
pc_ctrl <= latch_pc;
left_ctrl <= acca_left;
right_ctrl <= accb_right;
case op_code(3 downto 0) is
when "0000" => -- sba
alu_ctrl <= alu_sub8;
cc_ctrl <= load_cc;
acca_ctrl <= load_acca;
accb_ctrl <= latch_accb;
when "0001" => -- cba
alu_ctrl <= alu_sub8;
cc_ctrl <= load_cc;
acca_ctrl <= latch_acca;
accb_ctrl <= latch_accb;
when "0110" => -- tab
alu_ctrl <= alu_st8;
cc_ctrl <= load_cc;
acca_ctrl <= latch_acca;
accb_ctrl <= load_accb;
when "0111" => -- tba
alu_ctrl <= alu_ld8;
cc_ctrl <= load_cc;
acca_ctrl <= load_acca;
accb_ctrl <= latch_accb;
when "1001" => -- daa
alu_ctrl <= alu_daa;
cc_ctrl <= load_cc;
acca_ctrl <= load_acca;
accb_ctrl <= latch_accb;
when "1011" => -- aba
alu_ctrl <= alu_add8;
cc_ctrl <= load_cc;
acca_ctrl <= load_acca;
accb_ctrl <= latch_accb;
when others =>
alu_ctrl <= alu_nop;
cc_ctrl <= latch_cc;
acca_ctrl <= latch_acca;
accb_ctrl <= latch_accb;
end case;
next_state <= fetch_state;
when "0010" => -- branch conditional
acca_ctrl <= latch_acca;
accb_ctrl <= latch_accb;
ix_ctrl <= latch_ix;
sp_ctrl <= latch_sp;
-- increment the pc
left_ctrl <= pc_left;
right_ctrl <= plus_one_right;
alu_ctrl <= alu_add16;
cc_ctrl <= latch_cc;
pc_ctrl <= load_pc;
case op_code(3 downto 0) is
when "0000" => -- bra
next_state <= branch_state;
when "0001" => -- brn
next_state <= fetch_state;
when "0010" => -- bhi
if (cc(CBIT) or cc(ZBIT)) = '0' then
next_state <= branch_state;
else
next_state <= fetch_state;
end if;
when "0011" => -- bls
if (cc(CBIT) or cc(ZBIT)) = '1' then
next_state <= branch_state;
else
next_state <= fetch_state;
end if;
when "0100" => -- bcc/bhs
if cc(CBIT) = '0' then
next_state <= branch_state;
else
next_state <= fetch_state;
end if;
when "0101" => -- bcs/blo
if cc(CBIT) = '1' then
next_state <= branch_state;
else
next_state <= fetch_state;
end if;
when "0110" => -- bne
if cc(ZBIT) = '0' then
next_state <= branch_state;
else
next_state <= fetch_state;
end if;
when "0111" => -- beq
if cc(ZBIT) = '1' then
next_state <= branch_state;
else
next_state <= fetch_state;
end if;
when "1000" => -- bvc
if cc(VBIT) = '0' then
next_state <= branch_state;
else
next_state <= fetch_state;
end if;
when "1001" => -- bvs
if cc(VBIT) = '1' then
next_state <= branch_state;
else
next_state <= fetch_state;
end if;
when "1010" => -- bpl
if cc(NBIT) = '0' then
next_state <= branch_state;
else
next_state <= fetch_state;
end if;
when "1011" => -- bmi
if cc(NBIT) = '1' then
next_state <= branch_state;
else
next_state <= fetch_state;
end if;
when "1100" => -- bge
if (cc(NBIT) xor cc(VBIT)) = '0' then
next_state <= branch_state;
else
next_state <= fetch_state;
end if;
when "1101" => -- blt
if (cc(NBIT) xor cc(VBIT)) = '1' then
next_state <= branch_state;
else
next_state <= fetch_state;
end if;
when "1110" => -- bgt
if (cc(ZBIT) or (cc(NBIT) xor cc(VBIT))) = '0' then
next_state <= branch_state;
else
next_state <= fetch_state;
end if;
when "1111" => -- ble
if (cc(ZBIT) or (cc(NBIT) xor cc(VBIT))) = '1' then
next_state <= branch_state;
else
next_state <= fetch_state;
end if;
when others =>
next_state <= fetch_state;
end case;
--
-- Single byte stack operators
-- Do not advance PC
--
when "0011" =>
acca_ctrl <= latch_acca;
accb_ctrl <= latch_accb;
pc_ctrl <= latch_pc;
case op_code(3 downto 0) is
when "0000" => -- tsx
left_ctrl <= sp_left;
right_ctrl <= plus_one_right;
alu_ctrl <= alu_add16;
cc_ctrl <= latch_cc;
ix_ctrl <= load_ix;
sp_ctrl <= latch_sp;
next_state <= fetch_state;
when "0001" => -- ins
left_ctrl <= sp_left;
right_ctrl <= plus_one_right;
alu_ctrl <= alu_add16;
cc_ctrl <= latch_cc;
ix_ctrl <= latch_ix;
sp_ctrl <= load_sp;
next_state <= fetch_state;
when "0010" => -- pula
left_ctrl <= sp_left;
right_ctrl <= plus_one_right;
alu_ctrl <= alu_add16;
cc_ctrl <= latch_cc;
ix_ctrl <= latch_ix;
sp_ctrl <= load_sp;
next_state <= pula_state;
when "0011" => -- pulb
left_ctrl <= sp_left;
right_ctrl <= plus_one_right;
alu_ctrl <= alu_add16;
cc_ctrl <= latch_cc;
ix_ctrl <= latch_ix;
sp_ctrl <= load_sp;
next_state <= pulb_state;
when "0100" => -- des
-- decrement sp
left_ctrl <= sp_left;
right_ctrl <= plus_one_right;
alu_ctrl <= alu_sub16;
cc_ctrl <= latch_cc;
ix_ctrl <= latch_ix;
sp_ctrl <= load_sp;
next_state <= fetch_state;
when "0101" => -- txs
left_ctrl <= ix_left;
right_ctrl <= plus_one_right;
alu_ctrl <= alu_sub16;
cc_ctrl <= latch_cc;
ix_ctrl <= latch_ix;
sp_ctrl <= load_sp;
next_state <= fetch_state;
when "0110" => -- psha
left_ctrl <= sp_left;
right_ctrl <= zero_right;
alu_ctrl <= alu_nop;
cc_ctrl <= latch_cc;
ix_ctrl <= latch_ix;
sp_ctrl <= latch_sp;
next_state <= psha_state;
when "0111" => -- pshb
left_ctrl <= sp_left;
right_ctrl <= zero_right;
alu_ctrl <= alu_nop;
cc_ctrl <= latch_cc;
ix_ctrl <= latch_ix;
sp_ctrl <= latch_sp;
next_state <= pshb_state;
when "1000" => -- pulx
left_ctrl <= sp_left;
right_ctrl <= plus_one_right;
alu_ctrl <= alu_add16;
cc_ctrl <= latch_cc;
ix_ctrl <= latch_ix;
sp_ctrl <= load_sp;
next_state <= pulx_hi_state;
when "1001" => -- rts
left_ctrl <= sp_left;
right_ctrl <= plus_one_right;
alu_ctrl <= alu_add16;
cc_ctrl <= latch_cc;
ix_ctrl <= latch_ix;
sp_ctrl <= load_sp;
next_state <= rts_hi_state;
when "1010" => -- abx
left_ctrl <= ix_left;
right_ctrl <= accb_right;
alu_ctrl <= alu_add16;
cc_ctrl <= latch_cc;
ix_ctrl <= load_ix;
sp_ctrl <= latch_sp;
next_state <= fetch_state;
when "1011" => -- rti
left_ctrl <= sp_left;
right_ctrl <= plus_one_right;
alu_ctrl <= alu_add16;
cc_ctrl <= latch_cc;
ix_ctrl <= latch_ix;
sp_ctrl <= load_sp;
next_state <= rti_cc_state;
when "1100" => -- pshx
left_ctrl <= sp_left;
right_ctrl <= zero_right;
alu_ctrl <= alu_nop;
cc_ctrl <= latch_cc;
ix_ctrl <= latch_ix;
sp_ctrl <= latch_sp;
next_state <= pshx_lo_state;
when "1101" => -- mul
left_ctrl <= acca_left;
right_ctrl <= accb_right;
alu_ctrl <= alu_add16;
cc_ctrl <= latch_cc;
ix_ctrl <= latch_ix;
sp_ctrl <= latch_sp;
next_state <= mul_state;
when "1110" => -- wai
left_ctrl <= sp_left;
right_ctrl <= zero_right;
alu_ctrl <= alu_nop;
cc_ctrl <= latch_cc;
ix_ctrl <= latch_ix;
sp_ctrl <= latch_sp;
next_state <= int_pcl_state;
when "1111" => -- swi
left_ctrl <= sp_left;
right_ctrl <= zero_right;
alu_ctrl <= alu_nop;
cc_ctrl <= latch_cc;
ix_ctrl <= latch_ix;
sp_ctrl <= latch_sp;
next_state <= int_pcl_state;
when others =>
left_ctrl <= sp_left;
right_ctrl <= zero_right;
alu_ctrl <= alu_nop;
cc_ctrl <= latch_cc;
ix_ctrl <= latch_ix;
sp_ctrl <= latch_sp;
next_state <= fetch_state;
end case;
--
-- Accumulator A Single operand
-- source = Acc A dest = Acc A
-- Do not advance PC
--
when "0100" => -- acca single op
accb_ctrl <= latch_accb;
pc_ctrl <= latch_pc;
ix_ctrl <= latch_ix;
sp_ctrl <= latch_sp;
left_ctrl <= acca_left;
case op_code(3 downto 0) is
when "0000" => -- neg
right_ctrl <= zero_right;
alu_ctrl <= alu_neg;
acca_ctrl <= load_acca;
cc_ctrl <= load_cc;
when "0011" => -- com
right_ctrl <= zero_right;
alu_ctrl <= alu_com;
acca_ctrl <= load_acca;
cc_ctrl <= load_cc;
when "0100" => -- lsr
right_ctrl <= zero_right;
alu_ctrl <= alu_lsr8;
acca_ctrl <= load_acca;
cc_ctrl <= load_cc;
when "0110" => -- ror
right_ctrl <= zero_right;
alu_ctrl <= alu_ror8;
acca_ctrl <= load_acca;
cc_ctrl <= load_cc;
when "0111" => -- asr
right_ctrl <= zero_right;
alu_ctrl <= alu_asr8;
acca_ctrl <= load_acca;
cc_ctrl <= load_cc;
when "1000" => -- asl
right_ctrl <= zero_right;
alu_ctrl <= alu_asl8;
acca_ctrl <= load_acca;
cc_ctrl <= load_cc;
when "1001" => -- rol
right_ctrl <= zero_right;
alu_ctrl <= alu_rol8;
acca_ctrl <= load_acca;
cc_ctrl <= load_cc;
when "1010" => -- dec
right_ctrl <= plus_one_right;
alu_ctrl <= alu_dec;
acca_ctrl <= load_acca;
cc_ctrl <= load_cc;
when "1011" => -- undefined
right_ctrl <= zero_right;
alu_ctrl <= alu_nop;
acca_ctrl <= latch_acca;
cc_ctrl <= latch_cc;
when "1100" => -- inc
right_ctrl <= plus_one_right;
alu_ctrl <= alu_inc;
acca_ctrl <= load_acca;
cc_ctrl <= load_cc;
when "1101" => -- tst
right_ctrl <= zero_right;
alu_ctrl <= alu_st8;
acca_ctrl <= latch_acca;
cc_ctrl <= load_cc;
when "1110" => -- jmp
right_ctrl <= zero_right;
alu_ctrl <= alu_nop;
acca_ctrl <= latch_acca;
cc_ctrl <= latch_cc;
when "1111" => -- clr
right_ctrl <= zero_right;
alu_ctrl <= alu_ld8;
acca_ctrl <= load_acca;
cc_ctrl <= load_cc;
when others =>
right_ctrl <= zero_right;
alu_ctrl <= alu_nop;
acca_ctrl <= latch_acca;
cc_ctrl <= latch_cc;
end case;
next_state <= fetch_state;
--
-- single operand acc b
-- Do not advance PC
--
when "0101" =>
acca_ctrl <= latch_acca;
pc_ctrl <= latch_pc;
ix_ctrl <= latch_ix;
sp_ctrl <= latch_sp;
left_ctrl <= accb_left;
case op_code(3 downto 0) is
when "0000" => -- neg
right_ctrl <= zero_right;
alu_ctrl <= alu_neg;
accb_ctrl <= load_accb;
cc_ctrl <= load_cc;
when "0011" => -- com
right_ctrl <= zero_right;
alu_ctrl <= alu_com;
accb_ctrl <= load_accb;
cc_ctrl <= load_cc;
when "0100" => -- lsr
right_ctrl <= zero_right;
alu_ctrl <= alu_lsr8;
accb_ctrl <= load_accb;
cc_ctrl <= load_cc;
when "0110" => -- ror
right_ctrl <= zero_right;
alu_ctrl <= alu_ror8;
accb_ctrl <= load_accb;
cc_ctrl <= load_cc;
when "0111" => -- asr
right_ctrl <= zero_right;
alu_ctrl <= alu_asr8;
accb_ctrl <= load_accb;
cc_ctrl <= load_cc;
when "1000" => -- asl
right_ctrl <= zero_right;
alu_ctrl <= alu_asl8;
accb_ctrl <= load_accb;
cc_ctrl <= load_cc;
when "1001" => -- rol
right_ctrl <= zero_right;
alu_ctrl <= alu_rol8;
accb_ctrl <= load_accb;
cc_ctrl <= load_cc;
when "1010" => -- dec
right_ctrl <= plus_one_right;
alu_ctrl <= alu_dec;
accb_ctrl <= load_accb;
cc_ctrl <= load_cc;
when "1011" => -- undefined
right_ctrl <= zero_right;
alu_ctrl <= alu_nop;
accb_ctrl <= latch_accb;
cc_ctrl <= latch_cc;
when "1100" => -- inc
right_ctrl <= plus_one_right;
alu_ctrl <= alu_inc;
accb_ctrl <= load_accb;
cc_ctrl <= load_cc;
when "1101" => -- tst
right_ctrl <= zero_right;
alu_ctrl <= alu_st8;
accb_ctrl <= latch_accb;
cc_ctrl <= load_cc;
when "1110" => -- jmp
right_ctrl <= zero_right;
alu_ctrl <= alu_nop;
accb_ctrl <= latch_accb;
cc_ctrl <= latch_cc;
when "1111" => -- clr
right_ctrl <= zero_right;
alu_ctrl <= alu_ld8;
accb_ctrl <= load_accb;
cc_ctrl <= load_cc;
when others =>
right_ctrl <= zero_right;
alu_ctrl <= alu_nop;
accb_ctrl <= latch_accb;
cc_ctrl <= latch_cc;
end case;
next_state <= fetch_state;
--
-- Single operand indexed
-- Two byte instruction so advance PC
-- EA should hold index offset
--
when "0110" => -- indexed single op
acca_ctrl <= latch_acca;
accb_ctrl <= latch_accb;
ix_ctrl <= latch_ix;
sp_ctrl <= latch_sp;
-- increment the pc
left_ctrl <= pc_left;
right_ctrl <= plus_one_right;
alu_ctrl <= alu_add16;
cc_ctrl <= latch_cc;
pc_ctrl <= load_pc;
next_state <= indexed_state;
--
-- Single operand extended addressing
-- three byte instruction so advance the PC
-- Low order EA holds high order address
--
when "0111" => -- extended single op
acca_ctrl <= latch_acca;
accb_ctrl <= latch_accb;
ix_ctrl <= latch_ix;
sp_ctrl <= latch_sp;
-- increment the pc
left_ctrl <= pc_left;
right_ctrl <= plus_one_right;
alu_ctrl <= alu_add16;
cc_ctrl <= latch_cc;
pc_ctrl <= load_pc;
next_state <= extended_state;
 
when "1000" => -- acca immediate
acca_ctrl <= latch_acca;
accb_ctrl <= latch_accb;
ix_ctrl <= latch_ix;
sp_ctrl <= latch_sp;
-- increment the pc
left_ctrl <= pc_left;
right_ctrl <= plus_one_right;
alu_ctrl <= alu_add16;
cc_ctrl <= latch_cc;
pc_ctrl <= load_pc;
case op_code(3 downto 0) is
when "0011" | -- subdd #
"1100" | -- cpx #
"1110" => -- lds #
next_state <= immediate16_state;
when "1101" => -- bsr
next_state <= bsr_state;
when others =>
next_state <= execute_state;
end case;
 
when "1001" => -- acca direct
acca_ctrl <= latch_acca;
accb_ctrl <= latch_accb;
ix_ctrl <= latch_ix;
sp_ctrl <= latch_sp;
-- increment the pc
left_ctrl <= pc_left;
right_ctrl <= plus_one_right;
alu_ctrl <= alu_add16;
cc_ctrl <= latch_cc;
pc_ctrl <= load_pc;
case op_code(3 downto 0) is
when "0111" | -- staa direct
"1111" => -- sts direct
next_state <= execute_state;
when "1101" => -- jsr direct
next_state <= jsr_state;
when others =>
next_state <= direct_state;
end case;
 
when "1010" => -- acca indexed
acca_ctrl <= latch_acca;
accb_ctrl <= latch_accb;
ix_ctrl <= latch_ix;
sp_ctrl <= latch_sp;
-- increment the pc
left_ctrl <= pc_left;
right_ctrl <= plus_one_right;
alu_ctrl <= alu_add16;
cc_ctrl <= latch_cc;
pc_ctrl <= load_pc;
next_state <= indexed_state;
 
when "1011" => -- acca extended
acca_ctrl <= latch_acca;
accb_ctrl <= latch_accb;
ix_ctrl <= latch_ix;
sp_ctrl <= latch_sp;
-- increment the pc
left_ctrl <= pc_left;
right_ctrl <= plus_one_right;
alu_ctrl <= alu_add16;
cc_ctrl <= latch_cc;
pc_ctrl <= load_pc;
next_state <= extended_state;
 
when "1100" => -- accb immediate
acca_ctrl <= latch_acca;
accb_ctrl <= latch_accb;
ix_ctrl <= latch_ix;
sp_ctrl <= latch_sp;
-- increment the pc
left_ctrl <= pc_left;
right_ctrl <= plus_one_right;
alu_ctrl <= alu_add16;
cc_ctrl <= latch_cc;
pc_ctrl <= load_pc;
case op_code(3 downto 0) is
when "0011" | -- addd #
"1100" | -- ldd #
"1110" => -- ldx #
next_state <= immediate16_state;
when others =>
next_state <= execute_state;
end case;
 
when "1101" => -- accb direct
acca_ctrl <= latch_acca;
accb_ctrl <= latch_accb;
ix_ctrl <= latch_ix;
sp_ctrl <= latch_sp;
-- increment the pc
left_ctrl <= pc_left;
right_ctrl <= plus_one_right;
alu_ctrl <= alu_add16;
cc_ctrl <= latch_cc;
pc_ctrl <= load_pc;
case op_code(3 downto 0) is
when "0111" | -- stab direct
"1101" | -- std direct
"1111" => -- stx direct
next_state <= execute_state;
when others =>
next_state <= direct_state;
end case;
 
when "1110" => -- accb indexed
acca_ctrl <= latch_acca;
accb_ctrl <= latch_accb;
ix_ctrl <= latch_ix;
sp_ctrl <= latch_sp;
-- increment the pc
left_ctrl <= pc_left;
right_ctrl <= plus_one_right;
alu_ctrl <= alu_add16;
cc_ctrl <= latch_cc;
pc_ctrl <= load_pc;
next_state <= indexed_state;
 
when "1111" => -- accb extended
acca_ctrl <= latch_acca;
accb_ctrl <= latch_accb;
ix_ctrl <= latch_ix;
sp_ctrl <= latch_sp;
-- increment the pc
left_ctrl <= pc_left;
right_ctrl <= plus_one_right;
alu_ctrl <= alu_add16;
cc_ctrl <= latch_cc;
pc_ctrl <= load_pc;
next_state <= extended_state;
 
when others =>
acca_ctrl <= latch_acca;
accb_ctrl <= latch_accb;
ix_ctrl <= latch_ix;
sp_ctrl <= latch_sp;
-- idle the pc
left_ctrl <= pc_left;
right_ctrl <= zero_right;
alu_ctrl <= alu_nop;
cc_ctrl <= latch_cc;
pc_ctrl <= latch_pc;
next_state <= fetch_state;
end case;
 
when immediate16_state =>
acca_ctrl <= latch_acca;
accb_ctrl <= latch_accb;
ix_ctrl <= latch_ix;
sp_ctrl <= latch_sp;
op_ctrl <= latch_op;
iv_ctrl <= latch_iv;
nmi_ctrl <= latch_nmi;
ea_ctrl <= latch_ea;
-- increment pc
left_ctrl <= pc_left;
right_ctrl <= plus_one_right;
alu_ctrl <= alu_add16;
cc_ctrl <= latch_cc;
pc_ctrl <= load_pc;
-- fetch next immediate byte
md_ctrl <= fetch_next_md;
addr_ctrl <= fetch_ad;
dout_ctrl <= md_lo_dout;
next_state <= execute_state;
--
-- ea holds 8 bit index offet
-- calculate the effective memory address
-- using the alu
--
when indexed_state =>
acca_ctrl <= latch_acca;
accb_ctrl <= latch_accb;
ix_ctrl <= latch_ix;
sp_ctrl <= latch_sp;
pc_ctrl <= latch_pc;
md_ctrl <= latch_md;
iv_ctrl <= latch_iv;
op_ctrl <= latch_op;
nmi_ctrl <= latch_nmi;
-- calculate effective address from index reg
-- index offest is not sign extended
left_ctrl <= ix_left;
right_ctrl <= ea_right;
alu_ctrl <= alu_add16;
cc_ctrl <= latch_cc;
ea_ctrl <= load_ea;
-- idle the bus
addr_ctrl <= idle_ad;
dout_ctrl <= md_lo_dout;
-- work out next state
case op_code(7 downto 4) is
when "0110" => -- single op indexed
case op_code(3 downto 0) is
when "1011" => -- undefined
next_state <= fetch_state;
when "1110" => -- jmp
next_state <= jmp_state;
when others =>
next_state <= direct_state;
end case;
when "1010" => -- acca indexed
case op_code(3 downto 0) is
when "0111" | -- staa
"1111" => -- sts
next_state <= execute_state;
when "1101" => -- jsr
next_state <= jsr_state;
when others =>
next_state <= direct_state;
end case;
when "1110" => -- accb indexed
case op_code(3 downto 0) is
when "0111" | -- stab
"1101" | -- std
"1111" => -- stx
next_state <= execute_state;
when others =>
next_state <= direct_state;
end case;
when others =>
next_state <= fetch_state;
end case;
--
-- ea holds the low byte of the absolute address
-- Move ea low byte into ea high byte
-- load new ea low byte to for absolute 16 bit address
-- advance the program counter
--
when extended_state => -- fetch ea low byte
acca_ctrl <= latch_acca;
accb_ctrl <= latch_accb;
ix_ctrl <= latch_ix;
sp_ctrl <= latch_sp;
md_ctrl <= latch_md;
iv_ctrl <= latch_iv;
op_ctrl <= latch_op;
nmi_ctrl <= latch_nmi;
-- increment pc
left_ctrl <= pc_left;
right_ctrl <= plus_one_right;
alu_ctrl <= alu_add16;
cc_ctrl <= latch_cc;
pc_ctrl <= load_pc;
-- fetch next effective address bytes
ea_ctrl <= fetch_next_ea;
addr_ctrl <= fetch_ad;
dout_ctrl <= md_lo_dout;
-- work out the next state
case op_code(7 downto 4) is
when "0111" => -- single op extended
case op_code(3 downto 0) is
when "1011" => -- undefined
next_state <= fetch_state;
when "1110" => -- jmp
next_state <= jmp_state;
when others =>
next_state <= direct_state;
end case;
when "1011" => -- acca extended
case op_code(3 downto 0) is
when "0111" | -- staa extended
"1111" => -- sts
next_state <= execute_state;
when "1101" => -- jsr
next_state <= jsr_state;
when others =>
next_state <= direct_state;
end case;
when "1111" => -- accb extended
case op_code(3 downto 0) is
when "0111" | -- stab extended
"1101" | -- std
"1111" => -- stx
next_state <= execute_state;
when others =>
next_state <= direct_state;
end case;
when others =>
next_state <= fetch_state;
end case;
--
-- here if ea holds low byte (direct page)
-- can enter here from extended addressing
-- read memory location
-- note that reads may be 8 or 16 bits
--
when direct_state => -- read data
acca_ctrl <= latch_acca;
accb_ctrl <= latch_accb;
ix_ctrl <= latch_ix;
sp_ctrl <= latch_sp;
pc_ctrl <= latch_pc;
iv_ctrl <= latch_iv;
op_ctrl <= latch_op;
nmi_ctrl <= latch_nmi;
-- read first data byte from ea
md_ctrl <= fetch_first_md;
addr_ctrl <= read_ad;
dout_ctrl <= md_lo_dout;
case op_code(7 downto 4) is
when "0110" | "0111" => -- single operand
left_ctrl <= ea_left;
right_ctrl <= zero_right;
alu_ctrl <= alu_nop;
cc_ctrl <= latch_cc;
ea_ctrl <= latch_ea;
next_state <= execute_state;
when "1001" | "1010" | "1011" => -- acca
case op_code(3 downto 0) is
when "0011" | -- subd
"1110" | -- lds
"1100" => -- cpx
-- increment the effective address in case of 16 bit load
left_ctrl <= ea_left;
right_ctrl <= plus_one_right;
alu_ctrl <= alu_add16;
cc_ctrl <= latch_cc;
ea_ctrl <= load_ea;
next_state <= direct16_state;
when others =>
left_ctrl <= ea_left;
right_ctrl <= zero_right;
alu_ctrl <= alu_nop;
cc_ctrl <= latch_cc;
ea_ctrl <= latch_ea;
next_state <= execute_state;
end case;
when "1101" | "1110" | "1111" => -- accb
case op_code(3 downto 0) is
when "0011" | -- addd
"1100" | -- ldd
"1110" => -- ldx
-- increment the effective address in case of 16 bit load
left_ctrl <= ea_left;
right_ctrl <= plus_one_right;
alu_ctrl <= alu_add16;
cc_ctrl <= latch_cc;
ea_ctrl <= load_ea;
next_state <= direct16_state;
when others =>
left_ctrl <= ea_left;
right_ctrl <= zero_right;
alu_ctrl <= alu_nop;
cc_ctrl <= latch_cc;
ea_ctrl <= latch_ea;
next_state <= execute_state;
end case;
when others =>
left_ctrl <= ea_left;
right_ctrl <= zero_right;
alu_ctrl <= alu_nop;
cc_ctrl <= latch_cc;
ea_ctrl <= latch_ea;
next_state <= fetch_state;
end case;
 
when direct16_state => -- read second data byte from ea
-- default
acca_ctrl <= latch_acca;
accb_ctrl <= latch_accb;
ix_ctrl <= latch_ix;
sp_ctrl <= latch_sp;
pc_ctrl <= latch_pc;
iv_ctrl <= latch_iv;
op_ctrl <= latch_op;
nmi_ctrl <= latch_nmi;
-- idle the effective address
left_ctrl <= ea_left;
right_ctrl <= plus_one_right;
alu_ctrl <= alu_nop;
cc_ctrl <= latch_cc;
ea_ctrl <= latch_ea;
-- read the low byte of the 16 bit data
md_ctrl <= fetch_next_md;
addr_ctrl <= read_ad;
dout_ctrl <= md_lo_dout;
next_state <= execute_state;
 
when jmp_state =>
acca_ctrl <= latch_acca;
accb_ctrl <= latch_accb;
ix_ctrl <= latch_ix;
sp_ctrl <= latch_sp;
md_ctrl <= latch_md;
iv_ctrl <= latch_iv;
op_ctrl <= latch_op;
nmi_ctrl <= latch_nmi;
ea_ctrl <= latch_ea;
-- load PC with effective address
left_ctrl <= pc_left;
right_ctrl <= ea_right;
alu_ctrl <= alu_ld16;
cc_ctrl <= latch_cc;
pc_ctrl <= load_pc;
-- idle the bus
addr_ctrl <= idle_ad;
dout_ctrl <= md_lo_dout;
next_state <= fetch_state;
 
when jsr_state => -- JSR
acca_ctrl <= latch_acca;
accb_ctrl <= latch_accb;
ix_ctrl <= latch_ix;
sp_ctrl <= latch_sp;
pc_ctrl <= latch_pc;
md_ctrl <= latch_md;
iv_ctrl <= latch_iv;
op_ctrl <= latch_op;
nmi_ctrl <= latch_nmi;
ea_ctrl <= latch_ea;
-- decrement sp
left_ctrl <= sp_left;
right_ctrl <= plus_one_right;
alu_ctrl <= alu_sub16;
cc_ctrl <= latch_cc;
sp_ctrl <= load_sp;
-- write pc low
addr_ctrl <= push_ad;
dout_ctrl <= pc_lo_dout;
next_state <= jsr1_state;
 
when jsr1_state => -- JSR
acca_ctrl <= latch_acca;
accb_ctrl <= latch_accb;
ix_ctrl <= latch_ix;
pc_ctrl <= latch_pc;
md_ctrl <= latch_md;
iv_ctrl <= latch_iv;
op_ctrl <= latch_op;
nmi_ctrl <= latch_nmi;
ea_ctrl <= latch_ea;
-- decrement sp
left_ctrl <= sp_left;
right_ctrl <= plus_one_right;
alu_ctrl <= alu_sub16;
cc_ctrl <= latch_cc;
sp_ctrl <= load_sp;
-- write pc hi
addr_ctrl <= push_ad;
dout_ctrl <= pc_hi_dout;
next_state <= jmp_state;
 
when branch_state => -- Bcc
-- default registers
acca_ctrl <= latch_acca;
accb_ctrl <= latch_accb;
ix_ctrl <= latch_ix;
sp_ctrl <= latch_sp;
md_ctrl <= latch_md;
iv_ctrl <= latch_iv;
op_ctrl <= latch_op;
nmi_ctrl <= latch_nmi;
ea_ctrl <= latch_ea;
-- calculate signed branch
left_ctrl <= pc_left;
right_ctrl <= sexea_right; -- right must be sign extended effective address
alu_ctrl <= alu_add16;
cc_ctrl <= latch_cc;
pc_ctrl <= load_pc;
-- idle the bus
addr_ctrl <= idle_ad;
dout_ctrl <= md_lo_dout;
next_state <= fetch_state;
 
when bsr_state => -- BSR
-- default
acca_ctrl <= latch_acca;
accb_ctrl <= latch_accb;
ix_ctrl <= latch_ix;
pc_ctrl <= latch_pc;
md_ctrl <= latch_md;
iv_ctrl <= latch_iv;
op_ctrl <= latch_op;
nmi_ctrl <= latch_nmi;
ea_ctrl <= latch_ea;
-- decrement sp
left_ctrl <= sp_left;
right_ctrl <= plus_one_right;
alu_ctrl <= alu_sub16;
cc_ctrl <= latch_cc;
sp_ctrl <= load_sp;
-- write pc low
addr_ctrl <= push_ad;
dout_ctrl <= pc_lo_dout;
next_state <= bsr1_state;
 
when bsr1_state => -- BSR
-- default registers
acca_ctrl <= latch_acca;
accb_ctrl <= latch_accb;
ix_ctrl <= latch_ix;
pc_ctrl <= latch_pc;
md_ctrl <= latch_md;
iv_ctrl <= latch_iv;
op_ctrl <= latch_op;
nmi_ctrl <= latch_nmi;
ea_ctrl <= latch_ea;
-- decrement sp
left_ctrl <= sp_left;
right_ctrl <= plus_one_right;
alu_ctrl <= alu_sub16;
cc_ctrl <= latch_cc;
sp_ctrl <= load_sp;
-- write pc hi
addr_ctrl <= push_ad;
dout_ctrl <= pc_hi_dout;
next_state <= branch_state;
 
when rts_hi_state => -- RTS
-- default
acca_ctrl <= latch_acca;
accb_ctrl <= latch_accb;
ix_ctrl <= latch_ix;
pc_ctrl <= latch_pc;
md_ctrl <= latch_md;
iv_ctrl <= latch_iv;
op_ctrl <= latch_op;
nmi_ctrl <= latch_nmi;
ea_ctrl <= latch_ea;
-- increment the sp
left_ctrl <= sp_left;
right_ctrl <= plus_one_right;
alu_ctrl <= alu_add16;
cc_ctrl <= latch_cc;
sp_ctrl <= load_sp;
-- read pc hi
pc_ctrl <= pull_hi_pc;
addr_ctrl <= pull_ad;
dout_ctrl <= pc_hi_dout;
next_state <= rts_lo_state;
 
when rts_lo_state => -- RTS1
-- default
acca_ctrl <= latch_acca;
accb_ctrl <= latch_accb;
ix_ctrl <= latch_ix;
sp_ctrl <= latch_sp;
md_ctrl <= latch_md;
iv_ctrl <= latch_iv;
op_ctrl <= latch_op;
nmi_ctrl <= latch_nmi;
ea_ctrl <= latch_ea;
-- idle the ALU
left_ctrl <= acca_left;
right_ctrl <= zero_right;
alu_ctrl <= alu_nop;
cc_ctrl <= latch_cc;
-- read pc low
pc_ctrl <= pull_lo_pc;
addr_ctrl <= pull_ad;
dout_ctrl <= pc_lo_dout;
next_state <= fetch_state;
 
when mul_state =>
-- default
acca_ctrl <= latch_acca;
accb_ctrl <= latch_accb;
ix_ctrl <= latch_ix;
sp_ctrl <= latch_sp;
pc_ctrl <= latch_pc;
iv_ctrl <= latch_iv;
op_ctrl <= latch_op;
nmi_ctrl <= latch_nmi;
ea_ctrl <= latch_ea;
-- move acca to md
left_ctrl <= acca_left;
right_ctrl <= zero_right;
alu_ctrl <= alu_st16;
cc_ctrl <= latch_cc;
md_ctrl <= load_md;
-- idle bus
addr_ctrl <= idle_ad;
dout_ctrl <= md_lo_dout;
next_state <= mulea_state;
 
when mulea_state =>
-- default
acca_ctrl <= latch_acca;
accb_ctrl <= latch_accb;
ix_ctrl <= latch_ix;
sp_ctrl <= latch_sp;
pc_ctrl <= latch_pc;
iv_ctrl <= latch_iv;
op_ctrl <= latch_op;
nmi_ctrl <= latch_nmi;
md_ctrl <= latch_md;
-- move accb to ea
left_ctrl <= accb_left;
right_ctrl <= zero_right;
alu_ctrl <= alu_st16;
cc_ctrl <= latch_cc;
ea_ctrl <= load_ea;
-- idle bus
addr_ctrl <= idle_ad;
dout_ctrl <= md_lo_dout;
next_state <= muld_state;
 
when muld_state =>
-- default
ix_ctrl <= latch_ix;
sp_ctrl <= latch_sp;
pc_ctrl <= latch_pc;
iv_ctrl <= latch_iv;
op_ctrl <= latch_op;
nmi_ctrl <= latch_nmi;
ea_ctrl <= latch_ea;
md_ctrl <= latch_md;
-- clear accd
left_ctrl <= acca_left;
right_ctrl <= zero_right;
alu_ctrl <= alu_ld8;
cc_ctrl <= latch_cc;
acca_ctrl <= load_hi_acca;
accb_ctrl <= load_accb;
-- idle bus
addr_ctrl <= idle_ad;
dout_ctrl <= md_lo_dout;
next_state <= mul0_state;
 
when mul0_state =>
-- default
ix_ctrl <= latch_ix;
sp_ctrl <= latch_sp;
pc_ctrl <= latch_pc;
iv_ctrl <= latch_iv;
op_ctrl <= latch_op;
nmi_ctrl <= latch_nmi;
ea_ctrl <= latch_ea;
-- if bit 0 of ea set, add accd to md
left_ctrl <= accd_left;
right_ctrl <= md_right;
alu_ctrl <= alu_add16;
if ea(0) = '1' then
cc_ctrl <= load_cc;
acca_ctrl <= load_hi_acca;
accb_ctrl <= load_accb;
else
cc_ctrl <= latch_cc;
acca_ctrl <= latch_acca;
accb_ctrl <= latch_accb;
end if;
md_ctrl <= shiftl_md;
-- idle bus
addr_ctrl <= idle_ad;
dout_ctrl <= md_lo_dout;
next_state <= mul1_state;
 
when mul1_state =>
-- default
ix_ctrl <= latch_ix;
sp_ctrl <= latch_sp;
pc_ctrl <= latch_pc;
iv_ctrl <= latch_iv;
op_ctrl <= latch_op;
nmi_ctrl <= latch_nmi;
ea_ctrl <= latch_ea;
-- if bit 1 of ea set, add accd to md
left_ctrl <= accd_left;
right_ctrl <= md_right;
alu_ctrl <= alu_add16;
if ea(1) = '1' then
cc_ctrl <= load_cc;
acca_ctrl <= load_hi_acca;
accb_ctrl <= load_accb;
else
cc_ctrl <= latch_cc;
acca_ctrl <= latch_acca;
accb_ctrl <= latch_accb;
end if;
md_ctrl <= shiftl_md;
-- idle bus
addr_ctrl <= idle_ad;
dout_ctrl <= md_lo_dout;
next_state <= mul2_state;
 
when mul2_state =>
-- default
ix_ctrl <= latch_ix;
sp_ctrl <= latch_sp;
pc_ctrl <= latch_pc;
iv_ctrl <= latch_iv;
op_ctrl <= latch_op;
nmi_ctrl <= latch_nmi;
ea_ctrl <= latch_ea;
-- if bit 2 of ea set, add accd to md
left_ctrl <= accd_left;
right_ctrl <= md_right;
alu_ctrl <= alu_add16;
if ea(2) = '1' then
cc_ctrl <= load_cc;
acca_ctrl <= load_hi_acca;
accb_ctrl <= load_accb;
else
cc_ctrl <= latch_cc;
acca_ctrl <= latch_acca;
accb_ctrl <= latch_accb;
end if;
md_ctrl <= shiftl_md;
-- idle bus
addr_ctrl <= idle_ad;
dout_ctrl <= md_lo_dout;
next_state <= mul3_state;
 
when mul3_state =>
-- default
ix_ctrl <= latch_ix;
sp_ctrl <= latch_sp;
pc_ctrl <= latch_pc;
iv_ctrl <= latch_iv;
op_ctrl <= latch_op;
nmi_ctrl <= latch_nmi;
ea_ctrl <= latch_ea;
-- if bit 3 of ea set, add accd to md
left_ctrl <= accd_left;
right_ctrl <= md_right;
alu_ctrl <= alu_add16;
if ea(3) = '1' then
cc_ctrl <= load_cc;
acca_ctrl <= load_hi_acca;
accb_ctrl <= load_accb;
else
cc_ctrl <= latch_cc;
acca_ctrl <= latch_acca;
accb_ctrl <= latch_accb;
end if;
md_ctrl <= shiftl_md;
-- idle bus
addr_ctrl <= idle_ad;
dout_ctrl <= md_lo_dout;
next_state <= mul4_state;
 
when mul4_state =>
-- default
ix_ctrl <= latch_ix;
sp_ctrl <= latch_sp;
pc_ctrl <= latch_pc;
iv_ctrl <= latch_iv;
op_ctrl <= latch_op;
nmi_ctrl <= latch_nmi;
ea_ctrl <= latch_ea;
-- if bit 4 of ea set, add accd to md
left_ctrl <= accd_left;
right_ctrl <= md_right;
alu_ctrl <= alu_add16;
if ea(4) = '1' then
cc_ctrl <= load_cc;
acca_ctrl <= load_hi_acca;
accb_ctrl <= load_accb;
else
cc_ctrl <= latch_cc;
acca_ctrl <= latch_acca;
accb_ctrl <= latch_accb;
end if;
md_ctrl <= shiftl_md;
-- idle bus
addr_ctrl <= idle_ad;
dout_ctrl <= md_lo_dout;
next_state <= mul5_state;
 
when mul5_state =>
-- default
ix_ctrl <= latch_ix;
sp_ctrl <= latch_sp;
pc_ctrl <= latch_pc;
iv_ctrl <= latch_iv;
op_ctrl <= latch_op;
nmi_ctrl <= latch_nmi;
ea_ctrl <= latch_ea;
-- if bit 5 of ea set, add accd to md
left_ctrl <= accd_left;
right_ctrl <= md_right;
alu_ctrl <= alu_add16;
if ea(5) = '1' then
cc_ctrl <= load_cc;
acca_ctrl <= load_hi_acca;
accb_ctrl <= load_accb;
else
cc_ctrl <= latch_cc;
acca_ctrl <= latch_acca;
accb_ctrl <= latch_accb;
end if;
md_ctrl <= shiftl_md;
-- idle bus
addr_ctrl <= idle_ad;
dout_ctrl <= md_lo_dout;
next_state <= mul6_state;
 
when mul6_state =>
-- default
ix_ctrl <= latch_ix;
sp_ctrl <= latch_sp;
pc_ctrl <= latch_pc;
iv_ctrl <= latch_iv;
op_ctrl <= latch_op;
nmi_ctrl <= latch_nmi;
ea_ctrl <= latch_ea;
-- if bit 6 of ea set, add accd to md
left_ctrl <= accd_left;
right_ctrl <= md_right;
alu_ctrl <= alu_add16;
if ea(6) = '1' then
cc_ctrl <= load_cc;
acca_ctrl <= load_hi_acca;
accb_ctrl <= load_accb;
else
cc_ctrl <= latch_cc;
acca_ctrl <= latch_acca;
accb_ctrl <= latch_accb;
end if;
md_ctrl <= shiftl_md;
-- idle bus
addr_ctrl <= idle_ad;
dout_ctrl <= md_lo_dout;
next_state <= mul7_state;
 
when mul7_state =>
-- default
ix_ctrl <= latch_ix;
sp_ctrl <= latch_sp;
pc_ctrl <= latch_pc;
iv_ctrl <= latch_iv;
op_ctrl <= latch_op;
nmi_ctrl <= latch_nmi;
ea_ctrl <= latch_ea;
-- if bit 7 of ea set, add accd to md
left_ctrl <= accd_left;
right_ctrl <= md_right;
alu_ctrl <= alu_add16;
if ea(7) = '1' then
cc_ctrl <= load_cc;
acca_ctrl <= load_hi_acca;
accb_ctrl <= load_accb;
else
cc_ctrl <= latch_cc;
acca_ctrl <= latch_acca;
accb_ctrl <= latch_accb;
end if;
md_ctrl <= shiftl_md;
-- idle bus
addr_ctrl <= idle_ad;
dout_ctrl <= md_lo_dout;
next_state <= fetch_state;
 
when execute_state => -- execute
-- default
op_ctrl <= latch_op;
nmi_ctrl <= latch_nmi;
case op_code(7 downto 4) is
when "0000" |
"0001" |
"0010" | -- branch conditional
"0011" |
"0100" | -- acca single op
"0101" => -- accb single op
acca_ctrl <= latch_acca;
accb_ctrl <= latch_accb;
ix_ctrl <= latch_ix;
sp_ctrl <= latch_sp;
pc_ctrl <= latch_pc;
md_ctrl <= latch_md;
iv_ctrl <= latch_iv;
ea_ctrl <= latch_ea;
-- idle ALU
left_ctrl <= acca_left;
right_ctrl <= zero_right;
alu_ctrl <= alu_nop;
cc_ctrl <= latch_cc;
-- idle bus
addr_ctrl <= idle_ad;
dout_ctrl <= md_lo_dout;
next_state <= fetch_state;
 
when "0110" | -- indexed single op
"0111" => -- extended single op
acca_ctrl <= latch_acca;
accb_ctrl <= latch_accb;
ix_ctrl <= latch_ix;
sp_ctrl <= latch_sp;
pc_ctrl <= latch_pc;
iv_ctrl <= latch_iv;
ea_ctrl <= latch_ea;
-- idle the bus
addr_ctrl <= idle_ad;
dout_ctrl <= md_lo_dout;
case op_code(3 downto 0) is
when "0000" => -- neg
left_ctrl <= md_left;
right_ctrl <= zero_right;
alu_ctrl <= alu_neg;
cc_ctrl <= load_cc;
md_ctrl <= load_md;
next_state <= write8_state;
when "0011" => -- com
left_ctrl <= md_left;
right_ctrl <= zero_right;
alu_ctrl <= alu_com;
cc_ctrl <= load_cc;
md_ctrl <= load_md;
next_state <= write8_state;
when "0100" => -- lsr
left_ctrl <= md_left;
right_ctrl <= zero_right;
alu_ctrl <= alu_lsr8;
cc_ctrl <= load_cc;
md_ctrl <= load_md;
next_state <= write8_state;
when "0110" => -- ror
left_ctrl <= md_left;
right_ctrl <= zero_right;
alu_ctrl <= alu_ror8;
cc_ctrl <= load_cc;
md_ctrl <= load_md;
next_state <= write8_state;
when "0111" => -- asr
left_ctrl <= md_left;
right_ctrl <= zero_right;
alu_ctrl <= alu_asr8;
cc_ctrl <= load_cc;
md_ctrl <= load_md;
next_state <= write8_state;
when "1000" => -- asl
left_ctrl <= md_left;
right_ctrl <= zero_right;
alu_ctrl <= alu_asl8;
cc_ctrl <= load_cc;
md_ctrl <= load_md;
next_state <= write8_state;
when "1001" => -- rol
left_ctrl <= md_left;
right_ctrl <= zero_right;
alu_ctrl <= alu_rol8;
cc_ctrl <= load_cc;
md_ctrl <= load_md;
next_state <= write8_state;
when "1010" => -- dec
left_ctrl <= md_left;
right_ctrl <= plus_one_right;
alu_ctrl <= alu_dec;
cc_ctrl <= load_cc;
md_ctrl <= load_md;
next_state <= write8_state;
when "1011" => -- undefined
left_ctrl <= md_left;
right_ctrl <= zero_right;
alu_ctrl <= alu_nop;
cc_ctrl <= latch_cc;
md_ctrl <= latch_md;
next_state <= fetch_state;
when "1100" => -- inc
left_ctrl <= md_left;
right_ctrl <= plus_one_right;
alu_ctrl <= alu_inc;
cc_ctrl <= load_cc;
md_ctrl <= load_md;
next_state <= write8_state;
when "1101" => -- tst
left_ctrl <= md_left;
right_ctrl <= zero_right;
alu_ctrl <= alu_st8;
cc_ctrl <= load_cc;
md_ctrl <= latch_md;
next_state <= fetch_state;
when "1110" => -- jmp
left_ctrl <= md_left;
right_ctrl <= zero_right;
alu_ctrl <= alu_nop;
cc_ctrl <= latch_cc;
md_ctrl <= latch_md;
next_state <= fetch_state;
when "1111" => -- clr
left_ctrl <= md_left;
right_ctrl <= zero_right;
alu_ctrl <= alu_ld8;
cc_ctrl <= load_cc;
md_ctrl <= load_md;
next_state <= write8_state;
when others =>
left_ctrl <= md_left;
right_ctrl <= zero_right;
alu_ctrl <= alu_nop;
cc_ctrl <= latch_cc;
md_ctrl <= latch_md;
next_state <= fetch_state;
end case;
 
when "1000" | -- acca immediate
"1001" | -- acca direct
"1010" | -- acca indexed
"1011" => -- acca extended
pc_ctrl <= latch_pc;
iv_ctrl <= latch_iv;
ea_ctrl <= latch_ea;
-- idle the bus
addr_ctrl <= idle_ad;
dout_ctrl <= md_lo_dout;
case op_code(3 downto 0) is
when "0000" => -- suba
left_ctrl <= acca_left;
right_ctrl <= md_right;
alu_ctrl <= alu_sub8;
cc_ctrl <= load_cc;
acca_ctrl <= load_acca;
accb_ctrl <= latch_accb;
ix_ctrl <= latch_ix;
sp_ctrl <= latch_sp;
md_ctrl <= latch_md;
next_state <= fetch_state;
when "0001" => -- cmpa
left_ctrl <= acca_left;
right_ctrl <= md_right;
alu_ctrl <= alu_sub8;
cc_ctrl <= load_cc;
acca_ctrl <= latch_acca;
accb_ctrl <= latch_accb;
ix_ctrl <= latch_ix;
sp_ctrl <= latch_sp;
md_ctrl <= latch_md;
next_state <= fetch_state;
when "0010" => -- sbca
left_ctrl <= acca_left;
right_ctrl <= md_right;
alu_ctrl <= alu_sbc;
cc_ctrl <= load_cc;
acca_ctrl <= load_acca;
accb_ctrl <= latch_accb;
ix_ctrl <= latch_ix;
sp_ctrl <= latch_sp;
md_ctrl <= latch_md;
next_state <= fetch_state;
when "0011" => -- subd
left_ctrl <= accd_left;
right_ctrl <= md_right;
alu_ctrl <= alu_sub16;
cc_ctrl <= load_cc;
acca_ctrl <= load_hi_acca;
accb_ctrl <= load_accb;
ix_ctrl <= latch_ix;
sp_ctrl <= latch_sp;
md_ctrl <= latch_md;
next_state <= fetch_state;
when "0100" => -- anda
left_ctrl <= acca_left;
right_ctrl <= md_right;
alu_ctrl <= alu_and;
cc_ctrl <= load_cc;
acca_ctrl <= load_acca;
accb_ctrl <= latch_accb;
ix_ctrl <= latch_ix;
sp_ctrl <= latch_sp;
md_ctrl <= latch_md;
next_state <= fetch_state;
when "0101" => -- bita
left_ctrl <= acca_left;
right_ctrl <= md_right;
alu_ctrl <= alu_and;
cc_ctrl <= load_cc;
acca_ctrl <= latch_acca;
accb_ctrl <= latch_accb;
ix_ctrl <= latch_ix;
sp_ctrl <= latch_sp;
md_ctrl <= latch_md;
next_state <= fetch_state;
when "0110" => -- ldaa
left_ctrl <= acca_left;
right_ctrl <= md_right;
alu_ctrl <= alu_ld8;
cc_ctrl <= load_cc;
acca_ctrl <= load_acca;
accb_ctrl <= latch_accb;
ix_ctrl <= latch_ix;
sp_ctrl <= latch_sp;
md_ctrl <= latch_md;
next_state <= fetch_state;
when "0111" => -- staa
left_ctrl <= acca_left;
right_ctrl <= md_right;
alu_ctrl <= alu_st8;
cc_ctrl <= load_cc;
acca_ctrl <= latch_acca;
accb_ctrl <= latch_accb;
ix_ctrl <= latch_ix;
sp_ctrl <= latch_sp;
md_ctrl <= load_md;
next_state <= write8_state;
when "1000" => -- eora
left_ctrl <= acca_left;
right_ctrl <= md_right;
alu_ctrl <= alu_eor;
cc_ctrl <= load_cc;
acca_ctrl <= load_acca;
accb_ctrl <= latch_accb;
ix_ctrl <= latch_ix;
sp_ctrl <= latch_sp;
md_ctrl <= latch_md;
next_state <= fetch_state;
when "1001" => -- adca
left_ctrl <= acca_left;
right_ctrl <= md_right;
alu_ctrl <= alu_adc;
cc_ctrl <= load_cc;
acca_ctrl <= load_acca;
accb_ctrl <= latch_accb;
ix_ctrl <= latch_ix;
sp_ctrl <= latch_sp;
md_ctrl <= latch_md;
next_state <= fetch_state;
when "1010" => -- oraa
left_ctrl <= acca_left;
right_ctrl <= md_right;
alu_ctrl <= alu_ora;
cc_ctrl <= load_cc;
acca_ctrl <= load_acca;
accb_ctrl <= latch_accb;
ix_ctrl <= latch_ix;
sp_ctrl <= latch_sp;
md_ctrl <= latch_md;
next_state <= fetch_state;
when "1011" => -- adda
left_ctrl <= acca_left;
right_ctrl <= md_right;
alu_ctrl <= alu_add8;
cc_ctrl <= load_cc;
acca_ctrl <= load_acca;
accb_ctrl <= latch_accb;
ix_ctrl <= latch_ix;
sp_ctrl <= latch_sp;
md_ctrl <= latch_md;
next_state <= fetch_state;
when "1100" => -- cpx
left_ctrl <= ix_left;
right_ctrl <= md_right;
alu_ctrl <= alu_cpx;
cc_ctrl <= load_cc;
acca_ctrl <= latch_acca;
accb_ctrl <= latch_accb;
ix_ctrl <= latch_ix;
sp_ctrl <= latch_sp;
md_ctrl <= latch_md;
next_state <= fetch_state;
when "1101" => -- bsr / jsr
left_ctrl <= pc_left;
right_ctrl <= md_right;
alu_ctrl <= alu_nop;
cc_ctrl <= latch_cc;
acca_ctrl <= latch_acca;
accb_ctrl <= latch_accb;
ix_ctrl <= latch_ix;
sp_ctrl <= latch_sp;
md_ctrl <= latch_md;
next_state <= fetch_state;
when "1110" => -- lds
left_ctrl <= sp_left;
right_ctrl <= md_right;
alu_ctrl <= alu_ld16;
cc_ctrl <= load_cc;
acca_ctrl <= latch_acca;
accb_ctrl <= latch_accb;
ix_ctrl <= latch_ix;
sp_ctrl <= load_sp;
md_ctrl <= latch_md;
next_state <= fetch_state;
when "1111" => -- sts
left_ctrl <= sp_left;
right_ctrl <= md_right;
alu_ctrl <= alu_st16;
cc_ctrl <= load_cc;
acca_ctrl <= latch_acca;
accb_ctrl <= latch_accb;
ix_ctrl <= latch_ix;
sp_ctrl <= latch_sp;
md_ctrl <= load_md;
next_state <= write16_state;
when others =>
left_ctrl <= acca_left;
right_ctrl <= md_right;
alu_ctrl <= alu_nop;
cc_ctrl <= latch_cc;
acca_ctrl <= latch_acca;
accb_ctrl <= latch_accb;
ix_ctrl <= latch_ix;
sp_ctrl <= latch_sp;
md_ctrl <= latch_md;
next_state <= fetch_state;
end case;
when "1100" | -- accb immediate
"1101" | -- accb direct
"1110" | -- accb indexed
"1111" => -- accb extended
pc_ctrl <= latch_pc;
iv_ctrl <= latch_iv;
ea_ctrl <= latch_ea;
-- idle the bus
addr_ctrl <= idle_ad;
dout_ctrl <= md_lo_dout;
case op_code(3 downto 0) is
when "0000" => -- subb
left_ctrl <= accb_left;
right_ctrl <= md_right;
alu_ctrl <= alu_sub8;
cc_ctrl <= load_cc;
acca_ctrl <= latch_acca;
accb_ctrl <= load_accb;
ix_ctrl <= latch_ix;
sp_ctrl <= latch_sp;
md_ctrl <= latch_md;
next_state <= fetch_state;
when "0001" => -- cmpb
left_ctrl <= accb_left;
right_ctrl <= md_right;
alu_ctrl <= alu_sub8;
cc_ctrl <= load_cc;
acca_ctrl <= latch_acca;
accb_ctrl <= latch_accb;
ix_ctrl <= latch_ix;
sp_ctrl <= latch_sp;
md_ctrl <= latch_md;
next_state <= fetch_state;
when "0010" => -- sbcb
left_ctrl <= accb_left;
right_ctrl <= md_right;
alu_ctrl <= alu_sbc;
cc_ctrl <= load_cc;
acca_ctrl <= latch_acca;
accb_ctrl <= load_accb;
ix_ctrl <= latch_ix;
sp_ctrl <= latch_sp;
md_ctrl <= latch_md;
next_state <= fetch_state;
when "0011" => -- addd
left_ctrl <= accd_left;
right_ctrl <= md_right;
alu_ctrl <= alu_add16;
cc_ctrl <= load_cc;
acca_ctrl <= load_hi_acca;
accb_ctrl <= load_accb;
ix_ctrl <= latch_ix;
sp_ctrl <= latch_sp;
md_ctrl <= latch_md;
next_state <= fetch_state;
when "0100" => -- andb
left_ctrl <= accb_left;
right_ctrl <= md_right;
alu_ctrl <= alu_and;
cc_ctrl <= load_cc;
acca_ctrl <= latch_acca;
accb_ctrl <= load_accb;
ix_ctrl <= latch_ix;
sp_ctrl <= latch_sp;
md_ctrl <= latch_md;
next_state <= fetch_state;
when "0101" => -- bitb
left_ctrl <= accb_left;
right_ctrl <= md_right;
alu_ctrl <= alu_and;
cc_ctrl <= load_cc;
acca_ctrl <= latch_acca;
accb_ctrl <= latch_accb;
ix_ctrl <= latch_ix;
sp_ctrl <= latch_sp;
md_ctrl <= latch_md;
next_state <= fetch_state;
when "0110" => -- ldab
left_ctrl <= accb_left;
right_ctrl <= md_right;
alu_ctrl <= alu_ld8;
cc_ctrl <= load_cc;
acca_ctrl <= latch_acca;
accb_ctrl <= load_accb;
ix_ctrl <= latch_ix;
sp_ctrl <= latch_sp;
md_ctrl <= latch_md;
next_state <= fetch_state;
when "0111" => -- stab
left_ctrl <= accb_left;
right_ctrl <= md_right;
alu_ctrl <= alu_st8;
cc_ctrl <= load_cc;
acca_ctrl <= latch_acca;
accb_ctrl <= latch_accb;
ix_ctrl <= latch_ix;
sp_ctrl <= latch_sp;
md_ctrl <= load_md;
next_state <= write8_state;
when "1000" => -- eorb
left_ctrl <= accb_left;
right_ctrl <= md_right;
alu_ctrl <= alu_eor;
cc_ctrl <= load_cc;
acca_ctrl <= latch_acca;
accb_ctrl <= load_accb;
ix_ctrl <= latch_ix;
sp_ctrl <= latch_sp;
md_ctrl <= latch_md;
next_state <= fetch_state;
when "1001" => -- adcb
left_ctrl <= accb_left;
right_ctrl <= md_right;
alu_ctrl <= alu_adc;
cc_ctrl <= load_cc;
acca_ctrl <= latch_acca;
accb_ctrl <= load_accb;
ix_ctrl <= latch_ix;
sp_ctrl <= latch_sp;
md_ctrl <= latch_md;
next_state <= fetch_state;
when "1010" => -- orab
left_ctrl <= accb_left;
right_ctrl <= md_right;
alu_ctrl <= alu_ora;
cc_ctrl <= load_cc;
acca_ctrl <= latch_acca;
accb_ctrl <= load_accb;
ix_ctrl <= latch_ix;
sp_ctrl <= latch_sp;
md_ctrl <= latch_md;
next_state <= fetch_state;
when "1011" => -- addb
left_ctrl <= accb_left;
right_ctrl <= md_right;
alu_ctrl <= alu_add8;
cc_ctrl <= load_cc;
acca_ctrl <= latch_acca;
accb_ctrl <= load_accb;
ix_ctrl <= latch_ix;
sp_ctrl <= latch_sp;
md_ctrl <= latch_md;
next_state <= fetch_state;
when "1100" => -- ldd
left_ctrl <= accd_left;
right_ctrl <= md_right;
alu_ctrl <= alu_ld16;
cc_ctrl <= load_cc;
acca_ctrl <= load_hi_acca;
accb_ctrl <= load_accb;
ix_ctrl <= latch_ix;
sp_ctrl <= latch_sp;
md_ctrl <= latch_md;
next_state <= fetch_state;
when "1101" => -- std
left_ctrl <= accd_left;
right_ctrl <= md_right;
alu_ctrl <= alu_st16;
cc_ctrl <= latch_cc;
acca_ctrl <= latch_acca;
accb_ctrl <= latch_accb;
ix_ctrl <= latch_ix;
sp_ctrl <= latch_sp;
md_ctrl <= load_md;
next_state <= write16_state;
when "1110" => -- ldx
left_ctrl <= ix_left;
right_ctrl <= md_right;
alu_ctrl <= alu_ld16;
cc_ctrl <= load_cc;
acca_ctrl <= latch_acca;
accb_ctrl <= latch_accb;
ix_ctrl <= load_ix;
sp_ctrl <= latch_sp;
md_ctrl <= latch_md;
next_state <= fetch_state;
when "1111" => -- stx
left_ctrl <= ix_left;
right_ctrl <= md_right;
alu_ctrl <= alu_st16;
cc_ctrl <= load_cc;
acca_ctrl <= latch_acca;
accb_ctrl <= latch_accb;
ix_ctrl <= latch_ix;
sp_ctrl <= latch_sp;
md_ctrl <= load_md;
next_state <= write16_state;
when others =>
left_ctrl <= accb_left;
right_ctrl <= md_right;
alu_ctrl <= alu_nop;
cc_ctrl <= latch_cc;
acca_ctrl <= latch_acca;
accb_ctrl <= latch_accb;
ix_ctrl <= latch_ix;
sp_ctrl <= latch_sp;
md_ctrl <= latch_md;
next_state <= fetch_state;
end case;
when others =>
left_ctrl <= accd_left;
right_ctrl <= md_right;
alu_ctrl <= alu_nop;
cc_ctrl <= latch_cc;
acca_ctrl <= latch_acca;
accb_ctrl <= latch_accb;
ix_ctrl <= latch_ix;
sp_ctrl <= latch_sp;
pc_ctrl <= latch_pc;
md_ctrl <= latch_md;
iv_ctrl <= latch_iv;
ea_ctrl <= latch_ea;
-- idle the bus
addr_ctrl <= idle_ad;
dout_ctrl <= md_lo_dout;
next_state <= fetch_state;
end case;
--
-- 16 bit Write state
-- write high byte of ALU output.
-- EA hold address of memory to write to
-- Advance the effective address in ALU
--
when write16_state =>
-- default
acca_ctrl <= latch_acca;
accb_ctrl <= latch_accb;
ix_ctrl <= latch_ix;
sp_ctrl <= latch_sp;
pc_ctrl <= latch_pc;
md_ctrl <= latch_md;
iv_ctrl <= latch_iv;
op_ctrl <= latch_op;
nmi_ctrl <= latch_nmi;
-- increment the effective address
left_ctrl <= ea_left;
right_ctrl <= plus_one_right;
alu_ctrl <= alu_add16;
cc_ctrl <= latch_cc;
ea_ctrl <= load_ea;
-- write the ALU hi byte to ea
addr_ctrl <= write_ad;
dout_ctrl <= md_hi_dout;
next_state <= write8_state;
--
-- 8 bit write
-- Write low 8 bits of ALU output
--
when write8_state =>
-- default registers
acca_ctrl <= latch_acca;
accb_ctrl <= latch_accb;
ix_ctrl <= latch_ix;
sp_ctrl <= latch_sp;
pc_ctrl <= latch_pc;
md_ctrl <= latch_md;
iv_ctrl <= latch_iv;
op_ctrl <= latch_op;
nmi_ctrl <= latch_nmi;
ea_ctrl <= latch_ea;
-- idle the ALU
left_ctrl <= acca_left;
right_ctrl <= zero_right;
alu_ctrl <= alu_nop;
cc_ctrl <= latch_cc;
-- write ALU low byte output
addr_ctrl <= write_ad;
dout_ctrl <= md_lo_dout;
next_state <= fetch_state;
 
when psha_state =>
-- default registers
acca_ctrl <= latch_acca;
accb_ctrl <= latch_accb;
ix_ctrl <= latch_ix;
pc_ctrl <= latch_pc;
md_ctrl <= latch_md;
iv_ctrl <= latch_iv;
op_ctrl <= latch_op;
nmi_ctrl <= latch_nmi;
ea_ctrl <= latch_ea;
-- decrement sp
left_ctrl <= sp_left;
right_ctrl <= plus_one_right;
alu_ctrl <= alu_sub16;
cc_ctrl <= latch_cc;
sp_ctrl <= load_sp;
-- write acca
addr_ctrl <= push_ad;
dout_ctrl <= acca_dout;
next_state <= fetch_state;
 
when pula_state =>
-- default registers
acca_ctrl <= latch_acca;
accb_ctrl <= latch_accb;
ix_ctrl <= latch_ix;
pc_ctrl <= latch_pc;
md_ctrl <= latch_md;
iv_ctrl <= latch_iv;
op_ctrl <= latch_op;
nmi_ctrl <= latch_nmi;
ea_ctrl <= latch_ea;
-- idle sp
left_ctrl <= sp_left;
right_ctrl <= zero_right;
alu_ctrl <= alu_nop;
cc_ctrl <= latch_cc;
sp_ctrl <= latch_sp;
-- read acca
acca_ctrl <= pull_acca;
addr_ctrl <= pull_ad;
dout_ctrl <= acca_dout;
next_state <= fetch_state;
 
when pshb_state =>
-- default registers
acca_ctrl <= latch_acca;
accb_ctrl <= latch_accb;
ix_ctrl <= latch_ix;
pc_ctrl <= latch_pc;
md_ctrl <= latch_md;
iv_ctrl <= latch_iv;
op_ctrl <= latch_op;
nmi_ctrl <= latch_nmi;
ea_ctrl <= latch_ea;
-- decrement sp
left_ctrl <= sp_left;
right_ctrl <= plus_one_right;
alu_ctrl <= alu_sub16;
cc_ctrl <= latch_cc;
sp_ctrl <= load_sp;
-- write accb
addr_ctrl <= push_ad;
dout_ctrl <= accb_dout;
next_state <= fetch_state;
 
when pulb_state =>
-- default
acca_ctrl <= latch_acca;
accb_ctrl <= latch_accb;
ix_ctrl <= latch_ix;
pc_ctrl <= latch_pc;
md_ctrl <= latch_md;
iv_ctrl <= latch_iv;
op_ctrl <= latch_op;
nmi_ctrl <= latch_nmi;
ea_ctrl <= latch_ea;
-- idle sp
left_ctrl <= sp_left;
right_ctrl <= zero_right;
alu_ctrl <= alu_nop;
cc_ctrl <= latch_cc;
sp_ctrl <= latch_sp;
-- read accb
accb_ctrl <= pull_accb;
addr_ctrl <= pull_ad;
dout_ctrl <= accb_dout;
next_state <= fetch_state;
 
when pshx_lo_state =>
-- default
acca_ctrl <= latch_acca;
accb_ctrl <= latch_accb;
ix_ctrl <= latch_ix;
sp_ctrl <= latch_sp;
pc_ctrl <= latch_pc;
md_ctrl <= latch_md;
iv_ctrl <= latch_iv;
op_ctrl <= latch_op;
nmi_ctrl <= latch_nmi;
ea_ctrl <= latch_ea;
-- decrement sp
left_ctrl <= sp_left;
right_ctrl <= plus_one_right;
alu_ctrl <= alu_sub16;
cc_ctrl <= latch_cc;
sp_ctrl <= load_sp;
-- write ix low
addr_ctrl <= push_ad;
dout_ctrl <= ix_lo_dout;
next_state <= pshx_hi_state;
 
when pshx_hi_state =>
-- default registers
acca_ctrl <= latch_acca;
accb_ctrl <= latch_accb;
ix_ctrl <= latch_ix;
pc_ctrl <= latch_pc;
md_ctrl <= latch_md;
iv_ctrl <= latch_iv;
op_ctrl <= latch_op;
nmi_ctrl <= latch_nmi;
ea_ctrl <= latch_ea;
-- decrement sp
left_ctrl <= sp_left;
right_ctrl <= plus_one_right;
alu_ctrl <= alu_sub16;
cc_ctrl <= latch_cc;
sp_ctrl <= load_sp;
-- write ix hi
addr_ctrl <= push_ad;
dout_ctrl <= ix_hi_dout;
next_state <= fetch_state;
 
when pulx_hi_state =>
-- default
acca_ctrl <= latch_acca;
accb_ctrl <= latch_accb;
pc_ctrl <= latch_pc;
md_ctrl <= latch_md;
iv_ctrl <= latch_iv;
op_ctrl <= latch_op;
nmi_ctrl <= latch_nmi;
ea_ctrl <= latch_ea;
-- increment sp
left_ctrl <= sp_left;
right_ctrl <= plus_one_right;
alu_ctrl <= alu_add16;
cc_ctrl <= latch_cc;
sp_ctrl <= load_sp;
-- pull ix hi
ix_ctrl <= pull_hi_ix;
addr_ctrl <= pull_ad;
dout_ctrl <= ix_hi_dout;
next_state <= pulx_lo_state;
 
when pulx_lo_state =>
-- default
acca_ctrl <= latch_acca;
accb_ctrl <= latch_accb;
pc_ctrl <= latch_pc;
md_ctrl <= latch_md;
iv_ctrl <= latch_iv;
op_ctrl <= latch_op;
nmi_ctrl <= latch_nmi;
ea_ctrl <= latch_ea;
-- idle sp
left_ctrl <= sp_left;
right_ctrl <= zero_right;
alu_ctrl <= alu_nop;
cc_ctrl <= latch_cc;
sp_ctrl <= latch_sp;
-- read ix low
ix_ctrl <= pull_lo_ix;
addr_ctrl <= pull_ad;
dout_ctrl <= ix_lo_dout;
next_state <= fetch_state;
 
--
-- return from interrupt
-- enter here from bogus interrupts
--
when rti_state =>
-- default registers
acca_ctrl <= latch_acca;
accb_ctrl <= latch_accb;
ix_ctrl <= latch_ix;
pc_ctrl <= latch_pc;
md_ctrl <= latch_md;
iv_ctrl <= latch_iv;
op_ctrl <= latch_op;
nmi_ctrl <= latch_nmi;
ea_ctrl <= latch_ea;
-- increment sp
left_ctrl <= sp_left;
right_ctrl <= plus_one_right;
alu_ctrl <= alu_add16;
sp_ctrl <= load_sp;
-- idle address bus
cc_ctrl <= latch_cc;
addr_ctrl <= idle_ad;
dout_ctrl <= cc_dout;
next_state <= rti_cc_state;
 
when rti_cc_state =>
-- default registers
acca_ctrl <= latch_acca;
accb_ctrl <= latch_accb;
ix_ctrl <= latch_ix;
pc_ctrl <= latch_pc;
md_ctrl <= latch_md;
iv_ctrl <= latch_iv;
op_ctrl <= latch_op;
nmi_ctrl <= latch_nmi;
ea_ctrl <= latch_ea;
-- increment sp
left_ctrl <= sp_left;
right_ctrl <= plus_one_right;
alu_ctrl <= alu_add16;
sp_ctrl <= load_sp;
-- read cc
cc_ctrl <= pull_cc;
addr_ctrl <= pull_ad;
dout_ctrl <= cc_dout;
next_state <= rti_accb_state;
 
when rti_accb_state =>
-- default registers
acca_ctrl <= latch_acca;
ix_ctrl <= latch_ix;
pc_ctrl <= latch_pc;
md_ctrl <= latch_md;
iv_ctrl <= latch_iv;
op_ctrl <= latch_op;
nmi_ctrl <= latch_nmi;
ea_ctrl <= latch_ea;
-- increment sp
left_ctrl <= sp_left;
right_ctrl <= plus_one_right;
alu_ctrl <= alu_add16;
cc_ctrl <= latch_cc;
sp_ctrl <= load_sp;
-- read accb
accb_ctrl <= pull_accb;
addr_ctrl <= pull_ad;
dout_ctrl <= accb_dout;
next_state <= rti_acca_state;
 
when rti_acca_state =>
-- default registers
accb_ctrl <= latch_accb;
ix_ctrl <= latch_ix;
pc_ctrl <= latch_pc;
md_ctrl <= latch_md;
iv_ctrl <= latch_iv;
op_ctrl <= latch_op;
nmi_ctrl <= latch_nmi;
ea_ctrl <= latch_ea;
-- increment sp
left_ctrl <= sp_left;
right_ctrl <= plus_one_right;
alu_ctrl <= alu_add16;
cc_ctrl <= latch_cc;
sp_ctrl <= load_sp;
-- read acca
acca_ctrl <= pull_acca;
addr_ctrl <= pull_ad;
dout_ctrl <= acca_dout;
next_state <= rti_ixh_state;
 
when rti_ixh_state =>
-- default
acca_ctrl <= latch_acca;
accb_ctrl <= latch_accb;
pc_ctrl <= latch_pc;
md_ctrl <= latch_md;
iv_ctrl <= latch_iv;
op_ctrl <= latch_op;
nmi_ctrl <= latch_nmi;
ea_ctrl <= latch_ea;
-- increment sp
left_ctrl <= sp_left;
right_ctrl <= plus_one_right;
alu_ctrl <= alu_add16;
cc_ctrl <= latch_cc;
sp_ctrl <= load_sp;
-- read ix hi
ix_ctrl <= pull_hi_ix;
addr_ctrl <= pull_ad;
dout_ctrl <= ix_hi_dout;
next_state <= rti_ixl_state;
 
when rti_ixl_state =>
-- default
acca_ctrl <= latch_acca;
accb_ctrl <= latch_accb;
pc_ctrl <= latch_pc;
md_ctrl <= latch_md;
iv_ctrl <= latch_iv;
op_ctrl <= latch_op;
nmi_ctrl <= latch_nmi;
ea_ctrl <= latch_ea;
-- increment sp
left_ctrl <= sp_left;
right_ctrl <= plus_one_right;
alu_ctrl <= alu_add16;
cc_ctrl <= latch_cc;
sp_ctrl <= load_sp;
-- read ix low
ix_ctrl <= pull_lo_ix;
addr_ctrl <= pull_ad;
dout_ctrl <= ix_lo_dout;
next_state <= rti_pch_state;
 
when rti_pch_state =>
-- default
acca_ctrl <= latch_acca;
accb_ctrl <= latch_accb;
ix_ctrl <= latch_ix;
pc_ctrl <= latch_pc;
md_ctrl <= latch_md;
iv_ctrl <= latch_iv;
op_ctrl <= latch_op;
nmi_ctrl <= latch_nmi;
ea_ctrl <= latch_ea;
-- increment sp
left_ctrl <= sp_left;
right_ctrl <= plus_one_right;
alu_ctrl <= alu_add16;
cc_ctrl <= latch_cc;
sp_ctrl <= load_sp;
-- pull pc hi
pc_ctrl <= pull_hi_pc;
addr_ctrl <= pull_ad;
dout_ctrl <= pc_hi_dout;
next_state <= rti_pcl_state;
 
when rti_pcl_state =>
-- default
acca_ctrl <= latch_acca;
accb_ctrl <= latch_accb;
ix_ctrl <= latch_ix;
md_ctrl <= latch_md;
iv_ctrl <= latch_iv;
op_ctrl <= latch_op;
nmi_ctrl <= latch_nmi;
ea_ctrl <= latch_ea;
-- idle sp
left_ctrl <= sp_left;
right_ctrl <= zero_right;
alu_ctrl <= alu_nop;
cc_ctrl <= latch_cc;
sp_ctrl <= latch_sp;
-- pull pc low
pc_ctrl <= pull_lo_pc;
addr_ctrl <= pull_ad;
dout_ctrl <= pc_lo_dout;
next_state <= fetch_state;
 
--
-- here on interrupt
-- iv register hold interrupt type
--
when int_pcl_state =>
-- default
acca_ctrl <= latch_acca;
accb_ctrl <= latch_accb;
ix_ctrl <= latch_ix;
pc_ctrl <= latch_pc;
md_ctrl <= latch_md;
iv_ctrl <= latch_iv;
op_ctrl <= latch_op;
nmi_ctrl <= latch_nmi;
ea_ctrl <= latch_ea;
-- decrement sp
left_ctrl <= sp_left;
right_ctrl <= plus_one_right;
alu_ctrl <= alu_sub16;
cc_ctrl <= latch_cc;
sp_ctrl <= load_sp;
-- write pc low
addr_ctrl <= push_ad;
dout_ctrl <= pc_lo_dout;
next_state <= int_pch_state;
 
when int_pch_state =>
-- default
acca_ctrl <= latch_acca;
accb_ctrl <= latch_accb;
ix_ctrl <= latch_ix;
pc_ctrl <= latch_pc;
md_ctrl <= latch_md;
iv_ctrl <= latch_iv;
op_ctrl <= latch_op;
nmi_ctrl <= latch_nmi;
ea_ctrl <= latch_ea;
-- decrement sp
left_ctrl <= sp_left;
right_ctrl <= plus_one_right;
alu_ctrl <= alu_sub16;
cc_ctrl <= latch_cc;
sp_ctrl <= load_sp;
-- write pc hi
addr_ctrl <= push_ad;
dout_ctrl <= pc_hi_dout;
next_state <= int_ixl_state;
 
when int_ixl_state =>
-- default
acca_ctrl <= latch_acca;
accb_ctrl <= latch_accb;
ix_ctrl <= latch_ix;
pc_ctrl <= latch_pc;
md_ctrl <= latch_md;
iv_ctrl <= latch_iv;
op_ctrl <= latch_op;
nmi_ctrl <= latch_nmi;
ea_ctrl <= latch_ea;
-- decrement sp
left_ctrl <= sp_left;
right_ctrl <= plus_one_right;
alu_ctrl <= alu_sub16;
cc_ctrl <= latch_cc;
sp_ctrl <= load_sp;
-- write ix low
addr_ctrl <= push_ad;
dout_ctrl <= ix_lo_dout;
next_state <= int_ixh_state;
 
when int_ixh_state =>
-- default
acca_ctrl <= latch_acca;
accb_ctrl <= latch_accb;
ix_ctrl <= latch_ix;
pc_ctrl <= latch_pc;
md_ctrl <= latch_md;
iv_ctrl <= latch_iv;
op_ctrl <= latch_op;
nmi_ctrl <= latch_nmi;
ea_ctrl <= latch_ea;
-- decrement sp
left_ctrl <= sp_left;
right_ctrl <= plus_one_right;
alu_ctrl <= alu_sub16;
cc_ctrl <= latch_cc;
sp_ctrl <= load_sp;
-- write ix hi
addr_ctrl <= push_ad;
dout_ctrl <= ix_hi_dout;
next_state <= int_acca_state;
 
when int_acca_state =>
-- default
acca_ctrl <= latch_acca;
accb_ctrl <= latch_accb;
ix_ctrl <= latch_ix;
pc_ctrl <= latch_pc;
md_ctrl <= latch_md;
iv_ctrl <= latch_iv;
op_ctrl <= latch_op;
nmi_ctrl <= latch_nmi;
ea_ctrl <= latch_ea;
-- decrement sp
left_ctrl <= sp_left;
right_ctrl <= plus_one_right;
alu_ctrl <= alu_sub16;
cc_ctrl <= latch_cc;
sp_ctrl <= load_sp;
-- write acca
addr_ctrl <= push_ad;
dout_ctrl <= acca_dout;
next_state <= int_accb_state;
 
 
when int_accb_state =>
-- default
acca_ctrl <= latch_acca;
accb_ctrl <= latch_accb;
ix_ctrl <= latch_ix;
pc_ctrl <= latch_pc;
md_ctrl <= latch_md;
iv_ctrl <= latch_iv;
op_ctrl <= latch_op;
nmi_ctrl <= latch_nmi;
ea_ctrl <= latch_ea;
-- decrement sp
left_ctrl <= sp_left;
right_ctrl <= plus_one_right;
alu_ctrl <= alu_sub16;
cc_ctrl <= latch_cc;
sp_ctrl <= load_sp;
-- write accb
addr_ctrl <= push_ad;
dout_ctrl <= accb_dout;
next_state <= int_cc_state;
 
when int_cc_state =>
-- default
acca_ctrl <= latch_acca;
accb_ctrl <= latch_accb;
ix_ctrl <= latch_ix;
pc_ctrl <= latch_pc;
md_ctrl <= latch_md;
op_ctrl <= latch_op;
nmi_ctrl <= latch_nmi;
ea_ctrl <= latch_ea;
-- decrement sp
left_ctrl <= sp_left;
right_ctrl <= plus_one_right;
alu_ctrl <= alu_sub16;
cc_ctrl <= latch_cc;
sp_ctrl <= load_sp;
-- write cc
addr_ctrl <= push_ad;
dout_ctrl <= cc_dout;
nmi_ctrl <= latch_nmi;
--
-- nmi is edge triggered
-- nmi_req is cleared when nmi goes low.
--
if nmi_req = '1' then
iv_ctrl <= nmi_iv;
next_state <= vect_hi_state;
else
--
-- IRQ is level sensitive
--
if (irq = '1') and (cc(IBIT) = '0') then
iv_ctrl <= irq_iv;
next_state <= int_mask_state;
else
case op_code is
when "00111110" => -- WAI (wait for interrupt)
iv_ctrl <= latch_iv;
next_state <= int_wai_state;
when "00111111" => -- SWI (Software interrupt)
iv_ctrl <= swi_iv;
next_state <= vect_hi_state;
when others => -- bogus interrupt (return)
iv_ctrl <= latch_iv;
next_state <= rti_state;
end case;
end if;
end if;
 
when int_wai_state =>
-- default
acca_ctrl <= latch_acca;
accb_ctrl <= latch_accb;
ix_ctrl <= latch_ix;
pc_ctrl <= latch_pc;
md_ctrl <= latch_md;
op_ctrl <= latch_op;
ea_ctrl <= latch_ea;
-- enable interrupts
left_ctrl <= sp_left;
right_ctrl <= plus_one_right;
alu_ctrl <= alu_cli;
cc_ctrl <= load_cc;
sp_ctrl <= latch_sp;
-- idle bus
addr_ctrl <= idle_ad;
dout_ctrl <= cc_dout;
if (nmi_req = '1') and (nmi_ack='0') then
iv_ctrl <= nmi_iv;
nmi_ctrl <= set_nmi;
next_state <= vect_hi_state;
else
--
-- nmi request is not cleared until nmi input goes low
--
if (nmi_req = '0') and (nmi_ack='1') then
nmi_ctrl <= reset_nmi;
else
nmi_ctrl <= latch_nmi;
end if;
--
-- IRQ is level sensitive
--
if (irq = '1') and (cc(IBIT) = '0') then
iv_ctrl <= irq_iv;
next_state <= int_mask_state;
else
iv_ctrl <= latch_iv;
next_state <= int_wai_state;
end if;
end if;
 
when int_mask_state =>
-- default
acca_ctrl <= latch_acca;
accb_ctrl <= latch_accb;
ix_ctrl <= latch_ix;
pc_ctrl <= latch_pc;
md_ctrl <= latch_md;
iv_ctrl <= latch_iv;
op_ctrl <= latch_op;
nmi_ctrl <= latch_nmi;
ea_ctrl <= latch_ea;
-- Mask IRQ
left_ctrl <= sp_left;
right_ctrl <= zero_right;
alu_ctrl <= alu_sei;
cc_ctrl <= load_cc;
sp_ctrl <= latch_sp;
-- idle bus cycle
addr_ctrl <= idle_ad;
dout_ctrl <= md_lo_dout;
next_state <= vect_hi_state;
 
when others => -- halt on undefine states
-- default
acca_ctrl <= latch_acca;
accb_ctrl <= latch_accb;
ix_ctrl <= latch_ix;
sp_ctrl <= latch_sp;
pc_ctrl <= latch_pc;
md_ctrl <= latch_md;
iv_ctrl <= latch_iv;
op_ctrl <= latch_op;
nmi_ctrl <= latch_nmi;
ea_ctrl <= latch_ea;
-- do nothing in ALU
left_ctrl <= acca_left;
right_ctrl <= zero_right;
alu_ctrl <= alu_nop;
cc_ctrl <= latch_cc;
-- idle bus cycle
addr_ctrl <= idle_ad;
dout_ctrl <= md_lo_dout;
next_state <= halt_state;
end case;
end process;
 
--------------------------------
--
-- state machine
--
--------------------------------
 
change_state: process( clk, rst, state )
begin
if clk'event and clk = '1' then
if rst = '1' then
state <= reset_state;
else
state <= next_state;
end if;
end if;
end process;
-- output
end CPU_ARCH;
/tags/arelease/vhdl/datram.vhd
0,0 → 1,188
--===========================================================================--
--
-- S Y N T H E Z I A B L E Dynamic Address Translation Registers
--
-- www.OpenCores.Org - December 2002
-- This core adheres to the GNU public license
--
-- File name : datram.vhd
--
-- entity name : dat_ram
--
-- Purpose : Implements a Dynamic Address Translation RAM module
-- Maps the high order 4 address bits to 8 address lines
-- extending the memory addressing range to 1 Mbytes
-- Memory segments are mapped on 4 KByte boundaries
-- The DAT registers map to the top of memory
-- ($FFF0 - $FFFF) and are write only so can map over ROM.
-- Since the DAT is not supported by SWTBUG for the 6800,
-- the resgisters reset state map the bottom 64K of RAM.
--
-- Dependencies : ieee.Std_Logic_1164
-- ieee.std_logic_unsigned
--
-- Author : John E. Kent
--
--===========================================================================----
--
-- Revision History:
--
-- Date Revision Author
-- 10 Nov 2002 0.1 John Kent
--
 
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
 
entity dat_ram is
port (
clk : in std_logic;
rst : in std_logic;
cs : in std_logic;
rw : in std_logic;
addr_hi : in std_logic_vector(3 downto 0);
addr_lo : in std_logic_vector(3 downto 0);
data_in : in std_logic_vector(7 downto 0);
data_out : out std_logic_vector(7 downto 0));
end;
 
architecture datram_arch of dat_ram is
signal dat_reg0 : std_logic_vector(7 downto 0);
signal dat_reg1 : std_logic_vector(7 downto 0);
signal dat_reg2 : std_logic_vector(7 downto 0);
signal dat_reg3 : std_logic_vector(7 downto 0);
signal dat_reg4 : std_logic_vector(7 downto 0);
signal dat_reg5 : std_logic_vector(7 downto 0);
signal dat_reg6 : std_logic_vector(7 downto 0);
signal dat_reg7 : std_logic_vector(7 downto 0);
signal dat_reg8 : std_logic_vector(7 downto 0);
signal dat_reg9 : std_logic_vector(7 downto 0);
signal dat_reg10 : std_logic_vector(7 downto 0);
signal dat_reg11 : std_logic_vector(7 downto 0);
signal dat_reg12 : std_logic_vector(7 downto 0);
signal dat_reg13 : std_logic_vector(7 downto 0);
signal dat_reg14 : std_logic_vector(7 downto 0);
signal dat_reg15 : std_logic_vector(7 downto 0);
 
begin
 
---------------------------------
--
-- Write DAT RAM
--
---------------------------------
 
dat_write : process( clk, rst, addr_lo, cs, rw, data_in,
dat_reg0, dat_reg1, dat_reg2, dat_reg3,
dat_reg4, dat_reg5, dat_reg6, dat_reg7,
dat_reg8, dat_reg9, dat_reg10, dat_reg11,
dat_reg12, dat_reg13, dat_reg14, dat_reg15 )
begin
if clk'event and clk = '1' then
if rst = '1' then
dat_reg0 <= "00000000";
dat_reg1 <= "00000001";
dat_reg2 <= "00000010";
dat_reg3 <= "00000011";
dat_reg4 <= "00000100";
dat_reg5 <= "00000101";
dat_reg6 <= "00000110";
dat_reg7 <= "00000111";
dat_reg8 <= "00001000";
dat_reg9 <= "00001001";
dat_reg10 <= "00001010";
dat_reg11 <= "00001011";
dat_reg12 <= "00001100";
dat_reg13 <= "00001101";
dat_reg14 <= "00001110";
dat_reg15 <= "00001111";
else
if cs = '1' and rw = '0' then
case addr_lo is
when "0000" =>
dat_reg0 <= data_in;
when "0001" =>
dat_reg1 <= data_in;
when "0010" =>
dat_reg2 <= data_in;
when "0011" =>
dat_reg3 <= data_in;
when "0100" =>
dat_reg4 <= data_in;
when "0101" =>
dat_reg5 <= data_in;
when "0110" =>
dat_reg6 <= data_in;
when "0111" =>
dat_reg7 <= data_in;
when "1000" =>
dat_reg8 <= data_in;
when "1001" =>
dat_reg9 <= data_in;
when "1010" =>
dat_reg10 <= data_in;
when "1011" =>
dat_reg11 <= data_in;
when "1100" =>
dat_reg12 <= data_in;
when "1101" =>
dat_reg13 <= data_in;
when "1110" =>
dat_reg14 <= data_in;
when "1111" =>
dat_reg15 <= data_in;
when others =>
null;
end case;
end if;
end if;
end if;
end process;
 
dat_read : process( addr_hi,
dat_reg0, dat_reg1, dat_reg2, dat_reg3,
dat_reg4, dat_reg5, dat_reg6, dat_reg7,
dat_reg8, dat_reg9, dat_reg10, dat_reg11,
dat_reg12, dat_reg13, dat_reg14, dat_reg15 )
begin
case addr_hi is
when "0000" =>
data_out <= dat_reg0;
when "0001" =>
data_out <= dat_reg1;
when "0010" =>
data_out <= dat_reg2;
when "0011" =>
data_out <= dat_reg3;
when "0100" =>
data_out <= dat_reg4;
when "0101" =>
data_out <= dat_reg5;
when "0110" =>
data_out <= dat_reg6;
when "0111" =>
data_out <= dat_reg7;
when "1000" =>
data_out <= dat_reg8;
when "1001" =>
data_out <= dat_reg9;
when "1010" =>
data_out <= dat_reg10;
when "1011" =>
data_out <= dat_reg11;
when "1100" =>
data_out <= dat_reg12;
when "1101" =>
data_out <= dat_reg13;
when "1110" =>
data_out <= dat_reg14;
when "1111" =>
data_out <= dat_reg15;
when others =>
null;
end case;
end process;
 
end datram_arch;
/tags/arelease/vhdl/clkunit.vhd
0,0 → 1,130
--===========================================================================--
--
-- S Y N T H E Z I A B L E miniUART C O R E
--
-- www.OpenCores.Org - January 2000
-- This core adheres to the GNU public license
 
-- Design units : miniUART core for the OCRP-1
--
-- File name : clkUnit.vhd
--
-- Purpose : Implements an miniUART device for communication purposes
-- between the OR1K processor and the Host computer through
-- an RS-232 communication protocol.
--
-- Library : uart_lib.vhd
--
-- Dependencies : IEEE.Std_Logic_1164
--
--===========================================================================--
-------------------------------------------------------------------------------
-- Revision list
-- Version Author Date Changes
--
-- 0.1 Ovidiu Lupas 15 January 2000 New model
-- olupas@opencores.org
-- 2.0 John Kent 10 November 2002 Added programmable baud rate
-- 3.0 John Kent 15 December 2002 Fix TX clock divider
-------------------------------------------------------------------------------
-- Description : Generates the Baud clock and enable signals for RX & TX
-- units.
-------------------------------------------------------------------------------
-- Entity for Baud rate generator Unit - 9600 baudrate --
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library work;
-- use work.UART_Def.all;
-------------------------------------------------------------------------------
-- Baud rate generator
-------------------------------------------------------------------------------
entity ClkUnit is
port (
Clk : in Std_Logic; -- System Clock
Reset : in Std_Logic; -- Reset input
EnableRx : out Std_Logic; -- Control signal
EnableTx : out Std_Logic; -- Control signal
BaudRate : in Std_Logic_Vector(1 downto 0));
end entity; --================== End of entity ==============================--
-------------------------------------------------------------------------------
-- Architecture for Baud rate generator Unit
-------------------------------------------------------------------------------
architecture Behaviour of ClkUnit is
signal tmpEnRx : std_logic;
 
begin
-----------------------------------------------------------------------------
-- Divides the system clock of 40 MHz div 260 gives 153 KHz for 9600bps
-- 48 MHz div 156 gives 300 KHz for 19.2Kbps
-- 24 MHz div 156 gives 153 KHz for 9600bps
-- 4.9152MHz div 32 gives 153KHz for 9600bps
-----------------------------------------------------------------------------
DivClk : process(Clk,Reset,tmpEnRx, BaudRate)
variable Count : unsigned(7 downto 0);
constant CntOne : Unsigned(7 downto 0):="00000001";
begin
if Clk'event and Clk = '1' then
if Reset = '1' then
Count := "00000000";
tmpEnRx <= '0';
else
if Count = "00000000" then
tmpEnRx <= '1';
case BaudRate is
when "00" => -- divide by 1 ((1*2)-1) (fast)
Count := "00000001";
when "01" => -- divide by 16 ((16*2)-1) (9600 Baud)
Count := "00011111";
when "10" => -- divide by 64 ((64*2)-1) (2400 Baud)
Count := "01111111";
when others =>
-- when "11" => -- reset
Count := "00000000";
null;
end case;
else
tmpEnRx <= '0';
Count := Count - CntOne;
end if;
end if;
end if;
EnableRx <= tmpEnRx;
end process;
 
-----------------------------------------------------------------------------
-- Provides the EnableTX signal, at 9.6 KHz
-- Divide by 16
-- Except it wasn't ... it counted up to "10010" (18)
-----------------------------------------------------------------------------
DivClk16 : process(Clk,Reset,tmpEnRX)
variable Cnt16 : unsigned(4 downto 0);
constant CntOne : Unsigned(4 downto 0):="00001";
begin
if Clk'event and Clk = '1' then
if Reset = '1' then
Cnt16 := "00000";
EnableTX <= '0';
else
case Cnt16 is
when "00000" =>
if tmpEnRx = '1' then
Cnt16 := "01111";
EnableTx <='1';
else
Cnt16 := Cnt16;
EnableTx <= '0';
end if;
when others =>
if tmpEnRx = '1' then
Cnt16 := Cnt16 - CntOne;
else
Cnt16 := Cnt16;
end if;
EnableTX <= '0';
end case;
end if;
end if;
end process;
end Behaviour; --==================== End of architecture ===================--
/tags/arelease/vhdl/System68.npl
0,0 → 1,38
JDF E
// Created by ISE ver 1.0
PROJECT System68
DESIGN system68 Normal
DEVKIT xc2s200-5pq208
DEVFAM spartan2
FLOW XST VHDL
STIMULUS testbench1.vhd Normal
STIMULUS testbench2.vhd Normal
STIMULUS testbench3.vhd Normal
MODULE ioport.vhd
MODSTYLE ioport Normal
MODULE rxunit.vhd
MODSTYLE rxunit Normal
MODULE txunit.vhd
MODSTYLE txunit Normal
MODULE cpu68.vhd
MODSTYLE cpu68 Normal
MODULE datram.vhd
MODSTYLE dat_ram Normal
MODULE timer.vhd
MODSTYLE timer Normal
MODULE swtbug.vhd
MODSTYLE boot_rom Normal
MODULE clkunit.vhd
MODSTYLE clkunit Normal
MODULE System68.vhd
MODSTYLE system68 Normal
MODULE miniUART.vhd
MODSTYLE miniuart Normal
LIBFILE uart_def.vhd work ***
 
[STRATEGY-LIST]
Normal=True, 1030338967
 
[Normal]
p_impactPort=xstvhd, SPARTAN2, Implementation.t_impactProgrammingTool, 1036868796, LPT 1 (PC)
p_impactConfigMode=xstvhd, SPARTAN2, Implementation.t_impactProgrammingTool, 1031246025, Slave Serial
/tags/arelease/vhdl/swtbug.vhd
0,0 → 1,1076
--===========================================================================--
--
-- S Y N T H E Z I A B L E SWTBUG ROM C O R E
--
-- www.OpenCores.Org - December 2002
-- This core adheres to the GNU public license
--
-- File name : swtbug.vhd
--
-- entity name : boot_rom
--
-- Purpose : Implements a 1K x 8 ROM containing the
-- SWTBUG monitor program for the SWTPC 6800
--
-- Dependencies : ieee.Std_Logic_1164
-- ieee.std_logic_unsigned
-- ieee.std_logic_arith
--
-- Author : John E. Kent
--
--===========================================================================----
--
-- Revision History:
--
-- Date: Revision Author
-- 22 Sep 2002 0.1 John Kent
--
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
 
entity boot_rom is
port (
addr : in std_logic_vector(9 downto 0);
data : out std_logic_vector(7 downto 0)
);
end entity boot_rom;
 
architecture basic of boot_rom is
constant width : integer := 8;
constant memsize : integer := 1024;
 
type rom_array is array(0 to memsize-1) of std_logic_vector(width-1 downto 0);
 
constant rom_data : rom_array :=
(
"11111110",
"10100000",
"00000000",
"01101110",
"00000000",
"10001101",
"01000000",
"01101110",
"00000000",
"00010000",
"00010110",
"00000100",
"10111101",
"11100011",
"00110100",
"10001101",
"01100111",
"10000001",
"01010011",
"00100110",
"11111010",
"10001101",
"01100001",
"10000001",
"00111001",
"00100111",
"00101001",
"10000001",
"00110001",
"00100110",
"11110000",
"01111111",
"10100000",
"00001111",
"10001101",
"00110001",
"10000000",
"00000010",
"10110111",
"10100000",
"01000111",
"10001101",
"00011100",
"10001101",
"00101000",
"01111010",
"10100000",
"01000111",
"00100111",
"00001001",
"10100111",
"00000000",
"10100001",
"00000000",
"00100110",
"00001000",
"00001000",
"00100000",
"11110000",
"01111100",
"10100000",
"00001111",
"00100111",
"11001111",
"10000110",
"00111111",
"10001101",
"00110001",
"01111110",
"11100010",
"11010100",
"10001101",
"00001100",
"10110111",
"10100000",
"00001101",
"10001101",
"00000111",
"10110111",
"10100000",
"00001110",
"11111110",
"10100000",
"00001101",
"00111001",
"10001101",
"01010011",
"01001000",
"01001000",
"01001000",
"01001000",
"00010110",
"10001101",
"01001100",
"00011011",
"00010110",
"11111011",
"10100000",
"00001111",
"11110111",
"10100000",
"00001111",
"00111001",
"01000100",
"01000100",
"01000100",
"01000100",
"10000100",
"00001111",
"10001011",
"00110000",
"10000001",
"00111001",
"00100011",
"00000010",
"10001011",
"00000111",
"01111110",
"11100001",
"11010001",
"01111110",
"11100001",
"10101100",
"10001101",
"11111000",
"00001000",
"10100110",
"00000000",
"10000001",
"00000100",
"00100110",
"11110111",
"00111001",
"01111110",
"11100001",
"01001010",
"10001101",
"10111101",
"11001110",
"11100001",
"10011101",
"10001101",
"11101111",
"11001110",
"10100000",
"00001101",
"10001101",
"00110100",
"11111110",
"10100000",
"00001101",
"10001101",
"00110001",
"10001101",
"00110001",
"10001101",
"11011011",
"10000001",
"00100000",
"00100111",
"11111010",
"10000001",
"00001101",
"00100111",
"11100000",
"10000001",
"01011110",
"00100000",
"00101100",
"00000001",
"10001101",
"11001100",
"10000000",
"00110000",
"00101011",
"01001100",
"10000001",
"00001001",
"00101111",
"00001010",
"10000001",
"00010001",
"00101011",
"01000100",
"10000001",
"00010110",
"00101110",
"01000000",
"10000000",
"00000111",
"00111001",
"10100110",
"00000000",
"10001101",
"10100100",
"10100110",
"00000000",
"00001000",
"00100000",
"10100011",
"10001101",
"11110101",
"10001101",
"11110011",
"10000110",
"00100000",
"00100000",
"10100101",
"10001110",
"10100000",
"01000010",
"00100000",
"00101100",
"00100110",
"00000111",
"00001001",
"00001001",
"11111111",
"10100000",
"00001101",
"00100000",
"10101100",
"11111111",
"10100000",
"00001101",
"00100000",
"00000010",
"00100000",
"01101101",
"10000001",
"00110000",
"00100101",
"10100001",
"10000001",
"01000110",
"00100010",
"10011101",
"10001101",
"10111101",
"10111101",
"11100000",
"01010111",
"00001001",
"10100111",
"00000000",
"10100001",
"00000000",
"00100111",
"10010001",
"01111110",
"11100000",
"01000000",
"10111110",
"10100000",
"00001000",
"00100000",
"01001001",
"10111111",
"10100000",
"00001000",
"10000110",
"11111111",
"10111101",
"11100011",
"00001000",
"11001110",
"10000000",
"00000100",
"10111101",
"11100010",
"10000100",
"10100110",
"00000000",
"10100001",
"00000010",
"00100000",
"00000010",
"00100000",
"00011001",
"00100110",
"00111001",
"10000110",
"00000011",
"10100111",
"00000000",
"10000110",
"00010001",
"10100111",
"00000000",
"00100000",
"00101111",
"00000001",
"10111111",
"10100000",
"00001000",
"00110000",
"01101101",
"00000110",
"00100110",
"00000010",
"01101010",
"00000101",
"01101010",
"00000110",
"11001110",
"11100001",
"10011101",
"10111101",
"11100000",
"01111110",
"11111110",
"10100000",
"00001000",
"00001000",
"10001101",
"10001110",
"10001101",
"10001100",
"10001101",
"10001010",
"10001101",
"10000110",
"10001101",
"10000100",
"11001110",
"10100000",
"00001000",
"10111101",
"11100000",
"11001000",
"11111110",
"10100000",
"00010010",
"10001100",
"11100001",
"00100011",
"00100111",
"00011001",
"10001110",
"10100000",
"01000010",
"11001110",
"10000000",
"00000100",
"11111111",
"10100000",
"00001010",
"01111111",
"10100000",
"00001100",
"10001101",
"01110011",
"00100111",
"00000011",
"10111101",
"11100010",
"01111101",
"10111101",
"11100011",
"01010011",
"10111101",
"11100011",
"01000111",
"11001110",
"11100001",
"10011100",
"10111101",
"11100000",
"01111110",
"10001101",
"00111001",
"11001110",
"11100011",
"11010001",
"10100001",
"00000000",
"00100110",
"00000111",
"10111101",
"11100000",
"11001100",
"11101110",
"00000001",
"01101110",
"00000000",
"00001000",
"00001000",
"00001000",
"10001100",
"11100011",
"11111000",
"00100110",
"11101101",
"00100000",
"10111111",
"11111110",
"10100000",
"00010010",
"01101110",
"00000000",
"01010011",
"00111001",
"00000100",
"00001101",
"00001010",
"00010101",
"00000000",
"00000000",
"00000000",
"01010011",
"00110001",
"00000100",
"00010011",
"00001101",
"00001010",
"00010101",
"00000000",
"00000000",
"00000000",
"00100100",
"00000100",
"00100000",
"01001100",
"11111110",
"10100000",
"00000110",
"01101110",
"00000000",
"00100000",
"01000000",
"10111101",
"11100000",
"01000111",
"11111111",
"10100000",
"00000100",
"10111101",
"11100000",
"01000111",
"10111101",
"11100000",
"01010101",
"00010110",
"10100110",
"00000000",
"11111111",
"10100000",
"00001101",
"00010001",
"00100111",
"00000010",
"00100000",
"00100001",
"11001110",
"11100001",
"10011101",
"10111101",
"11100000",
"01111110",
"11001110",
"10100000",
"00001101",
"00100000",
"00010000",
"00111011",
"00100000",
"00111010",
"11111111",
"10100000",
"00010000",
"11111110",
"10100000",
"00001010",
"00110111",
"11100110",
"00000001",
"11100001",
"00000011",
"00110011",
"00111001",
"10111101",
"11100000",
"11001000",
"11111110",
"10100000",
"00001101",
"10111100",
"10100000",
"00000100",
"00100111",
"10011110",
"00001000",
"00100000",
"11001101",
"10001101",
"00000110",
"10000100",
"01111111",
"00111001",
"00110001",
"00110001",
"00110001",
"00110111",
"10001101",
"11011010",
"00100110",
"00101000",
"10000110",
"00010101",
"10100111",
"00000000",
"10100110",
"00000000",
"01000111",
"00100100",
"11111011",
"10100110",
"00000001",
"11110110",
"10100000",
"00001100",
"00100111",
"00000111",
"00100000",
"00010001",
"00110111",
"10001101",
"11000011",
"00100110",
"00101110",
"11000110",
"00010001",
"11100111",
"00000000",
"11100110",
"00000000",
"01010111",
"01010111",
"00100100",
"11111010",
"10100111",
"00000001",
"00110011",
"11111110",
"10100000",
"00010000",
"00111001",
"10100110",
"00000000",
"00101011",
"11111100",
"10001101",
"00111010",
"11000110",
"00000100",
"11100111",
"00000010",
"01011000",
"10001101",
"00101010",
"00001101",
"01101001",
"00000000",
"01000110",
"01011010",
"00100110",
"11110111",
"10001101",
"00100001",
"11110110",
"10100000",
"00001100",
"00100111",
"00010011",
"00100000",
"11011110",
"10001101",
"00100011",
"11000110",
"00001010",
"01101010",
"00000000",
"10001101",
"00010110",
"10001101",
"00010000",
"10100111",
"00000000",
"00001101",
"01000110",
"01011010",
"00100110",
"11110111",
"11100110",
"00000010",
"01011000",
"00101010",
"11001000",
"10001101",
"00000010",
"00100000",
"11000100",
"01101101",
"00000010",
"00101010",
"11111100",
"01101100",
"00000010",
"01101010",
"00000010",
"00111001",
"01101111",
"00000010",
"10001101",
"11110111",
"00100000",
"11110001",
"10001101",
"10000011",
"00010110",
"01111111",
"10100000",
"00001011",
"11111110",
"10100000",
"00001010",
"10001101",
"00010000",
"10001101",
"00000111",
"11001110",
"11100011",
"11101111",
"00010111",
"01111110",
"11100001",
"01110110",
"10000110",
"00110100",
"10100111",
"00000011",
"10100111",
"00000010",
"00111001",
"01101100",
"00000000",
"10000110",
"00000111",
"10100111",
"00000001",
"01101100",
"00000000",
"10100111",
"00000010",
"00111001",
"01111111",
"10000000",
"00010100",
"10001101",
"00101110",
"11000110",
"00001011",
"10001101",
"00100101",
"11100110",
"00000100",
"11000101",
"00000001",
"00100110",
"11111010",
"01101111",
"00000110",
"10001101",
"00011101",
"11000110",
"10011100",
"10001101",
"00010111",
"11001110",
"00100100",
"00000000",
"11000101",
"00000010",
"00100111",
"00000110",
"10110110",
"10000000",
"00011011",
"10100111",
"00000000",
"00001000",
"11110110",
"10000000",
"00011000",
"11000101",
"00000001",
"00100110",
"11101111",
"01111110",
"00100100",
"00000000",
"11100111",
"00000100",
"10001101",
"00000000",
"00111001",
"11001110",
"11111111",
"11111111",
"00001001",
"10001100",
"10000000",
"00010100",
"00100110",
"11111010",
"00111001",
"11001110",
"11100000",
"00001001",
"10111101",
"11100000",
"01111110",
"10001101",
"11110001",
"10111101",
"11100011",
"01000111",
"00100000",
"01011000",
"11001110",
"11100001",
"00100011",
"10111100",
"10100000",
"00010010",
"00100111",
"00011010",
"00001000",
"10001101",
"00110010",
"10111101",
"11100000",
"01000111",
"11111111",
"10100000",
"00010100",
"10100110",
"00000000",
"10110111",
"10100000",
"00010110",
"10000110",
"00111111",
"10100111",
"00000000",
"11001110",
"11100001",
"00100011",
"10001101",
"00011110",
"01111110",
"11100001",
"01101011",
"11111110",
"10100000",
"00010100",
"10110110",
"10100000",
"00010110",
"10100111",
"00000000",
"11001110",
"11100001",
"00100100",
"00100000",
"11011010",
"10110111",
"10100000",
"01000011",
"11111110",
"10100000",
"00010010",
"10001100",
"11100001",
"00100011",
"00100111",
"00000110",
"11001110",
"11100001",
"00100100",
"11111111",
"10100000",
"00010010",
"00111001",
"10001101",
"01011010",
"00100000",
"00001111",
"11001110",
"10100000",
"01001001",
"11111111",
"10100000",
"00000100",
"00001001",
"10001101",
"01010010",
"11001110",
"11100001",
"10010000",
"10111101",
"11100000",
"01111110",
"10001101",
"00100100",
"10001101",
"10010001",
"01111110",
"11100001",
"01010010",
"01110011",
"10100000",
"00001100",
"10000110",
"00010001",
"11000110",
"00100000",
"10001101",
"00011010",
"10111101",
"11100001",
"11011001",
"00100111",
"00000100",
"10000110",
"00111100",
"10100111",
"00000011",
"00111001",
"10000110",
"00010011",
"11000110",
"00010000",
"00100000",
"00001010",
"10000110",
"00010010",
"11000110",
"00000100",
"00100000",
"00000100",
"10000110",
"00010100",
"11000110",
"00001000",
"10111101",
"11100000",
"01110101",
"10111101",
"11100001",
"11010110",
"00100111",
"00010110",
"10000110",
"00000010",
"11001010",
"00000001",
"10001101",
"00001100",
"10001101",
"00001000",
"10000110",
"00000010",
"11000110",
"00000001",
"11100111",
"00000000",
"10001101",
"00000010",
"10000110",
"00000110",
"10100111",
"00000001",
"11100111",
"00000000",
"00111001",
"11111110",
"10100000",
"00000010",
"11111111",
"10100000",
"01000100",
"10001101",
"11001111",
"10110110",
"10100000",
"00000101",
"10110000",
"10100000",
"01000101",
"11110110",
"10100000",
"00000100",
"11110010",
"10100000",
"01000100",
"00100110",
"00000100",
"10000001",
"00010000",
"00100101",
"00000010",
"10000110",
"00001111",
"10001011",
"00000100",
"10110111",
"10100000",
"01000111",
"10000000",
"00000011",
"10110111",
"10100000",
"01000110",
"11001110",
"11100001",
"10010011",
"10111101",
"11100000",
"01111110",
"01011111",
"11001110",
"10100000",
"01000111",
"10001101",
"00100100",
"11001110",
"10100000",
"01000100",
"10001101",
"00011111",
"10001101",
"00011101",
"11111110",
"10100000",
"01000100",
"10001101",
"00011000",
"01111010",
"10100000",
"01000110",
"00100110",
"11111001",
"11111111",
"10100000",
"01000100",
"01010011",
"00110111",
"00110000",
"10001101",
"00001011",
"00110011",
"11111110",
"10100000",
"01000100",
"00001001",
"10111100",
"10100000",
"00000100",
"00100110",
"10110011",
"00111001",
"11101011",
"00000000",
"01111110",
"11100000",
"10111111",
"01000111",
"11100001",
"11010000",
"01011010",
"11000000",
"00000000",
"01001101",
"11100000",
"10001000",
"01000110",
"11100001",
"10101110",
"01010010",
"11100001",
"00110000",
"01001010",
"11100000",
"00000101",
"01000011",
"11100010",
"11001100",
"01000100",
"11100010",
"10001111",
"01000010",
"11100010",
"11011001",
"01001111",
"11100010",
"01101001",
"01010000",
"11100011",
"00011010",
"01001100",
"11100000",
"00001100",
"01000101",
"11100011",
"00011110",
"11100000",
"00000000",
"11100001",
"10001011",
"11100001",
"10100111",
"11100000",
"11010000"
);
begin
data <= rom_data(conv_integer(addr));
end architecture basic;
 
/tags/arelease/vhdl/ioport.vhd
0,0 → 1,321
--===========================================================================--
--
-- S Y N T H E Z I A B L E I/O Port C O R E
--
-- www.OpenCores.Org - December 2002
-- This core adheres to the GNU public license
--
-- File name : ioport.vhd
--
-- Purpose : Implements 4 x 8 bit parallel I/O ports
-- with programmable data direction registers
--
-- Dependencies : ieee.Std_Logic_1164
-- ieee.std_logic_unsigned
--
-- Author : John E. Kent
--
--===========================================================================----
--
-- Revision History:
--
-- Date: Revision Author
-- 6 Sep 2002 0.0 John Kent
-- Initial version
--
-- 11 Oct 2002 0.1 John Kent
-- used a loop counter for data direction & read port signals
--
--
--===========================================================================----
--
-- Memory Map
--
-- IO + $00 - Port A Data register
-- IO + $01 - Port B Data register
-- IO + $02 - Port C Data register
-- IO + $03 - Port D Data register
-- IO + $04 - Port A Data Direction Register
-- IO + $05 - Port B Data Direction Register
-- IO + $06 - Port C Data Direction Register
-- IO + $07 - Port D Data Direction Register
--
 
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
 
entity ioport is
port (
clk : in std_logic;
rst : in std_logic;
cs : in std_logic;
rw : in std_logic;
addr : in std_logic_vector(2 downto 0);
data_in : in std_logic_vector(7 downto 0);
data_out : out std_logic_vector(7 downto 0);
porta_io : inout std_logic_vector(7 downto 0);
portb_io : inout std_logic_vector(7 downto 0);
portc_io : inout std_logic_vector(7 downto 0);
portd_io : inout std_logic_vector(7 downto 0) );
end;
 
architecture ioport_arch of ioport is
signal porta_ddr : std_logic_vector(7 downto 0);
signal portb_ddr : std_logic_vector(7 downto 0);
signal portc_ddr : std_logic_vector(7 downto 0);
signal portd_ddr : std_logic_vector(7 downto 0);
signal porta_data : std_logic_vector(7 downto 0);
signal portb_data : std_logic_vector(7 downto 0);
signal portc_data : std_logic_vector(7 downto 0);
signal portd_data : std_logic_vector(7 downto 0);
 
begin
 
 
--------------------------------
--
-- read I/O port
--
--------------------------------
 
ioport_read : process( addr,
porta_ddr, portb_ddr, portc_ddr, portd_ddr,
porta_data, portb_data, portc_data, portd_data,
porta_io, portb_io, portc_io, portd_io )
variable count : integer;
begin
case addr is
when "000" =>
for count in 0 to 7 loop
if porta_ddr(count) = '1' then
data_out(count) <= porta_data(count);
else
data_out(count) <= porta_io(count);
end if;
end loop;
 
when "001" =>
for count in 0 to 7 loop
if portb_ddr(count) = '1' then
data_out(count) <= portb_data(count);
else
data_out(count) <= portb_io(count);
end if;
end loop;
 
when "010" =>
for count in 0 to 7 loop
if portc_ddr(count) = '1' then
data_out(count) <= portc_data(count);
else
data_out(count) <= portc_io(count);
end if;
end loop;
 
when "011" =>
for count in 0 to 7 loop
if portd_ddr(count) = '1' then
data_out(count) <= portd_data(count);
else
data_out(count) <= portd_io(count);
end if;
end loop;
 
when "100" =>
data_out <= porta_ddr;
when "101" =>
data_out <= portb_ddr;
when "110" =>
data_out <= portc_ddr;
when "111" =>
data_out <= portd_ddr;
when others =>
data_out <= "00000000";
end case;
end process;
 
---------------------------------
--
-- Write I/O ports
--
---------------------------------
 
ioport_write : process( clk, rst, addr, cs, rw, data_in,
porta_data, portb_data, portc_data, portd_data,
porta_ddr, portb_ddr, portc_ddr, portd_ddr )
begin
if clk'event and clk = '1' then
if rst = '1' then
porta_data <= "00000000";
portb_data <= "00000000";
portc_data <= "00000000";
portd_data <= "00000000";
porta_ddr <= "00000000";
portb_ddr <= "00000000";
portc_ddr <= "00000000";
portd_ddr <= "00000000";
elsif cs = '1' and rw = '0' then
case addr is
when "000" =>
porta_data <= data_in;
portb_data <= portb_data;
portc_data <= portc_data;
portd_data <= portd_data;
porta_ddr <= porta_ddr;
portb_ddr <= portb_ddr;
portc_ddr <= portc_ddr;
portd_ddr <= portd_ddr;
when "001" =>
porta_data <= porta_data;
portb_data <= data_in;
portc_data <= portc_data;
portd_data <= portd_data;
porta_ddr <= porta_ddr;
portb_ddr <= portb_ddr;
portc_ddr <= portc_ddr;
portd_ddr <= portd_ddr;
when "010" =>
porta_data <= porta_data;
portb_data <= portb_data;
portc_data <= data_in;
portd_data <= portd_data;
porta_ddr <= porta_ddr;
portb_ddr <= portb_ddr;
portc_ddr <= portc_ddr;
portd_ddr <= portd_ddr;
when "011" =>
porta_data <= porta_data;
portb_data <= portb_data;
portc_data <= portc_data;
portd_data <= data_in;
porta_ddr <= porta_ddr;
portb_ddr <= portb_ddr;
portc_ddr <= portc_ddr;
portd_ddr <= portd_ddr;
when "100" =>
porta_data <= porta_data;
portb_data <= portb_data;
portc_data <= portc_data;
portd_data <= portd_data;
porta_ddr <= data_in;
portb_ddr <= portb_ddr;
portc_ddr <= portc_ddr;
portd_ddr <= portd_ddr;
when "101" =>
porta_data <= porta_data;
portb_data <= portb_data;
portc_data <= portc_data;
portd_data <= portd_data;
porta_ddr <= porta_ddr;
portb_ddr <= data_in;
portc_ddr <= portc_ddr;
portd_ddr <= portd_ddr;
when "110" =>
porta_data <= porta_data;
portb_data <= portb_data;
portc_data <= portc_data;
portd_data <= portd_data;
porta_ddr <= porta_ddr;
portb_ddr <= portb_ddr;
portc_ddr <= data_in;
portd_ddr <= portd_ddr;
when "111" =>
porta_data <= porta_data;
portb_data <= portb_data;
portc_data <= portc_data;
portd_data <= portd_data;
porta_ddr <= porta_ddr;
portb_ddr <= portb_ddr;
portc_ddr <= portc_ddr;
portd_ddr <= data_in;
when others =>
porta_data <= porta_data;
portb_data <= portb_data;
portc_data <= portc_data;
portd_data <= portd_data;
porta_ddr <= porta_ddr;
portb_ddr <= portb_ddr;
portc_ddr <= portc_ddr;
portd_ddr <= portd_ddr;
end case;
else
porta_data <= porta_data;
portb_data <= portb_data;
portc_data <= portc_data;
portd_data <= portd_data;
porta_ddr <= porta_ddr;
portb_ddr <= portb_ddr;
portc_ddr <= portc_ddr;
portd_ddr <= portd_ddr;
end if;
end if;
end process;
 
---------------------------------
--
-- direction control port a
--
---------------------------------
porta_direction : process ( porta_data, porta_ddr )
variable count : integer;
begin
for count in 0 to 7 loop
if porta_ddr(count) = '1' then
porta_io(count) <= porta_data(count);
else
porta_io(count) <= 'Z';
end if;
end loop;
end process;
---------------------------------
--
-- direction control port b
--
---------------------------------
portb_direction : process ( portb_data, portb_ddr )
variable count : integer;
begin
for count in 0 to 7 loop
if portb_ddr(count) = '1' then
portb_io(count) <= portb_data(count);
else
portb_io(count) <= 'Z';
end if;
end loop;
end process;
---------------------------------
--
-- direction control port a
--
---------------------------------
portc_direction : process ( portc_data, portc_ddr )
variable count : integer;
begin
for count in 0 to 7 loop
if portc_ddr(count) = '1' then
portc_io(count) <= portc_data(count);
else
portc_io(count) <= 'Z';
end if;
end loop;
end process;
---------------------------------
--
-- direction control port d
--
---------------------------------
portd_direction : process ( portd_data, portd_ddr)
variable count : integer;
begin
for count in 0 to 7 loop
if portd_ddr(count) = '1' then
portd_io(count) <= portd_data(count);
else
portd_io(count) <= 'Z';
end if;
end loop;
end process;
 
end ioport_arch;
/tags/arelease/vhdl/timer.vhd
0,0 → 1,255
--===========================================================================--
--
-- S Y N T H E Z I A B L E Timer C O R E
--
-- www.OpenCores.Org - December 2002
-- This core adheres to the GNU public license
--
-- File name : timer.vhd
--
-- entity name : timer
--
-- Purpose : Implements a 8 bit timer module
--
-- Dependencies : ieee.Std_Logic_1164
-- ieee.std_logic_unsigned
--
-- Author : John E. Kent
--
--===========================================================================----
--
-- Revision History:
--
-- Date: Revision Author
-- ?? Sep 2002 0.1 John Kent
-- Initial version ( 3 timers )
--
-- 6 Sep 2002 1.0 John Kent
-- converted to a single timer
-- made syncronous with system clock
--
--===========================================================================----
--
-- Register Memory Map
--
-- addr=0 read down count
-- addr=0 write preset count
-- addr=1 read status
-- addr=1 write control
--
-- Control register
-- b0 = counter enable
-- b1 = mode (0 = counter, 1 = timer)
-- b7 = interrupt enable
--
-- Status register
-- b6 = timer output
-- b7 = interrupt flag
--
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
 
entity timer is
port (
clk : in std_logic;
rst : in std_logic;
cs : in std_logic;
rw : in std_logic;
addr : in std_logic;
data_in : in std_logic_vector(7 downto 0);
data_out : out std_logic_vector(7 downto 0);
irq : out std_logic;
timer_in : in std_logic;
timer_out : out std_logic
);
end;
 
architecture timer_arch of timer is
signal timer_ctrl : std_logic_vector(7 downto 0);
signal timer_stat : std_logic_vector(7 downto 0);
signal timer_reg : std_logic_vector(7 downto 0);
signal timer_count : std_logic_vector(7 downto 0);
signal timer_int : std_logic; -- Timer interrupt
signal timer_term : std_logic; -- Timer terminal count
signal timer_tog : std_logic; -- Timer output
--
-- control/status register bits
--
constant T_enab : integer := 0; -- 0=disable, 1=enabled
constant T_mode : integer := 1; -- 0=counter, 1=timer
constant T_out : integer := 6; -- 0=disabled, 1=enabled
constant T_irq : integer := 7; -- 0=disabled, 1-enabled
 
begin
 
--------------------------------
--
-- write control registers
-- doesn't do anything yet
--
--------------------------------
timer_write : process( clk, rst, cs, rw, addr, data_in,
timer_reg, timer_ctrl, timer_count )
begin
if clk'event and clk = '1' then
if rst = '1' then
timer_reg <= "00000000";
timer_ctrl <= "00000000";
elsif cs = '1' and rw = '0' then
if addr='0' then
timer_reg <= data_in;
timer_ctrl <= timer_ctrl;
timer_term <= '0';
else
timer_reg <= timer_reg;
timer_ctrl <= data_in;
timer_term <= timer_term;
end if;
else
timer_ctrl <= timer_ctrl;
timer_reg <= timer_reg;
if (timer_ctrl(T_enab) = '1') then
if (timer_count = "00000000" ) then
timer_term <= '1';
elsif timer_ctrl(T_mode) = '0' then
timer_term <= '0'; -- counter mode, reset on non zero
else
timer_term <= timer_term; -- timer mode, keep as is
end if;
else
timer_term <= timer_term;
end if;
end if;
end if;
end process;
 
--
-- timer data output mux
--
timer_read : process( addr, timer_count, timer_stat )
begin
if addr='0' then
data_out <= timer_count;
else
data_out <= timer_stat;
end if;
end process;
 
--------------------------------
--
-- counters
--
--------------------------------
 
my_counter: process( clk, rst, timer_ctrl, timer_count, timer_in )
variable timer_tmp : std_logic;
begin
if clk'event and clk='1' then
if rst = '1' then
timer_count <= "00000000";
timer_tmp := '0';
else
if timer_ctrl( T_enab ) = '1' then
if timer_in = '0' and timer_tmp = '1' then
timer_tmp := '0';
if timer_count = "00000000" then
timer_count <= timer_reg;
else
timer_count <= timer_count - 1;
end if;
elsif timer_in = '1' and timer_tmp = '0' then
timer_tmp := '1';
timer_count <= timer_count;
else
timer_tmp := timer_tmp;
timer_count <= timer_count;
end if;
else
timer_tmp := timer_tmp;
timer_count <= timer_count;
end if; -- timer_ctrl
end if; -- rst
end if; -- clk
end process;
 
--
-- read timer strobe to reset interrupts
--
timer_interrupt : process( Clk, rst, cs, rw, addr,
timer_term, timer_int, timer_count, timer_ctrl )
begin
if clk'event and clk = '1' then
if rst = '1' then
timer_int <= '0';
elsif cs = '1' and rw = '1' then
if addr = '0' then
timer_int <= '0'; -- reset interrupt on read count
else
timer_int <= timer_int;
end if;
else
if timer_term = '1' then
timer_int <= '1';
else
timer_int <= timer_int;
end if;
end if;
end if;
 
if timer_ctrl( T_irq ) = '1' then
irq <= timer_int;
else
irq <= '0';
end if;
end process;
 
--
-- timer status register
--
timer_status : process( timer_ctrl, timer_int, timer_tog )
begin
timer_stat(5 downto 0) <= timer_ctrl(5 downto 0);
timer_stat(T_out) <= timer_tog;
timer_stat(T_irq) <= timer_int;
end process;
 
--
-- timer output
--
timer_output : process( Clk, rst, timer_term, timer_ctrl, timer_tog )
variable timer_tmp : std_logic; -- tracks change in terminal count
begin
if clk'event and clk='1' then
if rst = '1' then
timer_tog <= '0';
timer_tmp := '0';
elsif timer_ctrl(T_mode) = '0' then -- free running ?
if (timer_term = '1') and (timer_tmp = '0') then
timer_tmp := '1';
timer_tog <= not timer_tog;
elsif (timer_term = '0') and (timer_tmp = '1') then
timer_tmp := '0';
timer_tog <= timer_tog;
else
timer_tmp := timer_tmp;
timer_tog <= timer_tog;
end if;
else -- one shot timer mode, follow terminal count
if (timer_term = '1') and (timer_tmp = '0') then
timer_tmp := '1';
timer_tog <= '1';
elsif (timer_term = '0') and (timer_tmp = '1') then
timer_tmp := '0';
timer_tog <= '0';
else
timer_tmp := timer_tmp;
timer_tog <= timer_tog;
end if;
end if;
end if;
timer_out <= timer_tog and timer_ctrl(T_out);
end process;
 
end timer_arch;
/tags/arelease/vhdl/miniUART.vhd
0,0 → 1,250
--===========================================================================--
--
-- S Y N T H E Z I A B L E miniUART C O R E
--
-- www.OpenCores.Org - January 2000
-- This core adheres to the GNU public license
--
-- Design units : miniUART core for the OCRP-1
--
-- File name : miniuart.vhd
--
-- Purpose : Implements an miniUART device for communication purposes
-- between the OR1K processor and the Host computer through
-- an RS-232 communication protocol.
--
-- Library : uart_lib.vhd
--
-- Dependencies : IEEE.Std_Logic_1164
--
-- Simulator : ModelSim PE/PLUS version 4.7b on a Windows95 PC
--===========================================================================--
-------------------------------------------------------------------------------
-- Revision list
-- Version Author Date Changes
--
-- 0.1 Ovidiu Lupas 15 January 2000 New model
-- 1.0 Ovidiu Lupas January 2000 Synthesis optimizations
-- 2.0 Ovidiu Lupas April 2000 Bugs removed - RSBusCtrl
-- the RSBusCtrl did not process all possible situations
--
-- olupas@opencores.org
--
-- 3.0 John Kent October 2002 Changed Status bits to match mc6805
-- Added CTS, RTS, Baud rate control & Software Reset
-------------------------------------------------------------------------------
-- Entity for miniUART Unit - 9600 baudrate --
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
 
entity miniUART is
port (
SysClk : in Std_Logic; -- System Clock
rst : in Std_Logic; -- Reset input (active high)
cs : in Std_Logic;
rw : in Std_Logic;
RxD : in Std_Logic;
TxD : out Std_Logic;
CTS_n : in Std_Logic;
RTS_n : out Std_Logic;
Irq : out Std_Logic; -- interrupt
Addr : in Std_Logic; -- Register Select
DataIn : in Std_Logic_Vector(7 downto 0); --
DataOut : out Std_Logic_Vector(7 downto 0)); --
end entity; --================== End of entity ==============================--
-------------------------------------------------------------------------------
-- Architecture for miniUART Controller Unit
-------------------------------------------------------------------------------
architecture uart of miniUART is
-----------------------------------------------------------------------------
-- Signals
-----------------------------------------------------------------------------
signal RxData : Std_Logic_Vector(7 downto 0); --
signal TxData : Std_Logic_Vector(7 downto 0); --
signal StatReg : Std_Logic_Vector(7 downto 0); -- status register
signal CtrlReg : Std_Logic_Vector(7 downto 0); -- control register
-- StatReg detailed
-----------+--------+--------+--------+--------+--------+--------+--------+
-- Int | PErr | ORErr | FErr | CTS | DCD | TBufE | DRdy |
-----------+--------+--------+--------+--------+--------+--------+--------+
signal EnabRx : Std_Logic; -- Enable RX unit
signal EnabTx : Std_Logic; -- Enable TX unit
signal DRdy : Std_Logic; -- Receive Data ready
signal TBufE : Std_Logic; -- Transmit buffer empty
signal FErr : Std_Logic; -- Frame error
signal OErr : Std_Logic; -- Output error
signal Read : Std_Logic; -- Read receive buffer
signal Load : Std_Logic; -- Load transmit buffer
signal Int : Std_Logic; -- Interrupt bit
signal Reset : Std_Logic; -- Reset (Software & Hardware)
-----------------------------------------------------------------------------
-- Baud rate Generator
-----------------------------------------------------------------------------
component ClkUnit is
port (
Clk : in Std_Logic; -- System Clock
Reset : in Std_Logic; -- Reset input
EnableRX : out Std_Logic; -- Control signal
EnableTX : out Std_Logic; -- Control signal
BaudRate : in Std_Logic_Vector(1 downto 0));
end component;
-----------------------------------------------------------------------------
-- Receive Unit
-----------------------------------------------------------------------------
component RxUnit is
port (
Clk : in Std_Logic; -- Clock signal
Reset : in Std_Logic; -- Reset input
Enable : in Std_Logic; -- Enable input
RxD : in Std_Logic; -- RS-232 data input
ReadD : in Std_Logic; -- Read data signal
FRErr : out Std_Logic; -- Status signal
ORErr : out Std_Logic; -- Status signal
DARdy : out Std_Logic; -- Status signal
DataI : out Std_Logic_Vector(7 downto 0));
end component;
-----------------------------------------------------------------------------
-- Transmitter Unit
-----------------------------------------------------------------------------
component TxUnit is
port (
Clk : in Std_Logic; -- Clock signal
Reset : in Std_Logic; -- Reset input
Enable : in Std_Logic; -- Enable input
LoadD : in Std_Logic; -- Load transmit data
TxD : out Std_Logic; -- RS-232 data output
TBE : out Std_Logic; -- Tx buffer empty
DataO : in Std_Logic_Vector(7 downto 0));
end component;
begin
-----------------------------------------------------------------------------
-- Instantiation of internal components
-----------------------------------------------------------------------------
 
ClkDiv : ClkUnit port map (
Clk => SysClk,
EnableRx => EnabRX,
EnableTx => EnabTX,
BaudRate => CtrlReg(1 downto 0),
Reset => Reset);
TxDev : TxUnit port map (
Clk => SysClk,
Reset => Reset,
Enable => EnabTX,
LoadD => Load,
TxD => TxD,
TBE => TBufE,
DataO => TxData);
 
RxDev : RxUnit port map (
Clk => SysClk,
Reset => Reset,
Enable => EnabRX,
RxD => RxD,
ReadD => Read,
FRErr => FErr,
ORErr => OErr,
DARdy => DRdy,
DataI => RxData);
 
-----------------------------------------------------------------------------
-- Implements the controller for Rx&Tx units
-----------------------------------------------------------------------------
RSBusCtrl : process(SysClk, Reset, DRdy, TBufE, FErr, OErr, Int, CtrlReg)
variable StatM : Std_Logic_Vector(7 downto 0);
begin
if SysClk'event and SysClk='0' then
if Reset = '1' then
StatM := "00000000";
Int <= '0';
else
StatM(0) := DRdy;
StatM(1) := TBufE;
StatM(2) := '0'; -- DCD
StatM(3) := CTS_n;
StatM(4) := FErr;
StatM(5) := OErr;
StatM(6) := '0'; -- Parrity error
StatM(7) := Int;
Int <= (CtrlReg(7) and DRdy) or
((not CtrlReg(6)) and CtrlReg(5) and TBufE);
end if;
 
RTS_n <= CtrlReg(6) and not CtrlReg(5);
Irq <= Int;
StatReg <= StatM;
end if;
end process;
 
-----------------------------------------------------------------------------
-- Combinational section
-----------------------------------------------------------------------------
 
control_strobe: process(SysClk, Reset, cs, rw, Addr, DataIn, CtrlReg )
begin
if SysClk'event and SysClk='1' then
if (reset = '1') then
CtrlReg <= "00000000";
Load <= '0';
Read <= '0';
else
if cs = '1' then
if Addr = '1' then
CtrlReg <= CtrlReg;
if rw = '0' then -- write data register
Load <= '1';
Read <= '0';
else -- read Data Register
Load <= '0';
Read <= '1';
end if; -- rw
else -- read Status Register
Load <= '0';
Read <= '0';
if rw = '0' then -- write data register
CtrlReg <= DataIn;
else -- read Data Register
CtrlReg <= CtrlReg;
end if; -- rw
end if; -- Addr
else -- not selected
Load <= '0';
Read <= '0';
CtrlReg <= CtrlReg;
end if; -- cs
end if; -- reset
end if; -- SysClk
end process;
 
---------------------------------------------------------------
--
-- set data output mux
--
--------------------------------------------------------------
 
data_port: process(Addr, StatReg, RxData, DataIn )
begin
TxData <= DataIn;
if Addr = '1' then
DataOut <= RxData; -- read data register
else
DataOut <= StatReg; -- read status register
end if; -- Addr
end process;
 
---------------------------------------------------------------
--
-- reset may be hardware or software
--
---------------------------------------------------------------
 
uart_reset: process(CtrlReg, rst )
begin
Reset <= (CtrlReg(1) and CtrlReg(0)) or rst;
end process;
 
end uart; --===================== End of architecture =======================--
 
/tags/arelease/vhdl/rxunit.vhd
0,0 → 1,149
--===========================================================================--
--
-- S Y N T H E Z I A B L E miniUART C O R E
--
-- www.OpenCores.Org - January 2000
-- This core adheres to the GNU public license
--
-- Design units : miniUART core for the OCRP-1
--
-- File name : RxUnit.vhd
--
-- Purpose : Implements an miniUART device for communication purposes
-- between the OR1K processor and the Host computer through
-- an RS-232 communication protocol.
--
-- Library : uart_lib.vhd
--
-- Dependencies : IEEE.Std_Logic_1164
--
--===========================================================================--
-------------------------------------------------------------------------------
-- Revision list
-- Version Author Date Changes
--
-- 0.1 Ovidiu Lupas 15 January 2000 New model
-- 2.0 Ovidiu Lupas 17 April 2000 samples counter cleared for bit 0
-- olupas@opencores.org
-------------------------------------------------------------------------------
-- Description : Implements the receive unit of the miniUART core. Samples
-- 16 times the RxD line and retain the value in the middle of
-- the time interval.
-------------------------------------------------------------------------------
-- Entity for Receive Unit - 9600 baudrate --
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
 
-------------------------------------------------------------------------------
-- Receive unit
-------------------------------------------------------------------------------
entity RxUnit is
port (
Clk : in Std_Logic; -- system clock signal
Reset : in Std_Logic; -- Reset input
Enable : in Std_Logic; -- Enable input
RxD : in Std_Logic; -- RS-232 data input
ReadD : in Std_Logic; -- Read data signal
FRErr : out Std_Logic; -- Status signal
ORErr : out Std_Logic; -- Status signal
DARdy : out Std_Logic; -- Status signal
DataI : out Std_Logic_Vector(7 downto 0));
end entity; --================== End of entity ==============================--
-------------------------------------------------------------------------------
-- Architecture for receive Unit
-------------------------------------------------------------------------------
architecture Behaviour of RxUnit is
-----------------------------------------------------------------------------
-- Signals
-----------------------------------------------------------------------------
signal Start : Std_Logic; -- Syncro signal
signal tmpRxD : Std_Logic; -- RxD buffer
signal tmpDRdy : Std_Logic; -- Data ready buffer
signal outErr : Std_Logic; --
signal frameErr : Std_Logic; --
signal BitCnt : Unsigned(3 downto 0); --
signal SampleCnt : Unsigned(3 downto 0); -- samples on one bit counter
signal ShtReg : Std_Logic_Vector(7 downto 0); --
signal DOut : Std_Logic_Vector(7 downto 0); --
 
begin
---------------------------------------------------------------------
-- Receiver process
---------------------------------------------------------------------
RcvProc : process(Clk,Reset,Enable,RxD)
constant CntOne : Unsigned(3 downto 0):="0001";
begin
if Clk'event and Clk='1' then
if Reset = '1' then
BitCnt <= "0000";
SampleCnt <= "0000";
Start <= '0';
tmpDRdy <= '0';
frameErr <= '0';
outErr <= '0';
 
ShtReg <= "00000000"; --
DOut <= "00000000"; --
else
if ReadD = '1' then
tmpDRdy <= '0'; -- Data was read
end if;
 
if Enable = '1' then
if Start = '0' then
if RxD = '0' then -- Start bit,
SampleCnt <= SampleCnt + CntOne;
Start <= '1';
end if;
else
if SampleCnt = "1000" then -- reads the RxD line
tmpRxD <= RxD;
SampleCnt <= SampleCnt + CntOne;
elsif SampleCnt = "1111" then
case BitCnt is
when "0000" =>
if tmpRxD = '1' then -- Start Bit
Start <= '0';
else
BitCnt <= BitCnt + CntOne;
end if;
SampleCnt <= SampleCnt + CntOne;
when "1001" =>
if tmpRxD = '0' then -- stop bit expected
frameErr <= '1';
else
frameErr <= '0';
end if;
 
if tmpDRdy = '1' then --
outErr <= '1';
else
outErr <= '0';
end if;
 
tmpDRdy <= '1';
DOut <= ShtReg;
BitCnt <= "0000";
Start <= '0';
when others =>
BitCnt <= BitCnt + CntOne;
SampleCnt <= SampleCnt + CntOne;
ShtReg <= tmpRxD & ShtReg(7 downto 1);
end case;
else
SampleCnt <= SampleCnt + CntOne;
end if;
end if;
end if;
end if;
end if;
end process;
 
DARdy <= tmpDRdy;
DataI <= DOut;
FRErr <= frameErr;
ORErr <= outErr;
 
end Behaviour; --==================== End of architecture ====================--
/tags/arelease/vhdl/uart_def.vhd
0,0 → 1,62
--===========================================================================--
--
-- S Y N T H E Z I A B L E miniUART C O R E
--
-- www.OpenCores.Org - January 2000
-- This core adheres to the GNU public license
--
-- Design units : UART_Def
--
-- File name : uart_lib.vhd
--
-- Purpose : Implements an miniUART device for communication purposes
-- between the OR1K processor and the Host computer through
-- an RS-232 communication protocol.
--
-- Library : uart_lib.vhd
--
-- Dependencies : IEEE.Std_Logic_1164
--
--===========================================================================--
-------------------------------------------------------------------------------
-- Revision list
-- Version Author Date Changes
--
-- 0.1 Ovidiu Lupas 15 January 2000 New model
-- olupas@opencores.org
-------------------------------------------------------------------------------
--------------------------------------------------------------------------------
-- package UART_Def
--------------------------------------------------------------------------------
library IEEE;
use IEEE.Std_Logic_1164.all;
use IEEE.Numeric_Std.all;
--**--
package UART_Def is
-----------------------------------------------------------------------------
-- Converts unsigned Std_LOGIC_Vector to Integer, leftmost bit is MSB
-- Error message for unknowns (U, X, W, Z, -), converted to 0
-- Verifies whether vector is too long (> 16 bits)
-----------------------------------------------------------------------------
function ToInteger (
Invector : in Unsigned(3 downto 0))
return Integer;
end UART_Def; --==================== End of package header ======================--
package body UART_Def is
function ToInteger (
InVector : in Unsigned(3 downto 0))
return Integer is
variable Result : Integer := 0;
constant HeaderMsg : String := "To_Integer:";
constant MsgSeverity : Severity_Level := Warning;
begin
for i in 0 to 3 loop
if (InVector(i) = '1') then
Result := Result + (2**I);
end if;
end loop;
return Result;
end ToInteger;
end UART_Def; --================ End of package body ================--
 
 
/tags/arelease/vhdl/txunit.vhd
0,0 → 1,112
--===========================================================================--
--
-- S Y N T H E Z I A B L E miniUART C O R E
--
-- www.OpenCores.Org - January 2000
-- This core adheres to the GNU public license
--
-- Design units : miniUART core for the OCRP-1
--
-- File name : TxUnit.vhd
--
-- Purpose : Implements an miniUART device for communication purposes
-- between the OR1K processor and the Host computer through
-- an RS-232 communication protocol.
--
-- Library : uart_lib.vhd
--
-- Dependencies : IEEE.Std_Logic_1164
--
--===========================================================================--
-------------------------------------------------------------------------------
-- Revision list
-- Version Author Date Changes
--
-- 0.1 Ovidiu Lupas 15 January 2000 New model
-- 2.0 Ovidiu Lupas 17 April 2000 unnecessary variable removed
-- olupas@opencores.org
-------------------------------------------------------------------------------
-- Description :
-------------------------------------------------------------------------------
-- Entity for the Tx Unit --
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library work;
-- use work.Uart_Def.all;
-------------------------------------------------------------------------------
-- Transmitter unit
-------------------------------------------------------------------------------
entity TxUnit is
port (
Clk : in Std_Logic; -- Clock signal
Reset : in Std_Logic; -- Reset input
Enable : in Std_Logic; -- Enable input
LoadD : in Std_Logic; -- Load transmit data
TxD : out Std_Logic; -- RS-232 data output
TBE : out Std_Logic; -- Tx buffer empty
DataO : in Std_Logic_Vector(7 downto 0));
end entity; --================== End of entity ==============================--
-------------------------------------------------------------------------------
-- Architecture for TxUnit
-------------------------------------------------------------------------------
architecture Behaviour of TxUnit is
-----------------------------------------------------------------------------
-- Signals
-----------------------------------------------------------------------------
signal TBuff : Std_Logic_Vector(7 downto 0); -- transmit buffer
signal TReg : Std_Logic_Vector(7 downto 0); -- transmit register
signal BitCnt : Unsigned(3 downto 0); -- bit counter
signal tmpTRegE : Std_Logic; --
signal tmpTBufE : Std_Logic; --
begin
-----------------------------------------------------------------------------
-- Implements the Tx unit
-----------------------------------------------------------------------------
process(Clk,Reset,Enable,LoadD,DataO,TBuff,TReg,tmpTRegE,tmpTBufE)
constant CntOne : Unsigned(3 downto 0):="0001";
begin
if Clk'event and Clk = '1' then
if Reset = '1' then
tmpTRegE <= '1';
tmpTBufE <= '1';
TxD <= '1';
BitCnt <= "0000";
elsif LoadD = '1' then
TBuff <= DataO;
tmpTBufE <= '0';
elsif Enable = '1' then
if ( tmpTBufE = '0') and (tmpTRegE = '1') then
TReg <= TBuff;
tmpTRegE <= '0';
tmpTBufE <= '1';
end if;
 
if tmpTRegE = '0' then
case BitCnt is
when "0000" =>
TxD <= '0';
BitCnt <= BitCnt + CntOne;
when "0001" | "0010" | "0011" |
"0100" | "0101" | "0110" |
"0111" | "1000" =>
TxD <= TReg(0);
TReg <= '1' & TReg(7 downto 1);
BitCnt <= BitCnt + CntOne;
when "1001" =>
TxD <= '1'; -- 2 stop bits
BitCnt <= BitCnt + CntOne;
when "1010" =>
TxD <= '1';
BitCnt <= "0000";
tmpTRegE <= '1';
when others => null;
end case;
end if;
end if;
end if;
end process;
 
TBE <= tmpTBufE;
end Behaviour; --=================== End of architecture ====================--
/tags/arelease/vhdl/system68.ucf
0,0 → 1,235
#### UCF file created by Project Navigator
# Connector J9
NET "ram_addr<0>" LOC = "p108";
NET "ram_addr<1>" LOC = "p109";
NET "ram_addr<2>" LOC = "p110";
NET "ram_addr<3>" LOC = "p111";
NET "ram_addr<4>" LOC = "p112";
NET "ram_addr<5>" LOC = "p113";
NET "ram_addr<6>" LOC = "p114";
NET "ram_addr<7>" LOC = "p115";
NET "ram_csn" LOC = "p119";
NET "ram_addr<8>" LOC = "p120";
NET "ram_addr<9>" LOC = "p121";
NET "ram_addr<10>" LOC = "p122";
NET "ram_addr<11>" LOC = "p123";
NET "ram_addr<12>" LOC = "p125";
NET "ram_addr<13>" LOC = "p126";
NET "ram_addr<14>" LOC = "p127";
NET "ram_addr<15>" LOC = "p129";
NET "ram_addr<16>" LOC = "p132";
# Connector J6
NET "ram_data<0>" LOC = "p133";
NET "ram_data<1>" LOC = "p134";
NET "ram_data<2>" LOC = "p135";
NET "ram_data<3>" LOC = "p136";
NET "ram_data<4>" LOC = "p138";
NET "ram_data<5>" LOC = "p139";
NET "ram_data<6>" LOC = "p140";
NET "ram_data<7>" LOC = "p141";
NET "ram_data<8>" LOC = "p142";
NET "ram_data<9>" LOC = "p146";
NET "ram_data<10>" LOC = "p147";
NET "ram_data<11>" LOC = "p148";
NET "ram_data<12>" LOC = "p149";
NET "ram_data<13>" LOC = "p150";
NET "ram_data<14>" LOC = "p151";
NET "ram_data<15>" LOC = "p152";
NET "ram_wrun" LOC = "p153";
NET "ram_wrln" LOC = "p154";
# Connector J4
NET "porta<0>" LOC = "p160";
NET "porta<1>" LOC = "p161";
NET "porta<2>" LOC = "p162";
NET "porta<3>" LOC = "p163";
NET "porta<4>" LOC = "p164";
NET "porta<5>" LOC = "p165";
NET "porta<6>" LOC = "p166";
NET "porta<7>" LOC = "p167";
NET "portb<0>" LOC = "p168";
NET "portb<1>" LOC = "p172";
NET "portb<2>" LOC = "p173";
NET "portb<3>" LOC = "p174";
NET "portb<4>" LOC = "p175";
NET "portb<5>" LOC = "p176";
NET "portb<6>" LOC = "p178";
NET "portb<7>" LOC = "p179";
#NET "timer0_out" LOC = "p180";
#NET "timer0_in" LOC = "p182";
NET "timer_out" LOC = "p180";
# Connector J3
NET "portc<0>" LOC = "p181";
NET "portc<1>" LOC = "p187";
NET "portc<2>" LOC = "p188";
NET "portc<3>" LOC = "p189";
NET "portc<4>" LOC = "p191";
NET "portc<5>" LOC = "p192";
NET "portc<6>" LOC = "p193";
NET "portc<7>" LOC = "p194";
NET "portd<0>" LOC = "p195";
NET "portd<1>" LOC = "p199";
NET "portd<2>" LOC = "p200";
NET "portd<3>" LOC = "p201";
NET "portd<4>" LOC = "p202";
NET "portd<5>" LOC = "p203";
NET "portd<6>" LOC = "p204";
NET "portd<7>" LOC = "p205";
#NET "timer1_out" LOC = "p206";
#NET "timer1_in" LOC = "p185";
# Connector J10
NET "sysclk" LOC = "p77"; #pin 2
NET "led" LOC = "p49"; #pin 3
NET "uart_csn" LOC = "p57"; #pin 4
NET "test_rw" LOC = "p58"; #pin 5
NET "test_d0" LOC = "p59"; #pin 6
NET "test_d1" LOC = "p60"; #pin 7
NET "reset_n" LOC = "p61"; #pin 8
NET "test_cc<0>" LOC = "p67"; #pin 11
NET "test_cc<1>" LOC = "p68"; #pin 12
NET "test_cc<2>" LOC = "p69"; #pin 13
NET "test_cc<3>" LOC = "p70"; #pin 14
NET "test_cc<4>" LOC = "p71"; #pin 15
NET "test_cc<5>" LOC = "p73"; #pin 16
NET "test_cc<6>" LOC = "p74"; #pin 17
NET "test_cc<7>" LOC = "p75"; #pin 18
# Connector J11
NET "test_alu<0>" LOC = "p82"; #pin 3
NET "test_alu<1>" LOC = "p83"; #pin 4
NET "test_alu<2>" LOC = "p84"; #pin 5
NET "test_alu<3>" LOC = "p86"; #pin 6
NET "test_alu<4>" LOC = "p87"; #pin 7
NET "test_alu<5>" LOC = "p88"; #pin 8
NET "test_alu<6>" LOC = "p89"; #pin 9
NET "test_alu<7>" LOC = "p90"; #pin 10
NET "test_alu<8>" LOC = "p94"; #pin 11
NET "test_alu<9>" LOC = "p95"; #pin 12
NET "test_alu<10>" LOC = "p96"; #pin 13
NET "test_alu<11>" LOC = "p97"; #pin 14
NET "test_alu<12>" LOC = "p98"; #pin 15
NET "test_alu<13>" LOC = "p99"; #pin 16
NET "test_alu<14>" LOC = "p100"; #pin 17
NET "test_alu<15>" LOC = "p101"; #pin 18
# Connector J8
#NET "aux_clock" LOC = "p24"; #pin 2
NET "buzzer" LOC = "p27"; #pin 3
#NET "mouse_clock" LOC = "p29"; #pin 4
#NET "mouse_data" LOC = "p30"; #pin 5
NET "cts_n" LOC = "p31"; #pin 6
NET "rts_n" LOC = "p33"; #pin 7
NET "txbit" LOC = "p34"; #pin 8
NET "rxbit" LOC = "p35"; #pin 9
#NET "kb_clock" LOC = "p36"; #pin 10
#NET "kb_data" LOC = "p37"; #pin 11
NET "v_drive" LOC = "p41"; #pin 12
NET "h_drive" LOC = "p42"; #pin 13
NET "blue_lo" LOC = "p43";
NET "blue_hi" LOC = "p44";
NET "green_lo" LOC = "p45";
NET "green_hi" LOC = "p46";
NET "red_lo" LOC = "p47";
NET "red_hi" LOC = "p48";
INST "ram_addr<0>" TNM = "ram_addr";
INST "ram_addr<1>" TNM = "ram_addr";
INST "ram_addr<2>" TNM = "ram_addr";
INST "ram_addr<3>" TNM = "ram_addr";
INST "ram_addr<4>" TNM = "ram_addr";
INST "ram_addr<5>" TNM = "ram_addr";
INST "ram_addr<6>" TNM = "ram_addr";
INST "ram_addr<7>" TNM = "ram_addr";
INST "ram_addr<8>" TNM = "ram_addr";
INST "ram_addr<9>" TNM = "ram_addr";
INST "ram_addr<10>" TNM = "ram_addr";
INST "ram_addr<11>" TNM = "ram_addr";
INST "ram_addr<12>" TNM = "ram_addr";
INST "ram_addr<13>" TNM = "ram_addr";
INST "ram_addr<14>" TNM = "ram_addr";
INST "ram_addr<15>" TNM = "ram_addr";
INST "ram_addr<16>" TNM = "ram_addr";
INST "ram_data<0>" TNM = "ram_data";
INST "ram_data<1>" TNM = "ram_data";
INST "ram_data<2>" TNM = "ram_data";
INST "ram_data<3>" TNM = "ram_data";
INST "ram_data<4>" TNM = "ram_data";
INST "ram_data<5>" TNM = "ram_data";
INST "ram_data<6>" TNM = "ram_data";
INST "ram_data<7>" TNM = "ram_data";
INST "ram_data<8>" TNM = "ram_data";
INST "ram_data<9>" TNM = "ram_data";
INST "ram_data<10>" TNM = "ram_data";
INST "ram_data<11>" TNM = "ram_data";
INST "ram_data<12>" TNM = "ram_data";
INST "ram_data<13>" TNM = "ram_data";
INST "ram_data<14>" TNM = "ram_data";
INST "ram_data<15>" TNM = "ram_data";
INST "ram_wrln" TNM = "ram_wr";
INST "ram_wrun" TNM = "ram_wr";
INST "ram_csn" TNM = "ram_cs";
INST "test_alu<0>" TNM = "test_alu";
INST "test_alu<1>" TNM = "test_alu";
INST "test_alu<2>" TNM = "test_alu";
INST "test_alu<3>" TNM = "test_alu";
INST "test_alu<4>" TNM = "test_alu";
INST "test_alu<5>" TNM = "test_alu";
INST "test_alu<6>" TNM = "test_alu";
INST "test_alu<7>" TNM = "test_alu";
INST "test_alu<8>" TNM = "test_alu";
INST "test_alu<9>" TNM = "test_alu";
INST "test_alu<10>" TNM = "test_alu";
INST "test_alu<11>" TNM = "test_alu";
INST "test_alu<12>" TNM = "test_alu";
INST "test_alu<13>" TNM = "test_alu";
INST "test_alu<14>" TNM = "test_alu";
INST "test_alu<15>" TNM = "test_alu";
INST "test_cc<0>" TNM = "test_cc";
INST "test_cc<1>" TNM = "test_cc";
INST "test_cc<2>" TNM = "test_cc";
INST "test_cc<3>" TNM = "test_cc";
INST "test_cc<4>" TNM = "test_cc";
INST "test_cc<5>" TNM = "test_cc";
INST "test_cc<6>" TNM = "test_cc";
INST "test_cc<7>" TNM = "test_cc";
TIMEGRP "ram_cs" OFFSET = OUT 35 ns AFTER "sysclk";
TIMEGRP "ram_wr" OFFSET = OUT 35 ns AFTER "sysclk";
TIMEGRP "ram_addr" OFFSET = OUT 35 ns AFTER "sysclk";
TIMEGRP "ram_data" OFFSET = OUT 35 ns AFTER "sysclk";
TIMEGRP "ram_data" OFFSET = IN 15 ns BEFORE "sysclk";
TIMEGRP "test_alu" OFFSET = OUT 90 ns AFTER "sysclk";
TIMEGRP "test_cc" OFFSET = OUT 90 ns AFTER "sysclk";
NET "sysclk" TNM_NET = "sysclk";
TIMESPEC "TS_sysclk" = PERIOD "sysclk" 100 ns HIGH 50 %;
NET "ram_addr<0>" FAST;
NET "ram_addr<1>" FAST;
NET "ram_addr<2>" FAST;
NET "ram_addr<3>" FAST;
NET "ram_addr<4>" FAST;
NET "ram_addr<5>" FAST;
NET "ram_addr<6>" FAST;
NET "ram_addr<7>" FAST;
NET "ram_addr<8>" FAST;
NET "ram_addr<9>" FAST;
NET "ram_addr<10>" FAST;
NET "ram_addr<11>" FAST;
NET "ram_addr<12>" FAST;
NET "ram_addr<13>" FAST;
NET "ram_addr<14>" FAST;
NET "ram_addr<15>" FAST;
NET "ram_addr<16>" FAST;
NET "ram_csn" FAST;
NET "ram_data<0>" FAST;
NET "ram_data<1>" FAST;
NET "ram_data<2>" FAST;
NET "ram_data<3>" FAST;
NET "ram_data<4>" FAST;
NET "ram_data<5>" FAST;
NET "ram_data<6>" FAST;
NET "ram_data<7>" FAST;
NET "ram_data<8>" FAST;
NET "ram_data<9>" FAST;
NET "ram_data<10>" FAST;
NET "ram_data<11>" FAST;
NET "ram_data<12>" FAST;
NET "ram_data<13>" FAST;
NET "ram_data<14>" FAST;
NET "ram_data<15>" FAST;
NET "ram_wrln" FAST;
NET "ram_wrun" FAST;

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