OpenCores
URL https://opencores.org/ocsvn/System68/System68/trunk

Subversion Repositories System68

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    from Rev 5 to Rev 6
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Rev 5 → Rev 6

/trunk/vhdl/uart_def.vhd File deleted
/trunk/vhdl/clkunit.vhd File deleted \ No newline at end of file
/trunk/vhdl/uart_lib.vhd File deleted
/trunk/vhdl/miniUART.vhd File deleted
/trunk/vhdl/System68.npl File deleted
/trunk/vhdl/rxunit.vhd File deleted \ No newline at end of file
/trunk/vhdl/txunit.vhd File deleted \ No newline at end of file
/trunk/vhdl/testbench1.vhd
89,6 → 89,8
address: out std_logic_vector(15 downto 0);
data_in: in std_logic_vector(7 downto 0);
data_out: out std_logic_vector(7 downto 0);
hold: in std_logic;
halt: in std_logic;
irq: in std_logic;
nmi: in std_logic;
test_alu: out std_logic_vector(15 downto 0);
106,6 → 108,8
address => cpu_addr(15 downto 0),
data_in => cpu_data_in,
data_out => cpu_data_out,
hold => cpu_hold,
halt => cpu_halt,
irq => uart_irq,
nmi => timer_irq,
test_alu => cpu_alu,
/trunk/vhdl/testbench2.vhd
76,15 → 76,19
 
component cpu68
port (
clk: in std_logic;
rst: in std_logic;
rw: out std_logic; -- Asynchronous memory interface
vma: out std_logic;
address: out std_logic_vector(15 downto 0);
data_in: in std_logic_vector(7 downto 0);
data_out: out std_logic_vector(7 downto 0);
address: out std_logic_vector(15 downto 0);
vma: out std_logic;
rw: out std_logic; -- Asynchronous memory interface
rst: in std_logic;
clk: in std_logic;
hold: in std_logic;
halt: in std_logic;
irq: in std_logic;
nmi: in std_logic
nmi: in std_logic;
test_alu: out std_logic_vector(15 downto 0);
test_cc: out std_logic_vector(7 downto 0)
);
end component cpu68;
 
91,15 → 95,19
 
begin
cpu : cpu68 port map (
clk => SysClk,
rst => cpu_reset,
rw => cpu_rw,
vma => cpu_vma,
address => cpu_addr(15 downto 0),
data_in => cpu_data_in,
data_out => cpu_data_out,
address => cpu_addr(15 downto 0),
vma => cpu_vma,
rw => cpu_rw,
rst => cpu_reset,
clk => SysClk,
hold => cpu_hold,
halt => cpu_halt,
irq => uart_irq,
nmi => timer_irq
nmi => timer_irq,
test_alu => cpu_alu,
test_cc => cpu_cc
);
 
-- *** Test Bench - User Defined Section ***
/trunk/vhdl/System68.vhd
2,15 → 2,23
--
-- S Y N T H E Z I A B L E System68 System On a Chip
--
-- www.OpenCores.Org - December 2002
-- This core adheres to the GNU public license
--
-- File name : system68.vhd
--
-- Purpose : Top level file for a 6800 compatible system on a chip
-- Designed for the Burch ED B3-Spartan II board with
-- X2S200 FPGA, 128 x 16 Word SRAM module and CPU I/O module
-- Designed for the Burch ED B5-Spartan IIe board with
-- X2S300e FPGA,
-- 128K x 16 Word SRAM module (B5-SRAM)
-- CPU I/O module (B5-Peripheral-Connectors)
-- Compact Flash Module (B5-CF)
-- Using mimiUart from open cores modified to look like a 6850
-- This version of System68 boots the monitor program
-- from LBA sectors $F478 / $F479 from a 32 Mbyte Compact Flash
-- On Reset the Boot ROM is mapped for read at $E000,
-- and Writes to $E000-$FFFF write to RAM
-- Writing 0 to location $8030 disables the boot ROM and
-- maps RAM for Read only at $E000 and Writes go to the DAT.
--
-- Dependencies : ieee.Std_Logic_1164
-- ieee.std_logic_unsigned
20,7 → 28,6
-- Uses : miniuart.vhd, rxunit.vhd, tx_unit.vhd, clkunit.vhd
-- swtbug.vhd (6800 SWTBUG ROM)
-- datram.vhd (Dynamic address translation registers)
-- ioport.vhd (4 x 8 port parallel I/O )
-- cpu68.vhd (6800 compatible CPU core)
-- timer.vhd (timer module)
--
34,17 → 41,38
-- Date: Revision Author
-- 22 September 2002 0.1 John Kent
-- Initial design.
-- 31 March 2003 0.2 John Kent
-- Removed Parallel I/O port
-- Added Compact Flash Interface
-- Added IO register to commit unused inputs
-- Used 16 byte port mapping
--
-- 28th June 2003 0.3 John Kent
-- updated CPU to include Halt and Hold signals
--
-- 9th January 2004 0.4 John Kent
-- Removed Redundant Map Switch Code.
-- Rearrange DAT
-- Added dual port IO at $8030 - $803F
--
-- 25th April 2004 0.5 John Kent
-- Changed CPU clock to run at 25MHz / 2 = 12.5 MHz
-- Added baud rate divider for 57.6 Kbaud.
--
-------------------------------------------------------------------------------
--
-- Memory Map:
--
-- $0000 - $7FFF RAM
-- $8000 - $9FFF IO
-- $8000 - $8003 Timer
-- $8004 - $8007 MiniUart / Acia
-- $8008 - $800F IO Port
-- $A000 - $DFFF RAM
-- $8000 - $8FFF IO
-- $8000 - $800F MiniUart / Acia
-- $8010 - $801F Compact Flash
-- $8020 - $802F Timer
-- $8030 - $803F IO port
-- $8040 - $804F Trap hardware
-- $9000 - $BFFF RAM
-- $C000 - $CFFF ROM
-- $D000 - $DFFF RAM
-- $E000 - $FFFF ROM (read) & DAT (write)
--
library ieee;
53,158 → 81,187
use IEEE.STD_LOGIC_UNSIGNED.ALL;
use ieee.numeric_std.all;
 
entity System68 is
entity Sys68 is
port(
SysClk : in Std_Logic; -- System Clock input
Reset_n : in Std_logic; -- Master Reset input (active low)
LED : out std_logic; -- Diagnostic LED Flasher
SysClk : in Std_Logic; -- System Clock input
Reset_n : in Std_logic; -- Master Reset input (active low)
 
-- Memory Interface signals
ram_csn : out Std_Logic; -- RAM Chip select (active low)
ram_wrln : out Std_Logic; -- lower byte write strobe (active low)
ram_wrun : out Std_Logic; -- upper byte write strobe (active low)
ram_addr : out Std_Logic_Vector(16 downto 0); -- RAM Address bus
-- Memory Interface signals B3-SRAM
ram_csn : out Std_Logic; -- RAM Chip select (active low)
ram_wrln : out Std_Logic; -- lower byte write strobe (active low)
ram_wrun : out Std_Logic; -- upper byte write strobe (active low)
ram_addr : out Std_Logic_Vector(16 downto 0); -- RAM Address bus
ram_data : inout Std_Logic_Vector(15 downto 0); -- RAM Data bus
 
-- Stuff on the peripheral board
-- aux_clock : in Std_Logic; -- FPGA-CPU-IO clock
-- Signals defined on B3-CPU-IO Module
LED : out std_logic; -- Diagnostic LED Flasher
 
-- PS/2 Mouse interface
-- mouse_clock : in Std_Logic;
-- mouse_data : in Std_Logic;
 
-- Uart Interface
rxbit : in Std_Logic; -- UART receive data
txbit : out Std_Logic; -- UART transmit data
rts_n : out Std_Logic; -- Request to send (active low)
cts_n : in Std_Logic; -- Clear to send (active low)
rxbit : in Std_Logic; -- UART receive data
txbit : out Std_Logic; -- UART transmit data
rts_n : out Std_Logic; -- Request to send (active low)
cts_n : in Std_Logic; -- Clear to send (active low)
 
-- CRTC output signals
-- Signal defined on B3-CPU-IO Module
-- Not currently used.
v_drive : out Std_Logic;
h_drive : out Std_Logic;
blue_lo : out std_logic;
blue_hi : out std_logic;
green_lo : out std_logic;
green_hi : out std_logic;
red_lo : out std_logic;
red_hi : out std_logic;
buzzer : out std_logic;
-- v_drive : out Std_Logic;
-- h_drive : out Std_Logic;
-- blue_lo : out std_logic;
-- blue_hi : out std_logic;
-- green_lo : out std_logic;
-- green_hi : out std_logic;
-- red_lo : out std_logic;
-- red_hi : out std_logic;
-- buzzer : out std_logic;
 
-- I/O Ports
PortA : inout std_logic_vector(7 downto 0);
PortB : inout std_logic_vector(7 downto 0);
PortC : inout std_logic_vector(7 downto 0);
PortD : inout std_logic_vector(7 downto 0);
-- Compact Flash B5-CF Module
cf_rst_n : out std_logic;
cf_cs0_n : out std_logic;
cf_cs1_n : out std_logic;
cf_rd_n : out std_logic;
cf_wr_n : out std_logic;
cf_cs16_n : out std_logic;
cf_a : out std_logic_vector(2 downto 0);
cf_d : inout std_logic_vector(15 downto 0);
-- cf_intrq : in std_logic;
-- cf_iordy : in std_logic;
-- cf_dase : in std_logic;
-- cf_pdiag : in std_logic;
-- cf_present : in std_logic;
 
-- Timer I/O
timer_out : out std_logic;
--- IOPort Pins
porta : inout std_logic_vector(7 downto 0);
portb : inout std_logic_vector(7 downto 0);
 
-- Test Pins
uart_csn : out std_logic; -- Uart chip select out (active low)
test_rw : out std_logic; -- Read / Write signal
test_d0 : out std_logic; -- Uart Chip select ANDed with Receive Data Ready bit
test_d1 : out std_logic; -- Uart Chip select ANDed with Transmit Data Ready bit
--- Timer output
timer_out : out std_logic;
 
test_alu : out std_logic_vector(15 downto 0); -- ALU output for timing constraints
test_cc : out std_logic_vector(7 downto 0) -- Condition Code Outputs for timing constraints
-- External Bus
bus_addr : out std_logic_vector(15 downto 0);
bus_data : inout std_logic_vector(7 downto 0);
bus_rw : out std_logic;
bus_cs : out std_logic;
bus_clk : out std_logic;
bus_reset : out std_logic
);
end System68;
end;
 
-------------------------------------------------------------------------------
-- Architecture for memio Controller Unit
-------------------------------------------------------------------------------
architecture my_computer of System68 is
architecture my_computer of Sys68 is
-----------------------------------------------------------------------------
-- Signals
-----------------------------------------------------------------------------
-- BOOT ROM
signal rom_data_out : Std_Logic_Vector(7 downto 0);
-- SWTBUG in Slices
signal monitor_cs : Std_Logic;
signal monitor_data_out : Std_Logic_Vector(7 downto 0);
 
-- SWTBUG in Block RAM
signal swtbug_cs : Std_Logic;
signal swtbug_data_out : Std_Logic_Vector(7 downto 0);
 
-- UART Interface signals
signal uart_data_out : Std_Logic_Vector(7 downto 0);
signal uart_cs : Std_Logic;
signal uart_irq : Std_Logic;
signal uart_cs : Std_Logic;
signal uart_data_out : Std_Logic_Vector(7 downto 0);
signal uart_irq : Std_Logic;
signal dcd_n : Std_Logic;
signal baudclk : Std_Logic;
 
-- timer
signal timer_data_out : std_logic_vector(7 downto 0);
signal timer_cs : std_logic;
signal timer_irq : std_logic;
signal timer_cs : std_logic;
signal timer_data_out : std_logic_vector(7 downto 0);
signal timer_irq : std_logic;
 
-- i/o port
-- trap
signal trap_cs : std_logic;
signal trap_data_out : std_logic_vector(7 downto 0);
signal trap_irq : std_logic;
 
-- ioport
signal ioport_cs : std_logic;
signal ioport_data_out : std_logic_vector(7 downto 0);
signal ioport_cs : std_logic;
 
-- compact flash port
signal cf_cs : std_logic;
signal cf_rd : std_logic;
signal cf_wr : std_logic;
signal cf_data_out : std_logic_vector(7 downto 0);
 
-- RAM
signal ram_cs : std_logic; -- memory chip select
signal ram_wrl : std_logic; -- memory write lower
signal ram_wru : std_logic; -- memory write upper
signal ram_cs : std_logic; -- memory chip select
signal ram_wrl : std_logic; -- memory write lower
signal ram_wru : std_logic; -- memory write upper
signal ram_data_out : std_logic_vector(7 downto 0);
 
-- CPU Interface signals
signal cpu_reset : Std_Logic;
signal cpu_clk : Std_Logic;
signal cpu_rw : std_logic;
signal cpu_vma : std_logic;
signal cpu_irq : std_logic;
signal cpu_nmi : std_logic;
signal cpu_addr : Std_Logic_Vector(15 downto 0);
signal cpu_data_in : Std_Logic_Vector(7 downto 0);
signal cpu_data_out: Std_Logic_Vector(7 downto 0);
signal cpu_reset : Std_Logic;
signal cpu_clk : Std_Logic;
signal cpu_rw : std_logic;
signal cpu_vma : std_logic;
signal cpu_halt : std_logic;
signal cpu_hold : std_logic;
signal cpu_irq : std_logic;
signal cpu_nmi : std_logic;
signal cpu_addr : Std_Logic_Vector(15 downto 0);
signal cpu_data_in : Std_Logic_Vector(7 downto 0);
signal cpu_data_out : Std_Logic_Vector(7 downto 0);
 
-- Dynamic Address Translation RAM
signal dat_cs : std_logic;
signal dat_addr : std_logic_vector(7 downto 0);
signal dat_cs : std_logic;
signal dat_addr : std_logic_vector(7 downto 0);
 
-- Flashing Led test signals
signal countL : std_logic_vector(23 downto 0);
-- Flashing Led test signals
signal countL : std_logic_vector(23 downto 0);
signal BaudCount : std_logic_vector(4 downto 0);
 
 
-----------------------------------------------------------------
--
-- Open Cores Mini UART
-- CPU68 CPU core
--
-----------------------------------------------------------------
 
component miniUART is
port (
SysClk : in Std_Logic; -- System Clock
rst : in Std_Logic; -- Reset input
cs : in Std_Logic;
rw : in Std_Logic;
RxD : in Std_Logic;
TxD : out Std_Logic;
CTS_n : in Std_Logic;
RTS_n : out Std_Logic;
Irq : out Std_logic;
Addr : in Std_Logic;
DataIn : in Std_Logic_Vector(7 downto 0); --
DataOut : out Std_Logic_Vector(7 downto 0)); --
component cpu68
port (
clk: in std_logic;
rst: in std_logic;
rw: out std_logic; -- Asynchronous memory interface
vma: out std_logic;
address: out std_logic_vector(15 downto 0);
data_in: in std_logic_vector(7 downto 0);
data_out: out std_logic_vector(7 downto 0);
hold: in std_logic;
halt: in std_logic;
irq: in std_logic;
nmi: in std_logic
);
end component;
 
--------------------------------------
-----------------------------------------------------------------
--
-- Three port parallel I/O
-- Open Cores Mini UART
--
---------------------------------------
-----------------------------------------------------------------
 
component ioport is
component miniUART
port (
clk : in std_logic;
rst : in std_logic;
cs : in std_logic;
rw : in std_logic;
addr : in std_logic_vector(2 downto 0);
data_in : in std_logic_vector(7 downto 0);
data_out : out std_logic_vector(7 downto 0);
porta_io : inout std_logic_vector(7 downto 0);
portb_io : inout std_logic_vector(7 downto 0);
portc_io : inout std_logic_vector(7 downto 0);
portd_io : inout std_logic_vector(7 downto 0)
);
clk : in Std_Logic; -- System Clock
rst : in Std_Logic; -- Reset input (active high)
cs : in Std_Logic; -- miniUART Chip Select
rw : in Std_Logic; -- Read / Not Write
irq : out Std_Logic; -- Interrupt
Addr : in Std_Logic; -- Register Select
DataIn : in Std_Logic_Vector(7 downto 0); -- Data Bus In
DataOut : out Std_Logic_Vector(7 downto 0); -- Data Bus Out
RxC : in Std_Logic; -- Receive Baud Clock
TxC : in Std_Logic; -- Transmit Baud Clock
RxD : in Std_Logic; -- Receive Data
TxD : out Std_Logic; -- Transmit Data
DCD_n : in Std_Logic; -- Data Carrier Detect
CTS_n : in Std_Logic; -- Clear To Send
RTS_n : out Std_Logic ); -- Request To send
end component;
 
 
----------------------------------------
--
-- Timer module
211,7 → 268,7
--
----------------------------------------
 
component timer is
component timer
port (
clk : in std_logic;
rst : in std_logic;
224,25 → 281,36
timer_in : in std_logic;
timer_out : out std_logic
);
end component timer;
end component;
 
component cpu68 is
port (
clk: in std_logic;
rst: in std_logic;
rw: out std_logic; -- Asynchronous memory interface
vma: out std_logic;
address: out std_logic_vector(15 downto 0);
data_in: in std_logic_vector(7 downto 0);
data_out: out std_logic_vector(7 downto 0);
irq: in std_logic;
nmi: in std_logic;
test_alu: out std_logic_vector(15 downto 0);
test_cc: out std_logic_vector(7 downto 0)
component trap
port (
clk : in std_logic;
rst : in std_logic;
cs : in std_logic;
rw : in std_logic;
vma : in std_logic;
addr : in std_logic_vector(15 downto 0);
data_in : in std_logic_vector(7 downto 0);
data_out : out std_logic_vector(7 downto 0);
irq : out std_logic
);
end component cpu68;
end component;
 
component dat_ram is
component ioport
port (
clk : in std_logic;
rst : in std_logic;
cs : in std_logic;
rw : in std_logic;
addr : in std_logic_vector(1 downto 0);
data_in : in std_logic_vector(7 downto 0);
data_out : out std_logic_vector(7 downto 0);
porta_io : inout std_logic_vector(7 downto 0);
portb_io : inout std_logic_vector(7 downto 0) );
end component;
 
component dat_ram
port (
clk: in std_logic;
rst: in std_logic;
253,51 → 321,81
data_in: in std_logic_vector(7 downto 0);
data_out: out std_logic_vector(7 downto 0)
);
end component dat_ram;
end component;
 
component boot_rom is
--
-- SWTBug Monitor ROM at $E000
--
component monitor_rom
port (
cs : in std_logic;
addr : in Std_Logic_Vector(9 downto 0); -- 1K byte boot rom
data : out Std_Logic_Vector(7 downto 0)
);
end component boot_rom;
end component;
 
 
component BUFG
port (
i: in std_logic;
o: out std_logic
);
end component;
 
--
-- SWTBUG Monitor in Block RAM at $C000
--
component swtbug_rom
port (
clk : in std_logic;
rst : in std_logic;
cs : in std_logic;
rw : in std_logic;
addr : in std_logic_vector (9 downto 0);
wdata : in std_logic_vector (7 downto 0);
rdata : out std_logic_vector (7 downto 0)
);
end component;
 
begin
-----------------------------------------------------------------------------
-- Instantiation of internal components
-----------------------------------------------------------------------------
 
my_cpu : cpu68 port map (
clk => cpu_clk,
rst => cpu_reset,
rw => cpu_rw,
vma => cpu_vma,
address => cpu_addr(15 downto 0),
data_in => cpu_data_in,
data_out => cpu_data_out,
hold => cpu_hold,
halt => cpu_halt,
irq => cpu_irq,
nmi => cpu_nmi
);
 
my_uart : miniUART port map (
SysClk => SysClk,
clk => cpu_clk,
rst => cpu_reset,
cs => uart_cs,
rw => cpu_rw,
irq => uart_irq,
Addr => cpu_addr(0),
Datain => cpu_data_out,
DataOut => uart_data_out,
RxC => baudclk,
TxC => baudclk,
RxD => rxbit,
TxD => txbit,
DCD_n => dcd_n,
CTS_n => cts_n,
RTS_n => rts_n,
Irq => uart_irq,
Addr => cpu_addr(0),
Datain => cpu_data_out,
DataOut => uart_data_out
RTS_n => rts_n
);
 
my_ioport : ioport port map (
clk => SysClk,
rst => cpu_reset,
cs => ioport_cs,
rw => cpu_rw,
addr => cpu_addr(2 downto 0),
data_in => cpu_data_out,
data_out => ioport_data_out,
porta_io => porta,
portb_io => portb,
portc_io => portc,
portd_io => portd
);
 
my_timer : timer port map (
clk => SysClk,
clk => cpu_clk,
rst => cpu_reset,
cs => timer_cs,
rw => cpu_rw,
309,23 → 407,32
timer_out => timer_out
);
 
my_cpu : cpu68 port map (
clk => SysClk,
rst => cpu_reset,
rw => cpu_rw,
vma => cpu_vma,
address => cpu_addr(15 downto 0),
data_in => cpu_data_in,
data_out => cpu_data_out,
irq => cpu_irq,
nmi => cpu_nmi,
test_alu => test_alu,
test_cc => test_cc
);
my_trap : trap port map (
clk => cpu_clk,
rst => cpu_reset,
cs => trap_cs,
rw => cpu_rw,
vma => cpu_vma,
addr => cpu_addr,
data_in => cpu_data_out,
data_out => trap_data_out,
irq => trap_irq
);
 
my_ioport : ioport port map (
clk => cpu_clk,
rst => cpu_reset,
cs => ioport_cs,
rw => cpu_rw,
addr => cpu_addr(1 downto 0),
data_in => cpu_data_out,
data_out => ioport_data_out,
porta_io => porta,
portb_io => portb
);
 
my_dat : dat_ram port map (
clk => SysClk,
clk => cpu_clk,
rst => cpu_reset,
cs => dat_cs,
rw => cpu_rw,
335,72 → 442,194
data_out => dat_addr(7 downto 0)
);
 
my_rom : boot_rom port map (
addr => cpu_addr(9 downto 0),
data => rom_data_out
--
-- SWTBUG Monitor
--
my_monitor_rom : monitor_rom port map (
cs => monitor_cs,
addr => cpu_addr(9 downto 0),
data => monitor_data_out
);
 
--
-- SWTBUG Monitor using BLOCKRAM
--
my_swtbug_rom : swtbug_rom port map (
clk => cpu_clk,
rst => cpu_reset,
cs => swtbug_cs,
rw => cpu_rw,
addr => cpu_addr(9 downto 0),
wdata => cpu_data_out,
rdata => swtbug_data_out
);
 
 
clock_buffer : BUFG port map (
i => CountL(0),
o => cpu_clk
);
----------------------------------------------------------------------
--
-- Processes to read and write memory based on bus signals
-- Processes to decode the CPU address
--
----------------------------------------------------------------------
 
memory: process( SysClk, Reset_n,
cpu_addr, cpu_rw, cpu_vma, cpu_data_out,
ram_cs, ram_wrl, ram_wru, dat_addr,
rom_data_out, ram_data_out,
ioport_data_out, timer_data_out, uart_data_out )
decode: process( cpu_addr, cpu_rw, cpu_vma, cpu_data_in,
monitor_data_out,
ram_data_out,
swtbug_data_out,
uart_data_out,
cf_data_out,
timer_data_out,
trap_data_out,
bus_data,
dat_cs )
begin
case cpu_addr(15 downto 13) is
when "111" => -- $E000 - $FFFF
cpu_data_in <= rom_data_out;
dat_cs <= cpu_vma;
ram_cs <= '0';
uart_cs <= '0';
ioport_cs <= '0';
timer_cs <= '0';
when "100" => -- $8000 - $9FFF
dat_cs <= '0';
ram_cs <= '0';
case cpu_addr(5 downto 2) is
when "0000" => -- $8000
--
-- Memory Map
--
case cpu_addr(15 downto 12) is
when "1111" | "1110" => -- $E000 - $FFFF
cpu_data_in <= monitor_data_out; -- read ROM
monitor_cs <= cpu_vma;
swtbug_cs <= '0';
dat_cs <= cpu_vma; -- write DAT
ram_cs <= '0';
uart_cs <= '0';
cf_cs <= '0';
timer_cs <= '0';
trap_cs <= '0';
ioport_cs <= '0';
bus_cs <= '0';
when "1100" => -- $C000 - $CFFF
cpu_data_in <= swtbug_data_out;
monitor_cs <= '0';
swtbug_cs <= cpu_vma;
dat_cs <= '0';
ram_cs <= '0';
uart_cs <= '0';
cf_cs <= '0';
timer_cs <= '0';
trap_cs <= '0';
ioport_cs <= '0';
bus_cs <= '0';
when "1000" => -- $8000 - $8FFF
monitor_cs <= '0';
swtbug_cs <= '0';
dat_cs <= '0';
ram_cs <= '0';
case cpu_addr(6 downto 4) is
--
-- UART
--
when "000" => -- ($8000 - $800F)
if cpu_addr(3 downto 2) = "01" then
cpu_data_in <= uart_data_out;
uart_cs <= cpu_vma;
cf_cs <= '0';
timer_cs <= '0';
trap_cs <= '0';
ioport_cs <= '0';
bus_cs <= '0';
else
cpu_data_in <= "00000000";
uart_cs <= '0';
cf_cs <= '0';
timer_cs <= '0';
trap_cs <= '0';
ioport_cs <= '0';
bus_cs <= '0';
end if;
--
-- Compact Flash
--
when "001" => -- ($8010 - $801F)
cpu_data_in <= cf_data_out;
uart_cs <= '0';
cf_cs <= cpu_vma;
timer_cs <= '0';
trap_cs <= '0';
ioport_cs <= '0';
bus_cs <= '0';
--
-- Timer
--
when "010" => -- ($8020 - $802F)
cpu_data_in <= timer_data_out;
uart_cs <= '0';
ioport_cs <= '0';
timer_cs <= cpu_vma;
when "0001" => -- $8004
cpu_data_in <= uart_data_out;
uart_cs <= cpu_vma;
uart_cs <= '0';
cf_cs <= '0';
timer_cs <= cpu_vma;
trap_cs <= '0';
ioport_cs <= '0';
timer_cs <= '0';
when "0010" | "0011" => -- $8008/$800C
bus_cs <= '0';
--
-- IO Port
--
when "011" => -- ($8030 - $803F)
cpu_data_in <= ioport_data_out;
uart_cs <= '0';
ioport_cs <= cpu_vma;
timer_cs <= '0';
when others => -- $8010 to $9FFF
cpu_data_in <= "00000000";
cf_cs <= '0';
timer_cs <= '0';
trap_cs <= '0';
ioport_cs <= cpu_vma;
bus_cs <= '0';
--
-- Trap hardware
--
when "100" => -- ($8040 - $804F)
cpu_data_in <= trap_data_out;
uart_cs <= '0';
cf_cs <= '0';
timer_cs <= '0';
trap_cs <= cpu_vma;
ioport_cs <= '0';
bus_cs <= '0';
--
-- Null devices
--
when others => -- $8050 to $9FFF
cpu_data_in <= bus_data;
uart_cs <= '0';
cf_cs <= '0';
timer_cs <= '0';
trap_cs <= '0';
ioport_cs <= '0';
bus_cs <= cpu_vma;
end case;
when others =>
cpu_data_in <= ram_data_out;
ram_cs <= cpu_vma;
dat_cs <= '0';
uart_cs <= '0';
ioport_cs <= '0';
timer_cs <= '0';
end case;
cpu_reset <= not Reset_n; -- CPU reset is active high
ram_csn <= not( ram_cs and Reset_n );
ram_wrl <= (not dat_addr(5)) and (not cpu_rw) and SysClk;
when others =>
cpu_data_in <= ram_data_out;
monitor_cs <= '0';
swtbug_cs <= '0';
ram_cs <= cpu_vma;
dat_cs <= '0';
uart_cs <= '0';
cf_cs <= '0';
timer_cs <= '0';
trap_cs <= '0';
ioport_cs <= '0';
end case;
end process;
 
 
----------------------------------------------------------------------
--
-- Processes to read and write B5_SRAM
--
----------------------------------------------------------------------
b5_sram: process( cpu_clk, Reset_n,
cpu_addr, cpu_rw, cpu_data_out,
ram_cs, ram_wrl, ram_wru,
dat_cs, dat_addr, ram_data_out )
begin
ram_csn <= not( ram_cs and Reset_n);
ram_wrl <= dat_addr(0) and (not cpu_rw) and cpu_clk;
ram_wrln <= not ram_wrl;
ram_wru <= dat_addr(5) and (not cpu_rw) and SysClk;
ram_wru <= (not dat_addr(0)) and (not cpu_rw) and cpu_clk;
ram_wrun <= not ram_wru;
ram_addr(16 downto 12) <= dat_addr(4 downto 0);
ram_addr(11 downto 0) <= cpu_addr(11 downto 0);
ram_addr(16 downto 12) <= dat_addr(5 downto 1);
ram_addr(11 downto 0 ) <= cpu_addr(11 downto 0);
 
if ram_wrl = '1' then
ram_data(7 downto 0) <= cpu_data_out;
414,63 → 643,106
ram_data(15 downto 8) <= "ZZZZZZZZ";
end if;
 
if dat_addr(5) = '1' then
if dat_addr(0) = '0' then
ram_data_out <= ram_data(15 downto 8);
else
ram_data_out <= ram_data(7 downto 0);
end if;
-- test pins
uart_csn <= not uart_cs;
test_rw <= cpu_rw;
test_d0 <= uart_data_out(0) and uart_cs;
test_d1 <= uart_data_out(1) and uart_cs;
 
end process;
 
--
-- tie together interrupts
-- B5-CF Compact Flash Control
--
interrupts : process( timer_irq, uart_irq )
b5_cf: process( Reset_n,
cpu_addr, cpu_rw, cpu_data_out,
cf_cs, cf_rd, cf_wr, cf_d )
begin
cpu_irq <= uart_irq;
cpu_nmi <= timer_irq;
cf_rst_n <= Reset_n;
cf_cs0_n <= not( cf_cs ) or cpu_addr(3);
cf_cs1_n <= not( cf_cs and cpu_addr(3));
cf_cs16_n <= '1';
cf_wr <= cf_cs and (not cpu_rw);
cf_rd <= cf_cs and cpu_rw;
cf_wr_n <= not cf_wr;
cf_rd_n <= not cf_rd;
cf_a <= cpu_addr(2 downto 0);
if cf_wr = '1' then
cf_d(7 downto 0) <= cpu_data_out;
else
cf_d(7 downto 0) <= "ZZZZZZZZ";
end if;
cf_data_out <= cf_d(7 downto 0);
cf_d(15 downto 8) <= "ZZZZZZZZ";
end process;
 
--
-- CPU bus signals
--
--clock_gen : process( SysClk, e_clk )
--begin
-- if SysClk'event and SysClk='1' then
-- e_clk <= not e_clk;
-- end if;
--end process;
my_bus : process( cpu_clk, cpu_reset, cpu_rw, cpu_addr, cpu_data_out )
begin
bus_clk <= cpu_clk;
bus_reset <= cpu_reset;
bus_rw <= cpu_rw;
bus_addr <= cpu_addr;
if( cpu_rw = '1' ) then
bus_data <= "ZZZZZZZZ";
else
bus_data <= cpu_data_out;
end if;
end process;
 
--
-- flash led to indicate code is working
--
increment: process (SysClk, CountL )
begin
if(SysClk'event and SysClk = '1') then
countL <= countL + 1;
 
--
-- Interrupts and Reset.
--
interrupts : process( Reset_n,
trap_irq, timer_irq, uart_irq )
begin
cpu_halt <= '0';
cpu_hold <= '0';
cpu_irq <= uart_irq or timer_irq;
cpu_nmi <= trap_irq;
cpu_reset <= not Reset_n; -- CPU reset is active high
end process;
 
--
-- flash led to indicate code is working
--
flash: process (SysClk, Reset_n, CountL )
begin
if(SysClk'event and SysClk = '0') then
-- if Reset_n = '0' then
-- countL <= "000000000000000000000000";
-- else
countL <= countL + 1;
-- end if;
end if;
LED <= countL(21);
end process;
-- baudclk <= countL(5); -- 9.8MHz / 64 = 153,600 KHz = 9600Bd * 16
-- baudclk <= countL(4); -- 9.8MHz / 32 = 307,200 KHz = 19200Bd * 16
-- baudclk <= countL(3); -- 9.8MHz / 16 = 614,400 KHz = 38400Bd * 16
-- baudclk <= countL(2); -- 4.9MHz / 8 = 614,400 KHz = 38400Bd * 16
dcd_n <= '0';
end process;
 
uncommitted: process( SysClk )
begin
--
-- CRTC output signals
--
v_drive <= '0';
h_drive <= '0';
blue_lo <= '0';
blue_hi <= '0';
green_lo <= '0';
green_hi <= '0';
red_lo <= '0';
red_hi <= '0';
buzzer <= '0';
end process;
 
--
-- 57.6 Kbaud * 16 divider for 25 MHz system clock
--
my_clock: process( SysClk )
begin
if(SysClk'event and SysClk = '0') then
if( BaudCount = 26 ) then
BaudCount <= "00000";
else
BaudCount <= BaudCount + 1;
end if;
end if;
baudclk <= BaudCount(4); -- 25MHz / 27 = 926,000 KHz = 57,870Bd * 16
dcd_n <= '0';
end process;
end my_computer; --===================== End of architecture =======================--
 
/trunk/vhdl/testbench3.vhd
79,15 → 79,19
 
component cpu68
port (
clk: in std_logic;
rst: in std_logic;
rw: out std_logic; -- Asynchronous memory interface
vma: out std_logic;
address: out std_logic_vector(15 downto 0);
data_in: in std_logic_vector(7 downto 0);
data_out: out std_logic_vector(7 downto 0);
address: out std_logic_vector(15 downto 0);
vma: out std_logic;
rw: out std_logic; -- Asynchronous memory interface
rst: in std_logic;
clk: in std_logic;
hold: in std_logic;
halt: in std_logic;
irq: in std_logic;
nmi: in std_logic
nmi: in std_logic;
test_alu: out std_logic_vector(15 downto 0);
test_cc: out std_logic_vector(7 downto 0)
);
end component cpu68;
 
94,15 → 98,19
 
begin
cpu : cpu68 port map (
clk => SysClk,
rst => cpu_reset,
rw => cpu_rw,
vma => cpu_vma,
address => cpu_addr(15 downto 0),
data_in => cpu_data_in,
data_out => cpu_data_out,
address => cpu_addr(15 downto 0),
vma => cpu_vma,
rw => cpu_rw,
rst => cpu_reset,
clk => SysClk,
hold => cpu_hold,
halt => cpu_halt,
irq => uart_irq,
nmi => timer_irq
nmi => timer_irq,
test_alu => cpu_alu,
test_cc => cpu_cc
);
 
-- *** Test Bench - User Defined Section ***
/trunk/vhdl/testbench4.vhd
0,0 → 1,173
--===========================================================================--
--
-- CPU68 Microprocessor Test Bench 4
-- Test Software - SWTBUG BLOCKRAM ROM
--
--
-- John Kent 4st September 2003
--
--
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use IEEE.STD_LOGIC_ARITH.ALL;
use ieee.numeric_std.all;
 
entity testbench4 is
end testbench4;
 
-------------------------------------------------------------------------------
-- Architecture for memio Controller Unit
-------------------------------------------------------------------------------
architecture behavior of testbench4 is
-----------------------------------------------------------------------------
-- Signals
-----------------------------------------------------------------------------
signal cpu_irq : std_Logic;
signal cpu_firq : std_logic;
signal cpu_nmi : std_logic;
 
-- CPU Interface signals
signal SysClk : Std_Logic;
signal cpu_reset : Std_Logic;
signal cpu_rw : Std_Logic;
signal cpu_vma : Std_Logic;
signal cpu_addr : Std_Logic_Vector(15 downto 0);
signal cpu_data_in : Std_Logic_Vector(7 downto 0);
signal cpu_data_out: Std_Logic_Vector(7 downto 0);
signal cpu_halt : Std_logic;
signal cpu_hold : Std_logic;
signal cpu_alu : Std_Logic_Vector(15 downto 0);
signal cpu_cc : Std_Logic_Vector(7 downto 0);
signal rom_data_out: Std_Logic_Vector(7 downto 0);
signal rom_cs : Std_Logic;
signal rom_hold : Std_Logic;
signal ram_data_out: Std_Logic_Vector(7 downto 0);
signal ram_cs : Std_Logic;
component cpu68 is
port (
clk : in std_logic;
rst : in std_logic;
rw : out std_logic; -- Asynchronous memory interface
vma : out std_logic;
address : out std_logic_vector(15 downto 0);
data_in : in std_logic_vector(7 downto 0);
data_out: out std_logic_vector(7 downto 0);
hold : in std_logic;
halt : in std_logic;
irq : in std_logic;
nmi : in std_logic;
test_alu: out std_logic_vector(15 downto 0);
test_cc : out std_logic_vector(7 downto 0)
);
end component cpu68;
 
component swtbug_rom is
Port (
clk : in std_logic;
rst : in std_logic;
cs : in std_logic;
hold : out std_logic;
rw : in std_logic;
addr : in std_logic_vector (9 downto 0);
wdata : in std_logic_vector (7 downto 0);
rdata : out std_logic_vector (7 downto 0)
);
end component swtbug_rom;
 
component block_ram is
Port (
MEMclk : in std_logic;
MEMcs : in std_logic;
MEMrw : in std_logic;
MEMaddr : in std_logic_vector (10 downto 0);
MEMrdata : out std_logic_vector (7 downto 0);
MEMwdata : in std_logic_vector (7 downto 0)
);
end component block_ram;
 
begin
 
my_cpu : cpu68 port map (
clk => SysClk,
rst => cpu_reset,
rw => cpu_rw,
vma => cpu_vma,
address => cpu_addr(15 downto 0),
data_in => cpu_data_in,
data_out => cpu_data_out,
hold => cpu_hold,
halt => cpu_halt,
irq => cpu_irq,
nmi => cpu_nmi,
test_alu => cpu_alu,
test_cc => cpu_cc
);
 
 
my_ram : block_ram port map (
MEMclk => SysClk,
MEMcs => ram_cs,
MEMrw => cpu_rw,
MEMaddr => cpu_addr(10 downto 0),
MEMrdata => ram_data_out,
MEMwdata => cpu_data_out
);
 
my_rom : swtbug_rom port map (
clk => SysClk,
rst => cpu_reset,
cs => rom_cs,
hold => rom_hold,
rw => cpu_rw,
addr => cpu_addr(9 downto 0),
wdata => cpu_data_out,
rdata => rom_data_out
);
 
-- *** Test Bench - User Defined Section ***
tb : PROCESS
variable count : integer;
BEGIN
 
cpu_reset <= '0';
SysClk <= '0';
cpu_irq <= '0';
cpu_nmi <= '0';
cpu_firq <= '0';
cpu_halt <= '0';
cpu_hold <= rom_hold;
 
for count in 0 to 512 loop
SysClk <= '0';
if count = 0 then
cpu_reset <= '1';
elsif count = 1 then
cpu_reset <= '0';
end if;
wait for 100 ns;
SysClk <= '1';
wait for 100 ns;
end loop;
 
wait; -- will wait forever
END PROCESS;
-- *** End Test Bench - User Defined Section ***
 
 
rom : PROCESS( cpu_addr, rom_data_out, ram_data_out )
begin
if( cpu_addr(15 downto 13) = "111" ) then
cpu_data_in <= rom_data_out;
ram_cs <= '0';
rom_cs <= '1';
else
cpu_data_in <= ram_data_out;
ram_cs <= '1';
rom_cs <= '0';
end if;
end process;
 
end behavior; --===================== End of architecture =======================--
 
/trunk/vhdl/testbench5.vhd
0,0 → 1,127
--===========================================================================--
--
-- CPU68 Microprocessor Test Bench 5
-- Test Software - BLOCKRAM
--
--
-- John Kent 4st September 2003
--
--
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use IEEE.STD_LOGIC_ARITH.ALL;
use ieee.numeric_std.all;
library unisim;
use unisim.all;
library simprim;
use simprim.all;
 
entity testbench5 is
end testbench5;
 
-------------------------------------------------------------------------------
-- Architecture for memio Controller Unit
-------------------------------------------------------------------------------
architecture behavior of testbench5 is
-----------------------------------------------------------------------------
-- Signals
-----------------------------------------------------------------------------
 
-- CPU Interface signals
signal SysClk : Std_Logic;
signal cpu_rw : Std_Logic;
signal cpu_addr : Std_Logic_Vector(10 downto 0);
signal cpu_data_out: Std_Logic_Vector(7 downto 0);
signal ram_data_out: Std_Logic_Vector(7 downto 0);
signal ram_cs : Std_Logic;
 
component block_ram is
Port (
MEMclk : in std_logic;
MEMcs : in std_logic;
MEMrw : in std_logic;
MEMaddr : in std_logic_vector (10 downto 0);
MEMrdata : out std_logic_vector (7 downto 0);
MEMwdata : in std_logic_vector (7 downto 0)
);
end component block_ram;
 
begin
 
 
my_ram: block_ram Port Map (
MEMclk => SysClk,
MEMcs => ram_cs,
MEMrw => cpu_rw,
MEMaddr => cpu_addr,
MEMrdata => ram_data_out,
MEMwdata => cpu_data_out
);
 
-- *** Test Bench - User Defined Section ***
tb : PROCESS
variable count : integer;
BEGIN
 
SysClk <= '0';
cpu_data_out <= "00000000";
cpu_addr <= "00000000000";
ram_cs <= '0';
cpu_rw <= '1';
for count in 0 to 5 loop
 
SysClk <= '0';
ram_cs <= '0';
wait for 30 ns;
cpu_addr <= "00111000111";
cpu_data_out <= "11110000";
cpu_rw <= '0'; -- write
ram_cs <= '1';
wait for 20 ns;
SysClk <= '1';
wait for 50 ns;
 
SysClk <= '0';
ram_cs <= '0';
wait for 30 ns;
cpu_addr <= "00111000110";
cpu_data_out <= "10101010";
cpu_rw <= '0'; -- write
ram_cs <= '1';
wait for 20 ns;
SysClk <= '1';
wait for 50 ns;
 
SysClk <= '0';
ram_cs <= '0';
wait for 30 ns;
cpu_addr <= "00111000111";
cpu_data_out <= "00001111";
cpu_rw <= '1'; -- read
ram_cs <= '1';
wait for 20 ns;
SysClk <= '1';
wait for 50 ns;
 
SysClk <= '0';
ram_cs <= '0';
wait for 30 ns;
cpu_addr <= "00111000110";
cpu_data_out <= "00001111";
cpu_rw <= '1'; -- read
ram_cs <= '1';
wait for 20 ns;
SysClk <= '1';
wait for 50 ns;
end loop;
 
wait; -- will wait forever
END PROCESS;
-- *** End Test Bench - User Defined Section ***
 
 
 
end behavior; --===================== End of architecture =======================--
 
/trunk/vhdl/cpu68.vhd
40,10 → 40,30
-- SEV and CLV were not defined in the ALU
-- Overflow Flag on NEG was incorrect
--
-- 16th Feb 2003 0.6 John Kent
-- Rearranged the execution cycle for dual operand instructions
-- so that occurs during the following fetch cycle.
-- This allows the reduction of one clock cycle from dual operand
-- instruction. Note that this also necessitated re-arranging the
-- program counter so that it is no longer incremented in the ALU.
-- The effective address has also been re-arranged to include a
-- separate added. The STD (store accd) now sets the condition codes.
--
-- 28th Jun 2003 0.7 John Kent
-- Added Hold and Halt signals. Hold is used to steal cycles from the
-- CPU or add wait states. Halt puts the CPU in the inactive state
-- and is only honoured in the fetch cycle. Both signals are active high.
--
-- 9th Jan 2004 0.8 John Kent
-- Clear instruction did an alu_ld8 rather than an alu_clr, so
-- the carry bit was not cleared correctly.
-- This error was picked up by Michael Hassenfratz.
--
 
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
 
entity cpu68 is
port (
54,10 → 74,12
address: out std_logic_vector(15 downto 0);
data_in: in std_logic_vector(7 downto 0);
data_out: out std_logic_vector(7 downto 0);
hold: in std_logic;
halt: in std_logic;
irq: in std_logic;
nmi: in std_logic;
test_alu: out std_logic_vector(15 downto 0);
test_cc: out std_logic_vector(7 downto 0)
nmi: in std_logic
-- test_alu: out std_logic_vector(15 downto 0);
-- test_cc: out std_logic_vector(7 downto 0)
);
end;
 
73,9 → 95,9
constant CBIT : integer := 0;
 
type state_type is (reset_state, fetch_state, decode_state,
extended_state, indexed_state, direct_state, direct16_state, immediate16_state,
extended_state, indexed_state, read8_state, read16_state, immediate16_state,
write8_state, write16_state,
execute_state, halt_state,
execute_state, halt_state, error_state,
mul_state, mulea_state, muld_state,
mul0_state, mul1_state, mul2_state, mul3_state,
mul4_state, mul5_state, mul6_state, mul7_state,
100,13 → 122,13
type cc_type is (reset_cc, load_cc, pull_cc, latch_cc );
type ix_type is (reset_ix, load_ix, pull_lo_ix, pull_hi_ix, latch_ix );
type sp_type is (reset_sp, latch_sp, load_sp );
type pc_type is (reset_pc, latch_pc, load_pc, pull_lo_pc, pull_hi_pc );
type pc_type is (reset_pc, latch_pc, load_ea_pc, add_ea_pc, pull_lo_pc, pull_hi_pc, inc_pc );
type md_type is (reset_md, latch_md, load_md, fetch_first_md, fetch_next_md, shiftl_md );
type ea_type is (reset_ea, latch_ea, load_ea, fetch_first_ea, fetch_next_ea );
type ea_type is (reset_ea, latch_ea, add_ix_ea, load_accb_ea, inc_ea, fetch_first_ea, fetch_next_ea );
type iv_type is (reset_iv, latch_iv, swi_iv, nmi_iv, irq_iv );
type nmi_type is (reset_nmi, set_nmi, latch_nmi );
type left_type is (acca_left, accb_left, accd_left, md_left, ix_left, pc_left, sp_left, ea_left );
type right_type is (md_right, zero_right, plus_one_right, accb_right, ea_right, sexea_right );
type left_type is (acca_left, accb_left, accd_left, md_left, ix_left, sp_left );
type right_type is (md_right, zero_right, plus_one_right, accb_right );
type alu_type is (alu_add8, alu_sub8, alu_add16, alu_sub16, alu_adc, alu_sbc,
alu_and, alu_ora, alu_eor,
alu_tst, alu_inc, alu_dec, alu_clr, alu_neg, alu_com,
158,7 → 180,7
 
----------------------------------
--
-- Address output multiplexer
-- Address bus multiplexer
--
----------------------------------
 
204,6 → 226,38
end case;
end process;
 
--------------------------------
--
-- Data Bus output
--
--------------------------------
dout_mux : process( clk, dout_ctrl, md, acca, accb, xreg, pc, cc )
begin
case dout_ctrl is
when md_hi_dout => -- alu output
data_out <= md(15 downto 8);
when md_lo_dout =>
data_out <= md(7 downto 0);
when acca_dout => -- accumulator a
data_out <= acca;
when accb_dout => -- accumulator b
data_out <= accb;
when ix_lo_dout => -- index reg
data_out <= xreg(7 downto 0);
when ix_hi_dout => -- index reg
data_out <= xreg(15 downto 8);
when cc_dout => -- condition codes
data_out <= cc;
when pc_lo_dout => -- low order pc
data_out <= pc(7 downto 0);
when pc_hi_dout => -- high order pc
data_out <= pc(15 downto 8);
when others =>
data_out <= "00000000";
end case;
end process;
 
 
----------------------------------
--
-- Program Counter Control
210,22 → 264,44
--
----------------------------------
 
pc_mux: process( clk, pc_ctrl, pc, out_alu, data_in )
pc_mux: process( clk, pc_ctrl, pc, out_alu, data_in, ea, hold )
variable tempof : std_logic_vector(15 downto 0);
variable temppc : std_logic_vector(15 downto 0);
begin
if clk'event and clk = '1' then
case pc_ctrl is
when reset_pc =>
pc <= "0000000000000000";
when load_pc =>
pc <= out_alu(15 downto 0);
when pull_lo_pc =>
pc(7 downto 0) <= data_in;
when pull_hi_pc =>
pc(15 downto 8) <= data_in;
when others =>
-- when latch_pc =>
case pc_ctrl is
when add_ea_pc =>
if ea(7) = '0' then
tempof := "00000000" & ea(7 downto 0);
else
tempof := "11111111" & ea(7 downto 0);
end if;
when inc_pc =>
tempof := "0000000000000001";
when others =>
tempof := "0000000000000000";
end case;
 
case pc_ctrl is
when reset_pc =>
temppc := "1111111111111110";
when load_ea_pc =>
temppc := ea;
when pull_lo_pc =>
temppc(7 downto 0) := data_in;
temppc(15 downto 8) := pc(15 downto 8);
when pull_hi_pc =>
temppc(7 downto 0) := pc(7 downto 0);
temppc(15 downto 8) := data_in;
when others =>
temppc := pc;
end case;
 
if clk'event and clk = '0' then
if hold = '1' then
pc <= pc;
end case;
else
pc <= temppc + tempof;
end if;
end if;
end process;
 
235,25 → 311,42
--
----------------------------------
 
ea_mux: process( clk, ea_ctrl, ea, out_alu, data_in )
ea_mux: process( clk, ea_ctrl, ea, out_alu, data_in, accb, xreg, hold )
variable tempind : std_logic_vector(15 downto 0);
variable tempea : std_logic_vector(15 downto 0);
begin
case ea_ctrl is
when add_ix_ea =>
tempind := "00000000" & ea(7 downto 0);
when inc_ea =>
tempind := "0000000000000001";
when others =>
tempind := "0000000000000000";
end case;
 
if clk'event and clk = '1' then
case ea_ctrl is
when reset_ea =>
ea <= "0000000000000000";
when fetch_first_ea =>
ea(7 downto 0) <= data_in;
ea(15 downto 8) <= "00000000";
when fetch_next_ea =>
ea(15 downto 8) <= ea(7 downto 0);
ea(7 downto 0) <= data_in;
when load_ea =>
ea <= out_alu(15 downto 0);
when others =>
-- when latch_ea =>
case ea_ctrl is
when reset_ea =>
tempea := "0000000000000000";
when load_accb_ea =>
tempea := "00000000" & accb(7 downto 0);
when add_ix_ea =>
tempea := xreg;
when fetch_first_ea =>
tempea(7 downto 0) := data_in;
tempea(15 downto 8) := "00000000";
when fetch_next_ea =>
tempea(7 downto 0) := data_in;
tempea(15 downto 8) := ea(7 downto 0);
when others =>
tempea := ea;
end case;
 
if clk'event and clk = '0' then
if hold = '1' then
ea <= ea;
end case;
else
ea <= tempea + tempind;
end if;
end if;
end process;
 
262,9 → 355,12
-- Accumulator A
--
--------------------------------
acca_mux : process( clk, acca_ctrl, out_alu, acca, data_in )
acca_mux : process( clk, acca_ctrl, out_alu, acca, data_in, hold )
begin
if clk'event and clk = '1' then
if clk'event and clk = '0' then
if hold = '1' then
acca <= acca;
else
case acca_ctrl is
when reset_acca =>
acca <= "00000000";
278,6 → 374,7
-- when latch_acca =>
acca <= acca;
end case;
end if;
end if;
end process;
 
286,9 → 383,12
-- Accumulator B
--
--------------------------------
accb_mux : process( clk, accb_ctrl, out_alu, accb, data_in )
accb_mux : process( clk, accb_ctrl, out_alu, accb, data_in, hold )
begin
if clk'event and clk = '1' then
if clk'event and clk = '0' then
if hold = '1' then
accb <= accb;
else
case accb_ctrl is
when reset_accb =>
accb <= "00000000";
300,6 → 400,7
-- when latch_accb =>
accb <= accb;
end case;
end if;
end if;
end process;
 
308,9 → 409,12
-- X Index register
--
--------------------------------
ix_mux : process( clk, ix_ctrl, out_alu, xreg, data_in )
ix_mux : process( clk, ix_ctrl, out_alu, xreg, data_in, hold )
begin
if clk'event and clk = '1' then
if clk'event and clk = '0' then
if hold = '1' then
xreg <= xreg;
else
case ix_ctrl is
when reset_ix =>
xreg <= "0000000000000000";
324,6 → 428,7
-- when latch_ix =>
xreg <= xreg;
end case;
end if;
end if;
end process;
 
332,9 → 437,12
-- stack pointer
--
--------------------------------
sp_mux : process( clk, sp_ctrl, out_alu )
sp_mux : process( clk, sp_ctrl, out_alu, hold )
begin
if clk'event and clk = '1' then
if clk'event and clk = '0' then
if hold = '1' then
sp <= sp;
else
case sp_ctrl is
when reset_sp =>
sp <= "0000000000000000";
344,6 → 452,7
-- when latch_sp =>
sp <= sp;
end case;
end if;
end if;
end process;
 
352,9 → 461,12
-- Memory Data
--
--------------------------------
md_mux : process( clk, md_ctrl, out_alu, data_in, md )
md_mux : process( clk, md_ctrl, out_alu, data_in, md, hold )
begin
if clk'event and clk = '1' then
if clk'event and clk = '0' then
if hold = '1' then
md <= md;
else
case md_ctrl is
when reset_md =>
md <= "0000000000000000";
373,6 → 485,7
-- when latch_md =>
md <= md;
end case;
end if;
end if;
end process;
 
383,9 → 496,12
--
----------------------------------
 
cc_mux: process( clk, cc_ctrl, cc_out, cc, data_in )
cc_mux: process( clk, cc_ctrl, cc_out, cc, data_in, hold )
begin
if clk'event and clk = '1' then
if clk'event and clk = '0' then
if hold = '1' then
cc <= cc;
else
case cc_ctrl is
when reset_cc =>
cc <= "11000000";
397,6 → 513,7
-- when latch_cc =>
cc <= cc;
end case;
end if;
end if;
end process;
 
406,9 → 523,12
--
----------------------------------
 
iv_mux: process( clk, iv_ctrl )
iv_mux: process( clk, iv_ctrl, hold )
begin
if clk'event and clk = '1' then
if clk'event and clk = '0' then
if hold = '1' then
iv <= iv;
else
case iv_ctrl is
when reset_iv =>
iv <= "11";
421,42 → 541,10
when others =>
iv <= iv;
end case;
end if;
end if;
end process;
 
 
--------------------------------
--
-- Data Bus output
--
--------------------------------
dout_mux : process( clk, dout_ctrl, md, acca, accb, xreg, pc, cc )
begin
case dout_ctrl is
when md_hi_dout => -- alu output
data_out <= md(15 downto 8);
when md_lo_dout =>
data_out <= md(7 downto 0);
when acca_dout => -- accumulator a
data_out <= acca;
when accb_dout => -- accumulator b
data_out <= accb;
when ix_lo_dout => -- index reg
data_out <= xreg(7 downto 0);
when ix_hi_dout => -- index reg
data_out <= xreg(15 downto 8);
when cc_dout => -- condition codes
data_out <= cc;
when pc_lo_dout => -- low order pc
data_out <= pc(7 downto 0);
when pc_hi_dout => -- high order pc
data_out <= pc(15 downto 8);
when others =>
data_out <= "00000000";
end case;
end process;
 
 
----------------------------------
--
-- op code fetch
463,12 → 551,15
--
----------------------------------
 
op_fetch: process( clk, data_in, op_ctrl, op_code )
op_fetch: process( clk, data_in, op_ctrl, op_code, hold )
begin
if clk'event and clk = '1' then
if clk'event and clk = '0' then
if hold = '1' then
op_code <= op_code;
else
case op_ctrl is
when reset_op =>
op_code <= "00000001";
op_code <= "00000001"; -- nop
when fetch_op =>
op_code <= data_in;
when others =>
475,6 → 566,7
-- when latch_op =>
op_code <= op_code;
end case;
end if;
end if;
end process;
 
496,17 → 588,13
when accd_left =>
left(15 downto 8) <= acca;
left(7 downto 0) <= accb;
when md_left =>
left <= md;
when ix_left =>
left <= xreg;
when sp_left =>
left <= sp;
when pc_left =>
left <= pc;
when others =>
-- when ea_left =>
left <= ea;
-- when md_left =>
left <= md;
end case;
end process;
----------------------------------
524,14 → 612,6
right <= "0000000000000001";
when accb_right =>
right <= "00000000" & accb;
when ea_right =>
right <= ea;
when sexea_right =>
if ea(7) = '0' then
right <= "00000000" & ea(7 downto 0);
else
right <= "11111111" & ea(7 downto 0);
end if;
when others =>
-- when md_right =>
right <= md;
809,8 → 889,8
cc_out(SBIT) <= cc(SBIT);
end case;
 
test_alu <= out_alu;
test_cc <= cc_out;
-- test_alu <= out_alu;
-- test_cc <= cc_out;
end process;
 
------------------------------------
821,7 → 901,10
 
nmi_handler : process( clk, rst, nmi, nmi_ack )
begin
if clk'event and clk='1' then
if clk'event and clk='0' then
if hold = '1' then
nmi_req <= nmi_req;
else
if rst='1' then
nmi_req <= '0';
else
835,6 → 918,7
end if;
end if;
end if;
end if;
end if;
end process;
 
844,9 → 928,12
--
------------------------------------
 
nmi_mux: process( clk, nmi_ctrl, nmi_ack )
nmi_mux: process( clk, nmi_ctrl, nmi_ack, hold )
begin
if clk'event and clk='1' then
if clk'event and clk='0' then
if hold = '1' then
nmi_ack <= nmi_ack;
else
case nmi_ctrl is
when set_nmi =>
nmi_ack <= '1';
856,6 → 943,7
-- when latch_nmi =>
nmi_ack <= nmi_ack;
end case;
end if;
end if;
end process;
 
864,7 → 952,7
-- state sequencer
--
------------------------------------
process( state, op_code, cc, ea, irq, nmi_req, nmi_ack )
process( state, op_code, cc, ea, irq, nmi_req, nmi_ack, hold, halt )
begin
case state is
when reset_state => -- released from reset
879,9 → 967,8
md_ctrl <= reset_md;
iv_ctrl <= reset_iv;
nmi_ctrl <= reset_nmi;
sp_ctrl <= reset_sp;
-- idle the ALU
left_ctrl <= pc_left;
left_ctrl <= acca_left;
right_ctrl <= zero_right;
alu_ctrl <= alu_nop;
cc_ctrl <= reset_cc;
907,7 → 994,7
ea_ctrl <= latch_ea;
iv_ctrl <= latch_iv;
-- idle the ALU
left_ctrl <= pc_left;
left_ctrl <= acca_left;
right_ctrl <= zero_right;
alu_ctrl <= alu_nop;
cc_ctrl <= latch_cc;
933,7 → 1020,7
ea_ctrl <= latch_ea;
iv_ctrl <= latch_iv;
-- idle the ALU
left_ctrl <= pc_left;
left_ctrl <= acca_left;
right_ctrl <= zero_right;
alu_ctrl <= alu_nop;
cc_ctrl <= latch_cc;
951,10 → 1038,353
-- or from the external input.
--
when fetch_state =>
acca_ctrl <= latch_acca;
accb_ctrl <= latch_accb;
ix_ctrl <= latch_ix;
sp_ctrl <= latch_sp;
case op_code(7 downto 4) is
when "0000" |
"0001" |
"0010" | -- branch conditional
"0011" |
"0100" | -- acca single op
"0101" | -- accb single op
"0110" | -- indexed single op
"0111" => -- extended single op
-- idle ALU
left_ctrl <= acca_left;
right_ctrl <= zero_right;
alu_ctrl <= alu_nop;
cc_ctrl <= latch_cc;
acca_ctrl <= latch_acca;
accb_ctrl <= latch_accb;
ix_ctrl <= latch_ix;
sp_ctrl <= latch_sp;
 
when "1000" | -- acca immediate
"1001" | -- acca direct
"1010" | -- acca indexed
"1011" => -- acca extended
case op_code(3 downto 0) is
when "0000" => -- suba
left_ctrl <= acca_left;
right_ctrl <= md_right;
alu_ctrl <= alu_sub8;
cc_ctrl <= load_cc;
acca_ctrl <= load_acca;
accb_ctrl <= latch_accb;
ix_ctrl <= latch_ix;
sp_ctrl <= latch_sp;
when "0001" => -- cmpa
left_ctrl <= acca_left;
right_ctrl <= md_right;
alu_ctrl <= alu_sub8;
cc_ctrl <= load_cc;
acca_ctrl <= latch_acca;
accb_ctrl <= latch_accb;
ix_ctrl <= latch_ix;
sp_ctrl <= latch_sp;
when "0010" => -- sbca
left_ctrl <= acca_left;
right_ctrl <= md_right;
alu_ctrl <= alu_sbc;
cc_ctrl <= load_cc;
acca_ctrl <= load_acca;
accb_ctrl <= latch_accb;
ix_ctrl <= latch_ix;
sp_ctrl <= latch_sp;
when "0011" => -- subd
left_ctrl <= accd_left;
right_ctrl <= md_right;
alu_ctrl <= alu_sub16;
cc_ctrl <= load_cc;
acca_ctrl <= load_hi_acca;
accb_ctrl <= load_accb;
ix_ctrl <= latch_ix;
sp_ctrl <= latch_sp;
when "0100" => -- anda
left_ctrl <= acca_left;
right_ctrl <= md_right;
alu_ctrl <= alu_and;
cc_ctrl <= load_cc;
acca_ctrl <= load_acca;
accb_ctrl <= latch_accb;
ix_ctrl <= latch_ix;
sp_ctrl <= latch_sp;
when "0101" => -- bita
left_ctrl <= acca_left;
right_ctrl <= md_right;
alu_ctrl <= alu_and;
cc_ctrl <= load_cc;
acca_ctrl <= latch_acca;
accb_ctrl <= latch_accb;
ix_ctrl <= latch_ix;
sp_ctrl <= latch_sp;
when "0110" => -- ldaa
left_ctrl <= acca_left;
right_ctrl <= md_right;
alu_ctrl <= alu_ld8;
cc_ctrl <= load_cc;
acca_ctrl <= load_acca;
accb_ctrl <= latch_accb;
ix_ctrl <= latch_ix;
sp_ctrl <= latch_sp;
when "0111" => -- staa
left_ctrl <= acca_left;
right_ctrl <= md_right;
alu_ctrl <= alu_st8;
cc_ctrl <= load_cc;
acca_ctrl <= latch_acca;
accb_ctrl <= latch_accb;
ix_ctrl <= latch_ix;
sp_ctrl <= latch_sp;
when "1000" => -- eora
left_ctrl <= acca_left;
right_ctrl <= md_right;
alu_ctrl <= alu_eor;
cc_ctrl <= load_cc;
acca_ctrl <= load_acca;
accb_ctrl <= latch_accb;
ix_ctrl <= latch_ix;
sp_ctrl <= latch_sp;
when "1001" => -- adca
left_ctrl <= acca_left;
right_ctrl <= md_right;
alu_ctrl <= alu_adc;
cc_ctrl <= load_cc;
acca_ctrl <= load_acca;
accb_ctrl <= latch_accb;
ix_ctrl <= latch_ix;
sp_ctrl <= latch_sp;
when "1010" => -- oraa
left_ctrl <= acca_left;
right_ctrl <= md_right;
alu_ctrl <= alu_ora;
cc_ctrl <= load_cc;
acca_ctrl <= load_acca;
accb_ctrl <= latch_accb;
ix_ctrl <= latch_ix;
sp_ctrl <= latch_sp;
when "1011" => -- adda
left_ctrl <= acca_left;
right_ctrl <= md_right;
alu_ctrl <= alu_add8;
cc_ctrl <= load_cc;
acca_ctrl <= load_acca;
accb_ctrl <= latch_accb;
ix_ctrl <= latch_ix;
sp_ctrl <= latch_sp;
when "1100" => -- cpx
left_ctrl <= ix_left;
right_ctrl <= md_right;
alu_ctrl <= alu_cpx;
cc_ctrl <= load_cc;
acca_ctrl <= latch_acca;
accb_ctrl <= latch_accb;
ix_ctrl <= latch_ix;
sp_ctrl <= latch_sp;
when "1101" => -- bsr / jsr
left_ctrl <= acca_left;
right_ctrl <= md_right;
alu_ctrl <= alu_nop;
cc_ctrl <= latch_cc;
acca_ctrl <= latch_acca;
accb_ctrl <= latch_accb;
ix_ctrl <= latch_ix;
sp_ctrl <= latch_sp;
when "1110" => -- lds
left_ctrl <= sp_left;
right_ctrl <= md_right;
alu_ctrl <= alu_ld16;
cc_ctrl <= load_cc;
acca_ctrl <= latch_acca;
accb_ctrl <= latch_accb;
ix_ctrl <= latch_ix;
sp_ctrl <= load_sp;
when "1111" => -- sts
left_ctrl <= sp_left;
right_ctrl <= md_right;
alu_ctrl <= alu_st16;
cc_ctrl <= load_cc;
acca_ctrl <= latch_acca;
accb_ctrl <= latch_accb;
ix_ctrl <= latch_ix;
sp_ctrl <= latch_sp;
when others =>
left_ctrl <= acca_left;
right_ctrl <= md_right;
alu_ctrl <= alu_nop;
cc_ctrl <= latch_cc;
acca_ctrl <= latch_acca;
accb_ctrl <= latch_accb;
ix_ctrl <= latch_ix;
sp_ctrl <= latch_sp;
end case;
when "1100" | -- accb immediate
"1101" | -- accb direct
"1110" | -- accb indexed
"1111" => -- accb extended
case op_code(3 downto 0) is
when "0000" => -- subb
left_ctrl <= accb_left;
right_ctrl <= md_right;
alu_ctrl <= alu_sub8;
cc_ctrl <= load_cc;
acca_ctrl <= latch_acca;
accb_ctrl <= load_accb;
ix_ctrl <= latch_ix;
sp_ctrl <= latch_sp;
when "0001" => -- cmpb
left_ctrl <= accb_left;
right_ctrl <= md_right;
alu_ctrl <= alu_sub8;
cc_ctrl <= load_cc;
acca_ctrl <= latch_acca;
accb_ctrl <= latch_accb;
ix_ctrl <= latch_ix;
sp_ctrl <= latch_sp;
when "0010" => -- sbcb
left_ctrl <= accb_left;
right_ctrl <= md_right;
alu_ctrl <= alu_sbc;
cc_ctrl <= load_cc;
acca_ctrl <= latch_acca;
accb_ctrl <= load_accb;
ix_ctrl <= latch_ix;
sp_ctrl <= latch_sp;
when "0011" => -- addd
left_ctrl <= accd_left;
right_ctrl <= md_right;
alu_ctrl <= alu_add16;
cc_ctrl <= load_cc;
acca_ctrl <= load_hi_acca;
accb_ctrl <= load_accb;
ix_ctrl <= latch_ix;
sp_ctrl <= latch_sp;
when "0100" => -- andb
left_ctrl <= accb_left;
right_ctrl <= md_right;
alu_ctrl <= alu_and;
cc_ctrl <= load_cc;
acca_ctrl <= latch_acca;
accb_ctrl <= load_accb;
ix_ctrl <= latch_ix;
sp_ctrl <= latch_sp;
when "0101" => -- bitb
left_ctrl <= accb_left;
right_ctrl <= md_right;
alu_ctrl <= alu_and;
cc_ctrl <= load_cc;
acca_ctrl <= latch_acca;
accb_ctrl <= latch_accb;
ix_ctrl <= latch_ix;
sp_ctrl <= latch_sp;
when "0110" => -- ldab
left_ctrl <= accb_left;
right_ctrl <= md_right;
alu_ctrl <= alu_ld8;
cc_ctrl <= load_cc;
acca_ctrl <= latch_acca;
accb_ctrl <= load_accb;
ix_ctrl <= latch_ix;
sp_ctrl <= latch_sp;
when "0111" => -- stab
left_ctrl <= accb_left;
right_ctrl <= md_right;
alu_ctrl <= alu_st8;
cc_ctrl <= load_cc;
acca_ctrl <= latch_acca;
accb_ctrl <= latch_accb;
ix_ctrl <= latch_ix;
sp_ctrl <= latch_sp;
when "1000" => -- eorb
left_ctrl <= accb_left;
right_ctrl <= md_right;
alu_ctrl <= alu_eor;
cc_ctrl <= load_cc;
acca_ctrl <= latch_acca;
accb_ctrl <= load_accb;
ix_ctrl <= latch_ix;
sp_ctrl <= latch_sp;
when "1001" => -- adcb
left_ctrl <= accb_left;
right_ctrl <= md_right;
alu_ctrl <= alu_adc;
cc_ctrl <= load_cc;
acca_ctrl <= latch_acca;
accb_ctrl <= load_accb;
ix_ctrl <= latch_ix;
sp_ctrl <= latch_sp;
when "1010" => -- orab
left_ctrl <= accb_left;
right_ctrl <= md_right;
alu_ctrl <= alu_ora;
cc_ctrl <= load_cc;
acca_ctrl <= latch_acca;
accb_ctrl <= load_accb;
ix_ctrl <= latch_ix;
sp_ctrl <= latch_sp;
when "1011" => -- addb
left_ctrl <= accb_left;
right_ctrl <= md_right;
alu_ctrl <= alu_add8;
cc_ctrl <= load_cc;
acca_ctrl <= latch_acca;
accb_ctrl <= load_accb;
ix_ctrl <= latch_ix;
sp_ctrl <= latch_sp;
when "1100" => -- ldd
left_ctrl <= accd_left;
right_ctrl <= md_right;
alu_ctrl <= alu_ld16;
cc_ctrl <= load_cc;
acca_ctrl <= load_hi_acca;
accb_ctrl <= load_accb;
ix_ctrl <= latch_ix;
sp_ctrl <= latch_sp;
when "1101" => -- std
left_ctrl <= accd_left;
right_ctrl <= md_right;
alu_ctrl <= alu_st16;
cc_ctrl <= load_cc;
acca_ctrl <= latch_acca;
accb_ctrl <= latch_accb;
ix_ctrl <= latch_ix;
sp_ctrl <= latch_sp;
when "1110" => -- ldx
left_ctrl <= ix_left;
right_ctrl <= md_right;
alu_ctrl <= alu_ld16;
cc_ctrl <= load_cc;
acca_ctrl <= latch_acca;
accb_ctrl <= latch_accb;
ix_ctrl <= load_ix;
sp_ctrl <= latch_sp;
when "1111" => -- stx
left_ctrl <= ix_left;
right_ctrl <= md_right;
alu_ctrl <= alu_st16;
cc_ctrl <= load_cc;
acca_ctrl <= latch_acca;
accb_ctrl <= latch_accb;
ix_ctrl <= latch_ix;
sp_ctrl <= latch_sp;
when others =>
left_ctrl <= accb_left;
right_ctrl <= md_right;
alu_ctrl <= alu_nop;
cc_ctrl <= latch_cc;
acca_ctrl <= latch_acca;
accb_ctrl <= latch_accb;
ix_ctrl <= latch_ix;
sp_ctrl <= latch_sp;
end case;
when others =>
left_ctrl <= accd_left;
right_ctrl <= md_right;
alu_ctrl <= alu_nop;
cc_ctrl <= latch_cc;
acca_ctrl <= latch_acca;
accb_ctrl <= latch_accb;
ix_ctrl <= latch_ix;
sp_ctrl <= latch_sp;
end case;
md_ctrl <= latch_md;
-- fetch the op code
op_ctrl <= fetch_op;
962,12 → 1392,12
addr_ctrl <= fetch_ad;
dout_ctrl <= md_lo_dout;
iv_ctrl <= latch_iv;
if halt = '1' then
pc_ctrl <= latch_pc;
nmi_ctrl <= latch_nmi;
next_state <= halt_state;
-- service non maskable interrupts
if (nmi_req = '1') and (nmi_ack = '0') then
left_ctrl <= acca_left;
right_ctrl <= zero_right;
alu_ctrl <= alu_nop;
cc_ctrl <= latch_cc;
elsif (nmi_req = '1') and (nmi_ack = '0') then
pc_ctrl <= latch_pc;
nmi_ctrl <= set_nmi;
next_state <= int_pcl_state;
985,19 → 1415,11
-- IRQ is level sensitive
--
if (irq = '1') and (cc(IBIT) = '0') then
left_ctrl <= acca_left;
right_ctrl <= zero_right;
alu_ctrl <= alu_nop;
cc_ctrl <= latch_cc;
pc_ctrl <= latch_pc;
next_state <= int_pcl_state;
else
-- Advance the PC to fetch next instruction byte
left_ctrl <= pc_left;
right_ctrl <= plus_one_right;
alu_ctrl <= alu_add16;
cc_ctrl <= latch_cc;
pc_ctrl <= load_pc;
pc_ctrl <= inc_pc;
next_state <= decode_state;
end if;
end if;
1008,7 → 1430,6
--
when decode_state =>
-- fetch first byte of address or immediate data
md_ctrl <= fetch_first_md;
ea_ctrl <= fetch_first_ea;
addr_ctrl <= fetch_ad;
dout_ctrl <= md_lo_dout;
1017,6 → 1438,7
iv_ctrl <= latch_iv;
case op_code(7 downto 4) is
when "0000" =>
md_ctrl <= fetch_first_md;
sp_ctrl <= latch_sp;
pc_ctrl <= latch_pc;
case op_code(3 downto 0) is
1136,6 → 1558,7
next_state <= fetch_state;
-- acca / accb inherent instructions
when "0001" =>
md_ctrl <= fetch_first_md;
ix_ctrl <= latch_ix;
sp_ctrl <= latch_sp;
pc_ctrl <= latch_pc;
1180,16 → 1603,17
end case;
next_state <= fetch_state;
when "0010" => -- branch conditional
md_ctrl <= fetch_first_md;
acca_ctrl <= latch_acca;
accb_ctrl <= latch_accb;
ix_ctrl <= latch_ix;
sp_ctrl <= latch_sp;
left_ctrl <= acca_left;
right_ctrl <= zero_right;
alu_ctrl <= alu_nop;
cc_ctrl <= latch_cc;
-- increment the pc
left_ctrl <= pc_left;
right_ctrl <= plus_one_right;
alu_ctrl <= alu_add16;
cc_ctrl <= latch_cc;
pc_ctrl <= load_pc;
pc_ctrl <= inc_pc;
case op_code(3 downto 0) is
when "0000" => -- bra
next_state <= branch_state;
1287,6 → 1711,7
-- Do not advance PC
--
when "0011" =>
md_ctrl <= fetch_first_md;
acca_ctrl <= latch_acca;
accb_ctrl <= latch_accb;
pc_ctrl <= latch_pc;
1435,6 → 1860,7
-- Do not advance PC
--
when "0100" => -- acca single op
md_ctrl <= fetch_first_md;
accb_ctrl <= latch_accb;
pc_ctrl <= latch_pc;
ix_ctrl <= latch_ix;
1503,7 → 1929,7
cc_ctrl <= latch_cc;
when "1111" => -- clr
right_ctrl <= zero_right;
alu_ctrl <= alu_ld8;
alu_ctrl <= alu_clr;
acca_ctrl <= load_acca;
cc_ctrl <= load_cc;
when others =>
1518,6 → 1944,7
-- Do not advance PC
--
when "0101" =>
md_ctrl <= fetch_first_md;
acca_ctrl <= latch_acca;
pc_ctrl <= latch_pc;
ix_ctrl <= latch_ix;
1586,7 → 2013,7
cc_ctrl <= latch_cc;
when "1111" => -- clr
right_ctrl <= zero_right;
alu_ctrl <= alu_ld8;
alu_ctrl <= alu_clr;
accb_ctrl <= load_accb;
cc_ctrl <= load_cc;
when others =>
1602,16 → 2029,17
-- EA should hold index offset
--
when "0110" => -- indexed single op
md_ctrl <= fetch_first_md;
acca_ctrl <= latch_acca;
accb_ctrl <= latch_accb;
ix_ctrl <= latch_ix;
sp_ctrl <= latch_sp;
-- increment the pc
left_ctrl <= pc_left;
right_ctrl <= plus_one_right;
alu_ctrl <= alu_add16;
left_ctrl <= acca_left;
right_ctrl <= zero_right;
alu_ctrl <= alu_nop;
cc_ctrl <= latch_cc;
pc_ctrl <= load_pc;
pc_ctrl <= inc_pc;
next_state <= indexed_state;
--
-- Single operand extended addressing
1619,29 → 2047,31
-- Low order EA holds high order address
--
when "0111" => -- extended single op
md_ctrl <= fetch_first_md;
acca_ctrl <= latch_acca;
accb_ctrl <= latch_accb;
ix_ctrl <= latch_ix;
sp_ctrl <= latch_sp;
-- increment the pc
left_ctrl <= pc_left;
right_ctrl <= plus_one_right;
alu_ctrl <= alu_add16;
left_ctrl <= acca_left;
right_ctrl <= zero_right;
alu_ctrl <= alu_nop;
cc_ctrl <= latch_cc;
pc_ctrl <= load_pc;
pc_ctrl <= inc_pc;
next_state <= extended_state;
 
when "1000" => -- acca immediate
md_ctrl <= fetch_first_md;
acca_ctrl <= latch_acca;
accb_ctrl <= latch_accb;
ix_ctrl <= latch_ix;
sp_ctrl <= latch_sp;
-- increment the pc
left_ctrl <= pc_left;
right_ctrl <= plus_one_right;
alu_ctrl <= alu_add16;
left_ctrl <= acca_left;
right_ctrl <= zero_right;
alu_ctrl <= alu_nop;
cc_ctrl <= latch_cc;
pc_ctrl <= load_pc;
pc_ctrl <= inc_pc;
case op_code(3 downto 0) is
when "0011" | -- subdd #
"1100" | -- cpx #
1650,7 → 2080,7
when "1101" => -- bsr
next_state <= bsr_state;
when others =>
next_state <= execute_state;
next_state <= fetch_state;
end case;
 
when "1001" => -- acca direct
1659,58 → 2089,78
ix_ctrl <= latch_ix;
sp_ctrl <= latch_sp;
-- increment the pc
left_ctrl <= pc_left;
right_ctrl <= plus_one_right;
alu_ctrl <= alu_add16;
cc_ctrl <= latch_cc;
pc_ctrl <= load_pc;
pc_ctrl <= inc_pc;
case op_code(3 downto 0) is
when "0111" | -- staa direct
"1111" => -- sts direct
next_state <= execute_state;
when "0111" => -- staa direct
left_ctrl <= acca_left;
right_ctrl <= zero_right;
alu_ctrl <= alu_st8;
cc_ctrl <= latch_cc;
md_ctrl <= load_md;
next_state <= write8_state;
when "1111" => -- sts direct
left_ctrl <= sp_left;
right_ctrl <= zero_right;
alu_ctrl <= alu_st16;
cc_ctrl <= latch_cc;
md_ctrl <= load_md;
next_state <= write16_state;
when "1101" => -- jsr direct
left_ctrl <= acca_left;
right_ctrl <= zero_right;
alu_ctrl <= alu_nop;
cc_ctrl <= latch_cc;
md_ctrl <= fetch_first_md;
next_state <= jsr_state;
when others =>
next_state <= direct_state;
left_ctrl <= acca_left;
right_ctrl <= zero_right;
alu_ctrl <= alu_nop;
cc_ctrl <= latch_cc;
md_ctrl <= fetch_first_md;
next_state <= read8_state;
end case;
 
when "1010" => -- acca indexed
md_ctrl <= fetch_first_md;
acca_ctrl <= latch_acca;
accb_ctrl <= latch_accb;
ix_ctrl <= latch_ix;
sp_ctrl <= latch_sp;
-- increment the pc
left_ctrl <= pc_left;
right_ctrl <= plus_one_right;
alu_ctrl <= alu_add16;
left_ctrl <= acca_left;
right_ctrl <= zero_right;
alu_ctrl <= alu_nop;
cc_ctrl <= latch_cc;
pc_ctrl <= load_pc;
pc_ctrl <= inc_pc;
next_state <= indexed_state;
 
when "1011" => -- acca extended
md_ctrl <= fetch_first_md;
acca_ctrl <= latch_acca;
accb_ctrl <= latch_accb;
ix_ctrl <= latch_ix;
sp_ctrl <= latch_sp;
-- increment the pc
left_ctrl <= pc_left;
right_ctrl <= plus_one_right;
alu_ctrl <= alu_add16;
left_ctrl <= acca_left;
right_ctrl <= zero_right;
alu_ctrl <= alu_nop;
cc_ctrl <= latch_cc;
pc_ctrl <= load_pc;
pc_ctrl <= inc_pc;
next_state <= extended_state;
 
when "1100" => -- accb immediate
md_ctrl <= fetch_first_md;
acca_ctrl <= latch_acca;
accb_ctrl <= latch_accb;
ix_ctrl <= latch_ix;
sp_ctrl <= latch_sp;
-- increment the pc
left_ctrl <= pc_left;
right_ctrl <= plus_one_right;
alu_ctrl <= alu_add16;
left_ctrl <= acca_left;
right_ctrl <= zero_right;
alu_ctrl <= alu_nop;
cc_ctrl <= latch_cc;
pc_ctrl <= load_pc;
pc_ctrl <= inc_pc;
case op_code(3 downto 0) is
when "0011" | -- addd #
"1100" | -- ldd #
1717,7 → 2167,7
"1110" => -- ldx #
next_state <= immediate16_state;
when others =>
next_state <= execute_state;
next_state <= fetch_state;
end case;
 
when "1101" => -- accb direct
1726,53 → 2176,74
ix_ctrl <= latch_ix;
sp_ctrl <= latch_sp;
-- increment the pc
left_ctrl <= pc_left;
right_ctrl <= plus_one_right;
alu_ctrl <= alu_add16;
cc_ctrl <= latch_cc;
pc_ctrl <= load_pc;
pc_ctrl <= inc_pc;
case op_code(3 downto 0) is
when "0111" | -- stab direct
"1101" | -- std direct
"1111" => -- stx direct
next_state <= execute_state;
when "0111" => -- stab direct
left_ctrl <= accb_left;
right_ctrl <= zero_right;
alu_ctrl <= alu_st8;
cc_ctrl <= latch_cc;
md_ctrl <= load_md;
next_state <= write8_state;
when "1101" => -- std direct
left_ctrl <= accd_left;
right_ctrl <= zero_right;
alu_ctrl <= alu_st16;
cc_ctrl <= latch_cc;
md_ctrl <= load_md;
next_state <= write16_state;
when "1111" => -- stx direct
left_ctrl <= ix_left;
right_ctrl <= zero_right;
alu_ctrl <= alu_st16;
cc_ctrl <= latch_cc;
md_ctrl <= load_md;
next_state <= write16_state;
when others =>
next_state <= direct_state;
left_ctrl <= acca_left;
right_ctrl <= zero_right;
alu_ctrl <= alu_nop;
cc_ctrl <= latch_cc;
md_ctrl <= fetch_first_md;
next_state <= read8_state;
end case;
 
when "1110" => -- accb indexed
md_ctrl <= fetch_first_md;
acca_ctrl <= latch_acca;
accb_ctrl <= latch_accb;
ix_ctrl <= latch_ix;
sp_ctrl <= latch_sp;
-- increment the pc
left_ctrl <= pc_left;
right_ctrl <= plus_one_right;
alu_ctrl <= alu_add16;
left_ctrl <= acca_left;
right_ctrl <= zero_right;
alu_ctrl <= alu_nop;
cc_ctrl <= latch_cc;
pc_ctrl <= load_pc;
pc_ctrl <= inc_pc;
next_state <= indexed_state;
 
when "1111" => -- accb extended
md_ctrl <= fetch_first_md;
acca_ctrl <= latch_acca;
accb_ctrl <= latch_accb;
ix_ctrl <= latch_ix;
sp_ctrl <= latch_sp;
-- increment the pc
left_ctrl <= pc_left;
right_ctrl <= plus_one_right;
alu_ctrl <= alu_add16;
left_ctrl <= acca_left;
right_ctrl <= zero_right;
alu_ctrl <= alu_nop;
cc_ctrl <= latch_cc;
pc_ctrl <= load_pc;
pc_ctrl <= inc_pc;
next_state <= extended_state;
 
when others =>
md_ctrl <= fetch_first_md;
acca_ctrl <= latch_acca;
accb_ctrl <= latch_accb;
ix_ctrl <= latch_ix;
sp_ctrl <= latch_sp;
-- idle the pc
left_ctrl <= pc_left;
left_ctrl <= acca_left;
right_ctrl <= zero_right;
alu_ctrl <= alu_nop;
cc_ctrl <= latch_cc;
1790,16 → 2261,16
nmi_ctrl <= latch_nmi;
ea_ctrl <= latch_ea;
-- increment pc
left_ctrl <= pc_left;
right_ctrl <= plus_one_right;
alu_ctrl <= alu_add16;
left_ctrl <= acca_left;
right_ctrl <= zero_right;
alu_ctrl <= alu_nop;
cc_ctrl <= latch_cc;
pc_ctrl <= load_pc;
pc_ctrl <= inc_pc;
-- fetch next immediate byte
md_ctrl <= fetch_next_md;
addr_ctrl <= fetch_ad;
dout_ctrl <= md_lo_dout;
next_state <= execute_state;
next_state <= fetch_state;
--
-- ea holds 8 bit index offet
-- calculate the effective memory address
1811,17 → 2282,12
ix_ctrl <= latch_ix;
sp_ctrl <= latch_sp;
pc_ctrl <= latch_pc;
md_ctrl <= latch_md;
iv_ctrl <= latch_iv;
op_ctrl <= latch_op;
nmi_ctrl <= latch_nmi;
-- calculate effective address from index reg
-- index offest is not sign extended
left_ctrl <= ix_left;
right_ctrl <= ea_right;
alu_ctrl <= alu_add16;
cc_ctrl <= latch_cc;
ea_ctrl <= load_ea;
ea_ctrl <= add_ix_ea;
-- idle the bus
addr_ctrl <= idle_ad;
dout_ctrl <= md_lo_dout;
1828,6 → 2294,11
-- work out next state
case op_code(7 downto 4) is
when "0110" => -- single op indexed
md_ctrl <= latch_md;
left_ctrl <= acca_left;
right_ctrl <= zero_right;
alu_ctrl <= alu_nop;
cc_ctrl <= latch_cc;
case op_code(3 downto 0) is
when "1011" => -- undefined
next_state <= fetch_state;
1834,28 → 2305,76
when "1110" => -- jmp
next_state <= jmp_state;
when others =>
next_state <= direct_state;
next_state <= read8_state;
end case;
when "1010" => -- acca indexed
case op_code(3 downto 0) is
when "0111" | -- staa
"1111" => -- sts
next_state <= execute_state;
when "0111" => -- staa
left_ctrl <= acca_left;
right_ctrl <= zero_right;
alu_ctrl <= alu_st8;
cc_ctrl <= latch_cc;
md_ctrl <= load_md;
next_state <= write8_state;
when "1101" => -- jsr
left_ctrl <= acca_left;
right_ctrl <= zero_right;
alu_ctrl <= alu_nop;
cc_ctrl <= latch_cc;
md_ctrl <= latch_md;
next_state <= jsr_state;
when "1111" => -- sts
left_ctrl <= sp_left;
right_ctrl <= zero_right;
alu_ctrl <= alu_st16;
cc_ctrl <= latch_cc;
md_ctrl <= load_md;
next_state <= write16_state;
when others =>
next_state <= direct_state;
left_ctrl <= acca_left;
right_ctrl <= zero_right;
alu_ctrl <= alu_nop;
cc_ctrl <= latch_cc;
md_ctrl <= latch_md;
next_state <= read8_state;
end case;
when "1110" => -- accb indexed
case op_code(3 downto 0) is
when "0111" | -- stab
"1101" | -- std
"1111" => -- stx
next_state <= execute_state;
when "0111" => -- stab direct
left_ctrl <= accb_left;
right_ctrl <= zero_right;
alu_ctrl <= alu_st8;
cc_ctrl <= latch_cc;
md_ctrl <= load_md;
next_state <= write8_state;
when "1101" => -- std direct
left_ctrl <= accd_left;
right_ctrl <= zero_right;
alu_ctrl <= alu_st16;
cc_ctrl <= latch_cc;
md_ctrl <= load_md;
next_state <= write16_state;
when "1111" => -- stx direct
left_ctrl <= ix_left;
right_ctrl <= zero_right;
alu_ctrl <= alu_st16;
cc_ctrl <= latch_cc;
md_ctrl <= load_md;
next_state <= write16_state;
when others =>
next_state <= direct_state;
left_ctrl <= acca_left;
right_ctrl <= zero_right;
alu_ctrl <= alu_nop;
cc_ctrl <= latch_cc;
md_ctrl <= latch_md;
next_state <= read8_state;
end case;
when others =>
md_ctrl <= latch_md;
left_ctrl <= acca_left;
right_ctrl <= zero_right;
alu_ctrl <= alu_nop;
cc_ctrl <= latch_cc;
next_state <= fetch_state;
end case;
--
1869,53 → 2388,101
accb_ctrl <= latch_accb;
ix_ctrl <= latch_ix;
sp_ctrl <= latch_sp;
md_ctrl <= latch_md;
iv_ctrl <= latch_iv;
op_ctrl <= latch_op;
nmi_ctrl <= latch_nmi;
-- increment pc
left_ctrl <= pc_left;
right_ctrl <= plus_one_right;
alu_ctrl <= alu_add16;
cc_ctrl <= latch_cc;
pc_ctrl <= load_pc;
pc_ctrl <= inc_pc;
-- fetch next effective address bytes
ea_ctrl <= fetch_next_ea;
addr_ctrl <= fetch_ad;
dout_ctrl <= md_lo_dout;
-- work out the next state
case op_code(7 downto 4) is
when "0111" => -- single op extended
case op_code(3 downto 0) is
when "1011" => -- undefined
next_state <= fetch_state;
when "1110" => -- jmp
next_state <= jmp_state;
when others =>
next_state <= direct_state;
end case;
when "1011" => -- acca extended
case op_code(3 downto 0) is
when "0111" | -- staa extended
"1111" => -- sts
next_state <= execute_state;
when "1101" => -- jsr
next_state <= jsr_state;
when others =>
next_state <= direct_state;
end case;
when "1111" => -- accb extended
case op_code(3 downto 0) is
when "0111" | -- stab extended
"1101" | -- std
"1111" => -- stx
next_state <= execute_state;
when others =>
next_state <= direct_state;
end case;
when others =>
next_state <= fetch_state;
end case;
case op_code(7 downto 4) is
when "0111" => -- single op extended
md_ctrl <= latch_md;
left_ctrl <= acca_left;
right_ctrl <= zero_right;
alu_ctrl <= alu_nop;
cc_ctrl <= latch_cc;
case op_code(3 downto 0) is
when "1011" => -- undefined
next_state <= fetch_state;
when "1110" => -- jmp
next_state <= jmp_state;
when others =>
next_state <= read8_state;
end case;
when "1011" => -- acca extended
case op_code(3 downto 0) is
when "0111" => -- staa
left_ctrl <= acca_left;
right_ctrl <= zero_right;
alu_ctrl <= alu_st8;
cc_ctrl <= latch_cc;
md_ctrl <= load_md;
next_state <= write8_state;
when "1101" => -- jsr
left_ctrl <= acca_left;
right_ctrl <= zero_right;
alu_ctrl <= alu_nop;
cc_ctrl <= latch_cc;
md_ctrl <= latch_md;
next_state <= jsr_state;
when "1111" => -- sts
left_ctrl <= sp_left;
right_ctrl <= zero_right;
alu_ctrl <= alu_st16;
cc_ctrl <= latch_cc;
md_ctrl <= load_md;
next_state <= write16_state;
when others =>
left_ctrl <= acca_left;
right_ctrl <= zero_right;
alu_ctrl <= alu_nop;
cc_ctrl <= latch_cc;
md_ctrl <= latch_md;
next_state <= read8_state;
end case;
when "1111" => -- accb extended
case op_code(3 downto 0) is
when "0111" => -- stab
left_ctrl <= accb_left;
right_ctrl <= zero_right;
alu_ctrl <= alu_st8;
cc_ctrl <= latch_cc;
md_ctrl <= load_md;
next_state <= write8_state;
when "1101" => -- std
left_ctrl <= accd_left;
right_ctrl <= zero_right;
alu_ctrl <= alu_st16;
cc_ctrl <= latch_cc;
md_ctrl <= load_md;
next_state <= write16_state;
when "1111" => -- stx
left_ctrl <= ix_left;
right_ctrl <= zero_right;
alu_ctrl <= alu_st16;
cc_ctrl <= latch_cc;
md_ctrl <= load_md;
next_state <= write16_state;
when others =>
left_ctrl <= acca_left;
right_ctrl <= zero_right;
alu_ctrl <= alu_nop;
cc_ctrl <= latch_cc;
md_ctrl <= latch_md;
next_state <= read8_state;
end case;
when others =>
md_ctrl <= latch_md;
left_ctrl <= acca_left;
right_ctrl <= zero_right;
alu_ctrl <= alu_nop;
cc_ctrl <= latch_cc;
next_state <= fetch_state;
end case;
--
-- here if ea holds low byte (direct page)
-- can enter here from extended addressing
1922,7 → 2489,7
-- read memory location
-- note that reads may be 8 or 16 bits
--
when direct_state => -- read data
when read8_state => -- read data
acca_ctrl <= latch_acca;
accb_ctrl <= latch_accb;
ix_ctrl <= latch_ix;
1931,68 → 2498,123
iv_ctrl <= latch_iv;
op_ctrl <= latch_op;
nmi_ctrl <= latch_nmi;
-- read first data byte from ea
md_ctrl <= fetch_first_md;
--
addr_ctrl <= read_ad;
dout_ctrl <= md_lo_dout;
case op_code(7 downto 4) is
when "0110" | "0111" => -- single operand
left_ctrl <= ea_left;
left_ctrl <= acca_left;
right_ctrl <= zero_right;
alu_ctrl <= alu_nop;
cc_ctrl <= latch_cc;
md_ctrl <= fetch_first_md;
ea_ctrl <= latch_ea;
next_state <= execute_state;
 
when "1001" | "1010" | "1011" => -- acca
case op_code(3 downto 0) is
when "0011" | -- subd
"1110" | -- lds
"1100" => -- cpx
left_ctrl <= acca_left;
right_ctrl <= zero_right;
alu_ctrl <= alu_nop;
cc_ctrl <= latch_cc;
md_ctrl <= fetch_first_md;
-- increment the effective address in case of 16 bit load
left_ctrl <= ea_left;
right_ctrl <= plus_one_right;
alu_ctrl <= alu_add16;
cc_ctrl <= latch_cc;
ea_ctrl <= load_ea;
next_state <= direct16_state;
ea_ctrl <= inc_ea;
next_state <= read16_state;
-- when "0111" => -- staa
-- left_ctrl <= acca_left;
-- right_ctrl <= zero_right;
-- alu_ctrl <= alu_st8;
-- cc_ctrl <= latch_cc;
-- md_ctrl <= load_md;
-- ea_ctrl <= latch_ea;
-- next_state <= write8_state;
-- when "1101" => -- jsr
-- left_ctrl <= acca_left;
-- right_ctrl <= zero_right;
-- alu_ctrl <= alu_nop;
-- cc_ctrl <= latch_cc;
-- md_ctrl <= latch_md;
-- ea_ctrl <= latch_ea;
-- next_state <= jsr_state;
-- when "1111" => -- sts
-- left_ctrl <= sp_left;
-- right_ctrl <= zero_right;
-- alu_ctrl <= alu_st16;
-- cc_ctrl <= latch_cc;
-- md_ctrl <= load_md;
-- ea_ctrl <= latch_ea;
-- next_state <= write16_state;
when others =>
left_ctrl <= ea_left;
left_ctrl <= acca_left;
right_ctrl <= zero_right;
alu_ctrl <= alu_nop;
cc_ctrl <= latch_cc;
ea_ctrl <= latch_ea;
next_state <= execute_state;
md_ctrl <= fetch_first_md;
ea_ctrl <= latch_ea;
next_state <= fetch_state;
end case;
 
when "1101" | "1110" | "1111" => -- accb
case op_code(3 downto 0) is
when "0011" | -- addd
"1100" | -- ldd
"1110" => -- ldx
left_ctrl <= acca_left;
right_ctrl <= zero_right;
alu_ctrl <= alu_nop;
cc_ctrl <= latch_cc;
md_ctrl <= fetch_first_md;
-- increment the effective address in case of 16 bit load
left_ctrl <= ea_left;
right_ctrl <= plus_one_right;
alu_ctrl <= alu_add16;
cc_ctrl <= latch_cc;
ea_ctrl <= load_ea;
next_state <= direct16_state;
ea_ctrl <= inc_ea;
next_state <= read16_state;
-- when "0111" => -- stab
-- left_ctrl <= accb_left;
-- right_ctrl <= zero_right;
-- alu_ctrl <= alu_st8;
-- cc_ctrl <= latch_cc;
-- md_ctrl <= load_md;
-- ea_ctrl <= latch_ea;
-- next_state <= write8_state;
-- when "1101" => -- std
-- left_ctrl <= accd_left;
-- right_ctrl <= zero_right;
-- alu_ctrl <= alu_st16;
-- cc_ctrl <= latch_cc;
-- md_ctrl <= load_md;
-- ea_ctrl <= latch_ea;
-- next_state <= write16_state;
-- when "1111" => -- stx
-- left_ctrl <= ix_left;
-- right_ctrl <= zero_right;
-- alu_ctrl <= alu_st16;
-- cc_ctrl <= latch_cc;
-- md_ctrl <= load_md;
-- ea_ctrl <= latch_ea;
-- next_state <= write16_state;
when others =>
left_ctrl <= ea_left;
left_ctrl <= acca_left;
right_ctrl <= zero_right;
alu_ctrl <= alu_nop;
cc_ctrl <= latch_cc;
md_ctrl <= fetch_first_md;
ea_ctrl <= latch_ea;
next_state <= execute_state;
end case;
when others =>
left_ctrl <= ea_left;
left_ctrl <= acca_left;
right_ctrl <= zero_right;
alu_ctrl <= alu_nop;
cc_ctrl <= latch_cc;
md_ctrl <= fetch_first_md;
ea_ctrl <= latch_ea;
next_state <= fetch_state;
end case;
 
when direct16_state => -- read second data byte from ea
when read16_state => -- read second data byte from ea
-- default
acca_ctrl <= latch_acca;
accb_ctrl <= latch_accb;
2002,17 → 2624,69
iv_ctrl <= latch_iv;
op_ctrl <= latch_op;
nmi_ctrl <= latch_nmi;
-- idle the effective address
left_ctrl <= ea_left;
right_ctrl <= plus_one_right;
left_ctrl <= acca_left;
right_ctrl <= zero_right;
alu_ctrl <= alu_nop;
cc_ctrl <= latch_cc;
-- idle the effective address
ea_ctrl <= latch_ea;
-- read the low byte of the 16 bit data
md_ctrl <= fetch_next_md;
addr_ctrl <= read_ad;
dout_ctrl <= md_lo_dout;
next_state <= execute_state;
next_state <= fetch_state;
--
-- 16 bit Write state
-- write high byte of ALU output.
-- EA hold address of memory to write to
-- Advance the effective address in ALU
--
when write16_state =>
-- default
acca_ctrl <= latch_acca;
accb_ctrl <= latch_accb;
ix_ctrl <= latch_ix;
sp_ctrl <= latch_sp;
pc_ctrl <= latch_pc;
md_ctrl <= latch_md;
iv_ctrl <= latch_iv;
op_ctrl <= latch_op;
nmi_ctrl <= latch_nmi;
-- increment the effective address
left_ctrl <= acca_left;
right_ctrl <= zero_right;
alu_ctrl <= alu_nop;
cc_ctrl <= latch_cc;
ea_ctrl <= inc_ea;
-- write the ALU hi byte to ea
addr_ctrl <= write_ad;
dout_ctrl <= md_hi_dout;
next_state <= write8_state;
--
-- 8 bit write
-- Write low 8 bits of ALU output
--
when write8_state =>
-- default registers
acca_ctrl <= latch_acca;
accb_ctrl <= latch_accb;
ix_ctrl <= latch_ix;
sp_ctrl <= latch_sp;
pc_ctrl <= latch_pc;
md_ctrl <= latch_md;
iv_ctrl <= latch_iv;
op_ctrl <= latch_op;
nmi_ctrl <= latch_nmi;
ea_ctrl <= latch_ea;
-- idle the ALU
left_ctrl <= acca_left;
right_ctrl <= zero_right;
alu_ctrl <= alu_nop;
cc_ctrl <= latch_cc;
-- write ALU low byte output
addr_ctrl <= write_ad;
dout_ctrl <= md_lo_dout;
next_state <= fetch_state;
 
when jmp_state =>
acca_ctrl <= latch_acca;
2025,11 → 2699,11
nmi_ctrl <= latch_nmi;
ea_ctrl <= latch_ea;
-- load PC with effective address
left_ctrl <= pc_left;
right_ctrl <= ea_right;
alu_ctrl <= alu_ld16;
left_ctrl <= acca_left;
right_ctrl <= zero_right;
alu_ctrl <= alu_nop;
cc_ctrl <= latch_cc;
pc_ctrl <= load_pc;
pc_ctrl <= load_ea_pc;
-- idle the bus
addr_ctrl <= idle_ad;
dout_ctrl <= md_lo_dout;
2090,11 → 2764,11
nmi_ctrl <= latch_nmi;
ea_ctrl <= latch_ea;
-- calculate signed branch
left_ctrl <= pc_left;
right_ctrl <= sexea_right; -- right must be sign extended effective address
alu_ctrl <= alu_add16;
left_ctrl <= acca_left;
right_ctrl <= zero_right;
alu_ctrl <= alu_nop;
cc_ctrl <= latch_cc;
pc_ctrl <= load_pc;
pc_ctrl <= add_ea_pc;
-- idle the bus
addr_ctrl <= idle_ad;
dout_ctrl <= md_lo_dout;
2222,12 → 2896,13
op_ctrl <= latch_op;
nmi_ctrl <= latch_nmi;
md_ctrl <= latch_md;
-- move accb to ea
left_ctrl <= accb_left;
-- idle ALU
left_ctrl <= acca_left;
right_ctrl <= zero_right;
alu_ctrl <= alu_st16;
alu_ctrl <= alu_nop;
cc_ctrl <= latch_cc;
ea_ctrl <= load_ea;
-- move accb to ea
ea_ctrl <= load_accb_ea;
-- idle bus
addr_ctrl <= idle_ad;
dout_ctrl <= md_lo_dout;
2479,35 → 3154,11
dout_ctrl <= md_lo_dout;
next_state <= fetch_state;
 
when execute_state => -- execute
when execute_state => -- execute single operand instruction
-- default
op_ctrl <= latch_op;
nmi_ctrl <= latch_nmi;
case op_code(7 downto 4) is
when "0000" |
"0001" |
"0010" | -- branch conditional
"0011" |
"0100" | -- acca single op
"0101" => -- accb single op
acca_ctrl <= latch_acca;
accb_ctrl <= latch_accb;
ix_ctrl <= latch_ix;
sp_ctrl <= latch_sp;
pc_ctrl <= latch_pc;
md_ctrl <= latch_md;
iv_ctrl <= latch_iv;
ea_ctrl <= latch_ea;
-- idle ALU
left_ctrl <= acca_left;
right_ctrl <= zero_right;
alu_ctrl <= alu_nop;
cc_ctrl <= latch_cc;
-- idle bus
addr_ctrl <= idle_ad;
dout_ctrl <= md_lo_dout;
next_state <= fetch_state;
 
when "0110" | -- indexed single op
"0111" => -- extended single op
acca_ctrl <= latch_acca;
2520,9 → 3171,9
-- idle the bus
addr_ctrl <= idle_ad;
dout_ctrl <= md_lo_dout;
left_ctrl <= md_left;
case op_code(3 downto 0) is
when "0000" => -- neg
left_ctrl <= md_left;
right_ctrl <= zero_right;
alu_ctrl <= alu_neg;
cc_ctrl <= load_cc;
2529,7 → 3180,6
md_ctrl <= load_md;
next_state <= write8_state;
when "0011" => -- com
left_ctrl <= md_left;
right_ctrl <= zero_right;
alu_ctrl <= alu_com;
cc_ctrl <= load_cc;
2536,7 → 3186,6
md_ctrl <= load_md;
next_state <= write8_state;
when "0100" => -- lsr
left_ctrl <= md_left;
right_ctrl <= zero_right;
alu_ctrl <= alu_lsr8;
cc_ctrl <= load_cc;
2543,7 → 3192,6
md_ctrl <= load_md;
next_state <= write8_state;
when "0110" => -- ror
left_ctrl <= md_left;
right_ctrl <= zero_right;
alu_ctrl <= alu_ror8;
cc_ctrl <= load_cc;
2550,7 → 3198,6
md_ctrl <= load_md;
next_state <= write8_state;
when "0111" => -- asr
left_ctrl <= md_left;
right_ctrl <= zero_right;
alu_ctrl <= alu_asr8;
cc_ctrl <= load_cc;
2557,7 → 3204,6
md_ctrl <= load_md;
next_state <= write8_state;
when "1000" => -- asl
left_ctrl <= md_left;
right_ctrl <= zero_right;
alu_ctrl <= alu_asl8;
cc_ctrl <= load_cc;
2564,7 → 3210,6
md_ctrl <= load_md;
next_state <= write8_state;
when "1001" => -- rol
left_ctrl <= md_left;
right_ctrl <= zero_right;
alu_ctrl <= alu_rol8;
cc_ctrl <= load_cc;
2571,7 → 3216,6
md_ctrl <= load_md;
next_state <= write8_state;
when "1010" => -- dec
left_ctrl <= md_left;
right_ctrl <= plus_one_right;
alu_ctrl <= alu_dec;
cc_ctrl <= load_cc;
2578,7 → 3222,6
md_ctrl <= load_md;
next_state <= write8_state;
when "1011" => -- undefined
left_ctrl <= md_left;
right_ctrl <= zero_right;
alu_ctrl <= alu_nop;
cc_ctrl <= latch_cc;
2585,7 → 3228,6
md_ctrl <= latch_md;
next_state <= fetch_state;
when "1100" => -- inc
left_ctrl <= md_left;
right_ctrl <= plus_one_right;
alu_ctrl <= alu_inc;
cc_ctrl <= load_cc;
2592,7 → 3234,6
md_ctrl <= load_md;
next_state <= write8_state;
when "1101" => -- tst
left_ctrl <= md_left;
right_ctrl <= zero_right;
alu_ctrl <= alu_st8;
cc_ctrl <= load_cc;
2599,7 → 3240,6
md_ctrl <= latch_md;
next_state <= fetch_state;
when "1110" => -- jmp
left_ctrl <= md_left;
right_ctrl <= zero_right;
alu_ctrl <= alu_nop;
cc_ctrl <= latch_cc;
2606,14 → 3246,12
md_ctrl <= latch_md;
next_state <= fetch_state;
when "1111" => -- clr
left_ctrl <= md_left;
right_ctrl <= zero_right;
alu_ctrl <= alu_ld8;
alu_ctrl <= alu_clr;
cc_ctrl <= load_cc;
md_ctrl <= load_md;
next_state <= write8_state;
when others =>
left_ctrl <= md_left;
right_ctrl <= zero_right;
alu_ctrl <= alu_nop;
cc_ctrl <= latch_cc;
2621,404 → 3259,6
next_state <= fetch_state;
end case;
 
when "1000" | -- acca immediate
"1001" | -- acca direct
"1010" | -- acca indexed
"1011" => -- acca extended
pc_ctrl <= latch_pc;
iv_ctrl <= latch_iv;
ea_ctrl <= latch_ea;
-- idle the bus
addr_ctrl <= idle_ad;
dout_ctrl <= md_lo_dout;
case op_code(3 downto 0) is
when "0000" => -- suba
left_ctrl <= acca_left;
right_ctrl <= md_right;
alu_ctrl <= alu_sub8;
cc_ctrl <= load_cc;
acca_ctrl <= load_acca;
accb_ctrl <= latch_accb;
ix_ctrl <= latch_ix;
sp_ctrl <= latch_sp;
md_ctrl <= latch_md;
next_state <= fetch_state;
when "0001" => -- cmpa
left_ctrl <= acca_left;
right_ctrl <= md_right;
alu_ctrl <= alu_sub8;
cc_ctrl <= load_cc;
acca_ctrl <= latch_acca;
accb_ctrl <= latch_accb;
ix_ctrl <= latch_ix;
sp_ctrl <= latch_sp;
md_ctrl <= latch_md;
next_state <= fetch_state;
when "0010" => -- sbca
left_ctrl <= acca_left;
right_ctrl <= md_right;
alu_ctrl <= alu_sbc;
cc_ctrl <= load_cc;
acca_ctrl <= load_acca;
accb_ctrl <= latch_accb;
ix_ctrl <= latch_ix;
sp_ctrl <= latch_sp;
md_ctrl <= latch_md;
next_state <= fetch_state;
when "0011" => -- subd
left_ctrl <= accd_left;
right_ctrl <= md_right;
alu_ctrl <= alu_sub16;
cc_ctrl <= load_cc;
acca_ctrl <= load_hi_acca;
accb_ctrl <= load_accb;
ix_ctrl <= latch_ix;
sp_ctrl <= latch_sp;
md_ctrl <= latch_md;
next_state <= fetch_state;
when "0100" => -- anda
left_ctrl <= acca_left;
right_ctrl <= md_right;
alu_ctrl <= alu_and;
cc_ctrl <= load_cc;
acca_ctrl <= load_acca;
accb_ctrl <= latch_accb;
ix_ctrl <= latch_ix;
sp_ctrl <= latch_sp;
md_ctrl <= latch_md;
next_state <= fetch_state;
when "0101" => -- bita
left_ctrl <= acca_left;
right_ctrl <= md_right;
alu_ctrl <= alu_and;
cc_ctrl <= load_cc;
acca_ctrl <= latch_acca;
accb_ctrl <= latch_accb;
ix_ctrl <= latch_ix;
sp_ctrl <= latch_sp;
md_ctrl <= latch_md;
next_state <= fetch_state;
when "0110" => -- ldaa
left_ctrl <= acca_left;
right_ctrl <= md_right;
alu_ctrl <= alu_ld8;
cc_ctrl <= load_cc;
acca_ctrl <= load_acca;
accb_ctrl <= latch_accb;
ix_ctrl <= latch_ix;
sp_ctrl <= latch_sp;
md_ctrl <= latch_md;
next_state <= fetch_state;
when "0111" => -- staa
left_ctrl <= acca_left;
right_ctrl <= md_right;
alu_ctrl <= alu_st8;
cc_ctrl <= load_cc;
acca_ctrl <= latch_acca;
accb_ctrl <= latch_accb;
ix_ctrl <= latch_ix;
sp_ctrl <= latch_sp;
md_ctrl <= load_md;
next_state <= write8_state;
when "1000" => -- eora
left_ctrl <= acca_left;
right_ctrl <= md_right;
alu_ctrl <= alu_eor;
cc_ctrl <= load_cc;
acca_ctrl <= load_acca;
accb_ctrl <= latch_accb;
ix_ctrl <= latch_ix;
sp_ctrl <= latch_sp;
md_ctrl <= latch_md;
next_state <= fetch_state;
when "1001" => -- adca
left_ctrl <= acca_left;
right_ctrl <= md_right;
alu_ctrl <= alu_adc;
cc_ctrl <= load_cc;
acca_ctrl <= load_acca;
accb_ctrl <= latch_accb;
ix_ctrl <= latch_ix;
sp_ctrl <= latch_sp;
md_ctrl <= latch_md;
next_state <= fetch_state;
when "1010" => -- oraa
left_ctrl <= acca_left;
right_ctrl <= md_right;
alu_ctrl <= alu_ora;
cc_ctrl <= load_cc;
acca_ctrl <= load_acca;
accb_ctrl <= latch_accb;
ix_ctrl <= latch_ix;
sp_ctrl <= latch_sp;
md_ctrl <= latch_md;
next_state <= fetch_state;
when "1011" => -- adda
left_ctrl <= acca_left;
right_ctrl <= md_right;
alu_ctrl <= alu_add8;
cc_ctrl <= load_cc;
acca_ctrl <= load_acca;
accb_ctrl <= latch_accb;
ix_ctrl <= latch_ix;
sp_ctrl <= latch_sp;
md_ctrl <= latch_md;
next_state <= fetch_state;
when "1100" => -- cpx
left_ctrl <= ix_left;
right_ctrl <= md_right;
alu_ctrl <= alu_cpx;
cc_ctrl <= load_cc;
acca_ctrl <= latch_acca;
accb_ctrl <= latch_accb;
ix_ctrl <= latch_ix;
sp_ctrl <= latch_sp;
md_ctrl <= latch_md;
next_state <= fetch_state;
when "1101" => -- bsr / jsr
left_ctrl <= pc_left;
right_ctrl <= md_right;
alu_ctrl <= alu_nop;
cc_ctrl <= latch_cc;
acca_ctrl <= latch_acca;
accb_ctrl <= latch_accb;
ix_ctrl <= latch_ix;
sp_ctrl <= latch_sp;
md_ctrl <= latch_md;
next_state <= fetch_state;
when "1110" => -- lds
left_ctrl <= sp_left;
right_ctrl <= md_right;
alu_ctrl <= alu_ld16;
cc_ctrl <= load_cc;
acca_ctrl <= latch_acca;
accb_ctrl <= latch_accb;
ix_ctrl <= latch_ix;
sp_ctrl <= load_sp;
md_ctrl <= latch_md;
next_state <= fetch_state;
when "1111" => -- sts
left_ctrl <= sp_left;
right_ctrl <= md_right;
alu_ctrl <= alu_st16;
cc_ctrl <= load_cc;
acca_ctrl <= latch_acca;
accb_ctrl <= latch_accb;
ix_ctrl <= latch_ix;
sp_ctrl <= latch_sp;
md_ctrl <= load_md;
next_state <= write16_state;
when others =>
left_ctrl <= acca_left;
right_ctrl <= md_right;
alu_ctrl <= alu_nop;
cc_ctrl <= latch_cc;
acca_ctrl <= latch_acca;
accb_ctrl <= latch_accb;
ix_ctrl <= latch_ix;
sp_ctrl <= latch_sp;
md_ctrl <= latch_md;
next_state <= fetch_state;
end case;
when "1100" | -- accb immediate
"1101" | -- accb direct
"1110" | -- accb indexed
"1111" => -- accb extended
pc_ctrl <= latch_pc;
iv_ctrl <= latch_iv;
ea_ctrl <= latch_ea;
-- idle the bus
addr_ctrl <= idle_ad;
dout_ctrl <= md_lo_dout;
case op_code(3 downto 0) is
when "0000" => -- subb
left_ctrl <= accb_left;
right_ctrl <= md_right;
alu_ctrl <= alu_sub8;
cc_ctrl <= load_cc;
acca_ctrl <= latch_acca;
accb_ctrl <= load_accb;
ix_ctrl <= latch_ix;
sp_ctrl <= latch_sp;
md_ctrl <= latch_md;
next_state <= fetch_state;
when "0001" => -- cmpb
left_ctrl <= accb_left;
right_ctrl <= md_right;
alu_ctrl <= alu_sub8;
cc_ctrl <= load_cc;
acca_ctrl <= latch_acca;
accb_ctrl <= latch_accb;
ix_ctrl <= latch_ix;
sp_ctrl <= latch_sp;
md_ctrl <= latch_md;
next_state <= fetch_state;
when "0010" => -- sbcb
left_ctrl <= accb_left;
right_ctrl <= md_right;
alu_ctrl <= alu_sbc;
cc_ctrl <= load_cc;
acca_ctrl <= latch_acca;
accb_ctrl <= load_accb;
ix_ctrl <= latch_ix;
sp_ctrl <= latch_sp;
md_ctrl <= latch_md;
next_state <= fetch_state;
when "0011" => -- addd
left_ctrl <= accd_left;
right_ctrl <= md_right;
alu_ctrl <= alu_add16;
cc_ctrl <= load_cc;
acca_ctrl <= load_hi_acca;
accb_ctrl <= load_accb;
ix_ctrl <= latch_ix;
sp_ctrl <= latch_sp;
md_ctrl <= latch_md;
next_state <= fetch_state;
when "0100" => -- andb
left_ctrl <= accb_left;
right_ctrl <= md_right;
alu_ctrl <= alu_and;
cc_ctrl <= load_cc;
acca_ctrl <= latch_acca;
accb_ctrl <= load_accb;
ix_ctrl <= latch_ix;
sp_ctrl <= latch_sp;
md_ctrl <= latch_md;
next_state <= fetch_state;
when "0101" => -- bitb
left_ctrl <= accb_left;
right_ctrl <= md_right;
alu_ctrl <= alu_and;
cc_ctrl <= load_cc;
acca_ctrl <= latch_acca;
accb_ctrl <= latch_accb;
ix_ctrl <= latch_ix;
sp_ctrl <= latch_sp;
md_ctrl <= latch_md;
next_state <= fetch_state;
when "0110" => -- ldab
left_ctrl <= accb_left;
right_ctrl <= md_right;
alu_ctrl <= alu_ld8;
cc_ctrl <= load_cc;
acca_ctrl <= latch_acca;
accb_ctrl <= load_accb;
ix_ctrl <= latch_ix;
sp_ctrl <= latch_sp;
md_ctrl <= latch_md;
next_state <= fetch_state;
when "0111" => -- stab
left_ctrl <= accb_left;
right_ctrl <= md_right;
alu_ctrl <= alu_st8;
cc_ctrl <= load_cc;
acca_ctrl <= latch_acca;
accb_ctrl <= latch_accb;
ix_ctrl <= latch_ix;
sp_ctrl <= latch_sp;
md_ctrl <= load_md;
next_state <= write8_state;
when "1000" => -- eorb
left_ctrl <= accb_left;
right_ctrl <= md_right;
alu_ctrl <= alu_eor;
cc_ctrl <= load_cc;
acca_ctrl <= latch_acca;
accb_ctrl <= load_accb;
ix_ctrl <= latch_ix;
sp_ctrl <= latch_sp;
md_ctrl <= latch_md;
next_state <= fetch_state;
when "1001" => -- adcb
left_ctrl <= accb_left;
right_ctrl <= md_right;
alu_ctrl <= alu_adc;
cc_ctrl <= load_cc;
acca_ctrl <= latch_acca;
accb_ctrl <= load_accb;
ix_ctrl <= latch_ix;
sp_ctrl <= latch_sp;
md_ctrl <= latch_md;
next_state <= fetch_state;
when "1010" => -- orab
left_ctrl <= accb_left;
right_ctrl <= md_right;
alu_ctrl <= alu_ora;
cc_ctrl <= load_cc;
acca_ctrl <= latch_acca;
accb_ctrl <= load_accb;
ix_ctrl <= latch_ix;
sp_ctrl <= latch_sp;
md_ctrl <= latch_md;
next_state <= fetch_state;
when "1011" => -- addb
left_ctrl <= accb_left;
right_ctrl <= md_right;
alu_ctrl <= alu_add8;
cc_ctrl <= load_cc;
acca_ctrl <= latch_acca;
accb_ctrl <= load_accb;
ix_ctrl <= latch_ix;
sp_ctrl <= latch_sp;
md_ctrl <= latch_md;
next_state <= fetch_state;
when "1100" => -- ldd
left_ctrl <= accd_left;
right_ctrl <= md_right;
alu_ctrl <= alu_ld16;
cc_ctrl <= load_cc;
acca_ctrl <= load_hi_acca;
accb_ctrl <= load_accb;
ix_ctrl <= latch_ix;
sp_ctrl <= latch_sp;
md_ctrl <= latch_md;
next_state <= fetch_state;
when "1101" => -- std
left_ctrl <= accd_left;
right_ctrl <= md_right;
alu_ctrl <= alu_st16;
cc_ctrl <= latch_cc;
acca_ctrl <= latch_acca;
accb_ctrl <= latch_accb;
ix_ctrl <= latch_ix;
sp_ctrl <= latch_sp;
md_ctrl <= load_md;
next_state <= write16_state;
when "1110" => -- ldx
left_ctrl <= ix_left;
right_ctrl <= md_right;
alu_ctrl <= alu_ld16;
cc_ctrl <= load_cc;
acca_ctrl <= latch_acca;
accb_ctrl <= latch_accb;
ix_ctrl <= load_ix;
sp_ctrl <= latch_sp;
md_ctrl <= latch_md;
next_state <= fetch_state;
when "1111" => -- stx
left_ctrl <= ix_left;
right_ctrl <= md_right;
alu_ctrl <= alu_st16;
cc_ctrl <= load_cc;
acca_ctrl <= latch_acca;
accb_ctrl <= latch_accb;
ix_ctrl <= latch_ix;
sp_ctrl <= latch_sp;
md_ctrl <= load_md;
next_state <= write16_state;
when others =>
left_ctrl <= accb_left;
right_ctrl <= md_right;
alu_ctrl <= alu_nop;
cc_ctrl <= latch_cc;
acca_ctrl <= latch_acca;
accb_ctrl <= latch_accb;
ix_ctrl <= latch_ix;
sp_ctrl <= latch_sp;
md_ctrl <= latch_md;
next_state <= fetch_state;
end case;
when others =>
left_ctrl <= accd_left;
right_ctrl <= md_right;
3028,67 → 3268,15
accb_ctrl <= latch_accb;
ix_ctrl <= latch_ix;
sp_ctrl <= latch_sp;
pc_ctrl <= latch_pc;
md_ctrl <= latch_md;
iv_ctrl <= latch_iv;
ea_ctrl <= latch_ea;
pc_ctrl <= latch_pc;
md_ctrl <= latch_md;
iv_ctrl <= latch_iv;
ea_ctrl <= latch_ea;
-- idle the bus
addr_ctrl <= idle_ad;
dout_ctrl <= md_lo_dout;
next_state <= fetch_state;
end case;
--
-- 16 bit Write state
-- write high byte of ALU output.
-- EA hold address of memory to write to
-- Advance the effective address in ALU
--
when write16_state =>
-- default
acca_ctrl <= latch_acca;
accb_ctrl <= latch_accb;
ix_ctrl <= latch_ix;
sp_ctrl <= latch_sp;
pc_ctrl <= latch_pc;
md_ctrl <= latch_md;
iv_ctrl <= latch_iv;
op_ctrl <= latch_op;
nmi_ctrl <= latch_nmi;
-- increment the effective address
left_ctrl <= ea_left;
right_ctrl <= plus_one_right;
alu_ctrl <= alu_add16;
cc_ctrl <= latch_cc;
ea_ctrl <= load_ea;
-- write the ALU hi byte to ea
addr_ctrl <= write_ad;
dout_ctrl <= md_hi_dout;
next_state <= write8_state;
--
-- 8 bit write
-- Write low 8 bits of ALU output
--
when write8_state =>
-- default registers
acca_ctrl <= latch_acca;
accb_ctrl <= latch_accb;
ix_ctrl <= latch_ix;
sp_ctrl <= latch_sp;
pc_ctrl <= latch_pc;
md_ctrl <= latch_md;
iv_ctrl <= latch_iv;
op_ctrl <= latch_op;
nmi_ctrl <= latch_nmi;
ea_ctrl <= latch_ea;
-- idle the ALU
left_ctrl <= acca_left;
right_ctrl <= zero_right;
alu_ctrl <= alu_nop;
cc_ctrl <= latch_cc;
-- write ALU low byte output
addr_ctrl <= write_ad;
dout_ctrl <= md_lo_dout;
next_state <= fetch_state;
 
when psha_state =>
-- default registers
3701,7 → 3889,7
dout_ctrl <= md_lo_dout;
next_state <= vect_hi_state;
 
when others => -- halt on undefine states
when halt_state => -- halt CPU.
-- default
acca_ctrl <= latch_acca;
accb_ctrl <= latch_accb;
3721,7 → 3909,33
-- idle bus cycle
addr_ctrl <= idle_ad;
dout_ctrl <= md_lo_dout;
next_state <= halt_state;
if halt = '1' then
next_state <= halt_state;
else
next_state <= fetch_state;
end if;
 
when others => -- error state halt on undefine states
-- default
acca_ctrl <= latch_acca;
accb_ctrl <= latch_accb;
ix_ctrl <= latch_ix;
sp_ctrl <= latch_sp;
pc_ctrl <= latch_pc;
md_ctrl <= latch_md;
iv_ctrl <= latch_iv;
op_ctrl <= latch_op;
nmi_ctrl <= latch_nmi;
ea_ctrl <= latch_ea;
-- do nothing in ALU
left_ctrl <= acca_left;
right_ctrl <= zero_right;
alu_ctrl <= alu_nop;
cc_ctrl <= latch_cc;
-- idle bus cycle
addr_ctrl <= idle_ad;
dout_ctrl <= md_lo_dout;
next_state <= error_state;
end case;
end process;
 
3731,12 → 3945,14
--
--------------------------------
 
change_state: process( clk, rst, state )
change_state: process( clk, rst, state, hold )
begin
if clk'event and clk = '1' then
if clk'event and clk = '0' then
if rst = '1' then
state <= reset_state;
else
elsif hold = '1' then
state <= state;
else
state <= next_state;
end if;
end if;
/trunk/vhdl/trap.vhd
0,0 → 1,288
--===========================================================================--
--
-- S Y N T H E Z I A B L E Timer C O R E
--
-- www.OpenCores.Org - May 2003
-- This core adheres to the GNU public license
--
-- File name : Trap.vhd
--
-- entity name : trap
--
-- Purpose : Implements a 8 bit address and data comparitor module
--
-- Dependencies : ieee.Std_Logic_1164
-- ieee.std_logic_unsigned
--
-- Author : John E. Kent
--
--===========================================================================----
--
-- Revision History:
--
-- Date: Revision Author
-- 5 May 2003 0.1 John Kent
--
--===========================================================================----
--
-- Register Memory Map
--
-- $00 - Address Comparitor High Byte
-- $01 - Address Comparitor Low byte
-- $02 - Data Comparitor
-- $03 - Control Comparitor
-- $04 - Address Qualifier High Byte
-- $05 - Address Qualifier Low byte
-- $06 - Data Qualifier
-- $07 - Control Qualifier
--
-- Address, Data and Control signals must match in the Comparitor registers
-- Matches are qualified by setting a bit in the Qualifier registers
--
-- Control Comparitor / Qualify (write)
-- b0 - r/w 1=read 0=write
-- b1 - vma 1=valid 0=invalid
-- b7 - irq output 1=match 0=mismatch
--
-- Control Qualifier Read
-- b7 - match flag
--
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
 
entity trap is
port (
clk : in std_logic;
rst : in std_logic;
cs : in std_logic;
rw : in std_logic;
vma : in std_logic;
addr : in std_logic_vector(15 downto 0);
data_in : in std_logic_vector(7 downto 0);
data_out : out std_logic_vector(7 downto 0);
irq : out std_logic
);
end;
 
architecture trap_arch of trap is
 
--
-- Trap registers
--
signal comp_addr_hi : std_logic_vector(7 downto 0);
signal comp_addr_lo : std_logic_vector(7 downto 0);
signal qual_addr_hi : std_logic_vector(7 downto 0);
signal qual_addr_lo : std_logic_vector(7 downto 0);
signal comp_data : std_logic_vector(7 downto 0);
signal qual_data : std_logic_vector(7 downto 0);
signal comp_ctrl : std_logic_vector(7 downto 0);
signal qual_ctrl : std_logic_vector(7 downto 0);
signal match_flag : std_logic;
begin
 
 
--------------------------------
--
-- write control registers
--
--------------------------------
trap_write : process( clk, rst, cs, rw, addr, data_in,
comp_addr_hi, comp_addr_lo, comp_data, comp_ctrl,
qual_addr_hi, qual_addr_lo, qual_data, qual_ctrl )
begin
if clk'event and clk = '0' then
if rst = '1' then
comp_addr_hi <= "00000000";
comp_addr_lo <= "00000000";
comp_data <= "00000000";
comp_ctrl <= "00000000";
qual_addr_hi <= "00000000";
qual_addr_lo <= "00000000";
qual_data <= "00000000";
qual_ctrl <= "00000000";
elsif cs = '1' and rw = '0' then
case addr(2 downto 0) is
when "000" =>
comp_addr_hi <= data_in;
comp_addr_lo <= comp_addr_lo;
comp_data <= comp_data;
comp_ctrl <= comp_ctrl;
qual_addr_hi <= qual_addr_hi;
qual_addr_lo <= qual_addr_lo;
qual_data <= qual_data;
qual_ctrl <= qual_ctrl;
when "001" =>
comp_addr_hi <= comp_addr_hi;
comp_addr_lo <= data_in;
comp_data <= comp_data;
comp_ctrl <= comp_ctrl;
qual_addr_hi <= qual_addr_hi;
qual_addr_lo <= qual_addr_lo;
qual_data <= qual_data;
qual_ctrl <= qual_ctrl;
when "010" =>
comp_addr_hi <= comp_addr_hi;
comp_addr_lo <= comp_addr_lo;
comp_data <= data_in;
comp_ctrl <= comp_ctrl;
qual_addr_hi <= qual_addr_hi;
qual_addr_lo <= qual_addr_lo;
qual_data <= qual_data;
qual_ctrl <= qual_ctrl;
when "011" =>
comp_addr_hi <= comp_addr_hi;
comp_addr_lo <= comp_addr_lo;
comp_data <= comp_data;
comp_ctrl <= data_in;
qual_addr_hi <= qual_addr_hi;
qual_addr_lo <= qual_addr_lo;
qual_data <= qual_data;
qual_ctrl <= qual_ctrl;
when "100" =>
comp_addr_hi <= comp_addr_hi;
comp_addr_lo <= comp_addr_lo;
comp_data <= comp_data;
comp_ctrl <= comp_ctrl;
qual_addr_hi <= data_in;
qual_addr_lo <= qual_addr_lo;
qual_data <= qual_data;
qual_ctrl <= qual_ctrl;
when "101" =>
comp_addr_hi <= comp_addr_hi;
comp_addr_lo <= comp_addr_lo;
comp_data <= comp_data;
comp_ctrl <= comp_ctrl;
qual_addr_hi <= qual_addr_hi;
qual_addr_lo <= data_in;
qual_data <= qual_data;
qual_ctrl <= qual_ctrl;
when "110" =>
comp_addr_hi <= comp_addr_hi;
comp_addr_lo <= comp_addr_lo;
comp_data <= comp_data;
comp_ctrl <= comp_ctrl;
qual_addr_hi <= qual_addr_hi;
qual_addr_lo <= qual_addr_lo;
qual_data <= data_in;
qual_ctrl <= qual_ctrl;
-- when "111" =>
when others =>
comp_addr_hi <= comp_addr_hi;
comp_addr_lo <= comp_addr_lo;
comp_data <= comp_data;
comp_ctrl <= comp_ctrl;
qual_addr_hi <= qual_addr_hi;
qual_addr_lo <= qual_addr_lo;
qual_data <= qual_data;
qual_ctrl <= data_in;
end case;
else
comp_addr_hi <= comp_addr_hi;
comp_addr_lo <= comp_addr_lo;
comp_data <= comp_data;
comp_ctrl <= comp_ctrl;
qual_addr_hi <= qual_addr_hi;
qual_addr_lo <= qual_addr_lo;
qual_data <= qual_data;
qual_ctrl <= qual_ctrl;
end if;
end if;
end process;
 
--
-- trap data output mux
--
trap_read : process( addr,
comp_addr_hi, comp_addr_lo, comp_data, comp_ctrl,
qual_addr_hi, qual_addr_lo, qual_data, qual_ctrl,
match_flag )
begin
case addr(2 downto 0) is
when "000" =>
data_out <= comp_addr_hi;
when "001" =>
data_out <= comp_addr_lo;
when "010" =>
data_out <= comp_data;
when "011" =>
data_out <= comp_ctrl;
when "100" =>
data_out <= qual_addr_hi;
when "101" =>
data_out <= qual_addr_lo;
when "110" =>
data_out <= qual_data;
-- when "111" =>
when others =>
data_out(6 downto 0) <= qual_ctrl(6 downto 0);
data_out(7) <= match_flag;
end case;
end process;
 
 
--
-- Trap hardware
--
trap_match : process( Clk, rst, cs, rw, addr, vma, match_flag, data_in,
comp_addr_hi, comp_addr_lo, comp_data, comp_ctrl,
qual_addr_hi, qual_addr_lo, qual_data, qual_ctrl)
variable match : std_logic;
variable match_addr_hi : std_logic;
variable match_addr_lo : std_logic;
variable match_data : std_logic;
variable match_ctrl : std_logic;
 
begin
match_addr_hi :=
((comp_addr_hi(7) xor addr(15) ) and qual_addr_hi(7) ) or
((comp_addr_hi(6) xor addr(14) ) and qual_addr_hi(6) ) or
((comp_addr_hi(5) xor addr(13) ) and qual_addr_hi(5) ) or
((comp_addr_hi(4) xor addr(12) ) and qual_addr_hi(4) ) or
((comp_addr_hi(3) xor addr(11) ) and qual_addr_hi(3) ) or
((comp_addr_hi(2) xor addr(10) ) and qual_addr_hi(2) ) or
((comp_addr_hi(1) xor addr( 9) ) and qual_addr_hi(1) ) or
((comp_addr_hi(0) xor addr( 8) ) and qual_addr_hi(0) );
match_addr_lo :=
((comp_addr_lo(7) xor addr( 7) ) and qual_addr_lo(7) ) or
((comp_addr_lo(6) xor addr( 6) ) and qual_addr_lo(6) ) or
((comp_addr_lo(5) xor addr( 5) ) and qual_addr_lo(5) ) or
((comp_addr_lo(4) xor addr( 4) ) and qual_addr_lo(4) ) or
((comp_addr_lo(3) xor addr( 3) ) and qual_addr_lo(3) ) or
((comp_addr_lo(2) xor addr( 2) ) and qual_addr_lo(2) ) or
((comp_addr_lo(1) xor addr( 1) ) and qual_addr_lo(1) ) or
((comp_addr_lo(0) xor addr( 0) ) and qual_addr_lo(0) );
match_data :=
((comp_data(7) xor data_in(7)) and qual_data(7) ) or
((comp_data(6) xor data_in(6)) and qual_data(6) ) or
((comp_data(5) xor data_in(5)) and qual_data(5) ) or
((comp_data(4) xor data_in(4)) and qual_data(4) ) or
((comp_data(3) xor data_in(3)) and qual_data(3) ) or
((comp_data(2) xor data_in(2)) and qual_data(2) ) or
((comp_data(1) xor data_in(1)) and qual_data(1) ) or
((comp_data(0) xor data_in(0)) and qual_data(0) );
match_ctrl :=
((comp_ctrl(0) xor rw ) and qual_ctrl(0) ) or
((comp_ctrl(1) xor vma ) and qual_ctrl(1) );
 
match := not ( match_addr_hi or match_addr_lo or match_data or match_ctrl);
 
if clk'event and clk = '0' then
if rst = '1' then
match_flag <= '0';
elsif cs = '1' and rw = '0' then
match_flag <= '0';
else
if match = comp_ctrl(7) then
match_flag <= '1';
else
match_flag <= match_flag;
end if;
 
end if;
end if;
irq <= match_flag and qual_ctrl(7);
end process;
 
end trap_arch;
/trunk/vhdl/datram.vhd
79,7 → 79,7
dat_reg8, dat_reg9, dat_reg10, dat_reg11,
dat_reg12, dat_reg13, dat_reg14, dat_reg15 )
begin
if clk'event and clk = '1' then
if clk'event and clk = '0' then
if rst = '1' then
dat_reg0 <= "00000000";
dat_reg1 <= "00000001";
/trunk/vhdl/miniUART3.vhd
0,0 → 1,394
--===========================================================================--
--
-- S Y N T H E Z I A B L E miniUART C O R E
--
-- www.OpenCores.Org - January 2000
-- This core adheres to the GNU public license
--
-- Design units : miniUART core for the System68
--
-- File name : miniuart2.vhd
--
-- Purpose : Implements an miniUART device for communication purposes
-- between the CPU68 processor and the Host computer through
-- an RS-232 communication protocol.
--
-- Dependencies : ieee.std_logic_1164
-- ieee.numeric_std
--
--===========================================================================--
-------------------------------------------------------------------------------
-- Revision list
-- Version Author Date Changes
--
-- 0.1 Ovidiu Lupas 15 January 2000 New model
-- 1.0 Ovidiu Lupas January 2000 Synthesis optimizations
-- 2.0 Ovidiu Lupas April 2000 Bugs removed - RSBusCtrl
-- the RSBusCtrl did not process all possible situations
--
-- olupas@opencores.org
--
-- 3.0 John Kent October 2002 Changed Status bits to match mc6805
-- Added CTS, RTS, Baud rate control
-- & Software Reset
-- 3.1 John Kent 5 January 2003 Added Word Format control a'la mc6850
-- 3.2 John Kent 19 July 2003 Latched Data input to UART
-- 3.3 John Kent 16 January 2004 Integrated clkunit in rxunit & txunit
-- Now has external TX 7 RX Baud Clock
-- inputs like the MC6850...
-- also supports x1 clock and DCD.
--
-- dilbert57@opencores.org
--
-------------------------------------------------------------------------------
-- Entity for miniUART Unit - 9600 baudrate --
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
 
entity miniUART is
port (
--
-- CPU signals
--
clk : in Std_Logic; -- System Clock
rst : in Std_Logic; -- Reset input (active high)
cs : in Std_Logic; -- miniUART Chip Select
rw : in Std_Logic; -- Read / Not Write
irq : out Std_Logic; -- Interrupt
Addr : in Std_Logic; -- Register Select
DataIn : in Std_Logic_Vector(7 downto 0); -- Data Bus In
DataOut : out Std_Logic_Vector(7 downto 0); -- Data Bus Out
--
-- Uart Signals
--
RxC : in Std_Logic; -- Receive Baud Clock
TxC : in Std_Logic; -- Transmit Baud Clock
RxD : in Std_Logic; -- Receive Data
TxD : out Std_Logic; -- Transmit Data
DCD_n : in Std_Logic; -- Data Carrier Detect
CTS_n : in Std_Logic; -- Clear To Send
RTS_n : out Std_Logic ); -- Request To send
end; --================== End of entity ==============================--
-------------------------------------------------------------------------------
-- Architecture for miniUART Controller Unit
-------------------------------------------------------------------------------
architecture uart of miniUART is
-----------------------------------------------------------------------------
-- Signals
-----------------------------------------------------------------------------
signal RxData : Std_Logic_Vector(7 downto 0); --
signal TxData : Std_Logic_Vector(7 downto 0); --
signal StatReg : Std_Logic_Vector(7 downto 0); -- status register
-- StatReg detailed
-----------+--------+--------+--------+--------+--------+--------+--------+
-- Irq | PErr | ORErr | FErr | CTS | DCD | TBufE | DRdy |
-----------+--------+--------+--------+--------+--------+--------+--------+
signal CtrlReg : Std_Logic_Vector(7 downto 0); -- control register
-- CtrlReg detailed
-----------+--------+--------+--------+--------+--------+--------+--------+
-- RxIEnb |TxCtl(1)|TxCtl(0)|WdFmt(2)|WdFmt(1)|WdFmt(0)|BdCtl(1)|BdCtl(0)|
-----------+--------+--------+--------+--------+--------+--------+--------+
-- RxIEnb
-- 0 - Rx Interrupt disabled
-- 1 - Rx Interrupt enabled
-- TxCtl
-- 0 1 - Tx Interrupt Enable
-- 1 0 - RTS high
-- WdFmt
-- 0 0 0 - 7 data, even parity, 2 stop
-- 0 0 1 - 7 data, odd parity, 2 stop
-- 0 1 0 - 7 data, even parity, 1 stop
-- 0 1 1 - 7 data, odd parity, 1 stop
-- 1 0 0 - 8 data, no parity, 2 stop
-- 1 0 1 - 8 data, no parity, 1 stop
-- 1 1 0 - 8 data, even parity, 1 stop
-- 1 1 1 - 8 data, odd parity, 1 stop
-- BdCtl
-- 0 0 - Baud Clk divide by 1
-- 0 1 - Baud Clk divide by 16
-- 1 0 - Baud Clk divide by 64
-- 1 1 - reset
signal TxDbit : Std_Logic; -- Transmit data bit
signal DRdy : Std_Logic; -- Receive Data ready
signal TBufE : Std_Logic; -- Transmit buffer empty
signal FErr : Std_Logic; -- Frame error
signal OErr : Std_Logic; -- Output error
signal PErr : Std_Logic; -- Parity Error
signal TxIEnb : Std_Logic; -- Transmit interrupt enable
signal Read : Std_Logic; -- Read receive buffer
signal Load : Std_Logic; -- Load transmit buffer
signal ReadCS : Std_Logic; -- Read Status register
signal LoadCS : Std_Logic; -- Load Control register
signal Reset : Std_Logic; -- Reset (Software & Hardware)
signal RxRst : Std_Logic; -- Receive Reset (Software & Hardware)
signal TxRst : Std_Logic; -- Transmit Reset (Software & Hardware)
signal DCDDel : Std_Logic; -- Delayed DCD_n
signal DCDEdge : Std_Logic; -- Rising DCD_N Edge Pulse
signal DCDState : Std_Logic; -- DCD Reset sequencer
signal DCDInt : Std_Logic; -- DCD Interrupt
 
-----------------------------------------------------------------------------
-- Receive Unit
-----------------------------------------------------------------------------
component RxUnit
port (
Clk : in Std_Logic; -- Clock signal
Reset : in Std_Logic; -- Reset input
ReadD : in Std_Logic; -- Read data signal
WdFmt : in Std_Logic_Vector(2 downto 0); -- word format
BdFmt : in Std_Logic_Vector(1 downto 0); -- baud format
RxClk : in Std_Logic; -- RS-232 clock input
RxDat : in Std_Logic; -- RS-232 data input
FRErr : out Std_Logic; -- Status signal
ORErr : out Std_Logic; -- Status signal
PAErr : out Std_logic; -- Status signal
DARdy : out Std_Logic; -- Status signal
DAOut : out Std_Logic_Vector(7 downto 0));
end component;
-----------------------------------------------------------------------------
-- Transmitter Unit
-----------------------------------------------------------------------------
component TxUnit
port (
Clk : in Std_Logic; -- Clock signal
Reset : in Std_Logic; -- Reset input
LoadD : in Std_Logic; -- Load transmit data
DAIn : in Std_Logic_Vector(7 downto 0);
WdFmt : in Std_Logic_Vector(2 downto 0); -- word format
BdFmt : in Std_Logic_Vector(1 downto 0); -- baud format
TxClk : in Std_Logic; -- Enable input
TxDat : out Std_Logic; -- RS-232 data output
TBE : out Std_Logic ); -- Tx buffer empty
end component;
begin
-----------------------------------------------------------------------------
-- Instantiation of internal components
-----------------------------------------------------------------------------
 
RxDev : RxUnit port map (
Clk => clk,
Reset => RxRst,
ReadD => Read,
WdFmt => CtrlReg(4 downto 2),
BdFmt => CtrlReg(1 downto 0),
RxClk => RxC,
RxDat => RxD,
FRErr => FErr,
ORErr => OErr,
PAErr => PErr,
DARdy => DRdy,
DAOut => RxData
);
 
TxDev : TxUnit port map (
Clk => clk,
Reset => TxRst,
LoadD => Load,
DAIn => TxData,
WdFmt => CtrlReg(4 downto 2),
BdFmt => CtrlReg(1 downto 0),
TxClk => TxC,
TxDat => TxDbit,
TBE => TBufE
);
 
-----------------------------------------------------------------------------
-- Implements the controller for Rx&Tx units
-----------------------------------------------------------------------------
miniUart_Status : process(clk, Reset, CtrlReg, TxIEnb,
DRdy, TBufE, DCD_n, CTS_n, DCDInt,
FErr, OErr, PErr )
variable Int : Std_Logic;
begin
if Reset = '1' then
Int := '0';
StatReg <= "00000000";
irq <= '0';
elsif clk'event and clk='0' then
Int := (CtrlReg(7) and DRdy) or
(CtrlReg(7) and DCDInt) or
(TxIEnb and TBufE);
StatReg(0) <= DRdy; -- Receive Data Ready
StatReg(1) <= TBufE and (not CTS_n); -- Transmit Buffer Empty
StatReg(2) <= DCDInt; -- Data Carrier Detect
StatReg(3) <= CTS_n; -- Clear To Send
StatReg(4) <= FErr; -- Framing error
StatReg(5) <= OErr; -- Overrun error
StatReg(6) <= PErr; -- Parity error
StatReg(7) <= Int;
irq <= Int;
end if;
end process;
 
 
-----------------------------------------------------------------------------
-- Transmit control
-----------------------------------------------------------------------------
 
miniUart_TxControl : process( CtrlReg, TxDbit )
begin
case CtrlReg(6 downto 5) is
when "00" => -- Disable TX Interrupts, Assert RTS
RTS_n <= '0';
TxIEnb <= '0';
TxD <= TxDbit;
when "01" => -- Enable TX interrupts, Assert RTS
RTS_n <= '0';
TxIEnb <= '1';
TxD <= TxDbit;
when "10" => -- Disable Tx Interrupts, Clear RTS
RTS_n <= '1';
TxIEnb <= '0';
TxD <= TxDbit;
when "11" => -- Disable Tx interrupts, Assert RTS, send break
RTS_n <= '0';
TxIEnb <= '0';
TxD <= '0';
when others =>
RTS_n <= '0';
TxIEnb <= '0';
TxD <= TxDbit;
end case;
end process;
 
-----------------------------------------------------------------------------
-- Write to control register
-----------------------------------------------------------------------------
 
miniUart_Control: process(clk, Reset, cs, rw, Addr, DataIn, CtrlReg, TxData )
begin
if (reset = '1') then
TxData <= "00000000";
Load <= '0';
Read <= '0';
CtrlReg <= "00000000";
LoadCS <= '0';
ReadCS <= '0';
elsif clk'event and clk='0' then
if cs = '1' then
if Addr = '1' then -- Data Register
if rw = '0' then -- write data register
TxData <= DataIn;
Load <= '1';
Read <= '0';
else -- read Data Register
TxData <= TxData;
Load <= '0';
Read <= '1';
end if; -- rw
CtrlReg <= CtrlReg;
LoadCS <= '0';
ReadCS <= '0';
else -- Control / Status register
TxData <= TxData;
Load <= '0';
Read <= '0';
if rw = '0' then -- write control register
CtrlReg <= DataIn;
LoadCS <= '1';
ReadCS <= '0';
else -- read status Register
CtrlReg <= CtrlReg;
LoadCS <= '0';
ReadCS <= '1';
end if; -- rw
end if; -- Addr
else -- not selected
TxData <= TxData;
Load <= '0';
Read <= '0';
CtrlReg <= CtrlReg;
LoadCS <= '0';
ReadCS <= '0';
 
end if; -- cs
end if; -- clk / reset
end process;
 
---------------------------------------------------------------
--
-- set data output mux
--
--------------------------------------------------------------
 
miniUart_data_read: process(Addr, StatReg, RxData)
begin
if Addr = '1' then
DataOut <= RxData; -- read data register
else
DataOut <= StatReg; -- read status register
end if; -- Addr
end process;
 
 
---------------------------------------------------------------
--
-- Data Carrier Detect Edge rising edge detect
--
---------------------------------------------------------------
miniUart_DCD_edge : process( reset, clk, DCD_n, DCDDel )
begin
if reset = '1' then
DCDEdge <= '0';
DCDDel <= '0';
elsif clk'event and clk = '0' then
DCDDel <= DCD_n;
DCDEdge <= DCD_n and (not DCDDel);
end if;
end process;
 
 
---------------------------------------------------------------
--
-- Data Carrier Detect Interrupt
--
---------------------------------------------------------------
miniUart_DCD_int : process( reset, clk, DCDEdge, DCDState, Read, ReadCS, DCDInt )
begin
if reset = '1' then
DCDInt <= '0';
DCDState <= '0';
elsif clk'event and clk = '0' then
if DCDEdge = '1' then
DCDInt <= '1';
DCDState <= '0';
elsif DCDState = '0' then
-- To reset DCD interrupt, First read status
if (ReadCS <= '1') and (DCDInt = '1') then
DCDState <= '1';
else
DCDState <= '0';
end if;
DCDInt <= DCDInt;
else -- DCDstate = '1'
-- Then read the data register
if Read <= '1' then
DCDState <= '0';
DCDInt <= '0';
else
DCDState <= DCDState;
DCDInt <= DCDInt;
end if;
end if; -- DCDState
end if; -- clk / reset
end process;
 
---------------------------------------------------------------
--
-- reset may be hardware or software
--
---------------------------------------------------------------
 
miniUart_reset: process(rst, CtrlReg, Reset, DCD_n )
begin
Reset <= (CtrlReg(1) and CtrlReg(0)) or rst;
TxRst <= Reset;
RxRst <= Reset or DCD_n;
end process;
 
end; --===================== End of architecture =======================--
 
/trunk/vhdl/swtbug.vhd
7,7 → 7,7
--
-- File name : swtbug.vhd
--
-- entity name : boot_rom
-- entity name : monitor_rom
--
-- Purpose : Implements a 1K x 8 ROM containing the
-- SWTBUG monitor program for the SWTPC 6800
30,14 → 30,15
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
 
entity boot_rom is
entity monitor_rom is
port (
addr : in std_logic_vector(9 downto 0);
data : out std_logic_vector(7 downto 0)
cs : in std_logic;
addr : in std_logic_vector(9 downto 0);
data : out std_logic_vector(7 downto 0)
);
end entity boot_rom;
end;
 
architecture basic of boot_rom is
architecture basic of monitor_rom is
constant width : integer := 8;
constant memsize : integer := 1024;
 
1071,6 → 1072,6
"11010000"
);
begin
data <= rom_data(conv_integer(addr));
end architecture basic;
data <= rom_data(conv_integer(addr));
end;
 
/trunk/vhdl/rxunit3.vhd
0,0 → 1,396
--===========================================================================--
--
-- S Y N T H E Z I A B L E miniUART C O R E
--
-- www.OpenCores.Org - January 2000
-- This core adheres to the GNU public license
--
-- Design units : miniUART core for the System68
--
-- File name : rxunit3.vhd
--
-- Purpose : Implements an miniUART device for communication purposes
-- between the cpu68 cpu and the Host computer through
-- an RS-232 communication protocol.
--
-- Dependencies : ieee.std_logic_1164.all;
-- ieee.numeric_std.all;
--
--===========================================================================--
-------------------------------------------------------------------------------
-- Revision list
-- Version Author Date Changes
--
-- 0.1 Ovidiu Lupas 15 January 2000 New model
-- 2.0 Ovidiu Lupas 17 April 2000 samples counter cleared for bit 0
-- olupas@opencores.org
--
-- 3.0 John Kent 5 January 2003 Added 6850 word format control
-- 3.1 John Kent 12 January 2003 Significantly revamped receive code.
-- 3.2 John Kent 10 January 2004 Rewrite of code.
-- dilbert57@opencores.org
-------------------------------------------------------------------------------
-- Description : Implements the receive unit of the miniUART core. Samples
-- 16 times the RxD line and retain the value in the middle of
-- the time interval.
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
 
-------------------------------------------------------------------------------
-- Receive unit
-------------------------------------------------------------------------------
entity RxUnit is
port (
Clk : in Std_Logic; -- Clock signal
Reset : in Std_Logic; -- Reset input
ReadD : in Std_Logic; -- Read data signal
WdFmt : in Std_Logic_Vector(2 downto 0); -- word format
BdFmt : in Std_Logic_Vector(1 downto 0); -- baud format
RxClk : in Std_Logic; -- RS-232 clock input
RxDat : in Std_Logic; -- RS-232 data input
FRErr : out Std_Logic; -- Status signal
ORErr : out Std_Logic; -- Status signal
PAErr : out Std_logic; -- Status signal
DARdy : out Std_Logic; -- Status signal
DAOut : out Std_Logic_Vector(7 downto 0)
);
end; --================== End of entity ==============================--
-------------------------------------------------------------------------------
-- Architecture for receive Unit
-------------------------------------------------------------------------------
architecture Behaviour of RxUnit is
-----------------------------------------------------------------------------
-- Signals
-----------------------------------------------------------------------------
signal RxDebDel0 : Std_Logic; -- Debounce Delayed Rx Data
signal RxDebDel1 : Std_Logic; -- Debounce Delayed Rx Data
signal RxDebDel2 : Std_Logic; -- Debounce Delayed Rx Data
signal RxDebDel3 : Std_Logic; -- Debounce Delayed Rx Data
signal RxDeb : Std_Logic; -- Debounced Rx Data
signal RxDatDel : Std_Logic; -- Delayed Rx Data
signal RxDatEdge : Std_Logic; -- Rx Data Edge pulse
signal RxClkDel : Std_Logic; -- Delayed Rx Input Clock
signal RxClkEdge : Std_Logic; -- Rx Input Clock Edge pulse
signal RxClkCnt : Std_Logic_Vector(5 downto 0); -- Rx Baud Clock Counter
signal RxBdClk : Std_Logic; -- Rx Baud Clock
signal RxBdDel : Std_Logic; -- Delayed Rx Baud Clock
signal RxBdEdge : Std_Logic; -- Rx Baud Clock Edge pulse
signal RxStart : Std_Logic; -- Rx Start bit detected
 
signal tmpDRdy : Std_Logic; -- Data Ready flag
signal RxValid : Std_Logic; -- Rx Data Valid
signal tmpRxVal : Std_Logic; -- Rx Data Valid
signal outErr : Std_Logic; -- Over run error bit
signal frameErr : Std_Logic; -- Framing error bit
signal ParityErr : Std_Logic; -- Parity Error Bit
signal RxParity : Std_Logic; -- Calculated RX parity bit
signal RxState : Std_Logic_Vector(3 downto 0); -- receive bit state
signal ShtReg : Std_Logic_Vector(7 downto 0); -- Shift Register
signal DataOut : Std_Logic_Vector(7 downto 0); -- Data Output register
 
begin
 
---------------------------------------------------------------------
-- Receiver Data Debounce
-- Input level must be stable for 4 Receive Clock cycles.
---------------------------------------------------------------------
rxunit_data_debounce : process(Clk, Reset, RxClkEdge, RxDat,
RxDebDel0, RxDebDel1, RxDebDel2, RxDebDel3 )
begin
if Reset = '1' then
RxDebDel0 <= RxDat;
RxDebDel1 <= RxDat;
RxDebDel2 <= RxDat;
RxDebDel3 <= RxDat;
elsif Clk'event and Clk = '0' then
if RxClkEdge = '1' then
RxDebDel0 <= RxDat;
RxDebDel1 <= RxDebDel0;
RxDebDel2 <= RxDebDel1;
RxDebDel3 <= RxDebDel2;
if (RxDebDel3 or RxDebDel2 or RxDebDel1 or RxDebDel0) = '0' then
RxDeb <= '0';
elsif (RxDebDel3 and RxDebDel2 and RxDebDel1 and RxDebDel0) = '1' then
RxDeb <= '1';
else
RxDeb <= RxDeb;
end if;
else
RxDebDel0 <= RxDebDel0;
RxDebDel1 <= RxDebDel1;
RxDebDel2 <= RxDebDel2;
RxDebDel3 <= RxDebDel3;
RxDeb <= RxDeb;
end if;
end if;
end process;
 
---------------------------------------------------------------------
-- Receiver Data Edge Detection
-- A falling edge will produce a one clock cycle pulse
---------------------------------------------------------------------
rxunit_data_edge : process(Clk, Reset, RxDeb, RxDatDel )
begin
if Reset = '1' then
RxDatDel <= RxDeb;
RxDatEdge <= '0';
elsif Clk'event and Clk = '0' then
RxDatDel <= RxDeb;
RxDatEdge <= RxDatDel and (not RxDeb);
end if;
end process;
 
---------------------------------------------------------------------
-- Receiver Clock Edge Detection
-- A rising edge will produce a one clock cycle pulse
-- RxClock
---------------------------------------------------------------------
rxunit_clock_edge : process(Clk, Reset, RxClk, RxClkDel )
begin
if Reset = '1' then
RxClkDel <= RxClk;
RxClkEdge <= '0';
elsif Clk'event and Clk = '0' then
RxClkDel <= RxClk;
RxClkEdge <= RxClk and (not RxClkDel);
end if;
end process;
 
 
---------------------------------------------------------------------
-- Receiver Clock Divider
-- Reset the Rx Clock divider on any data edge
-- Note that debounce data will be skewed by 4 clock cycles.
-- Advance the count only on an input clock pulse
---------------------------------------------------------------------
rxunit_clock_divide : process(Clk, Reset, RxDatEdge, RxState, RxStart,
RxClkEdge, RxClkCnt )
begin
if Reset = '1' then
RxClkCnt <= "000000";
RxStart <= '0';
elsif Clk'event and Clk = '0' then
 
if RxState = "1111" then -- idle state
if RxStart = '0' then -- in hunt mode
if RxDatEdge = '1' then -- falling edge starts counter
RxStart <= '1';
else
RxStart <= RxStart; -- other wise remain halted
end if;
else
RxStart <= RxStart; -- Acquired start, stay in this state
end if;
else
RxStart <= '0'; -- non idle, reset start flag
end if; -- RxState
 
if RxState = "1111" and RxStart = '0' then
RxClkCnt <= "000011"; -- Reset to 3 to account for debounce skew
else
if RxClkEdge = '1' then
RxClkCnt <= RxClkCnt + "000001";
else
RxClkCnt <= RxClkCnt;
end if; -- RxClkEdge
end if; -- RxState
end if; -- clk / reset
end process;
 
---------------------------------------------------------------------
-- Receiver Clock Selector
-- Select output then look for rising edge
---------------------------------------------------------------------
rxunit_clock_select : process(Clk, Reset, BdFmt, RxClk, RxClkCnt,
RxBdDel, RxBdEdge )
begin
-- BdFmt
-- 0 0 - Baud Clk divide by 1
-- 0 1 - Baud Clk divide by 16
-- 1 0 - Baud Clk divide by 64
-- 1 1 - reset
case BdFmt is
when "00" => -- Div by 1
RxBdClk <= RxClk;
when "01" => -- Div by 16
RxBdClk <= RxClkCnt(3);
when "10" => -- Div by 64
RxBdClk <= RxClkCnt(5);
when others => -- reset
RxBdClk <= '0';
end case;
 
if Reset = '1' then
RxBdDel <= RxBdClk;
RxBdEdge <= '0';
elsif Clk'event and Clk = '0' then
RxBdDel <= RxBdClk;
RxBdEdge <= RxBdClk and (not RxBdDel);
end if;
 
end process;
 
 
---------------------------------------------------------------------
-- Receiver process
---------------------------------------------------------------------
rxunit_receive : process(Clk, Reset, RxState, RxBdEdge, RxDat )
begin
if Reset = '1' then
frameErr <= '0';
outErr <= '0';
parityErr <= '0';
 
ShtReg <= "00000000"; -- Shift register
DataOut <= "00000000";
RxParity <= '0'; -- Parity bit
RxValid <= '0'; -- Data RX data valid flag
RxState <= "1111";
elsif Clk'event and Clk='0' then
if RxBdEdge = '1' then
case RxState is
when "0000" | "0001" | "0010" | "0011" |
"0100" | "0101" | "0110" => -- data bits 0 to 6
ShtReg <= RxDat & ShtReg(7 downto 1);
RxParity <= RxParity xor RxDat;
parityErr <= parityErr;
frameErr <= frameErr;
outErr <= outErr;
RxValid <= '0';
DataOut <= DataOut;
if RxState = "0110" then
if WdFmt(2) = '0' then
RxState <= "1000"; -- 7 data + parity
else
RxState <= "0111"; -- 8 data bits
end if; -- WdFmt(2)
else
RxState <= RxState + "0001";
end if; -- RxState
 
when "0111" => -- data bit 7
ShtReg <= RxDat & ShtReg(7 downto 1);
RxParity <= RxParity xor RxDat;
parityErr <= parityErr;
frameErr <= frameErr;
outErr <= outErr;
RxValid <= '0';
DataOut <= DataOut;
if WdFmt(1) = '1' then -- parity bit ?
RxState <= "1000"; -- yes, go to parity
else
RxState <= "1001"; -- no, must be 2 stop bit bits
end if;
 
when "1000" => -- parity bit
if WdFmt(2) = '0' then
ShtReg <= RxDat & ShtReg(7 downto 1); -- 7 data + parity
else
ShtReg <= ShtReg; -- 8 data + parity
end if;
RxParity <= RxParity;
if WdFmt(0) = '0' then -- parity polarity ?
if RxParity = RxDat then -- check even parity
parityErr <= '1';
else
parityErr <= '0';
end if;
else
if RxParity = RxDat then -- check for odd parity
parityErr <= '0';
else
parityErr <= '1';
end if;
end if;
frameErr <= frameErr;
outErr <= outErr;
RxValid <= '0';
DataOut <= DataOut;
RxState <= "1001";
 
when "1001" => -- stop bit (Only one required for RX)
ShtReg <= ShtReg;
RxParity <= RxParity;
parityErr <= parityErr;
if RxDat = '1' then -- stop bit expected
frameErr <= '0'; -- yes, no framing error
else
frameErr <= '1'; -- no, framing error
end if;
if tmpDRdy = '1' then -- Has previous data been read ?
outErr <= '1'; -- no, overrun error
else
outErr <= '0'; -- yes, no over run error
end if;
RxValid <= '1';
DataOut <= ShtReg;
RxState <= "1111";
 
when others => -- this is the idle state
ShtReg <= ShtReg;
RxParity <= RxParity;
parityErr <= parityErr;
frameErr <= frameErr;
outErr <= outErr;
RxValid <= '0';
DataOut <= DataOut;
if RxDat = '0' then -- look for start request
RxState <= "0000"; -- yes, read data
else
RxState <= "1111"; -- otherwise idle
end if;
end case; -- RxState
else -- RxBdEdge
ShtReg <= ShtReg;
RxParity <= RxParity;
parityErr <= parityErr;
frameErr <= frameErr;
outErr <= outErr;
RxValid <= RxValid;
DataOut <= DataOut;
RxState <= RxState;
end if; -- RxBdEdge
end if; -- clk / reset
end process;
 
 
---------------------------------------------------------------------
-- Receiver Read process
---------------------------------------------------------------------
rxunit_read : process(Clk, Reset, ReadD, RxValid, tmpRxVal, tmpDRdy )
begin
if Reset = '1' then
tmpDRdy <= '0';
tmpRxVal <= '0';
elsif Clk'event and Clk='0' then
if ReadD = '1' then
-- Data was read, reset data ready
tmpDRdy <= '0';
tmpRxVal <= tmpRxVal;
else
if RxValid = '1' and tmpRxVal = '0' then
-- Data was received, set Data ready
tmpDRdy <= '1';
tmpRxVal <= '1';
else
-- Test for falling edge of RxValid.
tmpDRdy <= tmpDRdy;
if RxValid = '0' and tmpRxVal = '1' then
tmpRxVal <= '0';
else
tmpRxVal <= tmpRxVal;
end if;
end if; -- RxValid
end if; -- ReadD
end if; -- clk / reset
end process;
 
 
DARdy <= tmpDRdy;
DAOut <= DataOut;
FRErr <= frameErr;
ORErr <= outErr;
PAErr <= parityErr;
 
end Behaviour; --==================== End of architecture ====================--
/trunk/vhdl/ioport.vhd
7,7 → 7,7
--
-- File name : ioport.vhd
--
-- Purpose : Implements 4 x 8 bit parallel I/O ports
-- Purpose : Implements 2 x 8 bit parallel I/O ports
-- with programmable data direction registers
--
-- Dependencies : ieee.Std_Logic_1164
26,7 → 26,8
-- 11 Oct 2002 0.1 John Kent
-- used a loop counter for data direction & read port signals
--
--
-- 9th Jan 2004 0.2 John Kent
-- Turned into two port device.
--===========================================================================----
--
-- Memory Map
33,12 → 34,8
--
-- IO + $00 - Port A Data register
-- IO + $01 - Port B Data register
-- IO + $02 - Port C Data register
-- IO + $03 - Port D Data register
-- IO + $04 - Port A Data Direction Register
-- IO + $05 - Port B Data Direction Register
-- IO + $06 - Port C Data Direction Register
-- IO + $07 - Port D Data Direction Register
-- IO + $02 - Port A Data Direction Register
-- IO + $03 - Port B Data Direction Register
--
 
library ieee;
51,24 → 48,18
rst : in std_logic;
cs : in std_logic;
rw : in std_logic;
addr : in std_logic_vector(2 downto 0);
addr : in std_logic_vector(1 downto 0);
data_in : in std_logic_vector(7 downto 0);
data_out : out std_logic_vector(7 downto 0);
porta_io : inout std_logic_vector(7 downto 0);
portb_io : inout std_logic_vector(7 downto 0);
portc_io : inout std_logic_vector(7 downto 0);
portd_io : inout std_logic_vector(7 downto 0) );
portb_io : inout std_logic_vector(7 downto 0) );
end;
 
architecture ioport_arch of ioport is
signal porta_ddr : std_logic_vector(7 downto 0);
signal portb_ddr : std_logic_vector(7 downto 0);
signal portc_ddr : std_logic_vector(7 downto 0);
signal portd_ddr : std_logic_vector(7 downto 0);
signal porta_data : std_logic_vector(7 downto 0);
signal portb_data : std_logic_vector(7 downto 0);
signal portc_data : std_logic_vector(7 downto 0);
signal portd_data : std_logic_vector(7 downto 0);
 
begin
 
80,13 → 71,13
--------------------------------
 
ioport_read : process( addr,
porta_ddr, portb_ddr, portc_ddr, portd_ddr,
porta_data, portb_data, portc_data, portd_data,
porta_io, portb_io, portc_io, portd_io )
porta_ddr, portb_ddr,
porta_data, portb_data,
porta_io, portb_io )
variable count : integer;
begin
case addr is
when "000" =>
when "00" =>
for count in 0 to 7 loop
if porta_ddr(count) = '1' then
data_out(count) <= porta_data(count);
95,7 → 86,7
end if;
end loop;
 
when "001" =>
when "01" =>
for count in 0 to 7 loop
if portb_ddr(count) = '1' then
data_out(count) <= portb_data(count);
104,32 → 95,10
end if;
end loop;
 
when "010" =>
for count in 0 to 7 loop
if portc_ddr(count) = '1' then
data_out(count) <= portc_data(count);
else
data_out(count) <= portc_io(count);
end if;
end loop;
 
when "011" =>
for count in 0 to 7 loop
if portd_ddr(count) = '1' then
data_out(count) <= portd_data(count);
else
data_out(count) <= portd_io(count);
end if;
end loop;
 
when "100" =>
when "10" =>
data_out <= porta_ddr;
when "101" =>
when "11" =>
data_out <= portb_ddr;
when "110" =>
data_out <= portc_ddr;
when "111" =>
data_out <= portd_ddr;
when others =>
data_out <= "00000000";
end case;
142,112 → 111,48
---------------------------------
 
ioport_write : process( clk, rst, addr, cs, rw, data_in,
porta_data, portb_data, portc_data, portd_data,
porta_ddr, portb_ddr, portc_ddr, portd_ddr )
porta_data, portb_data,
porta_ddr, portb_ddr )
begin
if clk'event and clk = '1' then
if rst = '1' then
porta_data <= "00000000";
portb_data <= "00000000";
portc_data <= "00000000";
portd_data <= "00000000";
porta_ddr <= "00000000";
portb_ddr <= "00000000";
portc_ddr <= "00000000";
portd_ddr <= "00000000";
elsif cs = '1' and rw = '0' then
case addr is
when "000" =>
when "00" =>
porta_data <= data_in;
portb_data <= portb_data;
portc_data <= portc_data;
portd_data <= portd_data;
porta_ddr <= porta_ddr;
portb_ddr <= portb_ddr;
portc_ddr <= portc_ddr;
portd_ddr <= portd_ddr;
when "001" =>
when "01" =>
porta_data <= porta_data;
portb_data <= data_in;
portc_data <= portc_data;
portd_data <= portd_data;
porta_ddr <= porta_ddr;
portb_ddr <= portb_ddr;
portc_ddr <= portc_ddr;
portd_ddr <= portd_ddr;
when "010" =>
when "10" =>
porta_data <= porta_data;
portb_data <= portb_data;
portc_data <= data_in;
portd_data <= portd_data;
porta_ddr <= porta_ddr;
portb_ddr <= portb_ddr;
portc_ddr <= portc_ddr;
portd_ddr <= portd_ddr;
when "011" =>
porta_data <= porta_data;
portb_data <= portb_data;
portc_data <= portc_data;
portd_data <= data_in;
porta_ddr <= porta_ddr;
portb_ddr <= portb_ddr;
portc_ddr <= portc_ddr;
portd_ddr <= portd_ddr;
when "100" =>
porta_data <= porta_data;
portb_data <= portb_data;
portc_data <= portc_data;
portd_data <= portd_data;
porta_ddr <= data_in;
portb_ddr <= portb_ddr;
portc_ddr <= portc_ddr;
portd_ddr <= portd_ddr;
when "101" =>
when "11" =>
porta_data <= porta_data;
portb_data <= portb_data;
portc_data <= portc_data;
portd_data <= portd_data;
porta_ddr <= porta_ddr;
portb_ddr <= data_in;
portc_ddr <= portc_ddr;
portd_ddr <= portd_ddr;
when "110" =>
porta_data <= porta_data;
portb_data <= portb_data;
portc_data <= portc_data;
portd_data <= portd_data;
porta_ddr <= porta_ddr;
portb_ddr <= portb_ddr;
portc_ddr <= data_in;
portd_ddr <= portd_ddr;
when "111" =>
porta_data <= porta_data;
portb_data <= portb_data;
portc_data <= portc_data;
portd_data <= portd_data;
porta_ddr <= porta_ddr;
portb_ddr <= portb_ddr;
portc_ddr <= portc_ddr;
portd_ddr <= data_in;
when others =>
porta_data <= porta_data;
portb_data <= portb_data;
portc_data <= portc_data;
portd_data <= portd_data;
porta_ddr <= porta_ddr;
portb_ddr <= portb_ddr;
portc_ddr <= portc_ddr;
portd_ddr <= portd_ddr;
end case;
else
porta_data <= porta_data;
portb_data <= portb_data;
portc_data <= portc_data;
portd_data <= portd_data;
porta_ddr <= porta_ddr;
portb_ddr <= portb_ddr;
portc_ddr <= portc_ddr;
portd_ddr <= portd_ddr;
end if;
end if;
end process;
284,38 → 189,6
end if;
end loop;
end process;
---------------------------------
--
-- direction control port a
--
---------------------------------
portc_direction : process ( portc_data, portc_ddr )
variable count : integer;
begin
for count in 0 to 7 loop
if portc_ddr(count) = '1' then
portc_io(count) <= portc_data(count);
else
portc_io(count) <= 'Z';
end if;
end loop;
end process;
---------------------------------
--
-- direction control port d
--
---------------------------------
portd_direction : process ( portd_data, portd_ddr)
variable count : integer;
begin
for count in 0 to 7 loop
if portd_ddr(count) = '1' then
portd_io(count) <= portd_data(count);
else
portd_io(count) <= 'Z';
end if;
end loop;
end process;
 
end ioport_arch;
/trunk/vhdl/miniuart_tb.vhd
0,0 → 1,197
--===========================================================================--
--
-- MiniUart3 Test Bench
--
--
-- John Kent 16th January 2004
--
--
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
use ieee.numeric_std.all;
 
entity miniuart3_testbench is
end miniuart3_testbench;
 
-------------------------------------------------------------------------------
-- Architecture for memio Controller Unit
-------------------------------------------------------------------------------
architecture behavior of miniuart3_testbench is
-----------------------------------------------------------------------------
-- Signals
-----------------------------------------------------------------------------
-- CPU Interface signals
signal SysClk : Std_Logic;
signal uart_reset : Std_Logic;
signal uart_cs : Std_Logic;
signal uart_rw : Std_Logic;
signal uart_addr : Std_Logic;
signal uart_data_in : Std_Logic_Vector(7 downto 0);
signal uart_data_out: Std_Logic_Vector(7 downto 0);
signal uart_irq : Std_Logic;
signal rxclk : Std_Logic;
signal txclk : Std_Logic;
signal rxbit : Std_Logic;
signal txbit : Std_Logic;
signal dcd_n : Std_Logic;
signal cts_n : Std_Logic;
signal rts_n : Std_Logic;
 
-----------------------------------------------------------------
--
-- Open Cores Mini UART
--
-----------------------------------------------------------------
component miniUART
port (
--
-- CPU signals
--
clk : in Std_Logic; -- System Clock
rst : in Std_Logic; -- Reset input (active high)
cs : in Std_Logic; -- miniUART Chip Select
rw : in Std_Logic; -- Read / Not Write
irq : out Std_Logic; -- Interrupt
Addr : in Std_Logic; -- Register Select
DataIn : in Std_Logic_Vector(7 downto 0); -- Data Bus In
DataOut : out Std_Logic_Vector(7 downto 0); -- Data Bus Out
--
-- Uart Signals
--
RxC : in Std_Logic; -- Receive Baud Clock
TxC : in Std_Logic; -- Transmit Baud Clock
RxD : in Std_Logic; -- Receive Data
TxD : out Std_Logic; -- Transmit Data
DCD_n : in Std_Logic; -- Data Carrier Detect
CTS_n : in Std_Logic; -- Clear To Send
RTS_n : out Std_Logic ); -- Request To send
end component; --================== End of entity ==============================--
 
begin
 
-----------------------------------------------------------------------------
-- Instantiation of internal components
-----------------------------------------------------------------------------
 
my_uart : miniUART port map (
clk => SysClk,
rst => uart_reset,
cs => uart_cs,
rw => uart_rw,
Irq => uart_irq,
Addr => uart_addr,
Datain => uart_data_in,
DataOut => uart_data_out,
RxC => rxclk,
TxC => txclk,
RxD => rxbit,
TxD => txbit,
DCD_n => dcd_n,
CTS_n => cts_n,
RTS_n => rts_n
);
 
 
-- *** Test Bench - User Defined Section ***
tb : PROCESS
variable count : integer;
BEGIN
 
cts_n <= '0';
dcd_n <= '0';
 
for count in 0 to 4096 loop
if (count mod 16) = 0 then
rxclk <= '1';
txclk <= '1';
elsif (count mod 16) = 8 then
rxclk <= '0';
txclk <= '0';
end if;
 
case count is
when 0 =>
uart_reset <= '1';
uart_cs <= '0';
uart_rw <= '1';
uart_addr <= '0';
uart_data_in <= "00000000";
rxbit <= '1';
when 1 =>
uart_reset <= '0';
when 3 =>
uart_cs <= '1';
uart_rw <= '0'; -- write control
uart_addr <= '0';
uart_data_in <= "00010001";
when 4 =>
uart_cs <= '0';
uart_rw <= '1';
uart_addr <= '0';
uart_data_in <= "00000000";
when 5 =>
uart_cs <= '1';
uart_rw <= '0'; -- write data
uart_addr <= '1';
uart_data_in <= "01010101";
when 6 =>
uart_cs <= '0';
uart_rw <= '1';
uart_addr <= '1';
uart_data_in <= "00000000";
when 256 =>
rxbit <= '0'; -- start
when 512 =>
rxbit <= '1'; -- bit 0
when 768 =>
rxbit <= '0'; -- bit 1
when 1024 =>
rxbit <= '1'; -- bit 2
when 1280 =>
rxbit <= '1'; -- bit3
when 1536 =>
rxbit <= '0'; -- bit 4
when 1792 =>
rxbit <= '0'; -- bit 5
when 2048 =>
rxbit <= '1'; -- bit 6
when 2304 =>
rxbit <= '0'; -- bit 7
when 2560 =>
rxbit <= '1'; -- stop 1
when 2816 =>
rxbit <= '1'; -- stop 2
when 3100 =>
uart_cs <= '1';
uart_rw <= '1'; -- read control
uart_addr <= '0';
when 3101 =>
uart_cs <= '0';
uart_rw <= '1';
uart_addr <= '0';
when 3102 =>
uart_cs <= '1';
uart_rw <= '1'; -- read data
uart_addr <= '1';
when 3103 =>
uart_cs <= '0';
uart_rw <= '1';
uart_addr <= '1';
when others =>
null;
end case;
SysClk <= '1';
wait for 100 ns;
SysClk <= '0';
wait for 100 ns;
end loop;
 
wait; -- will wait forever
END PROCESS;
-- *** End Test Bench - User Defined Section ***
 
end behavior; --===================== End of architecture =======================--
 
/trunk/vhdl/timer.vhd
86,40 → 86,26
--------------------------------
--
-- write control registers
-- doesn't do anything yet
--
--------------------------------
timer_write : process( clk, rst, cs, rw, addr, data_in,
timer_reg, timer_ctrl, timer_count )
timer_write : process( clk, rst, cs, rw, addr,
data_in, timer_reg, timer_ctrl )
begin
if clk'event and clk = '1' then
if rst = '1' then
timer_reg <= "00000000";
if rst = '1' then
timer_reg <= "00000000";
timer_ctrl <= "00000000";
elsif cs = '1' and rw = '0' then
elsif clk'event and clk = '0' then
if cs = '1' and rw = '0' then
if addr='0' then
timer_reg <= data_in;
timer_reg <= data_in;
timer_ctrl <= timer_ctrl;
timer_term <= '0';
else
timer_reg <= timer_reg;
timer_reg <= timer_reg;
timer_ctrl <= data_in;
timer_term <= timer_term;
end if;
else
timer_ctrl <= timer_ctrl;
timer_reg <= timer_reg;
if (timer_ctrl(T_enab) = '1') then
if (timer_count = "00000000" ) then
timer_term <= '1';
elsif timer_ctrl(T_mode) = '0' then
timer_term <= '0'; -- counter mode, reset on non zero
else
timer_term <= timer_term; -- timer mode, keep as is
end if;
else
timer_term <= timer_term;
end if;
timer_reg <= timer_reg;
end if;
end if;
end process;
136,20 → 122,58
end if;
end process;
 
 
--------------------------------
--
-- Terminal Count
--
--------------------------------
timer_terminal : process( clk, rst, cs, rw, addr, data_in,
timer_term, timer_ctrl, timer_count )
begin
if rst = '1' then
timer_term <= '0';
elsif clk'event and clk = '0' then
if cs = '1' and rw = '0' then
if addr='0' then
-- Reset terminal count on write to counter
timer_term <= '0';
else
timer_term <= timer_term;
end if;
else
if (timer_ctrl(T_enab) = '1') then
if (timer_count = "00000000" ) then
-- If timer enabled, set terminal output on zero count
timer_term <= '1';
elsif timer_ctrl(T_mode) = '0' then
-- counter mode, reset on non zero
timer_term <= '0';
else
-- timer mode, keep as is
timer_term <= timer_term;
end if; -- timer count
else
timer_term <= timer_term;
end if; -- timer ctrl
end if; -- cs
end if; -- rst / clk
end process;
 
 
--------------------------------
--
-- counters
--
--------------------------------
 
my_counter: process( clk, rst, timer_ctrl, timer_count, timer_in )
timer_counter: process( clk, rst, timer_ctrl, timer_count, timer_in )
variable timer_tmp : std_logic;
begin
if clk'event and clk='1' then
if rst = '1' then
if rst = '1' then
timer_count <= "00000000";
timer_tmp := '0';
else
elsif clk'event and clk = '0' then
if timer_ctrl( T_enab ) = '1' then
if timer_in = '0' and timer_tmp = '1' then
timer_tmp := '0';
169,8 → 193,7
timer_tmp := timer_tmp;
timer_count <= timer_count;
end if; -- timer_ctrl
end if; -- rst
end if; -- clk
end if; -- rst / clk
end process;
 
--
179,12 → 202,13
timer_interrupt : process( Clk, rst, cs, rw, addr,
timer_term, timer_int, timer_count, timer_ctrl )
begin
if clk'event and clk = '1' then
if clk'event and clk = '0' then
if rst = '1' then
timer_int <= '0';
elsif cs = '1' and rw = '1' then
if addr = '0' then
timer_int <= '0'; -- reset interrupt on read count
-- reset interrupt on read count
timer_int <= '0';
else
timer_int <= timer_int;
end if;
196,7 → 220,13
end if;
end if;
end if;
end process;
 
--
-- read timer strobe to reset interrupts
--
timer_irq : process( timer_int, timer_ctrl )
begin
if timer_ctrl( T_irq ) = '1' then
irq <= timer_int;
else
220,7 → 250,7
timer_output : process( Clk, rst, timer_term, timer_ctrl, timer_tog )
variable timer_tmp : std_logic; -- tracks change in terminal count
begin
if clk'event and clk='1' then
if clk'event and clk = '0' then
if rst = '1' then
timer_tog <= '0';
timer_tmp := '0';
/trunk/vhdl/System68_X300.npl
0,0 → 1,38
JDF G
// Created by Project Navigator ver 1.0
PROJECT System68_X300
DESIGN system68_x300
DEVFAM spartan2e
DEVFAMTIME 0
DEVICE xc2s300e
DEVICETIME 0
DEVPKG pq208
DEVPKGTIME 0
DEVSPEED -6
DEVSPEEDTIME 0
DEVTOPLEVELMODULETYPE HDL
TOPLEVELMODULETYPETIME 0
DEVSYNTHESISTOOL XST (VHDL/Verilog)
SYNTHESISTOOLTIME 0
DEVSIMULATOR Other
SIMULATORTIME 0
DEVGENERATEDSIMULATIONMODEL VHDL
GENERATEDSIMULATIONMODELTIME 0
SOURCE System68.vhd
SOURCE cpu68.vhd
SOURCE datram.vhd
SOURCE ioport.vhd
SOURCE timer.vhd
SOURCE trap.vhd
SOURCE swtbug_rom.vhd
SOURCE swtbug.vhd
SOURCE txunit3.vhd
SOURCE rxunit3.vhd
SOURCE miniUART3.vhd
STIMULUS miniuart_tb.vhd
DEPASSOC sys68 system68.ucf
[Normal]
p_impactConfigFileName=xstvhd, spartan2e, Implementation.t_impactProgrammingTool, 1066323192, C:\Vhdl\System68_X300\sys68.bit
p_impactConfigMode=xstvhd, spartan2e, Implementation.t_impactProgrammingTool, 1066323192, Boundary Scan
[STRATEGY-LIST]
Normal=True
/trunk/vhdl/System68_tb.vhd
0,0 → 1,764
--===========================================================================--
--
-- S Y N T H E Z I A B L E System68 System On a Chip
--
-- This core adheres to the GNU public license
--
-- File name : system68_tb.vhd
--
-- Purpose : Top level file for a 6800 compatible system on a chip
-- Designed for the Burch ED B5-Spartan IIe board with
-- X2S300e FPGA,
-- 128K x 16 Word SRAM module (Modified B3_SRAM)
-- CPU I/O module
-- B5 Compact Flash Module
-- Using mimiUart from open cores modified to look like a 6850
-- This version of System68 boots the monitor program
-- from LBA sectors $F478 / $F479 from a 32 Mbyte Compact Flash
-- On Reset the Boot ROM is mapped for read at $E000,
-- and Writes to $E000-$FFFF write to RAM
-- Writing 0 to location $8030 disables the boot ROM and
-- maps RAM for Read only at $E000 and Writes go to the DAT.
--
-- Dependencies : ieee.Std_Logic_1164
-- ieee.std_logic_unsigned
-- ieee.std_logic_arith
-- ieee.numeric_std
--
-- Uses : miniuart.vhd, rxunit.vhd, tx_unit.vhd, clkunit.vhd
-- swtbug.vhd (6800 SWTBUG ROM)
-- datram.vhd (Dynamic address translation registers)
-- cpu68.vhd (6800 compatible CPU core)
-- timer.vhd (timer module)
--
-- Author : John E. Kent
--
--===========================================================================----
--
-- Revision History:
--===========================================================================--
--
-- Date: Revision Author
-- 22 September 2002 0.1 John Kent
-- Initial design.
-- 31 March 2003 0.2 John Kent
-- Removed Parallel I/O port
-- Added Compact Flash Interface
-- Added IO register to commit unused inputs
-- Used 16 byte port mapping
-- 28th June 2003
-- updated CPU to include Halt and Hold signals
-------------------------------------------------------------------------------
--
-- Memory Map:
--
-- $0000 - $7FFF RAM
-- $8000 - $9FFF IO
-- $8000 - $800F MiniUart / Acia
-- $8010 - $801F Compact Flash
-- $8020 - $802F Timer
-- $8030 - $803F IO register / Map switch
-- $A000 - $DFFF RAM
-- $E000 - $FFFF ROM (read) & DAT (write)
--
library ieee;
use ieee.std_logic_1164.all;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
use ieee.numeric_std.all;
 
entity System68 is
port(
-- Memory Interface signals B3-SRAM
ram_csn : out Std_Logic; -- RAM Chip select (active low)
ram_wrln : out Std_Logic; -- lower byte write strobe (active low)
ram_wrun : out Std_Logic; -- upper byte write strobe (active low)
ram_addr : out Std_Logic_Vector(16 downto 0); -- RAM Address bus
ram_data : inout Std_Logic_Vector(15 downto 0); -- RAM Data bus
 
-- Signals defined on B3-CPU-IO Module
LED : out std_logic; -- Diagnostic LED Flasher
 
-- Uart Interface
rxbit : in Std_Logic; -- UART receive data
txbit : out Std_Logic; -- UART transmit data
rts_n : out Std_Logic; -- Request to send (active low)
cts_n : in Std_Logic; -- Clear to send (active low)
 
-- CRTC output signals
-- v_drive : out Std_Logic;
-- h_drive : out Std_Logic;
-- blue_lo : out std_logic;
-- blue_hi : out std_logic;
-- green_lo : out std_logic;
-- green_hi : out std_logic;
-- red_lo : out std_logic;
-- red_hi : out std_logic;
-- buzzer : out std_logic;
 
-- Compact Flash B5-CF Module
cf_rst_n : out std_logic;
cf_cs0_n : out std_logic;
cf_cs1_n : out std_logic;
cf_rd_n : out std_logic;
cf_wr_n : out std_logic;
cf_cs16_n : out std_logic;
cf_a : out std_logic_vector(2 downto 0);
cf_d : inout std_logic_vector(15 downto 0);
-- cf_intrq : in std_logic;
-- cf_iordy : in std_logic;
-- cf_dase : in std_logic;
-- cf_pdiag : in std_logic;
-- cf_present : in std_logic;
 
-- Test Pins
test_alu : out std_logic_vector(15 downto 0); -- ALU output for timing constraints
test_cc : out std_logic_vector(7 downto 0) -- Condition Code Outputs for timing constraints
);
end;
 
-------------------------------------------------------------------------------
-- Architecture for memio Controller Unit
-------------------------------------------------------------------------------
architecture my_computer of System68 is
-----------------------------------------------------------------------------
-- Signals
-----------------------------------------------------------------------------
Signal SysClk : std_logic;
signal reset_n : std_logic;
 
-- Compact Flash BOOT ROM
-- signal boot_cs : Std_Logic;
-- signal boot_data_out : Std_Logic_Vector(7 downto 0);
 
-- SWTBUG in Slices
signal monitor_cs : Std_Logic;
signal monitor_data_out : Std_Logic_Vector(7 downto 0);
 
-- SWTBUG in Block RAM
signal swtbug_cs : Std_Logic;
signal swtbug_hold : Std_Logic;
signal swtbug_data_out : Std_Logic_Vector(7 downto 0);
 
-- UART Interface signals
signal uart_cs : Std_Logic;
signal uart_data_out : Std_Logic_Vector(7 downto 0);
signal uart_irq : Std_Logic;
 
-- timer
signal timer_cs : std_logic;
signal timer_data_out : std_logic_vector(7 downto 0);
signal timer_irq : std_logic;
signal timer_out : std_logic;
 
-- trap
-- signal trap_cs : std_logic;
-- signal trap_data_out : std_logic_vector(7 downto 0);
-- signal trap_irq : std_logic;
 
-- compact flash port
signal cf_cs : std_logic;
signal cf_rd : std_logic;
signal cf_wr : std_logic;
signal cf_data_out : std_logic_vector(7 downto 0);
 
-- RAM
signal ram_cs : std_logic; -- memory chip select
signal ram_wrl : std_logic; -- memory write lower
signal ram_wru : std_logic; -- memory write upper
signal ram_data_out : std_logic_vector(7 downto 0);
 
-- CPU Interface signals
signal cpu_reset : Std_Logic;
signal cpu_rw : std_logic;
signal cpu_vma : std_logic;
signal cpu_halt : std_logic;
signal cpu_hold : std_logic;
signal cpu_irq : std_logic;
signal cpu_nmi : std_logic;
signal cpu_addr : Std_Logic_Vector(15 downto 0);
signal cpu_data_in : Std_Logic_Vector(7 downto 0);
signal cpu_data_out : Std_Logic_Vector(7 downto 0);
 
-- test signals
-- signal test_alu : std_logic_vector(15 downto 0); -- ALU output for timing constraints
-- signal test_cc : std_logic_vector(7 downto 0); -- Condition Code Outputs for timing constraints
 
-- Dynamic Address Translation RAM
signal dat_cs : std_logic;
signal dat_addr : std_logic_vector(7 downto 0);
 
-- Boot ROM map Switch
-- signal map_cs : std_logic;
-- signal map_sw : std_logic; -- reset high for ROM. Write low for RAM
 
-- Clock Generator
-- signal CpuClk : std_logic; -- unbuffered clock - SysClk / 4
-- signal cpu_clk : std_logic; -- buffered clock
-- signal clk_divider : std_logic_vector(1 downto 0); -- divide by 4 counter
 
-- Flashing Led test signals
signal countL : std_logic_vector(23 downto 0);
 
-----------------------------------------------------------------
--
-- CPU68 CPU core
--
-----------------------------------------------------------------
 
component cpu68
port (
clk: in std_logic;
rst: in std_logic;
rw: out std_logic; -- Asynchronous memory interface
vma: out std_logic;
address: out std_logic_vector(15 downto 0);
data_in: in std_logic_vector(7 downto 0);
data_out: out std_logic_vector(7 downto 0);
hold: in std_logic;
halt: in std_logic;
irq: in std_logic;
nmi: in std_logic;
test_alu: out std_logic_vector(15 downto 0);
test_cc: out std_logic_vector(7 downto 0)
);
end component;
 
-----------------------------------------------------------------
--
-- Open Cores Mini UART
--
-----------------------------------------------------------------
 
component miniUART
port (
clk : in Std_Logic; -- System Clock
rst : in Std_Logic; -- Reset input
cs : in Std_Logic;
rw : in Std_Logic;
RxD : in Std_Logic;
TxD : out Std_Logic;
CTS_n : in Std_Logic;
RTS_n : out Std_Logic;
Irq : out Std_logic;
Addr : in Std_Logic;
DataIn : in Std_Logic_Vector(7 downto 0); --
DataOut : out Std_Logic_Vector(7 downto 0)); --
end component;
 
 
----------------------------------------
--
-- Timer module
--
----------------------------------------
 
component timer
port (
clk : in std_logic;
rst : in std_logic;
cs : in std_logic;
rw : in std_logic;
addr : in std_logic;
data_in : in std_logic_vector(7 downto 0);
data_out : out std_logic_vector(7 downto 0);
irq : out std_logic;
timer_in : in std_logic;
timer_out : out std_logic
);
end component;
 
--component trap
-- port (
-- clk : in std_logic;
-- rst : in std_logic;
-- cs : in std_logic;
-- rw : in std_logic;
-- vma : in std_logic;
-- addr : in std_logic_vector(15 downto 0);
-- data_in : in std_logic_vector(7 downto 0);
-- data_out : out std_logic_vector(7 downto 0);
-- irq : out std_logic
-- );
--end component trap;
 
component dat_ram
port (
clk: in std_logic;
rst: in std_logic;
cs: in std_logic;
rw: in std_logic;
addr_lo: in std_logic_vector(3 downto 0);
addr_hi: in std_logic_vector(3 downto 0);
data_in: in std_logic_vector(7 downto 0);
data_out: out std_logic_vector(7 downto 0)
);
end component;
 
--component boot_rom
-- port (
-- cs : in std_logic;
-- addr : in Std_Logic_Vector(7 downto 0); -- 256 byte cf boot rom
-- data : out Std_Logic_Vector(7 downto 0)
-- );
--end component boot_rom;
 
--
-- SWTBug Monitor ROM at $E000
--
component monitor_rom
port (
cs : in std_logic;
addr : in Std_Logic_Vector(9 downto 0); -- 1K byte boot rom
data : out Std_Logic_Vector(7 downto 0)
);
end component;
 
 
component BUFG
port (
i: in std_logic;
o: out std_logic
);
end component;
 
--
-- SWTBUG Monitor in Block RAM
--
component swtbug_rom
port (
clk : in std_logic;
rst : in std_logic;
cs : in std_logic;
hold : out std_logic;
rw : in std_logic;
addr : in std_logic_vector (9 downto 0);
wdata : in std_logic_vector (7 downto 0);
rdata : out std_logic_vector (7 downto 0)
);
end component;
 
begin
-----------------------------------------------------------------------------
-- Instantiation of internal components
-----------------------------------------------------------------------------
 
my_cpu : cpu68 port map (
clk => SysClk,
-- clk => cpu_clk,
rst => cpu_reset,
rw => cpu_rw,
vma => cpu_vma,
address => cpu_addr(15 downto 0),
data_in => cpu_data_in,
data_out => cpu_data_out,
hold => cpu_hold,
halt => cpu_halt,
irq => cpu_irq,
nmi => cpu_nmi,
test_alu => test_alu,
test_cc => test_cc
);
 
my_uart : miniUART port map (
clk => SysClk,
-- clk => cpu_clk,
rst => cpu_reset,
cs => uart_cs,
rw => cpu_rw,
RxD => rxbit,
TxD => txbit,
CTS_n => cts_n,
RTS_n => rts_n,
Irq => uart_irq,
Addr => cpu_addr(0),
Datain => cpu_data_out,
DataOut => uart_data_out
);
 
my_timer : timer port map (
clk => SysClk,
-- clk => cpu_clk,
rst => cpu_reset,
cs => timer_cs,
rw => cpu_rw,
addr => cpu_addr(0),
data_in => cpu_data_out,
data_out => timer_data_out,
irq => timer_irq,
timer_in => CountL(5),
timer_out => timer_out
);
 
--my_trap : trap port map (
-- clk => cpu_clk,
-- rst => cpu_reset,
-- cs => trap_cs,
-- rw => cpu_rw,
-- vma => cpu_vma,
-- addr => cpu_addr,
-- data_in => cpu_data_out,
-- data_out => trap_data_out,
-- irq => trap_irq
-- );
 
my_dat : dat_ram port map (
clk => SysClk,
-- clk => cpu_clk,
rst => cpu_reset,
cs => dat_cs,
rw => cpu_rw,
addr_hi => cpu_addr(15 downto 12),
addr_lo => cpu_addr(3 downto 0),
data_in => cpu_data_out,
data_out => dat_addr(7 downto 0)
);
 
--my_boot_rom : boot_rom port map (
-- cs => boot_cs,
-- addr => cpu_addr(7 downto 0),
-- data => boot_data_out
-- );
 
--
-- SWTBUG Monitor
--
my_monitor_rom : monitor_rom port map (
cs => monitor_cs,
addr => cpu_addr(9 downto 0),
data => monitor_data_out
);
 
--
-- SWTBUG Monitor using BLOCKRAM
--
my_swtbug_rom : swtbug_rom port map (
clk => SysClk,
rst => cpu_reset,
cs => swtbug_cs,
hold => swtbug_hold,
rw => cpu_rw,
addr => cpu_addr(9 downto 0),
wdata => cpu_data_out,
rdata => swtbug_data_out
);
 
 
--clock_buffer : BUFG port map (
-- i => CpuClk,
-- o => cpu_clk
-- );
----------------------------------------------------------------------
--
-- Processes to decode the CPU address
--
----------------------------------------------------------------------
 
decode: process( cpu_addr, cpu_rw, cpu_vma, cpu_data_in,
-- boot_cs, boot_data_out,
monitor_cs, monitor_data_out,
ram_cs, ram_data_out,
swtbug_cs, swtbug_data_out,
uart_cs, uart_data_out,
cf_cs, cf_data_out,
timer_cs, timer_data_out,
-- trap_cs, trap_data_out,
-- map_cs, map_sw,
dat_cs )
begin
--
-- Memory Map
--
case cpu_addr(15 downto 13) is
when "111" => -- $E000 - $FFFF
cpu_data_in <= monitor_data_out; -- read ROM
monitor_cs <= cpu_vma;
swtbug_cs <= '0';
-- boot_cs <= '0';
dat_cs <= cpu_vma; -- write DAT
ram_cs <= '0';
uart_cs <= '0';
cf_cs <= '0';
timer_cs <= '0';
-- trap_cs <= '0';
-- map_cs <= '0';
-- when "1101" => -- $D000 - $DFFF
-- monitor_cs <= '0';
-- swtbug_cs <= '0';
-- if map_sw = '1' then
-- cpu_data_in <= boot_data_out; -- read ROM
-- boot_cs <= cpu_vma; -- boot rom read only
-- dat_cs <= '0'; -- disable write to DAT
-- ram_cs <= cpu_vma; -- enable write to RAM
-- else
-- cpu_data_in <= ram_data_out; -- read RAM
-- boot_cs <= '0'; -- disable boot rom
-- dat_cs <= cpu_vma; -- enable write DAT
-- ram_cs <= cpu_vma and cpu_rw; -- disable write to RAM
-- end if;
-- uart_cs <= '0';
-- cf_cs <= '0';
-- timer_cs <= '0';
-- trap_cs <= '0';
-- map_cs <= '0';
when "110" => -- $C000 - $DFFF
cpu_data_in <= swtbug_data_out;
monitor_cs <= '0';
swtbug_cs <= cpu_vma;
-- boot_cs <= '0';
dat_cs <= '0';
ram_cs <= '0';
uart_cs <= '0';
cf_cs <= '0';
timer_cs <= '0';
-- trap_cs <= '0';
-- map_cs <= '0';
when "100" => -- $8000 - $9FFF
monitor_cs <= '0';
swtbug_cs <= '0';
-- boot_cs <= '0';
dat_cs <= '0';
ram_cs <= '0';
case cpu_addr(6 downto 4) is
--
-- UART
--
when "000" => -- ($8000 - $800F)
cpu_data_in <= uart_data_out;
uart_cs <= cpu_vma;
cf_cs <= '0';
timer_cs <= '0';
-- trap_cs <= '0';
-- map_cs <= '0';
--
-- Compact Flash
--
when "001" => -- ($8010 - $801F)
cpu_data_in <= cf_data_out;
uart_cs <= '0';
cf_cs <= cpu_vma;
timer_cs <= '0';
-- trap_cs <= '0';
-- map_cs <= '0';
--
-- Timer
--
when "010" => -- ($8020 - $802F)
cpu_data_in <= timer_data_out;
uart_cs <= '0';
cf_cs <= '0';
timer_cs <= cpu_vma;
-- trap_cs <= '0';
-- map_cs <= '0';
--
-- Memory Map switch
--
when "011" => -- ($8030 - $803F)
cpu_data_in <= "00000000";
uart_cs <= '0';
cf_cs <= '0';
timer_cs <= '0';
-- trap_cs <= '0';
-- map_cs <= cpu_vma;
--
-- Trap hardware
--
-- when "100" => -- ($8040 - $804F)
-- cpu_data_in <= trap_data_out;
-- uart_cs <= '0';
-- cf_cs <= '0';
-- timer_cs <= '0';
-- trap_cs <= cpu_vma;
-- map_cs <= '0';
--
-- Null devices
--
when others => -- $8050 to $9FFF
cpu_data_in <= "00000000";
uart_cs <= '0';
cf_cs <= '0';
timer_cs <= '0';
-- trap_cs <= '0';
-- map_cs <= '0';
end case;
when "000" | -- $0000 - $1FFF
"001" | -- $2000 - $3FFF
"010" | -- $4000 - $5FFF
"011" | -- $6000 - $7FFF
"101" => -- $A000 - $BFFF
cpu_data_in <= ram_data_out;
monitor_cs <= '0';
swtbug_cs <= '0';
-- boot_cs <= '0';
ram_cs <= cpu_vma;
dat_cs <= '0';
uart_cs <= '0';
cf_cs <= '0';
timer_cs <= '0';
-- trap_cs <= '0';
-- map_cs <= '0';
when others =>
cpu_data_in <= "00000000";
monitor_cs <= '0';
swtbug_cs <= '0';
-- boot_cs <= '0';
ram_cs <= '0';
dat_cs <= '0';
uart_cs <= '0';
cf_cs <= '0';
timer_cs <= '0';
-- trap_cs <= '0';
-- map_cs <= '0';
end case;
end process;
 
 
----------------------------------------------------------------------
--
-- Processes to read and write B3_SRAM
--
----------------------------------------------------------------------
b3_sram: process( SysClk, Reset_n,
cpu_addr, cpu_rw, cpu_data_out,
ram_cs, ram_wrl, ram_wru,
dat_cs, dat_addr, ram_data_out )
begin
ram_csn <= not( ram_cs and Reset_n);
ram_wrl <= dat_addr(5) and (not cpu_rw) and SysClk;
ram_wrln <= not ram_wrl;
ram_wru <= (not dat_addr(5)) and (not cpu_rw) and SysClk;
ram_wrun <= not ram_wru;
ram_addr(16 downto 12) <= dat_addr(4 downto 0);
ram_addr(11 downto 0 ) <= cpu_addr(11 downto 0);
 
if ram_wrl = '1' then
ram_data(7 downto 0) <= cpu_data_out;
else
ram_data(7 downto 0) <= "ZZZZZZZZ";
end if;
 
if ram_wru = '1' then
ram_data(15 downto 8) <= cpu_data_out;
else
ram_data(15 downto 8) <= "ZZZZZZZZ";
end if;
 
if dat_addr(5) = '0' then
ram_data_out <= ram_data(15 downto 8);
else
ram_data_out <= ram_data(7 downto 0);
end if;
 
end process;
 
--
-- B5-CF Compact Flash Control
--
b5_cf: process( Reset_n,
cpu_addr, cpu_rw, cpu_data_out,
cf_cs, cf_rd, cf_wr, cf_d )
begin
cf_rst_n <= Reset_n;
cf_cs0_n <= not( cf_cs ) or cpu_addr(3);
cf_cs1_n <= not( cf_cs and cpu_addr(3));
cf_cs16_n <= '1';
cf_wr <= cf_cs and (not cpu_rw);
cf_rd <= cf_cs and cpu_rw;
cf_wr_n <= not cf_wr;
cf_rd_n <= not cf_rd;
cf_a <= cpu_addr(2 downto 0);
if cf_wr = '1' then
cf_d(7 downto 0) <= cpu_data_out;
else
cf_d(7 downto 0) <= "ZZZZZZZZ";
end if;
cf_data_out <= cf_d(7 downto 0);
cf_d(15 downto 8) <= "ZZZZZZZZ";
end process;
 
--
-- ROM Map switch
-- The Map switch output is initially set
-- On a Write to the Map Switch port, clear the Map Switch
-- and map the RAM in place of the boot ROM.
--
--map_proc : process( SysClk, Reset_n, map_cs, cpu_rw )
--begin
-- if Sysclk'event and Sysclk = '1' then
-- if Reset_n = '0' then
-- map_sw <= '1';
-- else
-- if (map_cs = '1') and (cpu_rw = '0') then
-- map_sw <= '0';
-- else
-- map_sw <= map_sw;
-- end if;
-- end if;
-- end if;
--end process;
 
--
-- Interrupts and Reset.
--
interrupts : process( Reset_n, cpu_vma,
-- trap_irq,
swtbug_hold,
timer_irq, uart_irq )
begin
cpu_halt <= '0';
cpu_hold <= swtbug_hold;
-- cpu_hold <= '0';
cpu_irq <= uart_irq or timer_irq;
-- cpu_nmi <= trap_irq;
cpu_nmi <= '0';
cpu_reset <= not Reset_n; -- CPU reset is active high
end process;
 
--
-- Divide by 4 clock generator
--
--clock_gen: process (SysClk, clk_divider )
--begin
-- if(SysClk'event and SysClk = '0') then
-- clk_divider <= clk_divider + "01";
-- end if;
-- CpuClk <= clk_divider(1);
--end process;
 
--
-- flash led to indicate code is working
--
flash: process (SysClk, CountL )
begin
if(SysClk'event and SysClk = '0') then
countL <= countL + 1;
end if;
LED <= countL(21);
end process;
 
-- *** Test Bench - User Defined Section ***
tb : PROCESS
variable count : integer;
BEGIN
 
SysClk <= '0';
Reset_n <= '0';
 
for count in 0 to 512 loop
SysClk <= '0';
if count = 0 then
Reset_n <= '0';
elsif count = 1 then
Reset_n <= '1';
end if;
wait for 100 ns;
SysClk <= '1';
wait for 100 ns;
end loop;
 
wait; -- will wait forever
END PROCESS;
end my_computer; --===================== End of architecture =======================--
 
/trunk/vhdl/swtbug_rom.vhd
0,0 → 1,126
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
library unisim;
use unisim.all;
--library simprim;
-- use simprim.all;
 
entity swtbug_rom is
Port (
clk : in std_logic;
rst : in std_logic;
cs : in std_logic;
rw : in std_logic;
addr : in std_logic_vector (9 downto 0);
wdata : in std_logic_vector (7 downto 0);
rdata : out std_logic_vector (7 downto 0)
);
end swtbug_rom;
 
architecture rtl of swtbug_rom is
 
signal we : std_logic;
signal reset : std_logic;
signal rdata0 : std_logic_vector (7 downto 0);
signal rdata1 : std_logic_vector (7 downto 0);
signal ena0 : std_logic;
signal ena1 : std_logic;
 
component RAMB4_S8
generic (
INIT_00, INIT_01, INIT_02, INIT_03,
INIT_04, INIT_05, INIT_06, INIT_07,
INIT_08, INIT_09, INIT_0A, INIT_0B,
INIT_0C, INIT_0D, INIT_0E, INIT_0F : bit_vector (255 downto 0) :=
x"0000000000000000000000000000000000000000000000000000000000000000"
);
 
port (
clk, we, en, rst : in std_logic;
addr : in std_logic_vector(8 downto 0);
di : in std_logic_vector(7 downto 0);
do : out std_logic_vector(7 downto 0)
);
end component;
 
begin
 
ROM0 : RAMB4_S8
generic map (
INIT_00 => x"7FF026318129273981618DFA265381678D34E3BD041610006E408D006E00A0FE",
INIT_01 => x"CF270FA07CF02008082600A100A7092747A07A288D1C8D47A0B70280318D0FA0",
INIT_02 => x"161B4C8D1648484848538D390DA0FE0EA0B7078D0DA0B70C8DD4E27E318D3F86",
INIT_03 => x"00A608F88DACE17ED1E17E078B02233981308B0F8444444444390FA0F70FA0FB",
INIT_04 => x"272081DB8D318D318D0DA0FE348D0DA0CEEF8D9DE1CEBD8D4AE17E39F7260481",
INIT_05 => x"A6390780402E1681442B11810A2F09814C2B3080CC8D012C205E81E0270D81FA",
INIT_06 => x"A0FFAC200DA0FF090907262C2042A08EA5202086F38DF58DA3200800A6A48D00",
INIT_07 => x"2008A0BE40E07E912700A100A70957E0BDBD8D9D224681A12530816D2002200D",
INIT_08 => x"A7118600A7038639261920022002A100A684E2BD0480CE08E3BDFF8608A0BF49",
INIT_09 => x"8A8D8C8D8E8D0808A0FE7EE0BD9DE1CE066A056A0226066D3008A0BF012F2000",
INIT_0A => x"738D0CA07F0AA0FF0480CE42A08E192723E18C12A0FEC8E0BD08A0CE848D868D",
INIT_0B => x"6E01EECCE0BD072600A1D1E3CE398D7EE0BD9CE1CE47E3BD53E3BD7DE2BD0327",
INIT_0C => x"150A0D13043153000000150A0D043953006E12A0FEBF20ED26F8E38C08080800",
INIT_0D => x"0DA0FF00A61655E0BD47E0BD04A0FF47E0BD4020006E06A0FE4C200424000000",
INIT_0E => x"393303E101E6370AA0FE10A0FF3A203B10200DA0CE7EE0BD9DE1CE2120022711",
INIT_0F => x"A600A715862826DA8D37313131397F84068DCD20089E2704A0BC0DA0FEC8E0BD"
)
 
port map ( clk => clk,
en => ena0,
we => we,
rst => reset,
addr(8 downto 0) => addr(8 downto 0),
di(7 downto 0) => wdata(7 downto 0),
do(7 downto 0) => rdata0(7 downto 0)
);
 
ROM1 : RAMB4_S8
generic map (
INIT_00 => x"FE3301A7FA24575700E600E711C62E26C38D37112007270CA0F601A6FB244700",
INIT_01 => x"DE2013270CA0F6218DF7265A4600690D2A8D5802E704C63A8DFC2B00A63910A0",
INIT_02 => x"026CFC2A026DC420028DC82A5802E6F7265A460D00A7108D168D006A0AC6238D",
INIT_03 => x"A7348676E17E17EFE3CE078D108D0AA0FE0BA07F16838DF120F78D026F39026A",
INIT_04 => x"066FFA2601C504E6258D0BC62E8D14807F3902A7006C01A70786006C3902A703",
INIT_05 => x"8D04E700247EEF2601C51880F60800A71B80B6062702C50024CE178D9CC61D8D",
INIT_06 => x"2712A0BC23E1CE582047E3BDF18D7EE0BD09E0CE39FA2614808C09FFFFCE3900",
INIT_07 => x"A0B614A0FE6BE17E1E8D23E1CE00A73F8616A0B700A614A0FF47E0BD328D081A",
INIT_08 => x"A0CE0F205A8D3912A0FF24E1CE062723E18C12A0FE43A0B7DA2024E1CE00A716",
INIT_09 => x"D9E1BD1A8D20C611860CA07352E17E918D248D7EE0BD90E1CE528D0904A0FF49",
INIT_0A => x"861627D6E1BD75E0BD08C61486042004C612860A2010C613863903A73C860427",
INIT_0B => x"A0B6CF8D44A0FF02A0FE3900E701A70686028D00E701C60286088D0C8D01CA02",
INIT_0C => x"BD93E1CE46A0B7038047A0B7048B0F8602251081042644A0F204A0F645A0B005",
INIT_0D => x"8D30375344A0FFF92646A07A188D44A0FE1D8D1F8D44A0CE248D47A0CE5F7EE0",
INIT_0E => x"30E152AEE14688E04D00C05AD0E147BFE07E00EB39B32604A0BC0944A0FE330B",
INIT_0F => x"D0E0A7E18BE100E01EE3450CE04C1AE35069E24FD9E2428FE244CCE24305E04A"
)
 
port map ( clk => clk,
en => ena1,
we => we,
rst => reset,
addr(8 downto 0) => addr(8 downto 0),
di(7 downto 0) => wdata(7 downto 0),
do(7 downto 0) => rdata1(7 downto 0)
);
 
my_swtbug : process ( clk, rst, cs, rw, rdata0, rdata1 )
begin
if addr(9) = '0' then
ena0 <= cs;
ena1 <= '0';
rdata <= rdata0;
else
ena0 <= '0';
ena1 <= cs;
rdata <= rdata1;
end if;
 
we <= cs and (not rw);
reset <= '0';
 
end process my_swtbug;
 
end;
 
/trunk/vhdl/blockram.vhd
0,0 → 1,245
--===========================================================================----
--
-- S Y N T H E Z I A B L E 2K Synchronous RAM Module
--
-- www.OpenCores.Org - September 2003
-- This core adheres to the GNU public license
--
-- File name : blockram.vhd
--
-- Purpose : 2KByte Block RAM instance
--
-- Dependencies : ieee.Std_Logic_1164
-- ieee.std_logic_unsigned
-- ieee.std_logic_arith
-- unisim
--
-- Uses : RAMB4_S8 from Xilinx Web pack ISE 4.2.03i
--
-- Author : John E. Kent
--
--===========================================================================----
--
-- Revision History:
--===========================================================================--
--
-- Version 1.0
-- John Kent - 6 Sep 2003 - Initial release to Open Cores
--
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
library unisim;
use unisim.all;
 
entity block_ram is
Port (
MEMclk : in std_logic;
MEMcs : in std_logic;
MEMrw : in std_logic;
MEMaddr : in std_logic_vector (10 downto 0);
MEMrdata : out std_logic_vector (7 downto 0);
MEMwdata : in std_logic_vector (7 downto 0)
);
end block_ram;
 
architecture rtl of block_ram is
 
signal dout0 : std_logic_vector (7 downto 0);
signal dout1 : std_logic_vector (7 downto 0);
signal dout2 : std_logic_vector (7 downto 0);
signal dout3 : std_logic_vector (7 downto 0);
 
signal ena0 : std_logic;
signal ena1 : std_logic;
signal ena2 : std_logic;
signal ena3 : std_logic;
 
signal we : std_logic;
signal reset : std_logic;
 
component RAMB4_S8
generic (
INIT_00, INIT_01, INIT_02, INIT_03,
INIT_04, INIT_05, INIT_06, INIT_07,
INIT_08, INIT_09, INIT_0A, INIT_0B,
INIT_0C, INIT_0D, INIT_0E, INIT_0F : bit_vector (255 downto 0)
);
 
port (
clk, we, en, rst : in std_logic;
addr : in std_logic_vector(8 downto 0);
di : in std_logic_vector(7 downto 0);
do : out std_logic_vector(7 downto 0)
);
end component;
 
begin
 
RAM0 : RAMB4_S8
generic map (
INIT_00 => x"0000000000000000000000000000000000000000000000000000000000000000",
INIT_01 => x"0000000000000000000000000000000000000000000000000000000000000000",
INIT_02 => x"0000000000000000000000000000000000000000000000000000000000000000",
INIT_03 => x"0000000000000000000000000000000000000000000000000000000000000000",
INIT_04 => x"0000000000000000000000000000000000000000000000000000000000000000",
INIT_05 => x"0000000000000000000000000000000000000000000000000000000000000000",
INIT_06 => x"0000000000000000000000000000000000000000000000000000000000000000",
INIT_07 => x"0000000000000000000000000000000000000000000000000000000000000000",
INIT_08 => x"0000000000000000000000000000000000000000000000000000000000000000",
INIT_09 => x"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0A => x"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0B => x"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0C => x"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0D => x"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0E => x"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0F => x"0000000000000000000000000000000000000000000000000000000000000000"
)
 
port map ( clk => MEMclk,
en => ena0,
we => we,
rst => reset,
addr(8 downto 0) => MEMaddr(8 downto 0),
di(7 downto 0) => MEMwdata,
do(7 downto 0) => dout0(7 downto 0)
);
 
RAM1 : RAMB4_S8
generic map (
INIT_00 => x"0000000000000000000000000000000000000000000000000000000000000000",
INIT_01 => x"0000000000000000000000000000000000000000000000000000000000000000",
INIT_02 => x"0000000000000000000000000000000000000000000000000000000000000000",
INIT_03 => x"0000000000000000000000000000000000000000000000000000000000000000",
INIT_04 => x"0000000000000000000000000000000000000000000000000000000000000000",
INIT_05 => x"0000000000000000000000000000000000000000000000000000000000000000",
INIT_06 => x"0000000000000000000000000000000000000000000000000000000000000000",
INIT_07 => x"0000000000000000000000000000000000000000000000000000000000000000",
INIT_08 => x"0000000000000000000000000000000000000000000000000000000000000000",
INIT_09 => x"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0A => x"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0B => x"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0C => x"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0D => x"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0E => x"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0F => x"0000000000000000000000000000000000000000000000000000000000000000"
)
 
port map ( clk => MEMclk,
en => ena1,
we => we,
rst => reset,
addr(8 downto 0) => MEMaddr(8 downto 0),
di(7 downto 0) => MEMwdata,
do(7 downto 0) => dout1(7 downto 0)
);
 
RAM2 : RAMB4_S8
generic map (
INIT_00 => x"0000000000000000000000000000000000000000000000000000000000000000",
INIT_01 => x"0000000000000000000000000000000000000000000000000000000000000000",
INIT_02 => x"0000000000000000000000000000000000000000000000000000000000000000",
INIT_03 => x"0000000000000000000000000000000000000000000000000000000000000000",
INIT_04 => x"0000000000000000000000000000000000000000000000000000000000000000",
INIT_05 => x"0000000000000000000000000000000000000000000000000000000000000000",
INIT_06 => x"0000000000000000000000000000000000000000000000000000000000000000",
INIT_07 => x"0000000000000000000000000000000000000000000000000000000000000000",
INIT_08 => x"0000000000000000000000000000000000000000000000000000000000000000",
INIT_09 => x"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0A => x"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0B => x"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0C => x"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0D => x"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0E => x"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0F => x"0000000000000000000000000000000000000000000000000000000000000000"
)
 
port map ( clk => MEMclk,
en => ena2,
we => we,
rst => reset,
addr(8 downto 0) => MEMaddr(8 downto 0),
di(7 downto 0) => MEMwdata,
do(7 downto 0) => dout2(7 downto 0)
);
 
RAM3 : RAMB4_S8
generic map (
INIT_00 => x"0000000000000000000000000000000000000000000000000000000000000000",
INIT_01 => x"0000000000000000000000000000000000000000000000000000000000000000",
INIT_02 => x"0000000000000000000000000000000000000000000000000000000000000000",
INIT_03 => x"0000000000000000000000000000000000000000000000000000000000000000",
INIT_04 => x"0000000000000000000000000000000000000000000000000000000000000000",
INIT_05 => x"0000000000000000000000000000000000000000000000000000000000000000",
INIT_06 => x"0000000000000000000000000000000000000000000000000000000000000000",
INIT_07 => x"0000000000000000000000000000000000000000000000000000000000000000",
INIT_08 => x"0000000000000000000000000000000000000000000000000000000000000000",
INIT_09 => x"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0A => x"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0B => x"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0C => x"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0D => x"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0E => x"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0F => x"0000000000000000000000000000000000000000000000000000000000000000"
)
 
port map ( clk => MEMclk,
en => ena3,
we => we,
rst => reset,
addr(8 downto 0) => MEMaddr(8 downto 0),
di(7 downto 0) => MEMwdata,
do(7 downto 0) => dout3(7 downto 0)
);
 
my_ram : process ( MEMaddr, MEMrw, MEMcs, dout0, dout1, dout2, dout3 )
begin
case MEMaddr(10 downto 9) is
when "00" =>
ena0 <= '1';
ena1 <= '0';
ena2 <= '0';
ena3 <= '0';
when "01" =>
ena0 <= '0';
ena1 <= '1';
ena2 <= '0';
ena3 <= '0';
when "10" =>
ena0 <= '0';
ena1 <= '0';
ena2 <= '1';
ena3 <= '0';
when "11" =>
ena0 <= '0';
ena1 <= '0';
ena2 <= '0';
ena3 <= '1';
when others =>
ena0 <= '0';
ena1 <= '0';
ena2 <= '0';
ena3 <= '0';
end case;
 
case MEMaddr(10 downto 9) is
when "00" =>
MEMrdata <= dout0;
when "01" =>
MEMrdata <= dout1;
when "10" =>
MEMrdata <= dout2;
when "11" =>
MEMrdata <= dout3;
when others =>
MEMrdata <= "00000000";
end case;
 
we <= MEMcs and (not MEMrw);
reset <= '0';
 
end process my_ram;
 
end;
 
/trunk/vhdl/system68.ucf
1,133 → 1,179
#### UCF file created by Project Navigator
# Connector J9
NET "ram_addr<0>" LOC = "p108";
NET "ram_addr<1>" LOC = "p109";
NET "ram_addr<2>" LOC = "p110";
NET "ram_addr<3>" LOC = "p111";
NET "ram_addr<4>" LOC = "p112";
NET "ram_addr<5>" LOC = "p113";
NET "ram_addr<6>" LOC = "p114";
NET "ram_addr<7>" LOC = "p115";
NET "ram_csn" LOC = "p119";
NET "ram_addr<8>" LOC = "p120";
NET "ram_addr<9>" LOC = "p121";
NET "ram_addr<10>" LOC = "p122";
NET "ram_addr<11>" LOC = "p123";
NET "ram_addr<12>" LOC = "p125";
NET "ram_addr<13>" LOC = "p126";
NET "ram_addr<14>" LOC = "p127";
NET "ram_addr<15>" LOC = "p129";
NET "ram_addr<16>" LOC = "p132";
# Connector J6
NET "ram_data<0>" LOC = "p133";
NET "ram_data<1>" LOC = "p134";
NET "ram_data<2>" LOC = "p135";
NET "ram_data<3>" LOC = "p136";
NET "ram_data<4>" LOC = "p138";
NET "ram_data<5>" LOC = "p139";
NET "ram_data<6>" LOC = "p140";
NET "ram_data<7>" LOC = "p141";
NET "ram_data<8>" LOC = "p142";
NET "ram_data<9>" LOC = "p146";
NET "ram_data<10>" LOC = "p147";
NET "ram_data<11>" LOC = "p148";
NET "ram_data<12>" LOC = "p149";
NET "ram_data<13>" LOC = "p150";
NET "ram_data<14>" LOC = "p151";
NET "ram_data<15>" LOC = "p152";
NET "ram_wrun" LOC = "p153";
NET "ram_wrln" LOC = "p154";
# Connector J4
NET "porta<0>" LOC = "p160";
NET "porta<1>" LOC = "p161";
NET "porta<2>" LOC = "p162";
NET "porta<3>" LOC = "p163";
NET "porta<4>" LOC = "p164";
NET "porta<5>" LOC = "p165";
NET "porta<6>" LOC = "p166";
NET "porta<7>" LOC = "p167";
NET "portb<0>" LOC = "p168";
NET "portb<1>" LOC = "p172";
NET "portb<2>" LOC = "p173";
NET "portb<3>" LOC = "p174";
NET "portb<4>" LOC = "p175";
NET "portb<5>" LOC = "p176";
NET "portb<6>" LOC = "p178";
NET "portb<7>" LOC = "p179";
#NET "timer0_out" LOC = "p180";
#NET "timer0_in" LOC = "p182";
NET "timer_out" LOC = "p180";
# Connector J3
NET "portc<0>" LOC = "p181";
NET "portc<1>" LOC = "p187";
NET "portc<2>" LOC = "p188";
NET "portc<3>" LOC = "p189";
NET "portc<4>" LOC = "p191";
NET "portc<5>" LOC = "p192";
NET "portc<6>" LOC = "p193";
NET "portc<7>" LOC = "p194";
NET "portd<0>" LOC = "p195";
NET "portd<1>" LOC = "p199";
NET "portd<2>" LOC = "p200";
NET "portd<3>" LOC = "p201";
NET "portd<4>" LOC = "p202";
NET "portd<5>" LOC = "p203";
NET "portd<6>" LOC = "p204";
NET "portd<7>" LOC = "p205";
#NET "timer1_out" LOC = "p206";
#NET "timer1_in" LOC = "p185";
# Connector J10
NET "sysclk" LOC = "p77"; #pin 2
NET "led" LOC = "p49"; #pin 3
NET "uart_csn" LOC = "p57"; #pin 4
NET "test_rw" LOC = "p58"; #pin 5
NET "test_d0" LOC = "p59"; #pin 6
NET "test_d1" LOC = "p60"; #pin 7
NET "reset_n" LOC = "p61"; #pin 8
NET "test_cc<0>" LOC = "p67"; #pin 11
NET "test_cc<1>" LOC = "p68"; #pin 12
NET "test_cc<2>" LOC = "p69"; #pin 13
NET "test_cc<3>" LOC = "p70"; #pin 14
NET "test_cc<4>" LOC = "p71"; #pin 15
NET "test_cc<5>" LOC = "p73"; #pin 16
NET "test_cc<6>" LOC = "p74"; #pin 17
NET "test_cc<7>" LOC = "p75"; #pin 18
# Connector J11
NET "test_alu<0>" LOC = "p82"; #pin 3
NET "test_alu<1>" LOC = "p83"; #pin 4
NET "test_alu<2>" LOC = "p84"; #pin 5
NET "test_alu<3>" LOC = "p86"; #pin 6
NET "test_alu<4>" LOC = "p87"; #pin 7
NET "test_alu<5>" LOC = "p88"; #pin 8
NET "test_alu<6>" LOC = "p89"; #pin 9
NET "test_alu<7>" LOC = "p90"; #pin 10
NET "test_alu<8>" LOC = "p94"; #pin 11
NET "test_alu<9>" LOC = "p95"; #pin 12
NET "test_alu<10>" LOC = "p96"; #pin 13
NET "test_alu<11>" LOC = "p97"; #pin 14
NET "test_alu<12>" LOC = "p98"; #pin 15
NET "test_alu<13>" LOC = "p99"; #pin 16
NET "test_alu<14>" LOC = "p100"; #pin 17
NET "test_alu<15>" LOC = "p101"; #pin 18
# Connector J8
#NET "aux_clock" LOC = "p24"; #pin 2
NET "buzzer" LOC = "p27"; #pin 3
#NET "mouse_clock" LOC = "p29"; #pin 4
#NET "mouse_data" LOC = "p30"; #pin 5
NET "cts_n" LOC = "p31"; #pin 6
NET "rts_n" LOC = "p33"; #pin 7
NET "txbit" LOC = "p34"; #pin 8
NET "rxbit" LOC = "p35"; #pin 9
#NET "kb_clock" LOC = "p36"; #pin 10
#NET "kb_data" LOC = "p37"; #pin 11
NET "v_drive" LOC = "p41"; #pin 12
NET "h_drive" LOC = "p42"; #pin 13
NET "blue_lo" LOC = "p43";
NET "blue_hi" LOC = "p44";
NET "green_lo" LOC = "p45";
NET "green_hi" LOC = "p46";
NET "red_lo" LOC = "p47";
NET "red_hi" LOC = "p48";
#
NET "reset_n" LOC = "p57" ;
NET "sysclk" LOC = "p77" ;
#
# For B5-Compact-Flash:
# Connector A
#
#NET "pin2" LOC = "P3" ; #J1-2
#NET "pin3" LOC = "P4" ; #J1-3
#NET "cf_intrq" LOC = "P5" ; #J1-4
NET "cf_wr_n" LOC = "P6" ; #J1-5
NET "cf_rd_n" LOC = "P7" ; #J1-6
NET "cf_cs1_n" LOC = "P8" ; #J1-7
NET "cf_d<15>" LOC = "P9" ; #J1-8
NET "cf_d<14>" LOC = "P10" ; #J1-9
NET "cf_d<13>" LOC = "P11" ; #J1-10
NET "cf_d<12>" LOC = "P15" ; #J1-11
NET "cf_d<11>" LOC = "P16" ; #J1-12
#NET "cf_present" LOC = "P17" ; #J1-13
NET "cf_d<3>" LOC = "P18" ; #J1-14
NET "cf_d<4>" LOC = "P20" ; #J1-15
NET "cf_d<5>" LOC = "P21" ; #J1-16
NET "cf_d<6>" LOC = "P22" ; #J1-17
NET "cf_d<7>" LOC = "P23" ; #J1-18
NET "cf_cs0_n" LOC = "P24" ; #J1-19
#
# For B5-Compact-Flash:
# Connector B
#
NET "cf_a<2>" LOC = "P33" ; #J2-6
NET "cf_a<1>" LOC = "P34" ; #J2-7
NET "cf_a<0>" LOC = "P35" ; #J2-8
NET "cf_d<0>" LOC = "P36" ; #J2-9
NET "cf_d<1>" LOC = "P40" ; #J2-10
NET "cf_d<2>" LOC = "P41" ; #J2-11
NET "cf_cs16_n" LOC = "P42" ; #J2-12
NET "cf_d<10>" LOC = "P43" ; #J2-13
NET "cf_d<9>" LOC = "P44" ; #J2-14
NET "cf_d<8>" LOC = "P45" ; #J2-15
#NET "cf_pdiag" LOC = "P46" ; #J2-16
#NET "cf_dase" LOC = "P47" ; #J2-17
#NET "cf_iordy" LOC = "P48" ; #J2-18
NET "cf_rst_n" LOC = "P49" ; #J2-19
#
# For B5-Peripheral-Connectors
# Connector C
#
#NET "v_drive" LOC = "p55" ; #pin 3
#NET "h_drive" LOC = "p56" ; #pin 4
#NET "blue_lo" LOC = "p58" ; #pin 5
#NET "blue_hi" LOC = "p59" ; #pin 6
#NET "green_lo" LOC = "p60" ; #pin 7
#NET "green_hi" LOC = "p61" ; #pin 8
#NET "red_lo" LOC = "p62" ; #pin 9
#NET "red_hi" LOC = "p63" ; #pin 10
#NET "kb_clock" LOC = "p64" ; #pin 11
#NET "kb_data" LOC = "p68" ; #pin 12
#NET "mouse-clock" LOC = "p69" ; #pin 13
#NET "mouse_data" LOC = "p70" ; #pin 14
#NET "buzzer" LOC = "p71" ; #pin 15
NET "cts_n" LOC = "p73" ; #pin 16
NET "rxbit" LOC = "p74" ; #pin 17
NET "txbit" LOC = "p75" ; #pin 18
NET "rts_n" LOC = "p81" ; #pin 19
#
# I/O Port
# Connector D
#
#NET "glob_clk0" LOC = "p80" ; #pin 2 GCK0 Global Clock Input
NET "led" LOC = "p82" ; #pin 3
NET "porta<0>" LOC = "p83" ; #pin 4
NET "porta<1>" LOC = "p84" ; #pin 5
NET "porta<2>" LOC = "p86" ; #pin 6
NET "porta<3>" LOC = "p87" ; #pin 7
NET "porta<4>" LOC = "p88" ; #pin 8
NET "porta<5>" LOC = "p89" ; #pin 9
NET "porta<6>" LOC = "p93" ; #pin 10
NET "porta<7>" LOC = "p94" ; #pin 11
NET "portb<0>" LOC = "p95" ; #pin 12
NET "portb<1>" LOC = "p96" ; #pin 13
NET "portb<2>" LOC = "p97" ; #pin 14
NET "portb<3>" LOC = "p98" ; #pin 15
NET "portb<4>" LOC = "p99" ; #pin 16
NET "portb<5>" LOC = "p100"; #pin 17
NET "portb<6>" LOC = "p101"; #pin 18
NET "portb<7>" LOC = "p102"; #pin 19
#
# For B5-SRAM
# Connector E
#
NET "ram_csn" LOC = "p108"; #J1.2
NET "ram_addr<16>" LOC = "p109"; #J1.3
NET "ram_addr<15>" LOC = "p110"; #J1.4
NET "ram_addr<14>" LOC = "p111"; #J1.5
NET "ram_addr<13>" LOC = "p112"; #J1.6
NET "ram_addr<12>" LOC = "p113"; #J1.7
NET "ram_addr<11>" LOC = "p114"; #J1.8
NET "ram_addr<10>" LOC = "p115"; #J1.9
NET "ram_addr<9>" LOC = "p116"; #J1.10
NET "ram_addr<8>" LOC = "p120"; #J1.11
NET "ram_addr<7>" LOC = "p121"; #J1.12
NET "ram_addr<6>" LOC = "p122"; #J1.13
NET "ram_addr<5>" LOC = "p123"; #J1.14
NET "ram_addr<4>" LOC = "p125"; #J1.15
NET "ram_addr<3>" LOC = "p126"; #J1.16
NET "ram_addr<2>" LOC = "p127"; #J1.17
NET "ram_addr<1>" LOC = "p129"; #J1.18
NET "ram_addr<0>" LOC = "p132"; #J1.19
#
# For B5-SRAM
# Connector F
#
NET "ram_wrun" LOC = "p133"; #J2.2
NET "ram_wrln" LOC = "p134"; #J2.3
NET "ram_data<15>" LOC = "p135"; #J2.4
NET "ram_data<14>" LOC = "p136"; #J2.5
NET "ram_data<13>" LOC = "p138"; #J2.6
NET "ram_data<12>" LOC = "p139"; #J2.7
NET "ram_data<11>" LOC = "p140"; #J2.8
NET "ram_data<10>" LOC = "p141"; #J2.9
NET "ram_data<9>" LOC = "p145"; #J2.10
NET "ram_data<8>" LOC = "p146"; #J2.11
NET "ram_data<7>" LOC = "p147"; #J2.12
NET "ram_data<6>" LOC = "p148"; #J2.13
NET "ram_data<5>" LOC = "p149"; #J2.14
NET "ram_data<4>" LOC = "p150"; #J2.15
NET "ram_data<3>" LOC = "p151"; #J2.16
NET "ram_data<2>" LOC = "p152"; #J2.17
NET "ram_data<1>" LOC = "p153"; #J2.18
NET "ram_data<0>" LOC = "p154"; #J2.19
#
# Connector G
#
#NET "pin2" LOC = "p182"; #pin 2 (clk input)
NET "bus_addr<0>" LOC = "p160"; #pin 3
NET "bus_addr<1>" LOC = "p161"; #pin 4
NET "bus_addr<2>" LOC = "p162"; #pin 5
NET "bus_addr<3>" LOC = "p163"; #pin 6
NET "bus_addr<4>" LOC = "p164"; #pin 7
NET "bus_addr<5>" LOC = "p165"; #pin 8
NET "bus_addr<6>" LOC = "p166"; #pin 9
NET "bus_addr<7>" LOC = "p167"; #pin 10
NET "bus_addr<8>" LOC = "p168"; #pin 11
NET "bus_addr<9>" LOC = "p169"; #pin 12
NET "bus_addr<10>" LOC = "p173"; #pin 13
NET "bus_addr<11>" LOC = "p174"; #pin 14
NET "bus_addr<12>" LOC = "p175"; #pin 15
NET "bus_addr<13>" LOC = "p176"; #pin 16
NET "bus_addr<14>" LOC = "p178"; #pin 17
NET "bus_addr<15>" LOC = "p179"; #pin 18
#NET "pin19" LOC = "p180"; #pin 19
#
# Connector H
#
#NET "pin2" LOC = "p185"; #pin 2 (clk input)
#NET "porta<0>" LOC = "p181"; #pin 3
#NET "porta<1>" LOC = "p187"; #pin 4
#NET "porta<2>" LOC = "p188"; #pin 5
#NET "porta<3>" LOC = "p189"; #pin 6
NET "bus_reset" LOC = "p191"; #pin 7
NET "bus_clk" LOC = "p192"; #pin 8
NET "bus_cs" LOC = "p193"; #pin 9
NET "bus_rw" LOC = "p194"; #pin 10
NET "bus_data<0>" LOC = "p198"; #pin 11
NET "bus_data<1>" LOC = "p199"; #pin 12
NET "bus_data<2>" LOC = "p200"; #pin 13
NET "bus_data<3>" LOC = "p201"; #pin 14
NET "bus_data<4>" LOC = "p202"; #pin 15
NET "bus_data<5>" LOC = "p203"; #pin 16
NET "bus_data<6>" LOC = "p204"; #pin 17
NET "bus_data<7>" LOC = "p205"; #pin 18
NET "timer_out" LOC = "p206"; #pin 19
#
# Timing Groups
#
INST "ram_addr<0>" TNM = "ram_addr";
INST "ram_addr<1>" TNM = "ram_addr";
INST "ram_addr<2>" TNM = "ram_addr";
164,39 → 210,45
INST "ram_wrln" TNM = "ram_wr";
INST "ram_wrun" TNM = "ram_wr";
INST "ram_csn" TNM = "ram_cs";
INST "test_alu<0>" TNM = "test_alu";
INST "test_alu<1>" TNM = "test_alu";
INST "test_alu<2>" TNM = "test_alu";
INST "test_alu<3>" TNM = "test_alu";
INST "test_alu<4>" TNM = "test_alu";
INST "test_alu<5>" TNM = "test_alu";
INST "test_alu<6>" TNM = "test_alu";
INST "test_alu<7>" TNM = "test_alu";
INST "test_alu<8>" TNM = "test_alu";
INST "test_alu<9>" TNM = "test_alu";
INST "test_alu<10>" TNM = "test_alu";
INST "test_alu<11>" TNM = "test_alu";
INST "test_alu<12>" TNM = "test_alu";
INST "test_alu<13>" TNM = "test_alu";
INST "test_alu<14>" TNM = "test_alu";
INST "test_alu<15>" TNM = "test_alu";
INST "test_cc<0>" TNM = "test_cc";
INST "test_cc<1>" TNM = "test_cc";
INST "test_cc<2>" TNM = "test_cc";
INST "test_cc<3>" TNM = "test_cc";
INST "test_cc<4>" TNM = "test_cc";
INST "test_cc<5>" TNM = "test_cc";
INST "test_cc<6>" TNM = "test_cc";
INST "test_cc<7>" TNM = "test_cc";
TIMEGRP "ram_cs" OFFSET = OUT 35 ns AFTER "sysclk";
TIMEGRP "ram_wr" OFFSET = OUT 35 ns AFTER "sysclk";
TIMEGRP "ram_addr" OFFSET = OUT 35 ns AFTER "sysclk";
TIMEGRP "ram_data" OFFSET = OUT 35 ns AFTER "sysclk";
TIMEGRP "ram_data" OFFSET = IN 15 ns BEFORE "sysclk";
TIMEGRP "test_alu" OFFSET = OUT 90 ns AFTER "sysclk";
TIMEGRP "test_cc" OFFSET = OUT 90 ns AFTER "sysclk";
NET "sysclk" TNM_NET = "sysclk";
TIMESPEC "TS_sysclk" = PERIOD "sysclk" 100 ns HIGH 50 %;
INST "bus_addr<0>" TNM = "bus_addr";
INST "bus_addr<1>" TNM = "bus_addr";
INST "bus_addr<2>" TNM = "bus_addr";
INST "bus_addr<3>" TNM = "bus_addr";
INST "bus_addr<4>" TNM = "bus_addr";
INST "bus_addr<5>" TNM = "bus_addr";
INST "bus_addr<6>" TNM = "bus_addr";
INST "bus_addr<7>" TNM = "bus_addr";
INST "bus_addr<8>" TNM = "bus_addr";
INST "bus_addr<9>" TNM = "bus_addr";
INST "bus_addr<10>" TNM = "bus_addr";
INST "bus_addr<11>" TNM = "bus_addr";
INST "bus_addr<12>" TNM = "bus_addr";
INST "bus_addr<13>" TNM = "bus_addr";
INST "bus_addr<14>" TNM = "bus_addr";
INST "bus_addr<15>" TNM = "bus_addr";
INST "bus_data<0>" TNM = "bus_data";
INST "bus_data<1>" TNM = "bus_data";
INST "bus_data<2>" TNM = "bus_data";
INST "bus_data<3>" TNM = "bus_data";
INST "bus_data<4>" TNM = "bus_data";
INST "bus_data<5>" TNM = "bus_data";
INST "bus_data<6>" TNM = "bus_data";
INST "bus_data<7>" TNM = "bus_data";
#
# Timing Constraints
#
#NET "cpu_clk" TNM_NET = "cpu_clk";
#TIMEGRP "ram_cs" OFFSET = OUT 40 ns AFTER "cpu_clk";
#TIMEGRP "ram_wr" OFFSET = OUT 40 ns AFTER "cpu_clk";
#TIMEGRP "ram_addr" OFFSET = OUT 40 ns AFTER "cpu_clk";
#TIMEGRP "ram_data" OFFSET = OUT 40 ns AFTER "cpu_clk";
#TIMEGRP "ram_data" OFFSET = IN 15 ns BEFORE "cpu_clk";
#TIMEGRP "bus_addr" OFFSET = OUT 90 ns AFTER "cpu_clk";
#TIMEGRP "bus_data" OFFSET = OUT 95 ns AFTER "cpu_clk";
#TIMESPEC "TS_cpu_clk" = PERIOD "cpu_clk" 100 ns HIGH 50 %;
#
# Fast I/O Pins
#
NET "ram_addr<0>" FAST;
NET "ram_addr<1>" FAST;
NET "ram_addr<2>" FAST;

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