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URL https://opencores.org/ocsvn/a-z80/a-z80/trunk

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    /a-z80/trunk/host
    from Rev 5 to Rev 6
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Rev 5 → Rev 6

/zxspectrum/zxspectrum_board.qsf
590,45 → 590,45
set_global_assignment -name PHYSICAL_SYNTHESIS_COMBO_LOGIC_FOR_AREA ON
set_global_assignment -name PHYSICAL_SYNTHESIS_MAP_LOGIC_TO_MEMORY_FOR_AREA ON
set_global_assignment -name PHYSICAL_SYNTHESIS_EFFORT EXTRA
set_global_assignment -name VERILOG_FILE ../../cpu/registers/reg_latch.v
set_global_assignment -name VERILOG_FILE ../../cpu/registers/reg_file.v
set_global_assignment -name VERILOG_FILE ../../cpu/registers/reg_control.v
set_global_assignment -name VERILOG_FILE ../../cpu/control/sequencer.v
set_global_assignment -name VERILOG_FILE ../../cpu/control/resets.v
set_global_assignment -name VERILOG_FILE ../../cpu/control/ir.v
set_global_assignment -name VERILOG_FILE ../../cpu/control/interrupts.v
set_global_assignment -name VERILOG_FILE ../../cpu/control/decode_state.v
set_global_assignment -name VERILOG_FILE ../../cpu/control/clk_delay.v
set_global_assignment -name VERILOG_FILE ../../cpu/control/pin_control.v
set_global_assignment -name SYSTEMVERILOG_FILE ../../cpu/control/pla_decode.sv
set_global_assignment -name VERILOG_FILE ../../cpu/control/memory_ifc.v
set_global_assignment -name SYSTEMVERILOG_FILE ../../cpu/control/execute.sv
set_global_assignment -name SYSTEMVERILOG_FILE ../../cpu/bus/bus_switch.sv
set_global_assignment -name VERILOG_FILE ../../cpu/bus/inc_dec_2bit.v
set_global_assignment -name VERILOG_FILE ../../cpu/bus/inc_dec.v
set_global_assignment -name VERILOG_FILE ../../cpu/bus/data_switch_mask.v
set_global_assignment -name VERILOG_FILE ../../cpu/bus/data_switch.v
set_global_assignment -name VERILOG_FILE ../../cpu/bus/data_pins.v
set_global_assignment -name VERILOG_FILE ../../cpu/bus/control_pins_n.v
set_global_assignment -name VERILOG_FILE ../../cpu/bus/bus_control.v
set_global_assignment -name VERILOG_FILE ../../cpu/bus/address_pins.v
set_global_assignment -name VERILOG_FILE ../../cpu/bus/address_latch.v
set_global_assignment -name VERILOG_FILE ../../cpu/bus/address_mux.v
set_global_assignment -name VERILOG_FILE ../../cpu/alu/alu_slice.v
set_global_assignment -name VERILOG_FILE ../../cpu/alu/alu_shifter_core.v
set_global_assignment -name VERILOG_FILE ../../cpu/alu/alu_select.v
set_global_assignment -name VERILOG_FILE ../../cpu/alu/alu_prep_daa.v
set_global_assignment -name VERILOG_FILE ../../cpu/alu/alu_mux_8.v
set_global_assignment -name VERILOG_FILE ../../cpu/alu/alu_mux_4.v
set_global_assignment -name VERILOG_FILE ../../cpu/alu/alu_mux_3z.v
set_global_assignment -name VERILOG_FILE ../../cpu/alu/alu_mux_2z.v
set_global_assignment -name VERILOG_FILE ../../cpu/alu/alu_mux_2.v
set_global_assignment -name VERILOG_FILE ../../cpu/alu/alu_flags.v
set_global_assignment -name VERILOG_FILE ../../cpu/alu/alu_core.v
set_global_assignment -name VERILOG_FILE ../../cpu/alu/alu_control.v
set_global_assignment -name VERILOG_FILE ../../cpu/alu/alu_bit_select.v
set_global_assignment -name VERILOG_FILE ../../cpu/alu/alu.v
set_global_assignment -name SYSTEMVERILOG_FILE ../../cpu/toplevel/z80_top_direct_n.sv
set_global_assignment -name SYSTEMVERILOG_FILE ../../cpu/deploy/z80_top_direct_n.sv
set_global_assignment -name VERILOG_FILE ../../cpu/deploy/sequencer.v
set_global_assignment -name VERILOG_FILE ../../cpu/deploy/resets.v
set_global_assignment -name VERILOG_FILE ../../cpu/deploy/reg_latch.v
set_global_assignment -name VERILOG_FILE ../../cpu/deploy/reg_file.v
set_global_assignment -name VERILOG_FILE ../../cpu/deploy/reg_control.v
set_global_assignment -name SYSTEMVERILOG_FILE ../../cpu/deploy/pla_decode.sv
set_global_assignment -name VERILOG_FILE ../../cpu/deploy/pin_control.v
set_global_assignment -name VERILOG_FILE ../../cpu/deploy/memory_ifc.v
set_global_assignment -name VERILOG_FILE ../../cpu/deploy/ir.v
set_global_assignment -name VERILOG_FILE ../../cpu/deploy/interrupts.v
set_global_assignment -name VERILOG_FILE ../../cpu/deploy/inc_dec_2bit.v
set_global_assignment -name VERILOG_FILE ../../cpu/deploy/inc_dec.v
set_global_assignment -name SYSTEMVERILOG_FILE ../../cpu/deploy/execute.sv
set_global_assignment -name VERILOG_FILE ../../cpu/deploy/decode_state.v
set_global_assignment -name VERILOG_FILE ../../cpu/deploy/data_switch_mask.v
set_global_assignment -name VERILOG_FILE ../../cpu/deploy/data_switch.v
set_global_assignment -name VERILOG_FILE ../../cpu/deploy/data_pins.v
set_global_assignment -name VERILOG_FILE ../../cpu/deploy/control_pins_n.v
set_global_assignment -name VERILOG_FILE ../../cpu/deploy/clk_delay.v
set_global_assignment -name SYSTEMVERILOG_FILE ../../cpu/deploy/bus_switch.sv
set_global_assignment -name VERILOG_FILE ../../cpu/deploy/bus_control.v
set_global_assignment -name VERILOG_FILE ../../cpu/deploy/alu_slice.v
set_global_assignment -name VERILOG_FILE ../../cpu/deploy/alu_shifter_core.v
set_global_assignment -name VERILOG_FILE ../../cpu/deploy/alu_select.v
set_global_assignment -name VERILOG_FILE ../../cpu/deploy/alu_prep_daa.v
set_global_assignment -name VERILOG_FILE ../../cpu/deploy/alu_mux_8.v
set_global_assignment -name VERILOG_FILE ../../cpu/deploy/alu_mux_4.v
set_global_assignment -name VERILOG_FILE ../../cpu/deploy/alu_mux_3z.v
set_global_assignment -name VERILOG_FILE ../../cpu/deploy/alu_mux_2z.v
set_global_assignment -name VERILOG_FILE ../../cpu/deploy/alu_mux_2.v
set_global_assignment -name VERILOG_FILE ../../cpu/deploy/alu_flags.v
set_global_assignment -name VERILOG_FILE ../../cpu/deploy/alu_core.v
set_global_assignment -name VERILOG_FILE ../../cpu/deploy/alu_control.v
set_global_assignment -name VERILOG_FILE ../../cpu/deploy/alu_bit_select.v
set_global_assignment -name VERILOG_FILE ../../cpu/deploy/alu.v
set_global_assignment -name VERILOG_FILE ../../cpu/deploy/address_pins.v
set_global_assignment -name VERILOG_FILE ../../cpu/deploy/address_mux.v
set_global_assignment -name VERILOG_FILE ../../cpu/deploy/address_latch.v
set_global_assignment -name SYSTEMVERILOG_FILE ula/zx_kbd.sv
set_global_assignment -name SYSTEMVERILOG_FILE ula/video.sv
set_global_assignment -name SYSTEMVERILOG_FILE ula/ula.sv

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