OpenCores
URL https://opencores.org/ocsvn/a-z80/a-z80/trunk

Subversion Repositories a-z80

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  • This comparison shows the changes necessary to convert path 
    /a-z80
    from Rev 12 to Rev 13
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  •

Rev 12 → Rev 13

/trunk/cpu/bus/data_pins_lattice.v
0,0 → 1,40
// Use this file with Lattice toolset instead of data_pins.v
//
// data_pins.v is auto-generated by Altera Quartus IDE from a
// block schematic file data_pins.bdf
 
module data_pins(
bus_db_pin_oe,
bus_db_pin_re,
ctl_bus_db_we,
clk,
ctl_bus_db_oe,
D,
db
);
 
input wire bus_db_pin_oe;
input wire bus_db_pin_re;
input wire ctl_bus_db_we;
input wire clk;
input wire ctl_bus_db_oe;
inout wire [7:0] D;
inout wire [7:0] db;
 
reg [7:0] dout;
 
always@(negedge clk)
begin
if (ctl_bus_db_we | bus_db_pin_re)
begin
if (bus_db_pin_re)
dout <= D;
else if (ctl_bus_db_we)
dout <= db;
end
end
 
assign db = ctl_bus_db_oe ? dout : 8'hZ;
assign D = bus_db_pin_oe ? dout : 8'hZ;
 
endmodule
/trunk/cpu/control/decode_state.bdf
85,22 → 85,6
)
(pin
(input)
(rect 40 624 216 640)
(text "INPUT" (rect 133 0 161 10)(font "Arial" (font_size 6)))
(text "ctl_state_tbl_clr" (rect 9 0 86 12)(font "Arial" ))
(pt 176 8)
(drawing
(line (pt 92 12)(pt 117 12))
(line (pt 92 4)(pt 117 4))
(line (pt 121 8)(pt 176 8))
(line (pt 92 12)(pt 92 4))
(line (pt 117 4)(pt 121 8))
(line (pt 117 12)(pt 121 8))
)
(text "VCC" (rect 136 7 156 17)(font "Arial" (font_size 6)))
)
(pin
(input)
(rect 40 680 216 696)
(text "INPUT" (rect 133 0 161 10)(font "Arial" (font_size 6)))
(text "ctl_state_tbl_ed_set" (rect 9 0 108 12)(font "Arial" ))
244,6 → 228,38
(text "VCC" (rect 136 7 156 17)(font "Arial" (font_size 6)))
)
(pin
(input)
(rect 40 592 216 608)
(text "INPUT" (rect 133 0 161 10)(font "Arial" (font_size 6)))
(text "ctl_state_tbl_we" (rect 9 0 88 12)(font "Arial" ))
(pt 176 8)
(drawing
(line (pt 92 12)(pt 117 12))
(line (pt 92 4)(pt 117 4))
(line (pt 121 8)(pt 176 8))
(line (pt 92 12)(pt 92 4))
(line (pt 117 4)(pt 121 8))
(line (pt 117 12)(pt 121 8))
)
(text "VCC" (rect 136 7 156 17)(font "Arial" (font_size 6)))
)
(pin
(input)
(rect 40 624 216 640)
(text "INPUT" (rect 133 0 161 10)(font "Arial" (font_size 6)))
(text "hold_clk_wait" (rect 9 0 73 12)(font "Arial" ))
(pt 176 8)
(drawing
(line (pt 92 12)(pt 117 12))
(line (pt 92 4)(pt 117 4))
(line (pt 121 8)(pt 176 8))
(line (pt 92 12)(pt 92 4))
(line (pt 117 4)(pt 121 8))
(line (pt 117 12)(pt 121 8))
)
(text "VCC" (rect 136 7 156 17)(font "Arial" (font_size 6)))
)
(pin
(output)
(rect 640 384 816 400)
(text "OUTPUT" (rect 1 0 39 10)(font "Arial" (font_size 6)))
393,7 → 409,7
(pt 64 24)
(output)
(text "OUT" (rect 48 15 65 27)(font "Courier New" (bold))(invisible))
(text "OUT" (rect 48 15 65 27)(font "Courier New" (bold))(invisible))
(text "OUT" (rect 48 15 62 27)(font "Courier New" (bold))(invisible))
(line (pt 48 24)(pt 64 24))
)
(drawing
405,46 → 421,6
)
)
(symbol
(rect 328 608 392 656)
(text "OR3" (rect 1 0 19 10)(font "Arial" (font_size 6)))
(text "inst1" (rect 3 37 30 51)(font "Arial" (font_size 8)))
(port
(pt 0 24)
(input)
(text "IN2" (rect 2 15 19 27)(font "Courier New" (bold))(invisible))
(text "IN2" (rect 2 15 19 27)(font "Courier New" (bold))(invisible))
(line (pt 0 24)(pt 18 24))
)
(port
(pt 0 32)
(input)
(text "IN3" (rect 2 24 19 36)(font "Courier New" (bold))(invisible))
(text "IN3" (rect 2 24 19 36)(font "Courier New" (bold))(invisible))
(line (pt 0 32)(pt 16 32))
)
(port
(pt 0 16)
(input)
(text "IN1" (rect 2 7 19 19)(font "Courier New" (bold))(invisible))
(text "IN1" (rect 2 7 19 19)(font "Courier New" (bold))(invisible))
(line (pt 0 16)(pt 16 16))
)
(port
(pt 64 24)
(output)
(text "OUT" (rect 47 15 64 27)(font "Courier New" (bold))(invisible))
(text "OUT" (rect 47 15 64 27)(font "Courier New" (bold))(invisible))
(line (pt 49 24)(pt 64 24))
)
(drawing
(line (pt 14 13)(pt 25 13))
(line (pt 14 36)(pt 25 36))
(arc (pt 7 29)(pt 7 19)(rect -14 8 19 41))
(arc (pt 49 24)(pt 25 13)(rect -6 13 57 76))
(arc (pt 25 35)(pt 49 24)(rect -6 -27 57 36))
)
)
(symbol
(rect 552 608 616 656)
(text "NOR2" (rect 1 0 26 10)(font "Arial" (font_size 6)))
(text "inst3" (rect 3 37 26 49)(font "Arial" ))
466,7 → 442,7
(pt 64 24)
(output)
(text "OUT" (rect 48 15 65 27)(font "Courier New" (bold))(invisible))
(text "OUT" (rect 48 15 65 27)(font "Courier New" (bold))(invisible))
(text "OUT" (rect 48 15 62 27)(font "Courier New" (bold))(invisible))
(line (pt 54 24)(pt 64 24))
)
(drawing
500,7 → 476,7
(pt 64 24)
(output)
(text "OUT" (rect 48 15 65 27)(font "Courier New" (bold))(invisible))
(text "OUT" (rect 48 15 65 27)(font "Courier New" (bold))(invisible))
(text "OUT" (rect 48 15 62 27)(font "Courier New" (bold))(invisible))
(line (pt 44 24)(pt 64 24))
)
(drawing
527,7 → 503,7
(pt 48 16)
(output)
(text "OUT" (rect 32 7 49 19)(font "Courier New" (bold))(invisible))
(text "OUT" (rect 32 7 49 19)(font "Courier New" (bold))(invisible))
(text "OUT" (rect 32 7 46 19)(font "Courier New" (bold))(invisible))
(line (pt 39 16)(pt 48 16))
)
(drawing
580,7 → 556,7
(pt 64 24)
(output)
(text "Q" (rect 45 20 50 32)(font "Courier New" (bold)))
(text "Q" (rect 43 20 48 32)(font "Courier New" (bold)))
(text "Q" (rect 43 20 47 32)(font "Courier New" (bold)))
(line (pt 52 24)(pt 64 24))
)
(drawing
616,7 → 592,7
(pt 64 24)
(output)
(text "OUT" (rect 48 15 65 27)(font "Courier New" (bold))(invisible))
(text "OUT" (rect 48 15 65 27)(font "Courier New" (bold))(invisible))
(text "OUT" (rect 48 15 62 27)(font "Courier New" (bold))(invisible))
(line (pt 48 24)(pt 64 24))
)
(drawing
670,7 → 646,7
(pt 64 24)
(output)
(text "Q" (rect 44 20 49 32)(font "Courier New" (bold)))
(text "Q" (rect 44 20 49 32)(font "Courier New" (bold)))
(text "Q" (rect 44 20 48 32)(font "Courier New" (bold)))
(line (pt 53 24)(pt 64 24))
)
(drawing
727,7 → 703,7
(pt 64 24)
(output)
(text "Q" (rect 44 20 49 32)(font "Courier New" (bold)))
(text "Q" (rect 44 20 49 32)(font "Courier New" (bold)))
(text "Q" (rect 44 20 48 32)(font "Courier New" (bold)))
(line (pt 53 24)(pt 64 24))
)
(drawing
784,7 → 760,7
(pt 64 24)
(output)
(text "Q" (rect 44 20 49 32)(font "Courier New" (bold)))
(text "Q" (rect 44 20 49 32)(font "Courier New" (bold)))
(text "Q" (rect 44 20 48 32)(font "Courier New" (bold)))
(line (pt 53 24)(pt 64 24))
)
(drawing
841,7 → 817,7
(pt 64 24)
(output)
(text "Q" (rect 44 20 49 32)(font "Courier New" (bold)))
(text "Q" (rect 44 20 49 32)(font "Courier New" (bold)))
(text "Q" (rect 44 20 48 32)(font "Courier New" (bold)))
(line (pt 53 24)(pt 64 24))
)
(drawing
898,7 → 874,7
(pt 64 24)
(output)
(text "Q" (rect 44 20 49 32)(font "Courier New" (bold)))
(text "Q" (rect 44 20 49 32)(font "Courier New" (bold)))
(text "Q" (rect 44 20 48 32)(font "Courier New" (bold)))
(line (pt 53 24)(pt 64 24))
)
(drawing
912,6 → 888,63
(circle (rect 28 68 36 76))
)
)
(symbol
(rect 312 584 376 632)
(text "AND2" (rect 1 0 25 10)(font "Arial" (font_size 6)))
(text "inst6" (rect 3 37 26 49)(font "Arial" ))
(port
(pt 0 16)
(input)
(text "IN1" (rect 2 7 19 19)(font "Courier New" (bold))(invisible))
(text "IN1" (rect 2 7 19 19)(font "Courier New" (bold))(invisible))
(line (pt 0 16)(pt 14 16))
)
(port
(pt 0 32)
(input)
(text "IN2" (rect 2 23 19 35)(font "Courier New" (bold))(invisible))
(text "IN2" (rect 2 23 19 35)(font "Courier New" (bold))(invisible))
(line (pt 0 32)(pt 14 32))
)
(port
(pt 64 24)
(output)
(text "OUT" (rect 48 15 65 27)(font "Courier New" (bold))(invisible))
(text "OUT" (rect 48 15 62 27)(font "Courier New" (bold))(invisible))
(line (pt 42 24)(pt 64 24))
)
(drawing
(line (pt 14 12)(pt 30 12))
(line (pt 14 37)(pt 31 37))
(line (pt 14 12)(pt 14 37))
(arc (pt 31 37)(pt 30 12)(rect 18 12 43 37))
)
)
(symbol
(rect 224 616 272 648)
(text "NOT" (rect 1 0 21 10)(font "Arial" (font_size 6)))
(text "inst8" (rect 3 21 26 33)(font "Arial" ))
(port
(pt 0 16)
(input)
(text "IN" (rect 2 7 13 19)(font "Courier New" (bold))(invisible))
(text "IN" (rect 2 7 13 19)(font "Courier New" (bold))(invisible))
(line (pt 0 16)(pt 13 16))
)
(port
(pt 48 16)
(output)
(text "OUT" (rect 32 7 49 19)(font "Courier New" (bold))(invisible))
(text "OUT" (rect 32 7 46 19)(font "Courier New" (bold))(invisible))
(line (pt 39 16)(pt 48 16))
)
(drawing
(line (pt 13 25)(pt 13 7))
(line (pt 13 7)(pt 31 16))
(line (pt 13 25)(pt 31 16))
(circle (rect 31 12 39 20))
)
)
(connector
(pt 376 104)
(pt 440 104)
1039,10 → 1072,6
(pt 472 472)
)
(connector
(pt 440 608)
(pt 408 608)
)
(connector
(pt 440 720)
(pt 408 720)
)
1077,30 → 1106,6
(pt 640 632)
)
(connector
(pt 248 688)
(pt 248 640)
)
(connector
(pt 248 640)
(pt 328 640)
)
(connector
(pt 248 624)
(pt 328 624)
)
(connector
(pt 248 576)
(pt 248 624)
)
(connector
(pt 408 632)
(pt 392 632)
)
(connector
(pt 216 632)
(pt 328 632)
)
(connector
(text "nreset" (rect 429 632 459 644)(font "Arial" ))
(pt 472 648)
(pt 424 648)
1127,30 → 1132,6
(pt 640 576)
)
(connector
(pt 216 688)
(pt 248 688)
)
(connector
(pt 248 688)
(pt 440 688)
)
(connector
(pt 216 576)
(pt 248 576)
)
(connector
(pt 248 576)
(pt 440 576)
)
(connector
(pt 408 608)
(pt 408 632)
)
(connector
(pt 408 632)
(pt 408 720)
)
(connector
(pt 472 632)
(pt 472 648)
)
1190,14 → 1171,52
(pt 472 912)
(pt 472 928)
)
(connector
(pt 216 576)
(pt 440 576)
)
(connector
(pt 216 688)
(pt 440 688)
)
(connector
(pt 288 616)
(pt 312 616)
)
(connector
(pt 408 608)
(pt 408 720)
)
(connector
(pt 376 608)
(pt 408 608)
)
(connector
(pt 408 608)
(pt 440 608)
)
(connector
(pt 216 600)
(pt 312 600)
)
(connector
(pt 224 632)
(pt 216 632)
)
(connector
(pt 288 616)
(pt 288 632)
)
(connector
(pt 288 632)
(pt 272 632)
)
(junction (pt 312 256))
(junction (pt 256 96))
(junction (pt 536 104))
(junction (pt 536 688))
(junction (pt 536 576))
(junction (pt 248 688))
(junction (pt 248 576))
(junction (pt 408 632))
(junction (pt 408 608))
(text "IX and IY state flags" (rect 416 32 551 48)(font "Arial" (font_size 10)))
(text "HALT state flag" (rect 432 328 537 344)(font "Arial" (font_size 10)))
(text "ALU feedback wire" (rect 392 960 519 976)(font "Arial" (font_size 10)))
1206,11 → 1225,11
(title_block
(rect 40 1024 297 1076)
(name "title-custom-small")
(section (rect 0 35 256 51)(text "DATE" (rect 2 0 30 12)(font "Arial" ))(text "August 9, 2014" (rect 56 3 143 17)(font "Arial" (font_size 8)))(border))
(section (rect 0 0 256 17)(text "PROJECT" (rect 2 0 52 12)(font "Arial" ))(text "A-Z80" (rect 56 2 94 17)(font "Arial" (font_size 9)(bold)))(border))
(section (rect 104 0 256 17)(text "MODULE" (rect 2 1 48 13)(font "Arial" ))(text "decode_state" (rect 43 2 135 17)(font "Arial" (font_size 9)(bold)))(border))
(section (rect 0 18 256 34)(text "DESIGNER" (rect 2 0 59 12)(font "Arial" ))(text "Goran Devic" (rect 56 2 135 17)(font "Arial" (font_size 9)))(border))
(section (rect 104 0 256 17)(text "MODULE" (rect 2 1 48 13)(font "Arial" ))(text "decode_state" (rect 43 2 135 17)(font "Arial" (font_size 9)(bold)))(border))
(section (rect 0 0 256 17)(text "PROJECT" (rect 2 0 52 12)(font "Arial" ))(text "A-Z80" (rect 56 2 94 17)(font "Arial" (font_size 9)(bold)))(border))
(section (rect 192 35 256 51)(text "REV" (rect 2 1 25 13)(font "Arial" ))(text "1.3" (rect 43 3 60 17)(font "Arial" (font_size 8)))(border))
(section (rect 0 35 256 51)(text "DATE" (rect 2 0 30 12)(font "Arial" ))(text "August 9, 2014, 2016" (rect 56 3 178 17)(font "Arial" (font_size 8)))(border))
(section (rect 192 35 256 51)(text "REV" (rect 2 1 25 13)(font "Arial" ))(text "1.4" (rect 43 3 60 17)(font "Arial" (font_size 8)))(border))
(drawing
)
)
/trunk/cpu/control/decode_state.bsf
75,53 → 75,60
(port
(pt 0 144)
(input)
(text "ctl_state_tbl_clr" (rect 0 0 89 14)(font "Arial" (font_size 8)))
(text "ctl_state_tbl_clr" (rect 21 139 110 153)(font "Arial" (font_size 8)))
(text "ctl_state_tbl_we" (rect 0 0 94 14)(font "Arial" (font_size 8)))
(text "ctl_state_tbl_we" (rect 21 139 115 153)(font "Arial" (font_size 8)))
(line (pt 0 144)(pt 16 144))
)
(port
(pt 0 160)
(input)
(text "ctl_state_tbl_ed_set" (rect 0 0 114 14)(font "Arial" (font_size 8)))
(text "ctl_state_tbl_ed_set" (rect 21 155 135 169)(font "Arial" (font_size 8)))
(text "hold_clk_wait" (rect 0 0 77 14)(font "Arial" (font_size 8)))
(text "hold_clk_wait" (rect 21 155 98 169)(font "Arial" (font_size 8)))
(line (pt 0 160)(pt 16 160))
)
(port
(pt 0 176)
(input)
(text "address_is_1" (rect 0 0 77 14)(font "Arial" (font_size 8)))
(text "address_is_1" (rect 21 171 98 185)(font "Arial" (font_size 8)))
(text "ctl_state_tbl_ed_set" (rect 0 0 114 14)(font "Arial" (font_size 8)))
(text "ctl_state_tbl_ed_set" (rect 21 171 135 185)(font "Arial" (font_size 8)))
(line (pt 0 176)(pt 16 176))
)
(port
(pt 0 192)
(input)
(text "clk" (rect 0 0 15 14)(font "Arial" (font_size 8)))
(text "clk" (rect 21 187 36 201)(font "Arial" (font_size 8)))
(text "address_is_1" (rect 0 0 77 14)(font "Arial" (font_size 8)))
(text "address_is_1" (rect 21 187 98 201)(font "Arial" (font_size 8)))
(line (pt 0 192)(pt 16 192))
)
(port
(pt 0 208)
(input)
(text "ctl_repeat_we" (rect 0 0 82 14)(font "Arial" (font_size 8)))
(text "ctl_repeat_we" (rect 21 203 103 217)(font "Arial" (font_size 8)))
(text "clk" (rect 0 0 15 14)(font "Arial" (font_size 8)))
(text "clk" (rect 21 203 36 217)(font "Arial" (font_size 8)))
(line (pt 0 208)(pt 16 208))
)
(port
(pt 0 224)
(input)
(text "nreset" (rect 0 0 36 14)(font "Arial" (font_size 8)))
(text "nreset" (rect 21 219 57 233)(font "Arial" (font_size 8)))
(text "ctl_repeat_we" (rect 0 0 82 14)(font "Arial" (font_size 8)))
(text "ctl_repeat_we" (rect 21 219 103 233)(font "Arial" (font_size 8)))
(line (pt 0 224)(pt 16 224))
)
(port
(pt 0 240)
(input)
(text "ctl_state_alu" (rect 0 0 71 14)(font "Arial" (font_size 8)))
(text "ctl_state_alu" (rect 21 235 92 249)(font "Arial" (font_size 8)))
(text "nreset" (rect 0 0 36 14)(font "Arial" (font_size 8)))
(text "nreset" (rect 21 235 57 249)(font "Arial" (font_size 8)))
(line (pt 0 240)(pt 16 240))
)
(port
(pt 0 256)
(input)
(text "ctl_state_alu" (rect 0 0 71 14)(font "Arial" (font_size 8)))
(text "ctl_state_alu" (rect 21 251 92 265)(font "Arial" (font_size 8)))
(line (pt 0 256)(pt 16 256))
)
(port
(pt 224 32)
(output)
(text "use_ix" (rect 0 0 37 14)(font "Arial" (font_size 8)))
/trunk/cpu/control/decode_state.v
14,7 → 14,7
 
// PROGRAM "Quartus II 64-Bit"
// VERSION "Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition"
// CREATED "Fri Oct 31 20:27:41 2014"
// CREATED "Wed Dec 07 00:18:12 2016"
 
module decode_state(
ctl_state_iy_set,
21,7 → 21,6
ctl_state_ixiy_clr,
ctl_state_ixiy_we,
ctl_state_halt_set,
ctl_state_tbl_clr,
ctl_state_tbl_ed_set,
ctl_state_tbl_cb_set,
ctl_state_alu,
31,6 → 30,8
in_intr,
in_nmi,
nreset,
ctl_state_tbl_we,
hold_clk_wait,
in_halt,
table_cb,
table_ed,
46,7 → 47,6
input wire ctl_state_ixiy_clr;
input wire ctl_state_ixiy_we;
input wire ctl_state_halt_set;
input wire ctl_state_tbl_clr;
input wire ctl_state_tbl_ed_set;
input wire ctl_state_tbl_cb_set;
input wire ctl_state_alu;
56,6 → 56,8
input wire in_intr;
input wire in_nmi;
input wire nreset;
input wire ctl_state_tbl_we;
input wire hold_clk_wait;
output reg in_halt;
output wire table_cb;
output wire table_ed;
71,8 → 73,9
reg DFFE_instED;
reg DFFE_instCB;
wire SYNTHESIZED_WIRE_0;
wire SYNTHESIZED_WIRE_1;
wire SYNTHESIZED_WIRE_5;
wire SYNTHESIZED_WIRE_4;
wire SYNTHESIZED_WIRE_3;
 
assign in_alu = ctl_state_alu;
assign table_cb = DFFE_instCB;
83,8 → 86,6
 
assign repeat_en = ~DFFE_instNonRep;
 
assign SYNTHESIZED_WIRE_4 = ctl_state_tbl_clr | ctl_state_tbl_ed_set | ctl_state_tbl_cb_set;
 
assign use_ixiy = DFFE_instIY1 | DFFE_inst4;
 
assign table_xx = ~(DFFE_instED | DFFE_instCB);
105,9 → 106,13
 
assign SYNTHESIZED_WIRE_0 = ~(ctl_state_iy_set | ctl_state_ixiy_clr);
 
assign SYNTHESIZED_WIRE_3 = in_nmi | in_intr;
assign SYNTHESIZED_WIRE_5 = ctl_state_tbl_we & SYNTHESIZED_WIRE_1;
 
assign SYNTHESIZED_WIRE_4 = in_nmi | in_intr;
 
assign SYNTHESIZED_WIRE_1 = ~hold_clk_wait;
 
 
always@(posedge clk or negedge nreset)
begin
if (!nreset)
115,7 → 120,7
DFFE_instCB <= 0;
end
else
if (SYNTHESIZED_WIRE_4)
if (SYNTHESIZED_WIRE_5)
begin
DFFE_instCB <= ctl_state_tbl_cb_set;
end
129,7 → 134,7
DFFE_instED <= 0;
end
else
if (SYNTHESIZED_WIRE_4)
if (SYNTHESIZED_WIRE_5)
begin
DFFE_instED <= ctl_state_tbl_ed_set;
end
144,7 → 149,7
end
else
begin
in_halt <= ~in_halt & ctl_state_halt_set | in_halt & ~SYNTHESIZED_WIRE_3;
in_halt <= ~in_halt & ctl_state_halt_set | in_halt & ~SYNTHESIZED_WIRE_4;
end
end
 
/trunk/cpu/control/exec_matrix.vh
3646,7 → 3646,7
ctl_flags_pf_we=1;
ctl_flags_nf_we=1; /* Previous NF, to be used when loading FLAGT */
ctl_flags_cf_we=1;
ctl_state_tbl_cb_set=1; setCBED=1; /* CB-table prefix */ end
ctl_state_tbl_we=1; ctl_state_tbl_cb_set=1; /* CB-table prefix */ end
if (M1 & T4) begin validPLA=1; nextM=1; ctl_mRead=1; end
if (M2 & T1) begin fMRead=1;
ctl_reg_sel_pc=1; ctl_reg_sys_hilo=2'b11; /* Select 16-bit PC */
3685,7 → 3685,7
 
if (pla[44]) begin
if (M1 & T2) begin
ctl_state_tbl_cb_set=1; setCBED=1; /* CB-table prefix */ end
ctl_state_tbl_we=1; ctl_state_tbl_cb_set=1; /* CB-table prefix */ end
if (M1 & T4) begin validPLA=1; setM1=1;
ctl_no_ints=1; /* Disable interrupt generation for this opcode (DI/EI/CB/ED/DD/FD) */ end
end
3692,7 → 3692,7
 
if (pla[51]) begin
if (M1 & T2) begin
ctl_state_tbl_ed_set=1; setCBED=1; /* ED-table prefix */ end
ctl_state_tbl_we=1; ctl_state_tbl_ed_set=1; /* ED-table prefix */ end
if (M1 & T4) begin validPLA=1; setM1=1;
ctl_no_ints=1; /* Disable interrupt generation for this opcode (DI/EI/CB/ED/DD/FD) */ end
end
3842,7 → 3842,7
ctl_alu_core_hf|=~ctl_alu_op_low;
ctl_flags_xy_we=1;
ctl_alu_sel_op2_neg=flags_sf;
ctl_state_ixiy_we=1; ctl_state_ixiy_clr=~setIXIY; /* Clear IX/IY flag */ end
ctl_state_ixiy_we=1; ctl_state_ixiy_clr=~setIXIY; /* Clear IX/IY flag if not explicitly set */ end
end
 
// Default instruction fetch (M1) state machine
3855,8 → 3855,8
ctl_reg_sel_ir=1; ctl_reg_sys_hilo=2'b11; /* Select 16-bit IR */
ctl_al_we=1; /* Write a value from the register bus to the address latch */
ctl_bus_db_oe=1; /* Read DB pads to internal data bus */
ctl_state_ixiy_we=1; ctl_state_ixiy_clr=~setIXIY; /* Clear IX/IY flag */
ctl_state_tbl_clr=~setCBED; /* Clear CB/ED prefix */
ctl_state_ixiy_we=1; ctl_state_ixiy_clr=~setIXIY; /* Clear IX/IY flag if not explicitly set */
ctl_state_tbl_we=1; /* Clear CB/ED prefix if not explicitly set */
ctl_ir_we=1;
ctl_bus_zero_oe=in_halt; ctl_bus_ff_oe=(in_intr & (im1 | im2)) | in_nmi; end
if (M1 & T3) begin
/trunk/cpu/control/exec_matrix_compiled.vh
5522,8 → 5522,8
ctl_flags_pf_we = ctl_flags_pf_we | (pla[49])&(M1&T3);
ctl_flags_nf_we = ctl_flags_nf_we | (pla[49])&(M1&T3);
ctl_flags_cf_we = ctl_flags_cf_we | (pla[49])&(M1&T3);
ctl_state_tbl_we = ctl_state_tbl_we | (pla[49])&(M1&T3);
ctl_state_tbl_cb_set = ctl_state_tbl_cb_set | (pla[49])&(M1&T3);
setCBED = setCBED | (pla[49])&(M1&T3);
validPLA = validPLA | (pla[49])&(M1&T4);
nextM = nextM | (pla[49])&(M1&T4);
ctl_mRead = ctl_mRead | (pla[49])&(M1&T4);
5575,13 → 5575,13
validPLA = validPLA | (pla[3])&(M1&T4);
setM1 = setM1 | (pla[3])&(M1&T4);
ctl_no_ints = ctl_no_ints | (pla[3])&(M1&T4);
ctl_state_tbl_we = ctl_state_tbl_we | (pla[44])&(M1&T2);
ctl_state_tbl_cb_set = ctl_state_tbl_cb_set | (pla[44])&(M1&T2);
setCBED = setCBED | (pla[44])&(M1&T2);
validPLA = validPLA | (pla[44])&(M1&T4);
setM1 = setM1 | (pla[44])&(M1&T4);
ctl_no_ints = ctl_no_ints | (pla[44])&(M1&T4);
ctl_state_tbl_we = ctl_state_tbl_we | (pla[51])&(M1&T2);
ctl_state_tbl_ed_set = ctl_state_tbl_ed_set | (pla[51])&(M1&T2);
setCBED = setCBED | (pla[51])&(M1&T2);
validPLA = validPLA | (pla[51])&(M1&T4);
setM1 = setM1 | (pla[51])&(M1&T4);
ctl_no_ints = ctl_no_ints | (pla[51])&(M1&T4);
5792,7 → 5792,7
ctl_bus_db_oe = ctl_bus_db_oe | (M1&T2);
ctl_state_ixiy_we = ctl_state_ixiy_we | (M1&T2);
ctl_state_ixiy_clr = ctl_state_ixiy_clr | (M1&T2)&(~setIXIY);
ctl_state_tbl_clr = ctl_state_tbl_clr | (M1&T2)&(~setCBED);
ctl_state_tbl_we = ctl_state_tbl_we | (M1&T2);
ctl_ir_we = ctl_ir_we | (M1&T2);
ctl_bus_zero_oe = ctl_bus_zero_oe | (M1&T2)&(in_halt);
ctl_bus_ff_oe = ctl_bus_ff_oe | (M1&T2)&((in_intr&(im1|im2))|in_nmi);
/trunk/cpu/control/exec_module.vh
5,11 → 5,11
output reg ctl_state_ixiy_clr,
output reg ctl_state_ixiy_we,
output reg ctl_state_halt_set,
output reg ctl_state_tbl_clr,
output reg ctl_state_tbl_ed_set,
output reg ctl_state_tbl_cb_set,
output reg ctl_state_alu,
output reg ctl_repeat_we,
output reg ctl_state_tbl_we,
 
// Module: control/interrupts.v
output reg ctl_iff1_iff2,
/trunk/cpu/control/exec_zero.vh
5,11 → 5,11
ctl_state_ixiy_clr = 0;
ctl_state_ixiy_we = 0;
ctl_state_halt_set = 0;
ctl_state_tbl_clr = 0;
ctl_state_tbl_ed_set = 0;
ctl_state_tbl_cb_set = 0;
ctl_state_alu = 0;
ctl_repeat_we = 0;
ctl_state_tbl_we = 0;
 
// Module: control/interrupts.v
ctl_iff1_iff2 = 0;
/trunk/cpu/control/execute.bsf
18,936 → 18,929
Altera or its authorized distributors. Please refer to the
applicable agreement for further details.
*/
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(line (pt 256 1152)(pt 240 1152))
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(text "ctl_reg_sel_pc" (rect 0 0 59 12)(font "Arial" ))
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(line (pt 256 1184)(pt 240 1184))
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(port
(pt 256 1200)
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(text "ctl_reg_sel_ir" (rect 0 0 54 12)(font "Arial" ))
(text "ctl_reg_sel_ir" (rect 181 1195 235 1207)(font "Arial" ))
(line (pt 256 1200)(pt 240 1200))
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(port
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(text "ctl_reg_sel_wz" (rect 0 0 59 12)(font "Arial" ))
(text "ctl_reg_sel_wz" (rect 176 1211 235 1223)(font "Arial" ))
(line (pt 256 1216)(pt 240 1216))
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(port
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(text "ctl_reg_not_pc" (rect 0 0 71 12)(font "Arial" ))
(text "ctl_reg_not_pc" (rect 0 0 60 12)(font "Arial" ))
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(line (pt 256 1248)(pt 240 1248))
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(text "ctl_reg_sys_we_lo" (rect 0 0 76 12)(font "Arial" ))
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(line (pt 256 1296)(pt 240 1296))
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(port
(pt 256 1312)
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(text "ctl_reg_gp_hilo[1..0]" (rect 0 0 99 12)(font "Arial" ))
(text "ctl_reg_gp_hilo[1..0]" (rect 152 1307 235 1319)(font "Arial" ))
(line (pt 256 1312)(pt 240 1312)(line_width 3))
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(text "ctl_sw_4d" (rect 194 1307 235 1319)(font "Arial" ))
(line (pt 256 1312)(pt 240 1312)(line_width 1))
)
(port
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(text "ctl_reg_gp_sel[1..0]" (rect 0 0 96 12)(font "Arial" ))
(text "ctl_reg_gp_sel[1..0]" (rect 154 1323 235 1335)(font "Arial" ))
(text "ctl_reg_gp_hilo[1..0]" (rect 0 0 79 12)(font "Arial" ))
(text "ctl_reg_gp_hilo[1..0]" (rect 156 1323 235 1335)(font "Arial" ))
(line (pt 256 1328)(pt 240 1328)(line_width 3))
)
(port
(pt 256 1344)
(output)
(text "ctl_reg_sys_hilo[1..0]" (rect 0 0 106 12)(font "Arial" ))
(text "ctl_reg_sys_hilo[1..0]" (rect 146 1339 235 1351)(font "Arial" ))
(text "ctl_reg_gp_sel[1..0]" (rect 0 0 77 12)(font "Arial" ))
(text "ctl_reg_gp_sel[1..0]" (rect 158 1339 235 1351)(font "Arial" ))
(line (pt 256 1344)(pt 240 1344)(line_width 3))
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(port
(pt 256 1360)
(output)
(text "ctl_inc_cy" (rect 0 0 50 12)(font "Arial" ))
(text "ctl_inc_cy" (rect 193 1355 235 1367)(font "Arial" ))
(line (pt 256 1360)(pt 240 1360))
(text "ctl_reg_sys_hilo[1..0]" (rect 0 0 84 12)(font "Arial" ))
(text "ctl_reg_sys_hilo[1..0]" (rect 151 1355 235 1367)(font "Arial" ))
(line (pt 256 1360)(pt 240 1360)(line_width 3))
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(port
(pt 256 1376)
(output)
(text "ctl_inc_dec" (rect 0 0 55 12)(font "Arial" ))
(text "ctl_inc_dec" (rect 189 1371 235 1383)(font "Arial" ))
(line (pt 256 1376)(pt 240 1376))
(text "ctl_inc_cy" (rect 0 0 41 12)(font "Arial" ))
(text "ctl_inc_cy" (rect 194 1371 235 1383)(font "Arial" ))
(line (pt 256 1376)(pt 240 1376)(line_width 1))
)
(port
(pt 256 1392)
(output)
(text "ctl_inc_zero" (rect 0 0 57 12)(font "Arial" ))
(text "ctl_inc_zero" (rect 187 1387 235 1399)(font "Arial" ))
(line (pt 256 1392)(pt 240 1392))
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(line (pt 256 1392)(pt 240 1392)(line_width 1))
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(port
(pt 256 1408)
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(text "ctl_al_we" (rect 0 0 44 12)(font "Arial" ))
(text "ctl_al_we" (rect 198 1403 235 1415)(font "Arial" ))
(line (pt 256 1408)(pt 240 1408))
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(text "ctl_al_we" (rect 199 1403 235 1415)(font "Arial" ))
(line (pt 256 1408)(pt 240 1408)(line_width 1))
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(port
(pt 256 1424)
(output)
(text "ctl_inc_limit6" (rect 0 0 63 12)(font "Arial" ))
(text "ctl_inc_limit6" (rect 182 1419 235 1431)(font "Arial" ))
(line (pt 256 1424)(pt 240 1424))
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(text "ctl_inc_limit6" (rect 186 1419 235 1431)(font "Arial" ))
(line (pt 256 1424)(pt 240 1424)(line_width 1))
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(port
(pt 256 1440)
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(text "ctl_bus_inc_oe" (rect 0 0 73 12)(font "Arial" ))
(text "ctl_bus_inc_oe" (rect 174 1435 235 1447)(font "Arial" ))
(line (pt 256 1440)(pt 240 1440))
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(text "ctl_bus_inc_oe" (rect 175 1435 235 1447)(font "Arial" ))
(line (pt 256 1440)(pt 240 1440)(line_width 1))
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(port
(pt 256 1456)
(output)
(text "ctl_apin_mux" (rect 0 0 64 12)(font "Arial" ))
(text "ctl_apin_mux" (rect 181 1451 235 1463)(font "Arial" ))
(line (pt 256 1456)(pt 240 1456))
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(text "ctl_apin_mux" (rect 182 1451 235 1463)(font "Arial" ))
(line (pt 256 1456)(pt 240 1456)(line_width 1))
)
(port
(pt 256 1472)
(output)
(text "ctl_apin_mux2" (rect 0 0 70 12)(font "Arial" ))
(text "ctl_apin_mux2" (rect 176 1467 235 1479)(font "Arial" ))
(line (pt 256 1472)(pt 240 1472))
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(text "ctl_apin_mux2" (rect 178 1467 235 1479)(font "Arial" ))
(line (pt 256 1472)(pt 240 1472)(line_width 1))
)
(port
(pt 256 1488)
(output)
(text "ctl_bus_ff_oe" (rect 0 0 68 12)(font "Arial" ))
(text "ctl_bus_ff_oe" (rect 178 1483 235 1495)(font "Arial" ))
(line (pt 256 1488)(pt 240 1488))
(text "ctl_bus_ff_oe" (rect 0 0 56 12)(font "Arial" ))
(text "ctl_bus_ff_oe" (rect 179 1483 235 1495)(font "Arial" ))
(line (pt 256 1488)(pt 240 1488)(line_width 1))
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(port
(pt 256 1504)
(output)
(text "ctl_bus_zero_oe" (rect 0 0 79 12)(font "Arial" ))
(text "ctl_bus_zero_oe" (rect 0 0 66 12)(font "Arial" ))
(text "ctl_bus_zero_oe" (rect 169 1499 235 1511)(font "Arial" ))
(line (pt 256 1504)(pt 240 1504))
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(port
(pt 256 1520)
(output)
(text "ctl_bus_db_oe" (rect 0 0 70 12)(font "Arial" ))
(text "ctl_bus_db_oe" (rect 176 1515 235 1527)(font "Arial" ))
(line (pt 256 1520)(pt 240 1520))
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(text "ctl_sw_1u" (rect 197 1515 235 1527)(font "Arial" ))
(line (pt 256 1520)(pt 240 1520)(line_width 1))
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(port
(pt 256 1536)
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(text "ctl_sw_1u" (rect 0 0 48 12)(font "Arial" ))
(text "ctl_sw_1u" (rect 195 1531 235 1543)(font "Arial" ))
(line (pt 256 1536)(pt 240 1536))
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(text "ctl_sw_1d" (rect 197 1531 235 1543)(font "Arial" ))
(line (pt 256 1536)(pt 240 1536)(line_width 1))
)
(port
(pt 256 1552)
(output)
(text "ctl_sw_1d" (rect 0 0 48 12)(font "Arial" ))
(text "ctl_sw_1d" (rect 195 1547 235 1559)(font "Arial" ))
(line (pt 256 1552)(pt 240 1552))
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(text "ctl_sw_2u" (rect 195 1547 235 1559)(font "Arial" ))
(line (pt 256 1552)(pt 240 1552)(line_width 1))
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(port
(pt 256 1568)
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(line (pt 256 1568)(pt 240 1568)(line_width 1))
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(text "ctl_sw_2d" (rect 195 1579 235 1591)(font "Arial" ))
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(line (pt 256 1616)(pt 240 1616)(line_width 1))
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(port
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(text "nextM" (rect 0 0 29 12)(font "Arial" ))
(text "nextM" (rect 0 0 24 12)(font "Arial" ))
(text "nextM" (rect 211 1627 235 1639)(font "Arial" ))
(line (pt 256 1632)(pt 240 1632))
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(line (pt 256 1648)(pt 240 1648))
(text "setM1" (rect 0 0 23 12)(font "Arial" ))
(text "setM1" (rect 212 1643 235 1655)(font "Arial" ))
(line (pt 256 1648)(pt 240 1648)(line_width 1))
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(port
(pt 256 1664)
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(text "fFetch" (rect 0 0 33 12)(font "Arial" ))
(text "fFetch" (rect 208 1659 235 1671)(font "Arial" ))
(line (pt 256 1664)(pt 240 1664))
(text "fFetch" (rect 0 0 25 12)(font "Arial" ))
(text "fFetch" (rect 210 1659 235 1671)(font "Arial" ))
(line (pt 256 1664)(pt 240 1664)(line_width 1))
)
(port
(pt 256 1680)
(output)
(text "fMRead" (rect 0 0 38 12)(font "Arial" ))
(text "fMRead" (rect 203 1675 235 1687)(font "Arial" ))
(line (pt 256 1680)(pt 240 1680))
(text "fMRead" (rect 0 0 34 12)(font "Arial" ))
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(line (pt 256 1680)(pt 240 1680)(line_width 1))
)
(port
(pt 256 1696)
(output)
(text "fMWrite" (rect 0 0 38 12)(font "Arial" ))
(text "fMWrite" (rect 203 1691 235 1703)(font "Arial" ))
(line (pt 256 1696)(pt 240 1696))
(text "fMWrite" (rect 0 0 34 12)(font "Arial" ))
(text "fMWrite" (rect 201 1691 235 1703)(font "Arial" ))
(line (pt 256 1696)(pt 240 1696)(line_width 1))
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(port
(pt 256 1712)
(output)
(text "fIORead" (rect 0 0 42 12)(font "Arial" ))
(text "fIORead" (rect 0 0 35 12)(font "Arial" ))
(text "fIORead" (rect 200 1707 235 1719)(font "Arial" ))
(line (pt 256 1712)(pt 240 1712))
(line (pt 256 1712)(pt 240 1712)(line_width 1))
)
(port
(pt 256 1728)
(output)
(text "fIOWrite" (rect 0 0 42 12)(font "Arial" ))
(text "fIOWrite" (rect 0 0 35 12)(font "Arial" ))
(text "fIOWrite" (rect 200 1723 235 1735)(font "Arial" ))
(line (pt 256 1728)(pt 240 1728))
(line (pt 256 1728)(pt 240 1728)(line_width 1))
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(drawing
(rectangle (rect 16 16 240 1760))
(rectangle (rect 16 16 240 1760)(line_width 1))
)
)
/trunk/cpu/control/execute.v
78,9 → 78,8
reg validPLA; // Valid PLA asserts this reg
// Activates a state machine to compute WZ=IX+d; takes 5T cycles
reg ixy_d; // Compute WX=IX+d
// Signals the setting of IX/IY and CB/ED prefix flags; inhibits clearing them
// Signals the setting of IX/IY prefix flags; inhibits clearing them
reg setIXIY; // Set IX/IY flag at the next T cycle
reg setCBED; // Set CB or ED flag at the next T cycle
// Holds asserted by non-repeating versions of block instructions (LDI/CPI,...)
reg nonRep; // Non-repeating block instruction
// Suspends incrementing PC through address latch unless in HALT or interrupt mode
139,7 → 138,6
fMRead = 0; fMWrite = 0; fIORead = 0; fIOWrite = 0;
ixy_d = 0;
setIXIY = 0;
setCBED = 0;
nonRep = 0;
pc_inc_hold = 0;
 
/trunk/cpu/control/gencompile.py
42,7 → 42,7
def is_ctl(name):
return name.startswith('ctl_') or name=='validPLA' or name=='nextM' or name=='setM1' \
or name=='fFetch' or name=='fMRead' or name=='fMWrite' or name=='fIORead' or name=='fIOWrite' \
or name=='ixy_d' or name=='setIXIY' or name=='setCBED' or name=='nonRep' or name=='pc_inc_hold'
or name=='ixy_d' or name=='setIXIY' or name=='nonRep' or name=='pc_inc_hold'
 
def str2tok(s):
t = io.BytesIO(bytes(s.encode()))
/trunk/cpu/control/ir.bdf
21,7 → 21,7
(header "graphic" (version "1.4"))
(pin
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(rect 40 80 216 96)
(rect 40 88 216 104)
(text "INPUT" (rect 133 0 161 10)(font "Arial" (font_size 6)))
(text "ctl_ir_we" (rect 9 0 51 12)(font "Arial" ))
(pt 176 8)
69,7 → 69,7
)
(pin
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(rect 40 120 216 136)
(rect 40 152 216 168)
(text "INPUT" (rect 133 0 161 10)(font "Arial" (font_size 6)))
(text "nreset" (rect 9 0 39 12)(font "Arial" ))
(pt 176 8)
84,6 → 84,22
(text "VCC" (rect 136 7 156 17)(font "Arial" (font_size 6)))
)
(pin
(input)
(rect 40 120 216 136)
(text "INPUT" (rect 133 0 161 10)(font "Arial" (font_size 6)))
(text "hold_clk_wait" (rect 9 0 73 12)(font "Arial" ))
(pt 176 8)
(drawing
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(pin
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(rect 504 48 680 64)
(text "OUTPUT" (rect 1 0 39 10)(font "Arial" (font_size 6)))
156,6 → 172,63
(circle (rect 28 68 36 76))
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(symbol
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(text "AND2" (rect 1 0 25 10)(font "Arial" (font_size 6)))
(text "inst5" (rect 3 37 26 49)(font "Arial" ))
(port
(pt 0 16)
(input)
(text "IN1" (rect 2 7 19 19)(font "Courier New" (bold))(invisible))
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(line (pt 0 16)(pt 14 16))
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(port
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(port
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(text "OUT" (rect 48 15 65 27)(font "Courier New" (bold))(invisible))
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(symbol
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(text "inst3" (rect 3 21 26 33)(font "Arial" ))
(port
(pt 0 16)
(input)
(text "IN" (rect 2 7 13 19)(font "Courier New" (bold))(invisible))
(text "IN" (rect 2 7 13 19)(font "Courier New" (bold))(invisible))
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(text "OUT" (rect 32 7 49 19)(font "Courier New" (bold))(invisible))
(text "OUT" (rect 32 7 49 19)(font "Courier New" (bold))(invisible))
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(drawing
(line (pt 13 25)(pt 13 7))
(line (pt 13 7)(pt 31 16))
(line (pt 13 25)(pt 31 16))
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(connector
(pt 216 56)
(pt 392 56)
171,26 → 244,54
(bus)
)
(connector
(pt 216 88)
(pt 392 88)
(pt 376 88)
)
(connector
(pt 216 128)
(pt 424 128)
(pt 424 160)
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)
(connector
(pt 424 128)
(pt 424 112)
(pt 424 160)
)
(text "8 latches implement the opcode Instruction Register" (rect 352 160 643 174)(font "Arial" (font_size 8)))
(connector
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(pt 232 128)
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(connector
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(connector
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(connector
(pt 296 112)
(pt 288 112)
)
(connector
(pt 288 112)
(pt 288 128)
)
(text "8 latches implement the opcode Instruction Register" (rect 328 216 619 230)(font "Arial" (font_size 8)))
(title_block
(rect 40 160 297 212)
(rect 40 216 297 268)
(name "title-custom-small")
(section (rect 0 35 256 51)(text "DATE" (rect 2 0 30 12)(font "Arial" ))(text "May 3, 2014, 2016" (rect 56 3 161 17)(font "Arial" (font_size 8)))(border))
(section (rect 0 18 256 34)(text "DESIGNER" (rect 2 0 59 12)(font "Arial" ))(text "Goran Devic" (rect 56 2 135 17)(font "Arial" (font_size 9)))(border))
(section (rect 104 0 256 17)(text "MODULE" (rect 2 1 48 13)(font "Arial" ))(text "ir" (rect 43 2 52 17)(font "Arial" (font_size 9)(bold)))(border))
(section (rect 0 0 256 17)(text "PROJECT" (rect 2 0 52 12)(font "Arial" ))(text "A-Z80" (rect 56 2 94 17)(font "Arial" (font_size 9)(bold)))(border))
(section (rect 192 35 256 51)(text "REV" (rect 2 1 25 13)(font "Arial" ))(text "1.3" (rect 43 3 60 17)(font "Arial" (font_size 8)))(border))
(section (rect 192 35 256 51)(text "REV" (rect 2 1 25 13)(font "Arial" ))(text "1.4" (rect 43 3 60 17)(font "Arial" (font_size 8)))(border))
(drawing
)
)
/trunk/cpu/control/ir.bsf
20,7 → 20,7
*/
(header "symbol" (version "1.2"))
(symbol
(rect 16 16 192 144)
(rect 16 16 216 144)
(text "ir" (rect 5 0 12 14)(font "Arial" (font_size 8)))
(text "inst" (rect 8 112 25 124)(font "Arial" ))
(port
47,18 → 47,25
(port
(pt 0 80)
(input)
(text "nreset" (rect 0 0 36 14)(font "Arial" (font_size 8)))
(text "nreset" (rect 21 75 57 89)(font "Arial" (font_size 8)))
(text "hold_clk_wait" (rect 0 0 77 14)(font "Arial" (font_size 8)))
(text "hold_clk_wait" (rect 21 75 98 89)(font "Arial" (font_size 8)))
(line (pt 0 80)(pt 16 80))
)
(port
(pt 176 32)
(pt 0 96)
(input)
(text "nreset" (rect 0 0 36 14)(font "Arial" (font_size 8)))
(text "nreset" (rect 21 91 57 105)(font "Arial" (font_size 8)))
(line (pt 0 96)(pt 16 96))
)
(port
(pt 200 32)
(output)
(text "opcode[7..0]" (rect 0 0 70 14)(font "Arial" (font_size 8)))
(text "opcode[7..0]" (rect 85 27 155 41)(font "Arial" (font_size 8)))
(line (pt 176 32)(pt 160 32)(line_width 3))
(text "opcode[7..0]" (rect 109 27 179 41)(font "Arial" (font_size 8)))
(line (pt 200 32)(pt 184 32)(line_width 3))
)
(drawing
(rectangle (rect 16 16 160 112))
(rectangle (rect 16 16 184 112))
)
)
/trunk/cpu/control/ir.v
20,6 → 20,7
ctl_ir_we,
clk,
nreset,
hold_clk_wait,
db,
opcode
);
28,14 → 29,21
input wire ctl_ir_we;
input wire clk;
input wire nreset;
input wire hold_clk_wait;
input wire [7:0] db;
output reg [7:0] opcode;
 
wire SYNTHESIZED_WIRE_0;
wire SYNTHESIZED_WIRE_1;
 
 
 
 
assign SYNTHESIZED_WIRE_0 = ~hold_clk_wait;
 
assign SYNTHESIZED_WIRE_1 = ctl_ir_we & SYNTHESIZED_WIRE_0;
 
 
always@(posedge clk or negedge nreset)
begin
if (!nreset)
43,7 → 51,7
opcode[7:0] <= 8'b00000000;
end
else
if (ctl_ir_we)
if (SYNTHESIZED_WIRE_1)
begin
opcode[7:0] <= db[7:0];
end
/trunk/cpu/control/memory_ifc.bdf
229,7 → 229,7
)
(pin
(output)
(rect 800 80 976 96)
(rect 800 184 976 200)
(text "OUTPUT" (rect 1 0 39 10)(font "Arial" (font_size 6)))
(text "nM1_out" (rect 90 0 131 12)(font "Arial" ))
(pt 0 8)
339,6 → 339,22
(line (pt 78 12)(pt 82 8))
)
)
(pin
(output)
(rect 800 472 976 488)
(text "OUTPUT" (rect 1 0 39 10)(font "Arial" (font_size 6)))
(text "wait_m1" (rect 90 0 130 12)(font "Arial" ))
(pt 0 8)
(drawing
(line (pt 0 8)(pt 52 8))
(line (pt 52 4)(pt 78 4))
(line (pt 52 12)(pt 78 12))
(line (pt 52 12)(pt 52 4))
(line (pt 78 4)(pt 82 8))
(line (pt 82 8)(pt 78 12))
(line (pt 78 12)(pt 82 8))
)
)
(symbol
(rect 640 112 688 144)
(text "NOT" (rect 1 0 21 10)(font "Arial" (font_size 6)))
2152,6 → 2168,64
(circle (rect 31 12 39 20))
)
)
(symbol
(rect 720 168 784 216)
(text "OR2" (rect 1 0 19 10)(font "Arial" (font_size 6)))
(text "inst41" (rect 3 37 32 49)(font "Arial" ))
(port
(pt 0 32)
(input)
(text "IN2" (rect 2 23 19 35)(font "Courier New" (bold))(invisible))
(text "IN2" (rect 2 23 19 35)(font "Courier New" (bold))(invisible))
(line (pt 0 32)(pt 15 32))
)
(port
(pt 0 16)
(input)
(text "IN1" (rect 2 7 19 19)(font "Courier New" (bold))(invisible))
(text "IN1" (rect 2 7 19 19)(font "Courier New" (bold))(invisible))
(line (pt 0 16)(pt 15 16))
)
(port
(pt 64 24)
(output)
(text "OUT" (rect 48 15 65 27)(font "Courier New" (bold))(invisible))
(text "OUT" (rect 48 15 62 27)(font "Courier New" (bold))(invisible))
(line (pt 48 24)(pt 64 24))
)
(drawing
(line (pt 14 36)(pt 25 36))
(line (pt 14 13)(pt 25 13))
(arc (pt 7 29)(pt 7 19)(rect -14 8 19 41))
(arc (pt 49 24)(pt 25 13)(rect -6 13 57 76))
(arc (pt 25 35)(pt 49 24)(rect -6 -27 57 36))
)
)
(symbol
(rect 640 184 688 216)
(text "NOT" (rect 1 0 21 10)(font "Arial" (font_size 6)))
(text "notff1" (rect 3 21 33 33)(font "Arial" ))
(port
(pt 0 16)
(input)
(text "IN" (rect 2 7 13 19)(font "Courier New" (bold))(invisible))
(text "IN" (rect 2 7 13 19)(font "Courier New" (bold))(invisible))
(line (pt 0 16)(pt 13 16))
)
(port
(pt 48 16)
(output)
(text "OUT" (rect 32 7 49 19)(font "Courier New" (bold))(invisible))
(text "OUT" (rect 32 7 46 19)(font "Courier New" (bold))(invisible))
(line (pt 39 16)(pt 48 16))
)
(drawing
(line (pt 13 25)(pt 13 7))
(line (pt 13 7)(pt 31 16))
(line (pt 13 25)(pt 31 16))
(circle (rect 31 12 39 20))
)
)
(connector
(pt 704 112)
(pt 720 112)
2161,10 → 2235,6
(pt 320 128)
)
(connector
(pt 704 88)
(pt 704 112)
)
(connector
(pt 416 304)
(pt 416 264)
)
2214,10 → 2284,6
(pt 704 88)
)
(connector
(pt 704 88)
(pt 800 88)
)
(connector
(pt 400 88)
(pt 400 128)
)
2243,7 → 2309,7
(pt 448 304)
)
(connector
(text "nq2" (rect 698 112 715 124)(font "Arial" ))
(text "nq2" (rect 690 96 707 108)(font "Arial" ))
(pt 688 128)
(pt 720 128)
)
2286,10 → 2352,6
(pt 528 304)
)
(connector
(pt 592 184)
(pt 592 232)
)
(connector
(pt 480 184)
(pt 480 232)
)
2583,15 → 2645,6
(pt 544 520)
)
(connector
(pt 512 480)
(pt 624 480)
)
(connector
(text "wait_m1" (rect 824 464 864 476)(font "Arial" ))
(pt 624 480)
(pt 864 480)
)
(connector
(pt 496 720)
(pt 512 720)
)
3472,13 → 3525,53
(pt 688 1808)
)
(connector
(pt 784 192)
(pt 800 192)
)
(connector
(pt 720 184)
(pt 704 184)
)
(connector
(pt 704 88)
(pt 704 112)
)
(connector
(pt 704 112)
(pt 704 184)
)
(connector
(pt 592 200)
(pt 640 200)
)
(connector
(pt 592 184)
(pt 592 200)
)
(connector
(pt 592 200)
(pt 592 232)
)
(connector
(pt 688 200)
(pt 720 200)
)
(connector
(pt 512 480)
(pt 624 480)
)
(connector
(text "wait_m1" (rect 752 464 792 476)(font "Arial" ))
(pt 624 480)
(pt 800 480)
)
(connector
(text "wait_m1" (rect 377 1840 417 1852)(font "Arial" ))
(pt 376 1856)
(pt 688 1856)
(pt 376 1856)
)
(junction (pt 248 144))
(junction (pt 272 320))
(junction (pt 704 88))
(junction (pt 416 304))
(junction (pt 400 128))
(junction (pt 352 408))
3539,6 → 3632,8
(junction (pt 576 1232))
(junction (pt 328 1536))
(junction (pt 624 880))
(junction (pt 704 112))
(junction (pt 592 200))
(text "MREQ DURING REFRESH" (rect 640 248 780 262)(font "Arial" (font_size 8)))
(text "STANDARD MEM REQ" (rect 712 408 837 422)(font "Arial" (font_size 8)))
(text "Refresh generator logic, USPTO 4,332,008 by Shima et al. FIG. 9A" (rect 40 32 506 48)(font "Arial" (font_size 10))(border))
3556,7 → 3651,7
(section (rect 104 0 256 17)(text "MODULE" (rect 2 1 48 13)(font "Arial" ))(text "memory_ifc" (rect 43 2 123 17)(font "Arial" (font_size 9)(bold)))(border))
(section (rect 0 18 256 34)(text "DESIGNER" (rect 2 0 59 12)(font "Arial" ))(text "Goran Devic" (rect 56 2 135 17)(font "Arial" (font_size 9)))(border))
(section (rect 0 35 256 51)(text "DATE" (rect 2 0 30 12)(font "Arial" ))(text "November 1, 2014" (rect 56 3 159 17)(font "Arial" (font_size 8)))(border))
(section (rect 192 35 256 51)(text "REV" (rect 2 1 25 13)(font "Arial" ))(text "1.0" (rect 43 3 60 17)(font "Arial" (font_size 8)))(border))
(section (rect 192 35 256 51)(text "REV" (rect 2 1 25 13)(font "Arial" ))(text "1.1" (rect 43 3 60 17)(font "Arial" (font_size 8)))(border))
(drawing
)
)
/trunk/cpu/control/memory_ifc.bsf
117,15 → 117,15
(port
(pt 200 32)
(output)
(text "nM1_out" (rect 0 0 48 14)(font "Arial" (font_size 8)))
(text "nM1_out" (rect 131 27 179 41)(font "Arial" (font_size 8)))
(text "nRFSH_out" (rect 0 0 63 14)(font "Arial" (font_size 8)))
(text "nRFSH_out" (rect 116 27 179 41)(font "Arial" (font_size 8)))
(line (pt 200 32)(pt 184 32))
)
(port
(pt 200 48)
(output)
(text "nRFSH_out" (rect 0 0 63 14)(font "Arial" (font_size 8)))
(text "nRFSH_out" (rect 116 43 179 57)(font "Arial" (font_size 8)))
(text "nM1_out" (rect 0 0 48 14)(font "Arial" (font_size 8)))
(text "nM1_out" (rect 131 43 179 57)(font "Arial" (font_size 8)))
(line (pt 200 48)(pt 184 48))
)
(port
138,31 → 138,38
(port
(pt 200 80)
(output)
(text "nRD_out" (rect 0 0 48 14)(font "Arial" (font_size 8)))
(text "nRD_out" (rect 131 75 179 89)(font "Arial" (font_size 8)))
(text "wait_m1" (rect 0 0 48 14)(font "Arial" (font_size 8)))
(text "wait_m1" (rect 131 75 179 89)(font "Arial" (font_size 8)))
(line (pt 200 80)(pt 184 80))
)
(port
(pt 200 96)
(output)
(text "nWR_out" (rect 0 0 51 14)(font "Arial" (font_size 8)))
(text "nWR_out" (rect 128 91 179 105)(font "Arial" (font_size 8)))
(text "nRD_out" (rect 0 0 48 14)(font "Arial" (font_size 8)))
(text "nRD_out" (rect 131 91 179 105)(font "Arial" (font_size 8)))
(line (pt 200 96)(pt 184 96))
)
(port
(pt 200 112)
(output)
(text "nIORQ_out" (rect 0 0 61 14)(font "Arial" (font_size 8)))
(text "nIORQ_out" (rect 118 107 179 121)(font "Arial" (font_size 8)))
(text "nWR_out" (rect 0 0 51 14)(font "Arial" (font_size 8)))
(text "nWR_out" (rect 128 107 179 121)(font "Arial" (font_size 8)))
(line (pt 200 112)(pt 184 112))
)
(port
(pt 200 128)
(output)
(text "latch_wait" (rect 0 0 59 14)(font "Arial" (font_size 8)))
(text "latch_wait" (rect 120 123 179 137)(font "Arial" (font_size 8)))
(text "nIORQ_out" (rect 0 0 61 14)(font "Arial" (font_size 8)))
(text "nIORQ_out" (rect 118 123 179 137)(font "Arial" (font_size 8)))
(line (pt 200 128)(pt 184 128))
)
(port
(pt 200 144)
(output)
(text "latch_wait" (rect 0 0 59 14)(font "Arial" (font_size 8)))
(text "latch_wait" (rect 120 139 179 153)(font "Arial" (font_size 8)))
(line (pt 200 144)(pt 184 144))
)
(drawing
(rectangle (rect 16 16 184 240))
)
/trunk/cpu/control/memory_ifc.v
14,7 → 14,7
 
// PROGRAM "Quartus II 64-Bit"
// VERSION "Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition"
// CREATED "Sun Nov 16 21:11:14 2014"
// CREATED "Sun Dec 04 01:04:33 2016"
 
module memory_ifc(
clk,
36,7 → 36,8
nRD_out,
nWR_out,
nIORQ_out,
latch_wait
latch_wait,
wait_m1
);
 
 
60,6 → 61,7
output wire nWR_out;
output wire nIORQ_out;
output wire latch_wait;
output wire wait_m1;
 
wire intr_iorq;
wire ioRead;
74,22 → 76,23
reg q1;
reg q2;
reg wait_iorq;
reg wait_m1;
reg wait_m_ALTERA_SYNTHESIZED1;
reg wait_mrd;
reg wait_mwr;
wire SYNTHESIZED_WIRE_0;
reg DFFE_m1_ff3;
wire SYNTHESIZED_WIRE_1;
reg SYNTHESIZED_WIRE_15;
reg SYNTHESIZED_WIRE_16;
reg DFFE_iorq_ff4;
reg SYNTHESIZED_WIRE_16;
reg SYNTHESIZED_WIRE_17;
reg DFFE_mrd_ff3;
reg DFFE_intr_ff3;
wire SYNTHESIZED_WIRE_2;
reg SYNTHESIZED_WIRE_17;
reg SYNTHESIZED_WIRE_18;
wire SYNTHESIZED_WIRE_19;
wire SYNTHESIZED_WIRE_4;
wire SYNTHESIZED_WIRE_3;
reg SYNTHESIZED_WIRE_19;
wire SYNTHESIZED_WIRE_20;
wire SYNTHESIZED_WIRE_5;
reg DFFE_iorq_ff1;
reg DFFE_m1_ff1;
reg DFFE_mrd_ff1;
96,7 → 99,6
reg DFFE_mwr_ff1;
reg DFFE_mreq_ff2;
 
assign nM1_out = SYNTHESIZED_WIRE_18;
 
 
 
104,15 → 106,15
 
assign ioRead = iorq & fIORead;
 
assign SYNTHESIZED_WIRE_1 = ~(DFFE_m1_ff3 | wait_m1);
assign SYNTHESIZED_WIRE_1 = ~(DFFE_m1_ff3 | wait_m_ALTERA_SYNTHESIZED1);
 
assign m1_mreq = ~(in_intr | SYNTHESIZED_WIRE_1);
 
assign iorq = SYNTHESIZED_WIRE_15 | DFFE_iorq_ff4 | SYNTHESIZED_WIRE_16;
assign iorq = SYNTHESIZED_WIRE_16 | DFFE_iorq_ff4 | SYNTHESIZED_WIRE_17;
 
assign ioWrite = iorq & fIOWrite;
 
assign latch_wait = wait_mrd | wait_iorq | wait_m1 | wait_mwr;
assign latch_wait = wait_mrd | wait_iorq | wait_m_ALTERA_SYNTHESIZED1 | wait_mwr;
 
assign nMEMRQ_int = ~(m1_mreq | mrd_mreq | mwr_mreq);
 
126,16 → 128,18
 
assign nIORQ_out = ~(intr_iorq | iorq);
 
assign SYNTHESIZED_WIRE_4 = ~hold_clk_wait;
assign SYNTHESIZED_WIRE_5 = ~hold_clk_wait;
 
assign intr_iorq = DFFE_intr_ff3 | wait_iorq;
 
assign SYNTHESIZED_WIRE_0 = ~(SYNTHESIZED_WIRE_2 & SYNTHESIZED_WIRE_17);
assign nM1_out = SYNTHESIZED_WIRE_2 | SYNTHESIZED_WIRE_18;
 
assign SYNTHESIZED_WIRE_0 = ~(SYNTHESIZED_WIRE_3 & SYNTHESIZED_WIRE_19);
 
assign nRFSH_out = ~(nq2 & SYNTHESIZED_WIRE_18);
 
 
always@(posedge SYNTHESIZED_WIRE_19 or negedge nreset)
always@(posedge SYNTHESIZED_WIRE_20 or negedge nreset)
begin
if (!nreset)
begin
155,7 → 159,7
DFFE_intr_ff3 <= 0;
end
else
if (SYNTHESIZED_WIRE_4)
if (SYNTHESIZED_WIRE_5)
begin
DFFE_intr_ff3 <= wait_iorq;
end
180,31 → 184,31
begin
if (!nreset)
begin
SYNTHESIZED_WIRE_16 <= 0;
SYNTHESIZED_WIRE_17 <= 0;
end
else
if (timings_en)
begin
SYNTHESIZED_WIRE_16 <= DFFE_iorq_ff1;
SYNTHESIZED_WIRE_17 <= DFFE_iorq_ff1;
end
end
 
 
always@(posedge SYNTHESIZED_WIRE_19 or negedge nreset)
always@(posedge SYNTHESIZED_WIRE_20 or negedge nreset)
begin
if (!nreset)
begin
SYNTHESIZED_WIRE_15 <= 0;
SYNTHESIZED_WIRE_16 <= 0;
end
else
if (timings_en)
begin
SYNTHESIZED_WIRE_15 <= SYNTHESIZED_WIRE_16;
SYNTHESIZED_WIRE_16 <= SYNTHESIZED_WIRE_17;
end
end
 
 
always@(posedge SYNTHESIZED_WIRE_19 or negedge nreset)
always@(posedge SYNTHESIZED_WIRE_20 or negedge nreset)
begin
if (!nreset)
begin
213,7 → 217,7
else
if (timings_en)
begin
DFFE_iorq_ff4 <= SYNTHESIZED_WIRE_15;
DFFE_iorq_ff4 <= SYNTHESIZED_WIRE_16;
end
end
 
232,7 → 236,7
end
 
 
always@(posedge SYNTHESIZED_WIRE_19 or negedge nreset)
always@(posedge SYNTHESIZED_WIRE_20 or negedge nreset)
begin
if (!nreset)
begin
246,16 → 250,16
end
 
 
always@(posedge SYNTHESIZED_WIRE_19 or negedge nreset)
always@(posedge SYNTHESIZED_WIRE_20 or negedge nreset)
begin
if (!nreset)
begin
wait_m1 <= 0;
wait_m_ALTERA_SYNTHESIZED1 <= 0;
end
else
if (timings_en)
begin
wait_m1 <= DFFE_m1_ff1;
wait_m_ALTERA_SYNTHESIZED1 <= DFFE_m1_ff1;
end
end
 
269,7 → 273,7
else
if (timings_en)
begin
DFFE_m1_ff3 <= wait_m1;
DFFE_m1_ff3 <= wait_m_ALTERA_SYNTHESIZED1;
end
end
 
288,7 → 292,7
end
 
 
always@(posedge SYNTHESIZED_WIRE_19 or negedge nreset)
always@(posedge SYNTHESIZED_WIRE_20 or negedge nreset)
begin
if (!nreset)
begin
302,7 → 306,7
end
 
 
always@(posedge SYNTHESIZED_WIRE_19 or negedge nreset)
always@(posedge SYNTHESIZED_WIRE_20 or negedge nreset)
begin
if (!nreset)
begin
316,21 → 320,21
end
 
 
always@(posedge SYNTHESIZED_WIRE_19 or negedge nreset)
always@(posedge SYNTHESIZED_WIRE_20 or negedge nreset)
begin
if (!nreset)
begin
SYNTHESIZED_WIRE_17 <= 0;
SYNTHESIZED_WIRE_19 <= 0;
end
else
if (timings_en)
begin
SYNTHESIZED_WIRE_17 <= SYNTHESIZED_WIRE_18;
SYNTHESIZED_WIRE_19 <= SYNTHESIZED_WIRE_18;
end
end
 
 
always@(posedge SYNTHESIZED_WIRE_19 or negedge nreset)
always@(posedge SYNTHESIZED_WIRE_20 or negedge nreset)
begin
if (!nreset)
begin
339,7 → 343,7
else
if (timings_en)
begin
DFFE_mreq_ff2 <= SYNTHESIZED_WIRE_17;
DFFE_mreq_ff2 <= SYNTHESIZED_WIRE_19;
end
end
 
358,7 → 362,7
end
 
 
always@(posedge SYNTHESIZED_WIRE_19 or negedge nreset)
always@(posedge SYNTHESIZED_WIRE_20 or negedge nreset)
begin
if (!nreset)
begin
372,7 → 376,7
end
 
 
always@(posedge SYNTHESIZED_WIRE_19 or negedge nreset)
always@(posedge SYNTHESIZED_WIRE_20 or negedge nreset)
begin
if (!nreset)
begin
385,13 → 389,15
end
end
 
assign SYNTHESIZED_WIRE_19 = ~clk;
assign SYNTHESIZED_WIRE_20 = ~clk;
 
assign nq2 = ~q2;
 
assign SYNTHESIZED_WIRE_2 = ~DFFE_mreq_ff2;
assign SYNTHESIZED_WIRE_2 = ~nreset;
 
assign SYNTHESIZED_WIRE_3 = ~DFFE_mreq_ff2;
 
 
always@(posedge clk or negedge nreset)
begin
if (!nreset)
419,5 → 425,6
end
end
 
assign wait_m1 = wait_m_ALTERA_SYNTHESIZED1;
 
endmodule
/trunk/cpu/control/resets.bdf
100,6 → 100,22
(text "VCC" (rect 136 7 156 17)(font "Arial" (font_size 6)))
)
(pin
(input)
(rect 32 640 208 656)
(text "INPUT" (rect 133 0 161 10)(font "Arial" (font_size 6)))
(text "hold_clk_wait" (rect 9 0 73 12)(font "Arial" ))
(pt 176 8)
(drawing
(line (pt 92 12)(pt 117 12))
(line (pt 92 4)(pt 117 4))
(line (pt 121 8)(pt 176 8))
(line (pt 92 12)(pt 92 4))
(line (pt 117 4)(pt 121 8))
(line (pt 117 12)(pt 121 8))
)
(text "VCC" (rect 136 7 156 17)(font "Arial" (font_size 6)))
)
(pin
(output)
(rect 776 488 952 504)
(text "OUTPUT" (rect 1 0 39 10)(font "Arial" (font_size 6)))
146,7 → 162,7
(pt 48 16)
(output)
(text "OUT" (rect 32 7 49 19)(font "Courier New" (bold))(invisible))
(text "OUT" (rect 32 7 49 19)(font "Courier New" (bold))(invisible))
(text "OUT" (rect 32 7 46 19)(font "Courier New" (bold))(invisible))
(line (pt 39 16)(pt 48 16))
)
(drawing
178,7 → 194,7
(pt 64 24)
(output)
(text "OUT" (rect 48 15 65 27)(font "Courier New" (bold))(invisible))
(text "OUT" (rect 48 15 65 27)(font "Courier New" (bold))(invisible))
(text "OUT" (rect 48 15 62 27)(font "Courier New" (bold))(invisible))
(line (pt 42 24)(pt 64 24))
)
(drawing
210,7 → 226,7
(pt 64 24)
(output)
(text "OUT" (rect 48 15 65 27)(font "Courier New" (bold))(invisible))
(text "OUT" (rect 48 15 65 27)(font "Courier New" (bold))(invisible))
(text "OUT" (rect 48 15 62 27)(font "Courier New" (bold))(invisible))
(line (pt 42 24)(pt 64 24))
)
(drawing
235,7 → 251,7
(pt 48 16)
(output)
(text "OUT" (rect 32 7 49 19)(font "Courier New" (bold))(invisible))
(text "OUT" (rect 32 7 49 19)(font "Courier New" (bold))(invisible))
(text "OUT" (rect 32 7 46 19)(font "Courier New" (bold))(invisible))
(line (pt 39 16)(pt 48 16))
)
(drawing
267,7 → 283,7
(pt 64 24)
(output)
(text "OUT" (rect 48 15 65 27)(font "Courier New" (bold))(invisible))
(text "OUT" (rect 48 15 65 27)(font "Courier New" (bold))(invisible))
(text "OUT" (rect 48 15 62 27)(font "Courier New" (bold))(invisible))
(line (pt 42 24)(pt 64 24))
)
(drawing
320,7 → 336,7
(pt 64 24)
(output)
(text "Q" (rect 45 20 50 32)(font "Courier New" (bold)))
(text "Q" (rect 43 20 48 32)(font "Courier New" (bold)))
(text "Q" (rect 43 20 47 32)(font "Courier New" (bold)))
(line (pt 52 24)(pt 64 24))
)
(drawing
349,7 → 365,7
(pt 48 16)
(output)
(text "OUT" (rect 32 7 49 19)(font "Courier New" (bold))(invisible))
(text "OUT" (rect 32 7 49 19)(font "Courier New" (bold))(invisible))
(text "OUT" (rect 32 7 46 19)(font "Courier New" (bold))(invisible))
(line (pt 39 16)(pt 48 16))
)
(drawing
402,7 → 418,7
(pt 64 24)
(output)
(text "Q" (rect 45 20 50 32)(font "Courier New" (bold)))
(text "Q" (rect 43 20 48 32)(font "Courier New" (bold)))
(text "Q" (rect 43 20 47 32)(font "Courier New" (bold)))
(line (pt 52 24)(pt 64 24))
)
(drawing
432,7 → 448,7
(pt 48 16)
(output)
(text "OUT" (rect 32 7 49 19)(font "Courier New" (bold))(invisible))
(text "OUT" (rect 32 7 49 19)(font "Courier New" (bold))(invisible))
(text "OUT" (rect 32 7 46 19)(font "Courier New" (bold))(invisible))
(line (pt 39 16)(pt 48 16))
)
(drawing
478,7 → 494,7
(pt 64 24)
(output)
(text "Q" (rect 45 20 50 32)(font "Courier New" (bold)))
(text "Q" (rect 43 20 48 32)(font "Courier New" (bold)))
(text "Q" (rect 43 20 47 32)(font "Courier New" (bold)))
(line (pt 52 24)(pt 64 24))
)
(drawing
507,7 → 523,7
(pt 16 0)
(output)
(text "OUT" (rect 32 7 49 19)(font "Courier New" (bold))(invisible))
(text "OUT" (rect 7 2 19 19)(font "Courier New" (bold))(vertical)(invisible))
(text "OUT" (rect 7 2 19 16)(font "Courier New" (bold))(vertical)(invisible))
(line (pt 16 9)(pt 16 0))
)
(drawing
519,60 → 535,66
(rotate90)
)
(symbol
(rect 296 520 360 600)
(text "DFF" (rect 1 0 19 10)(font "Arial" (font_size 6)))
(text "res1" (rect 3 68 24 80)(font "Arial" ))
(rect 680 456 744 536)
(text "OR4" (rect 1 0 19 10)(font "Arial" (font_size 6)))
(text "inst" (rect 3 69 20 81)(font "Arial" ))
(port
(pt 32 80)
(pt 0 16)
(input)
(text "CLRN" (rect 21 59 44 71)(font "Courier New" (bold)))
(text "CLRN" (rect 21 58 44 70)(font "Courier New" (bold)))
(line (pt 32 80)(pt 32 76))
(text "IN1" (rect 2 7 19 19)(font "Courier New" (bold))(invisible))
(text "IN1" (rect 2 7 19 19)(font "Courier New" (bold))(invisible))
(line (pt 0 16)(pt 13 16))
)
(port
(pt 0 40)
(pt 0 48)
(input)
(text "CLK" (rect 3 29 20 41)(font "Courier New" (bold))(invisible))
(text "CLK" (rect 3 29 20 41)(font "Courier New" (bold))(invisible))
(line (pt 0 40)(pt 12 40))
(text "IN3" (rect 2 39 19 51)(font "Courier New" (bold))(invisible))
(text "IN3" (rect 2 39 19 51)(font "Courier New" (bold))(invisible))
(line (pt 0 48)(pt 15 48))
)
(port
(pt 0 24)
(pt 0 64)
(input)
(text "D" (rect 14 20 19 32)(font "Courier New" (bold)))
(text "D" (rect 14 20 19 32)(font "Courier New" (bold)))
(line (pt 0 24)(pt 12 24))
(text "IN4" (rect 2 55 19 67)(font "Courier New" (bold))(invisible))
(text "IN4" (rect 2 55 19 67)(font "Courier New" (bold))(invisible))
(line (pt 0 64)(pt 13 64))
)
(port
(pt 32 0)
(pt 0 32)
(input)
(text "PRN" (rect 24 13 41 25)(font "Courier New" (bold)))
(text "PRN" (rect 24 11 41 23)(font "Courier New" (bold)))
(line (pt 32 4)(pt 32 0))
(text "IN2" (rect 2 23 19 35)(font "Courier New" (bold))(invisible))
(text "IN2" (rect 2 23 19 35)(font "Courier New" (bold))(invisible))
(line (pt 0 32)(pt 15 32))
)
(port
(pt 64 24)
(pt 64 40)
(output)
(text "Q" (rect 45 20 50 32)(font "Courier New" (bold)))
(text "Q" (rect 43 20 48 32)(font "Courier New" (bold)))
(line (pt 52 24)(pt 64 24))
(text "OUT" (rect 48 31 65 43)(font "Courier New" (bold))(invisible))
(text "OUT" (rect 48 31 62 43)(font "Courier New" (bold))(invisible))
(line (pt 48 40)(pt 64 40))
)
(drawing
(line (pt 12 12)(pt 52 12))
(line (pt 12 68)(pt 52 68))
(line (pt 52 68)(pt 52 12))
(line (pt 12 68)(pt 12 12))
(line (pt 19 40)(pt 12 47))
(line (pt 12 32)(pt 20 40))
(circle (rect 28 4 36 12))
(circle (rect 28 68 36 76))
(line (pt 13 67)(pt 13 51))
(line (pt 25 52)(pt 13 52))
(line (pt 13 12)(pt 13 29))
(line (pt 13 29)(pt 25 29))
(arc (pt 7 45)(pt 7 35)(rect -14 24 19 57))
(arc (pt 49 40)(pt 25 29)(rect -6 29 57 92))
(arc (pt 25 51)(pt 49 40)(rect -6 -11 57 52))
)
)
(symbol
(rect 408 520 472 600)
(text "DFF" (rect 1 0 19 10)(font "Arial" (font_size 6)))
(text "res2" (rect 3 68 24 80)(font "Arial" ))
(rect 520 520 584 600)
(text "DFFE" (rect 1 0 25 10)(font "Arial" (font_size 6)))
(text "intr_ff3" (rect 3 68 39 80)(font "Arial" ))
(port
(pt 32 0)
(input)
(text "PRN" (rect 24 13 41 25)(font "Courier New" (bold)))
(text "PRN" (rect 24 11 41 23)(font "Courier New" (bold)))
(line (pt 32 4)(pt 32 0))
)
(port
(pt 32 80)
(input)
(text "CLRN" (rect 21 59 44 71)(font "Courier New" (bold)))
580,13 → 602,6
(line (pt 32 80)(pt 32 76))
)
(port
(pt 0 40)
(input)
(text "CLK" (rect 3 29 20 41)(font "Courier New" (bold))(invisible))
(text "CLK" (rect 3 29 20 41)(font "Courier New" (bold))(invisible))
(line (pt 0 40)(pt 12 40))
)
(port
(pt 0 24)
(input)
(text "D" (rect 14 20 19 32)(font "Courier New" (bold)))
594,35 → 609,74
(line (pt 0 24)(pt 12 24))
)
(port
(pt 32 0)
(pt 0 40)
(input)
(text "PRN" (rect 24 13 41 25)(font "Courier New" (bold)))
(text "PRN" (rect 24 11 41 23)(font "Courier New" (bold)))
(line (pt 32 4)(pt 32 0))
(text "CLK" (rect 2 28 19 40)(font "Courier New" (bold))(invisible))
(text "CLK" (rect 2 28 19 40)(font "Courier New" (bold))(invisible))
(line (pt 0 40)(pt 12 40))
)
(port
(pt 0 56)
(input)
(text "ENA" (rect 14 50 31 62)(font "Courier New" (bold)))
(text "ENA" (rect 14 50 31 62)(font "Courier New" (bold)))
(line (pt 0 56)(pt 12 56))
)
(port
(pt 64 24)
(output)
(text "Q" (rect 45 20 50 32)(font "Courier New" (bold)))
(text "Q" (rect 43 20 48 32)(font "Courier New" (bold)))
(line (pt 52 24)(pt 64 24))
(text "Q" (rect 44 20 49 32)(font "Courier New" (bold)))
(text "Q" (rect 44 20 48 32)(font "Courier New" (bold)))
(line (pt 53 24)(pt 64 24))
)
(drawing
(line (pt 12 68)(pt 52 68))
(line (pt 12 12)(pt 52 12))
(line (pt 12 68)(pt 52 68))
(line (pt 52 68)(pt 52 12))
(line (pt 12 68)(pt 12 12))
(line (pt 19 40)(pt 12 47))
(line (pt 12 32)(pt 20 40))
(line (pt 12 34)(pt 19 41))
(line (pt 18 41)(pt 12 47))
(circle (rect 28 4 36 12))
(circle (rect 28 68 36 76))
)
)
(symbol
(rect 520 520 584 600)
(text "DFF" (rect 1 0 19 10)(font "Arial" (font_size 6)))
(text "res3" (rect 3 68 24 80)(font "Arial" ))
(rect 216 632 264 664)
(text "NOT" (rect 1 0 21 10)(font "Arial" (font_size 6)))
(text "inst4" (rect 3 21 26 33)(font "Arial" ))
(port
(pt 0 16)
(input)
(text "IN" (rect 2 7 13 19)(font "Courier New" (bold))(invisible))
(text "IN" (rect 2 7 13 19)(font "Courier New" (bold))(invisible))
(line (pt 0 16)(pt 13 16))
)
(port
(pt 48 16)
(output)
(text "OUT" (rect 32 7 49 19)(font "Courier New" (bold))(invisible))
(text "OUT" (rect 32 7 46 19)(font "Courier New" (bold))(invisible))
(line (pt 39 16)(pt 48 16))
)
(drawing
(line (pt 13 25)(pt 13 7))
(line (pt 13 7)(pt 31 16))
(line (pt 13 25)(pt 31 16))
(circle (rect 31 12 39 20))
)
)
(symbol
(rect 296 520 360 600)
(text "DFFE" (rect 1 0 25 10)(font "Arial" (font_size 6)))
(text "intr_ff4" (rect 3 68 39 80)(font "Arial" ))
(port
(pt 32 0)
(input)
(text "PRN" (rect 24 13 41 25)(font "Courier New" (bold)))
(text "PRN" (rect 24 11 41 23)(font "Courier New" (bold)))
(line (pt 32 4)(pt 32 0))
)
(port
(pt 32 80)
(input)
(text "CLRN" (rect 21 59 44 71)(font "Courier New" (bold)))
630,13 → 684,6
(line (pt 32 80)(pt 32 76))
)
(port
(pt 0 40)
(input)
(text "CLK" (rect 3 29 20 41)(font "Courier New" (bold))(invisible))
(text "CLK" (rect 3 29 20 41)(font "Courier New" (bold))(invisible))
(line (pt 0 40)(pt 12 40))
)
(port
(pt 0 24)
(input)
(text "D" (rect 14 20 19 32)(font "Courier New" (bold)))
644,77 → 691,92
(line (pt 0 24)(pt 12 24))
)
(port
(pt 32 0)
(pt 0 40)
(input)
(text "PRN" (rect 24 13 41 25)(font "Courier New" (bold)))
(text "PRN" (rect 24 11 41 23)(font "Courier New" (bold)))
(line (pt 32 4)(pt 32 0))
(text "CLK" (rect 2 28 19 40)(font "Courier New" (bold))(invisible))
(text "CLK" (rect 2 28 19 40)(font "Courier New" (bold))(invisible))
(line (pt 0 40)(pt 12 40))
)
(port
(pt 0 56)
(input)
(text "ENA" (rect 14 50 31 62)(font "Courier New" (bold)))
(text "ENA" (rect 14 50 31 62)(font "Courier New" (bold)))
(line (pt 0 56)(pt 12 56))
)
(port
(pt 64 24)
(output)
(text "Q" (rect 45 20 50 32)(font "Courier New" (bold)))
(text "Q" (rect 43 20 48 32)(font "Courier New" (bold)))
(line (pt 52 24)(pt 64 24))
(text "Q" (rect 44 20 49 32)(font "Courier New" (bold)))
(text "Q" (rect 44 20 48 32)(font "Courier New" (bold)))
(line (pt 53 24)(pt 64 24))
)
(drawing
(line (pt 12 68)(pt 52 68))
(line (pt 12 12)(pt 52 12))
(line (pt 12 68)(pt 52 68))
(line (pt 52 68)(pt 52 12))
(line (pt 12 68)(pt 12 12))
(line (pt 19 40)(pt 12 47))
(line (pt 12 32)(pt 20 40))
(line (pt 12 34)(pt 19 41))
(line (pt 18 41)(pt 12 47))
(circle (rect 28 4 36 12))
(circle (rect 28 68 36 76))
)
)
(symbol
(rect 680 456 744 536)
(text "OR4" (rect 1 0 19 10)(font "Arial" (font_size 6)))
(text "inst" (rect 3 69 20 81)(font "Arial" ))
(rect 408 520 472 600)
(text "DFFE" (rect 1 0 25 10)(font "Arial" (font_size 6)))
(text "intr_ff5" (rect 3 68 39 80)(font "Arial" ))
(port
(pt 0 16)
(pt 32 0)
(input)
(text "IN1" (rect 2 7 19 19)(font "Courier New" (bold))(invisible))
(text "IN1" (rect 2 7 19 19)(font "Courier New" (bold))(invisible))
(line (pt 0 16)(pt 13 16))
(text "PRN" (rect 24 13 41 25)(font "Courier New" (bold)))
(text "PRN" (rect 24 11 41 23)(font "Courier New" (bold)))
(line (pt 32 4)(pt 32 0))
)
(port
(pt 0 48)
(pt 32 80)
(input)
(text "IN3" (rect 2 39 19 51)(font "Courier New" (bold))(invisible))
(text "IN3" (rect 2 39 19 51)(font "Courier New" (bold))(invisible))
(line (pt 0 48)(pt 15 48))
(text "CLRN" (rect 21 59 44 71)(font "Courier New" (bold)))
(text "CLRN" (rect 21 58 44 70)(font "Courier New" (bold)))
(line (pt 32 80)(pt 32 76))
)
(port
(pt 0 64)
(pt 0 24)
(input)
(text "IN4" (rect 2 55 19 67)(font "Courier New" (bold))(invisible))
(text "IN4" (rect 2 55 19 67)(font "Courier New" (bold))(invisible))
(line (pt 0 64)(pt 13 64))
(text "D" (rect 14 20 19 32)(font "Courier New" (bold)))
(text "D" (rect 14 20 19 32)(font "Courier New" (bold)))
(line (pt 0 24)(pt 12 24))
)
(port
(pt 0 32)
(pt 0 40)
(input)
(text "IN2" (rect 2 23 19 35)(font "Courier New" (bold))(invisible))
(text "IN2" (rect 2 23 19 35)(font "Courier New" (bold))(invisible))
(line (pt 0 32)(pt 15 32))
(text "CLK" (rect 2 28 19 40)(font "Courier New" (bold))(invisible))
(text "CLK" (rect 2 28 19 40)(font "Courier New" (bold))(invisible))
(line (pt 0 40)(pt 12 40))
)
(port
(pt 64 40)
(pt 0 56)
(input)
(text "ENA" (rect 14 50 31 62)(font "Courier New" (bold)))
(text "ENA" (rect 14 50 31 62)(font "Courier New" (bold)))
(line (pt 0 56)(pt 12 56))
)
(port
(pt 64 24)
(output)
(text "OUT" (rect 48 31 65 43)(font "Courier New" (bold))(invisible))
(text "OUT" (rect 48 31 65 43)(font "Courier New" (bold))(invisible))
(line (pt 48 40)(pt 64 40))
(text "Q" (rect 44 20 49 32)(font "Courier New" (bold)))
(text "Q" (rect 44 20 48 32)(font "Courier New" (bold)))
(line (pt 53 24)(pt 64 24))
)
(drawing
(line (pt 13 67)(pt 13 51))
(line (pt 25 52)(pt 13 52))
(line (pt 13 12)(pt 13 29))
(line (pt 13 29)(pt 25 29))
(arc (pt 7 45)(pt 7 35)(rect -14 24 19 57))
(arc (pt 49 40)(pt 25 29)(rect -6 29 57 92))
(arc (pt 25 51)(pt 49 40)(rect -6 -11 57 52))
(line (pt 12 68)(pt 52 68))
(line (pt 12 12)(pt 52 12))
(line (pt 52 68)(pt 52 12))
(line (pt 12 68)(pt 12 12))
(line (pt 12 34)(pt 19 41))
(line (pt 18 41)(pt 12 47))
(circle (rect 28 4 36 12))
(circle (rect 28 68 36 76))
)
)
(connector
907,106 → 969,146
(pt 624 544)
)
(connector
(pt 680 504)
(pt 496 504)
(text "clrpc_int" (rect 630 456 671 468)(font "Arial" ))
(pt 680 472)
(pt 624 472)
)
(connector
(pt 496 504)
(pt 496 544)
(pt 744 496)
(pt 776 496)
)
(connector
(pt 472 544)
(pt 496 544)
(pt 712 296)
(pt 712 336)
)
(connector
(pt 496 544)
(pt 520 544)
(pt 712 336)
(pt 712 424)
)
(connector
(pt 232 320)
(pt 232 352)
)
(connector
(pt 208 648)
(pt 216 648)
)
(connector
(pt 296 560)
(pt 264 560)
)
(connector
(pt 264 616)
(pt 264 560)
)
(connector
(text "nclk" (rect 216 600 236 612)(font "Arial" ))
(pt 208 616)
(pt 264 616)
)
(connector
(pt 712 424)
(pt 264 424)
)
(connector
(pt 264 424)
(pt 264 544)
)
(connector
(pt 296 544)
(pt 264 544)
)
(connector
(pt 408 560)
(pt 376 560)
)
(connector
(pt 376 616)
(pt 376 560)
)
(connector
(pt 680 488)
(pt 384 488)
(pt 376 488)
)
(connector
(pt 384 488)
(pt 384 544)
(pt 376 544)
(pt 376 488)
)
(connector
(pt 360 544)
(pt 384 544)
(pt 376 544)
)
(connector
(pt 384 544)
(pt 376 544)
(pt 408 544)
)
(connector
(text "clrpc_int" (rect 630 456 671 468)(font "Arial" ))
(pt 680 472)
(pt 624 472)
(pt 520 560)
(pt 488 560)
)
(connector
(pt 744 496)
(pt 776 496)
(pt 488 560)
(pt 488 616)
)
(connector
(pt 712 296)
(pt 712 336)
(pt 264 616)
(pt 376 616)
)
(connector
(pt 712 336)
(pt 712 424)
(pt 376 616)
(pt 488 616)
)
(connector
(pt 712 424)
(pt 272 424)
(pt 680 504)
(pt 488 504)
)
(connector
(pt 272 424)
(pt 272 544)
(pt 488 544)
(pt 488 504)
)
(connector
(pt 296 544)
(pt 272 544)
(pt 472 544)
(pt 488 544)
)
(connector
(pt 520 560)
(pt 496 560)
(pt 488 544)
(pt 520 544)
)
(connector
(pt 496 560)
(pt 496 616)
(pt 504 648)
(pt 504 576)
)
(connector
(pt 232 320)
(pt 232 352)
(pt 520 576)
(pt 504 576)
)
(connector
(pt 408 560)
(pt 384 560)
(pt 408 576)
(pt 392 576)
)
(connector
(pt 384 560)
(pt 384 616)
(pt 392 576)
(pt 392 648)
)
(connector
(pt 496 616)
(pt 384 616)
(pt 392 648)
(pt 504 648)
)
(connector
(pt 296 560)
(pt 272 560)
(pt 296 576)
(pt 280 576)
)
(connector
(pt 272 560)
(pt 272 616)
(pt 280 576)
(pt 280 648)
)
(connector
(pt 272 616)
(pt 384 616)
(pt 264 648)
(pt 280 648)
)
(connector
(text "nclk" (rect 216 600 236 612)(font "Arial" ))
(pt 208 616)
(pt 272 616)
(pt 280 648)
(pt 392 648)
)
(junction (pt 232 144))
(junction (pt 368 96))
1016,11 → 1118,13
(junction (pt 320 320))
(junction (pt 232 352))
(junction (pt 712 224))
(junction (pt 496 544))
(junction (pt 384 544))
(junction (pt 712 336))
(junction (pt 384 616))
(junction (pt 272 616))
(junction (pt 264 616))
(junction (pt 376 616))
(junction (pt 376 544))
(junction (pt 488 544))
(junction (pt 392 648))
(junction (pt 280 648))
(text "Needed only for FPGAs" (rect 40 72 174 86)(font "Arial" (font_size 8)))
(text "Special reset, USPTO 4,486,827 by Shima et al." (rect 40 24 371 40)(font "Arial" (font_size 10))(border))
(text "Required 3 clock reset cycles to clear PC and IR" (rect 304 464 576 478)(font "Arial" (font_size 8)))
1033,7 → 1137,7
(section (rect 0 18 256 34)(text "DESIGNER" (rect 2 0 59 12)(font "Arial" ))(text "Goran Devic" (rect 56 2 135 17)(font "Arial" (font_size 9)))(border))
(section (rect 104 0 256 17)(text "MODULE" (rect 2 1 48 13)(font "Arial" ))(text "resets" (rect 43 2 86 17)(font "Arial" (font_size 9)(bold)))(border))
(section (rect 0 0 256 17)(text "PROJECT" (rect 2 0 52 12)(font "Arial" ))(text "A-Z80" (rect 56 2 94 17)(font "Arial" (font_size 9)(bold)))(border))
(section (rect 192 35 256 51)(text "REV" (rect 2 1 25 13)(font "Arial" ))(text "1.3" (rect 43 3 60 17)(font "Arial" (font_size 8)))(border))
(section (rect 192 35 256 51)(text "REV" (rect 2 1 25 13)(font "Arial" ))(text "1.4" (rect 43 3 60 17)(font "Arial" (font_size 8)))(border))
(drawing
)
)
/trunk/cpu/control/resets.bsf
20,9 → 20,9
*/
(header "symbol" (version "1.2"))
(symbol
(rect 16 16 168 144)
(rect 16 16 184 176)
(text "resets" (rect 5 0 41 14)(font "Arial" (font_size 8)))
(text "inst" (rect 8 112 25 124)(font "Arial" ))
(text "inst" (rect 8 144 25 156)(font "Arial" ))
(port
(pt 0 32)
(input)
59,20 → 59,27
(line (pt 0 96)(pt 16 96))
)
(port
(pt 152 32)
(output)
(text "clrpc" (rect 0 0 28 14)(font "Arial" (font_size 8)))
(text "clrpc" (rect 103 27 131 41)(font "Arial" (font_size 8)))
(line (pt 152 32)(pt 136 32))
(pt 0 112)
(input)
(text "hold_clk_wait" (rect 0 0 77 14)(font "Arial" (font_size 8)))
(text "hold_clk_wait" (rect 21 107 98 121)(font "Arial" (font_size 8)))
(line (pt 0 112)(pt 16 112))
)
(port
(pt 152 48)
(pt 168 32)
(output)
(text "nreset" (rect 0 0 36 14)(font "Arial" (font_size 8)))
(text "nreset" (rect 95 43 131 57)(font "Arial" (font_size 8)))
(line (pt 152 48)(pt 136 48))
(text "nreset" (rect 111 27 147 41)(font "Arial" (font_size 8)))
(line (pt 168 32)(pt 152 32))
)
(port
(pt 168 48)
(output)
(text "clrpc" (rect 0 0 28 14)(font "Arial" (font_size 8)))
(text "clrpc" (rect 119 43 147 57)(font "Arial" (font_size 8)))
(line (pt 168 48)(pt 152 48))
)
(drawing
(rectangle (rect 16 16 136 112))
(rectangle (rect 16 16 152 144))
)
)
/trunk/cpu/control/resets.v
14,7 → 14,7
 
// PROGRAM "Quartus II 64-Bit"
// VERSION "Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition"
// CREATED "Sat Feb 27 08:32:59 2016"
// CREATED "Thu Dec 08 21:08:44 2016"
 
module resets(
reset_in,
22,6 → 22,7
M1,
T2,
fpga_reset,
hold_clk_wait,
clrpc,
nreset
);
32,6 → 33,7
input wire M1;
input wire T2;
input wire fpga_reset;
input wire hold_clk_wait;
output wire clrpc;
output wire nreset;
 
40,24 → 42,25
reg x1;
wire x2;
wire x3;
wire SYNTHESIZED_WIRE_8;
wire SYNTHESIZED_WIRE_11;
wire SYNTHESIZED_WIRE_1;
reg SYNTHESIZED_WIRE_9;
reg DFF_res3;
reg SYNTHESIZED_WIRE_10;
wire SYNTHESIZED_WIRE_11;
reg SYNTHESIZED_WIRE_12;
reg DFFE_intr_ff3;
reg SYNTHESIZED_WIRE_13;
wire SYNTHESIZED_WIRE_14;
wire SYNTHESIZED_WIRE_3;
reg SYNTHESIZED_WIRE_12;
wire SYNTHESIZED_WIRE_6;
reg SYNTHESIZED_WIRE_15;
wire SYNTHESIZED_WIRE_16;
wire SYNTHESIZED_WIRE_9;
 
assign nreset = SYNTHESIZED_WIRE_6;
assign nreset = SYNTHESIZED_WIRE_9;
 
 
 
 
always@(posedge nclk or negedge SYNTHESIZED_WIRE_8)
always@(posedge nclk or negedge SYNTHESIZED_WIRE_11)
begin
if (!SYNTHESIZED_WIRE_8)
if (!SYNTHESIZED_WIRE_11)
begin
x1 <= 1;
end
67,42 → 70,41
end
end
 
assign clrpc = clrpc_int | SYNTHESIZED_WIRE_9 | DFF_res3 | SYNTHESIZED_WIRE_10;
assign clrpc = clrpc_int | SYNTHESIZED_WIRE_12 | DFFE_intr_ff3 | SYNTHESIZED_WIRE_13;
 
assign SYNTHESIZED_WIRE_1 = ~reset_in;
 
assign x2 = x1 & SYNTHESIZED_WIRE_11;
assign x2 = x1 & SYNTHESIZED_WIRE_14;
 
assign SYNTHESIZED_WIRE_11 = M1 & T2;
assign SYNTHESIZED_WIRE_14 = M1 & T2;
 
assign x3 = x1 & SYNTHESIZED_WIRE_3;
 
assign SYNTHESIZED_WIRE_6 = ~SYNTHESIZED_WIRE_12;
assign SYNTHESIZED_WIRE_9 = ~SYNTHESIZED_WIRE_15;
 
assign SYNTHESIZED_WIRE_3 = ~SYNTHESIZED_WIRE_11;
assign SYNTHESIZED_WIRE_16 = ~hold_clk_wait;
 
assign SYNTHESIZED_WIRE_3 = ~SYNTHESIZED_WIRE_14;
 
assign nclk = ~clk;
 
assign SYNTHESIZED_WIRE_8 = ~fpga_reset;
assign SYNTHESIZED_WIRE_11 = ~fpga_reset;
 
 
always@(posedge clk or negedge SYNTHESIZED_WIRE_8)
always@(posedge nclk)
begin
if (!SYNTHESIZED_WIRE_8)
if (SYNTHESIZED_WIRE_16)
begin
SYNTHESIZED_WIRE_12 <= 1;
DFFE_intr_ff3 <= SYNTHESIZED_WIRE_12;
end
else
begin
SYNTHESIZED_WIRE_12 <= x3;
end
end
 
 
always@(posedge nclk)
begin
if (SYNTHESIZED_WIRE_16)
begin
SYNTHESIZED_WIRE_10 <= SYNTHESIZED_WIRE_12;
SYNTHESIZED_WIRE_13 <= SYNTHESIZED_WIRE_15;
end
end
 
109,29 → 111,35
 
always@(posedge nclk)
begin
if (SYNTHESIZED_WIRE_16)
begin
SYNTHESIZED_WIRE_9 <= SYNTHESIZED_WIRE_10;
SYNTHESIZED_WIRE_12 <= SYNTHESIZED_WIRE_13;
end
end
 
 
always@(posedge nclk)
always@(posedge clk or negedge SYNTHESIZED_WIRE_11)
begin
if (!SYNTHESIZED_WIRE_11)
begin
DFF_res3 <= SYNTHESIZED_WIRE_9;
SYNTHESIZED_WIRE_15 <= 1;
end
else
begin
SYNTHESIZED_WIRE_15 <= x3;
end
end
 
 
always@(posedge nclk or negedge SYNTHESIZED_WIRE_6)
always@(posedge nclk or negedge SYNTHESIZED_WIRE_9)
begin
if (!SYNTHESIZED_WIRE_6)
if (!SYNTHESIZED_WIRE_9)
begin
clrpc_int <= 0;
end
else
begin
clrpc_int <= ~clrpc_int & x2 | clrpc_int & ~SYNTHESIZED_WIRE_11;
clrpc_int <= ~clrpc_int & x2 | clrpc_int & ~SYNTHESIZED_WIRE_14;
end
end
 
/trunk/cpu/control/simulation/modelsim/wave_reset.do
6,6 → 6,7
add wave -noupdate /test_reset/M1
add wave -noupdate /test_reset/T2
add wave -noupdate -color Gold /test_reset/clrpc
add wave -noupdate /test_reset/reset_block/hold_clk_wait
add wave -noupdate /test_reset/nreset
add wave -noupdate -color {Cadet Blue} /test_reset/reset_block/x1
add wave -noupdate -color {Cadet Blue} /test_reset/reset_block/x2
/trunk/cpu/control/test_reset.sv
23,8 → 23,11
logic T2 = 0;
 
wire clrpc; // Load 0 to PC
wire hold_clk_wait; // Hold clrpc
wire nreset; // Internal inverted reset signal
 
assign hold_clk_wait = 0; // Will not test this case
 
// ----------------- TEST -------------------
initial begin
// Test normal reset sequence - 3 clocks long
/trunk/cpu/control/timing_macros.i
323,11 → 323,11
 
WZ=IX+d ixy_d=1; // Compute WZ=IX+d
IX_IY ctl_state_ixiy_we=1; ctl_state_iy_set=op5; setIXIY=1; // IX/IY prefix
CLR_IX_IY ctl_state_ixiy_we=1; ctl_state_ixiy_clr=~setIXIY; // Clear IX/IY flag
CLR_IX_IY ctl_state_ixiy_we=1; ctl_state_ixiy_clr=~setIXIY; // Clear IX/IY flag if not explicitly set
 
CB ctl_state_tbl_cb_set=1; setCBED=1; // CB-table prefix
ED ctl_state_tbl_ed_set=1; setCBED=1; // ED-table prefix
CLR_CB_ED ctl_state_tbl_clr=~setCBED; // Clear CB/ED prefix
CB ctl_state_tbl_we=1; ctl_state_tbl_cb_set=1; // CB-table prefix
ED ctl_state_tbl_we=1; ctl_state_tbl_ed_set=1; // ED-table prefix
CLR_CB_ED ctl_state_tbl_we=1; // Clear CB/ED prefix if not explicitly set
 
// If the NF is set, complement HF and CF on the way out to the bus
// This is used to correctly set those flags after subtraction operations
/trunk/cpu/export.py
23,7 → 23,9
if len(sys.argv) != 2:
print ("\nUsage: export.py <destination-folder>\n")
print ("Copies all core A-Z80 Verilog files to a destination of your choice.")
print ("The files copied are necessary and sufficient to include with your project.")
print ("The files copied are necessary and sufficient to include with your project.\n")
print ("Note for the users of Lattice FPGA toolset: instead of data_pins.v, manually")
print ("copy and use data_pins_lattice.v file instead.")
exit(-1)
 
dest = sys.argv[1]
/trunk/cpu/registers/reg_control.bdf
340,6 → 340,22
(text "VCC" (rect 136 7 156 17)(font "Arial" (font_size 6)))
)
(pin
(input)
(rect 32 848 208 864)
(text "INPUT" (rect 133 0 161 10)(font "Arial" (font_size 6)))
(text "hold_clk_wait" (rect 9 0 73 12)(font "Arial" ))
(pt 176 8)
(drawing
(line (pt 92 12)(pt 117 12))
(line (pt 92 4)(pt 117 4))
(line (pt 121 8)(pt 176 8))
(line (pt 92 12)(pt 92 4))
(line (pt 117 4)(pt 121 8))
(line (pt 117 12)(pt 121 8))
)
(text "VCC" (rect 136 7 156 17)(font "Arial" (font_size 6)))
)
(pin
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(rect 1144 216 1320 232)
(text "OUTPUT" (rect 1 0 39 10)(font "Arial" (font_size 6)))
722,7 → 738,7
(pt 48 16)
(output)
(text "OUT" (rect 32 7 49 19)(font "Courier New" (bold))(invisible))
(text "OUT" (rect 32 7 49 19)(font "Courier New" (bold))(invisible))
(text "OUT" (rect 32 7 46 19)(font "Courier New" (bold))(invisible))
(line (pt 39 16)(pt 48 16))
)
(drawing
747,7 → 763,7
(pt 48 16)
(output)
(text "OUT" (rect 32 7 49 19)(font "Courier New" (bold))(invisible))
(text "OUT" (rect 32 7 49 19)(font "Courier New" (bold))(invisible))
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(line (pt 39 16)(pt 48 16))
)
(drawing
758,56 → 774,6
)
)
(symbol
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(text "TFF" (rect 1 0 18 10)(font "Arial" (font_size 6)))
(text "inst7" (rect 3 68 26 80)(font "Arial" ))
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(text "PRN" (rect 24 11 41 23)(font "Courier New" (bold)))
(line (pt 32 4)(pt 32 0))
)
(port
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(text "CLRN" (rect 21 58 44 70)(font "Courier New" (bold)))
(line (pt 32 80)(pt 32 76))
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(port
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(text "T" (rect 16 20 21 32)(font "Courier New" (bold)))
(line (pt 0 24)(pt 12 24))
)
(port
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(text "CLK" (rect 2 28 19 40)(font "Courier New" (bold))(invisible))
(line (pt 0 40)(pt 12 40))
)
(port
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)
(drawing
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(symbol
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(text "AND2" (rect 1 0 25 10)(font "Arial" (font_size 6)))
(text "inst8" (rect 3 37 26 49)(font "Arial" ))
829,7 → 795,7
(pt 64 24)
(output)
(text "OUT" (rect 48 15 65 27)(font "Courier New" (bold))(invisible))
(text "OUT" (rect 48 15 65 27)(font "Courier New" (bold))(invisible))
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(line (pt 42 24)(pt 64 24))
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(drawing
854,7 → 820,7
(pt 48 16)
(output)
(text "OUT" (rect 32 7 49 19)(font "Courier New" (bold))(invisible))
(text "OUT" (rect 32 7 49 19)(font "Courier New" (bold))(invisible))
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(line (pt 39 16)(pt 48 16))
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(drawing
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(pt 48 16)
(output)
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(line (pt 39 16)(pt 48 16))
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(drawing
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(pt 64 24)
(output)
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(text "OUT" (rect 48 15 65 27)(font "Courier New" (bold))(invisible))
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(line (pt 42 24)(pt 64 24))
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(drawing
943,7 → 909,7
(pt 64 24)
(output)
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(text "OUT" (rect 48 15 65 27)(font "Courier New" (bold))(invisible))
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(line (pt 42 24)(pt 64 24))
)
(drawing
968,7 → 934,7
(pt 48 16)
(output)
(text "OUT" (rect 32 7 49 19)(font "Courier New" (bold))(invisible))
(text "OUT" (rect 32 7 49 19)(font "Courier New" (bold))(invisible))
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(line (pt 39 16)(pt 48 16))
)
(drawing
993,7 → 959,7
(pt 48 16)
(output)
(text "OUT" (rect 32 7 49 19)(font "Courier New" (bold))(invisible))
(text "OUT" (rect 32 7 49 19)(font "Courier New" (bold))(invisible))
(text "OUT" (rect 32 7 46 19)(font "Courier New" (bold))(invisible))
(line (pt 39 16)(pt 48 16))
)
(drawing
1004,156 → 970,6
)
)
(symbol
(rect 680 800 744 880)
(text "TFF" (rect 1 0 18 10)(font "Arial" (font_size 6)))
(text "inst9" (rect 3 68 26 80)(font "Arial" ))
(port
(pt 32 0)
(input)
(text "PRN" (rect 24 13 41 25)(font "Courier New" (bold)))
(text "PRN" (rect 24 11 41 23)(font "Courier New" (bold)))
(line (pt 32 4)(pt 32 0))
)
(port
(pt 32 80)
(input)
(text "CLRN" (rect 21 59 44 71)(font "Courier New" (bold)))
(text "CLRN" (rect 21 58 44 70)(font "Courier New" (bold)))
(line (pt 32 80)(pt 32 76))
)
(port
(pt 0 24)
(input)
(text "T" (rect 16 20 21 32)(font "Courier New" (bold)))
(text "T" (rect 16 20 21 32)(font "Courier New" (bold)))
(line (pt 0 24)(pt 12 24))
)
(port
(pt 0 40)
(input)
(text "CLK" (rect 2 28 19 40)(font "Courier New" (bold))(invisible))
(text "CLK" (rect 2 28 19 40)(font "Courier New" (bold))(invisible))
(line (pt 0 40)(pt 12 40))
)
(port
(pt 64 24)
(output)
(text "Q" (rect 45 20 50 32)(font "Courier New" (bold)))
(text "Q" (rect 43 20 48 32)(font "Courier New" (bold)))
(line (pt 52 24)(pt 64 24))
)
(drawing
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(line (pt 18 41)(pt 12 47))
(circle (rect 28 4 36 12))
(circle (rect 28 68 36 76))
)
)
(symbol
(rect 680 488 744 568)
(text "TFF" (rect 1 0 18 10)(font "Arial" (font_size 6)))
(text "inst24" (rect 3 68 32 80)(font "Arial" ))
(port
(pt 32 0)
(input)
(text "PRN" (rect 24 13 41 25)(font "Courier New" (bold)))
(text "PRN" (rect 24 11 41 23)(font "Courier New" (bold)))
(line (pt 32 4)(pt 32 0))
)
(port
(pt 32 80)
(input)
(text "CLRN" (rect 21 59 44 71)(font "Courier New" (bold)))
(text "CLRN" (rect 21 58 44 70)(font "Courier New" (bold)))
(line (pt 32 80)(pt 32 76))
)
(port
(pt 0 24)
(input)
(text "T" (rect 16 20 21 32)(font "Courier New" (bold)))
(text "T" (rect 16 20 21 32)(font "Courier New" (bold)))
(line (pt 0 24)(pt 12 24))
)
(port
(pt 0 40)
(input)
(text "CLK" (rect 2 28 19 40)(font "Courier New" (bold))(invisible))
(text "CLK" (rect 2 28 19 40)(font "Courier New" (bold))(invisible))
(line (pt 0 40)(pt 12 40))
)
(port
(pt 64 24)
(output)
(text "Q" (rect 45 20 50 32)(font "Courier New" (bold)))
(text "Q" (rect 43 20 48 32)(font "Courier New" (bold)))
(line (pt 52 24)(pt 64 24))
)
(drawing
(line (pt 12 12)(pt 52 12))
(line (pt 12 68)(pt 52 68))
(line (pt 12 68)(pt 12 12))
(line (pt 52 68)(pt 52 12))
(line (pt 12 34)(pt 19 41))
(line (pt 18 41)(pt 12 47))
(circle (rect 28 4 36 12))
(circle (rect 28 68 36 76))
)
)
(symbol
(rect 680 376 744 456)
(text "TFF" (rect 1 0 18 10)(font "Arial" (font_size 6)))
(text "inst26" (rect 3 68 32 80)(font "Arial" ))
(port
(pt 32 0)
(input)
(text "PRN" (rect 24 13 41 25)(font "Courier New" (bold)))
(text "PRN" (rect 24 11 41 23)(font "Courier New" (bold)))
(line (pt 32 4)(pt 32 0))
)
(port
(pt 32 80)
(input)
(text "CLRN" (rect 21 59 44 71)(font "Courier New" (bold)))
(text "CLRN" (rect 21 58 44 70)(font "Courier New" (bold)))
(line (pt 32 80)(pt 32 76))
)
(port
(pt 0 24)
(input)
(text "T" (rect 16 20 21 32)(font "Courier New" (bold)))
(text "T" (rect 16 20 21 32)(font "Courier New" (bold)))
(line (pt 0 24)(pt 12 24))
)
(port
(pt 0 40)
(input)
(text "CLK" (rect 2 28 19 40)(font "Courier New" (bold))(invisible))
(text "CLK" (rect 2 28 19 40)(font "Courier New" (bold))(invisible))
(line (pt 0 40)(pt 12 40))
)
(port
(pt 64 24)
(output)
(text "Q" (rect 45 20 50 32)(font "Courier New" (bold)))
(text "Q" (rect 43 20 48 32)(font "Courier New" (bold)))
(line (pt 52 24)(pt 64 24))
)
(drawing
(line (pt 12 12)(pt 52 12))
(line (pt 12 68)(pt 52 68))
(line (pt 12 68)(pt 12 12))
(line (pt 52 68)(pt 52 12))
(line (pt 12 34)(pt 19 41))
(line (pt 18 41)(pt 12 47))
(circle (rect 28 4 36 12))
(circle (rect 28 68 36 76))
)
)
(symbol
(rect 944 616 1008 664)
(text "AND2" (rect 1 0 25 10)(font "Arial" (font_size 6)))
(text "i2" (rect 3 37 11 49)(font "Arial" ))
1175,7 → 991,7
(pt 64 24)
(output)
(text "OUT" (rect 48 15 65 27)(font "Courier New" (bold))(invisible))
(text "OUT" (rect 48 15 65 27)(font "Courier New" (bold))(invisible))
(text "OUT" (rect 48 15 62 27)(font "Courier New" (bold))(invisible))
(line (pt 42 24)(pt 64 24))
)
(drawing
1207,7 → 1023,7
(pt 64 24)
(output)
(text "OUT" (rect 48 15 65 27)(font "Courier New" (bold))(invisible))
(text "OUT" (rect 48 15 65 27)(font "Courier New" (bold))(invisible))
(text "OUT" (rect 48 15 62 27)(font "Courier New" (bold))(invisible))
(line (pt 42 24)(pt 64 24))
)
(drawing
1232,7 → 1048,7
(pt 48 16)
(output)
(text "OUT" (rect 32 7 49 19)(font "Courier New" (bold))(invisible))
(text "OUT" (rect 32 7 49 19)(font "Courier New" (bold))(invisible))
(text "OUT" (rect 32 7 46 19)(font "Courier New" (bold))(invisible))
(line (pt 39 16)(pt 48 16))
)
(drawing
1264,7 → 1080,7
(pt 64 24)
(output)
(text "OUT" (rect 48 15 65 27)(font "Courier New" (bold))(invisible))
(text "OUT" (rect 48 15 65 27)(font "Courier New" (bold))(invisible))
(text "OUT" (rect 48 15 62 27)(font "Courier New" (bold))(invisible))
(line (pt 42 24)(pt 64 24))
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(drawing
1296,7 → 1112,7
(pt 64 24)
(output)
(text "OUT" (rect 48 15 65 27)(font "Courier New" (bold))(invisible))
(text "OUT" (rect 48 15 65 27)(font "Courier New" (bold))(invisible))
(text "OUT" (rect 48 15 62 27)(font "Courier New" (bold))(invisible))
(line (pt 42 24)(pt 64 24))
)
(drawing
1328,7 → 1144,7
(pt 64 24)
(output)
(text "OUT" (rect 48 15 65 27)(font "Courier New" (bold))(invisible))
(text "OUT" (rect 48 15 65 27)(font "Courier New" (bold))(invisible))
(text "OUT" (rect 48 15 62 27)(font "Courier New" (bold))(invisible))
(line (pt 42 24)(pt 64 24))
)
(drawing
1353,7 → 1169,7
(pt 48 16)
(output)
(text "OUT" (rect 32 7 49 19)(font "Courier New" (bold))(invisible))
(text "OUT" (rect 32 7 49 19)(font "Courier New" (bold))(invisible))
(text "OUT" (rect 32 7 46 19)(font "Courier New" (bold))(invisible))
(line (pt 39 16)(pt 48 16))
)
(drawing
1385,7 → 1201,7
(pt 64 24)
(output)
(text "OUT" (rect 48 15 65 27)(font "Courier New" (bold))(invisible))
(text "OUT" (rect 48 15 65 27)(font "Courier New" (bold))(invisible))
(text "OUT" (rect 48 15 62 27)(font "Courier New" (bold))(invisible))
(line (pt 42 24)(pt 64 24))
)
(drawing
1417,7 → 1233,7
(pt 64 24)
(output)
(text "OUT" (rect 48 15 65 27)(font "Courier New" (bold))(invisible))
(text "OUT" (rect 48 15 65 27)(font "Courier New" (bold))(invisible))
(text "OUT" (rect 48 15 62 27)(font "Courier New" (bold))(invisible))
(line (pt 42 24)(pt 64 24))
)
(drawing
1449,7 → 1265,7
(pt 64 24)
(output)
(text "OUT" (rect 48 15 65 27)(font "Courier New" (bold))(invisible))
(text "OUT" (rect 48 15 65 27)(font "Courier New" (bold))(invisible))
(text "OUT" (rect 48 15 62 27)(font "Courier New" (bold))(invisible))
(line (pt 42 24)(pt 64 24))
)
(drawing
1481,7 → 1297,7
(pt 64 24)
(output)
(text "OUT" (rect 48 15 65 27)(font "Courier New" (bold))(invisible))
(text "OUT" (rect 48 15 65 27)(font "Courier New" (bold))(invisible))
(text "OUT" (rect 48 15 62 27)(font "Courier New" (bold))(invisible))
(line (pt 42 24)(pt 64 24))
)
(drawing
1513,7 → 1329,7
(pt 64 24)
(output)
(text "OUT" (rect 48 15 65 27)(font "Courier New" (bold))(invisible))
(text "OUT" (rect 48 15 65 27)(font "Courier New" (bold))(invisible))
(text "OUT" (rect 48 15 62 27)(font "Courier New" (bold))(invisible))
(line (pt 42 24)(pt 64 24))
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(drawing
1538,7 → 1354,7
(pt 48 16)
(output)
(text "OUT" (rect 32 7 49 19)(font "Courier New" (bold))(invisible))
(text "OUT" (rect 32 7 49 19)(font "Courier New" (bold))(invisible))
(text "OUT" (rect 32 7 46 19)(font "Courier New" (bold))(invisible))
(line (pt 39 16)(pt 48 16))
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(drawing
1570,7 → 1386,7
(pt 64 24)
(output)
(text "OUT" (rect 48 15 65 27)(font "Courier New" (bold))(invisible))
(text "OUT" (rect 48 15 65 27)(font "Courier New" (bold))(invisible))
(text "OUT" (rect 48 15 62 27)(font "Courier New" (bold))(invisible))
(line (pt 42 24)(pt 64 24))
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(drawing
1595,7 → 1411,7
(pt 48 16)
(output)
(text "OUT" (rect 32 7 49 19)(font "Courier New" (bold))(invisible))
(text "OUT" (rect 32 7 49 19)(font "Courier New" (bold))(invisible))
(text "OUT" (rect 32 7 46 19)(font "Courier New" (bold))(invisible))
(line (pt 39 16)(pt 48 16))
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(drawing
1620,7 → 1436,7
(pt 48 16)
(output)
(text "OUT" (rect 32 7 49 19)(font "Courier New" (bold))(invisible))
(text "OUT" (rect 32 7 49 19)(font "Courier New" (bold))(invisible))
(text "OUT" (rect 32 7 46 19)(font "Courier New" (bold))(invisible))
(line (pt 39 16)(pt 48 16))
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(drawing
1652,7 → 1468,7
(pt 64 24)
(output)
(text "OUT" (rect 48 15 65 27)(font "Courier New" (bold))(invisible))
(text "OUT" (rect 48 15 65 27)(font "Courier New" (bold))(invisible))
(text "OUT" (rect 48 15 62 27)(font "Courier New" (bold))(invisible))
(line (pt 48 24)(pt 64 24))
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(drawing
1685,7 → 1501,7
(pt 64 24)
(output)
(text "OUT" (rect 48 15 65 27)(font "Courier New" (bold))(invisible))
(text "OUT" (rect 48 15 65 27)(font "Courier New" (bold))(invisible))
(text "OUT" (rect 48 15 62 27)(font "Courier New" (bold))(invisible))
(line (pt 42 24)(pt 64 24))
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(drawing
1717,7 → 1533,7
(pt 64 24)
(output)
(text "OUT" (rect 48 15 65 27)(font "Courier New" (bold))(invisible))
(text "OUT" (rect 48 15 65 27)(font "Courier New" (bold))(invisible))
(text "OUT" (rect 48 15 62 27)(font "Courier New" (bold))(invisible))
(line (pt 42 24)(pt 64 24))
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(drawing
1749,7 → 1565,7
(pt 64 24)
(output)
(text "OUT" (rect 48 15 65 27)(font "Courier New" (bold))(invisible))
(text "OUT" (rect 48 15 65 27)(font "Courier New" (bold))(invisible))
(text "OUT" (rect 48 15 62 27)(font "Courier New" (bold))(invisible))
(line (pt 48 24)(pt 64 24))
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(drawing
1782,7 → 1598,7
(pt 64 24)
(output)
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(drawing
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(output)
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(drawing
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(output)
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(drawing
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(output)
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(drawing
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(output)
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(drawing
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(output)
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(drawing
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(output)
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(drawing
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(output)
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(drawing
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(output)
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(drawing
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(drawing
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(output)
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(drawing
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(output)
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(drawing
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(output)
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(text "OUT" (rect 48 15 65 27)(font "Courier New" (bold))(invisible))
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(drawing
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(output)
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(drawing
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(output)
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(text "OUT" (rect 48 15 65 27)(font "Courier New" (bold))(invisible))
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(drawing
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(output)
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(text "OUT" (rect 32 7 49 19)(font "Courier New" (bold))(invisible))
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(drawing
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(output)
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(text "OUT" (rect 48 15 65 27)(font "Courier New" (bold))(invisible))
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(drawing
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(output)
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(text "OUT" (rect 48 15 65 27)(font "Courier New" (bold))(invisible))
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(drawing
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(output)
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(text "OUT" (rect 32 7 49 19)(font "Courier New" (bold))(invisible))
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(drawing
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(output)
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(drawing
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(output)
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(drawing
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(output)
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(text "OUT" (rect 48 15 65 27)(font "Courier New" (bold))(invisible))
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(drawing
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(text "TFFE" (rect 1 0 24 10)(font "Arial" (font_size 6)))
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(port
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3501,6 → 3570,45
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(connector
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(connector
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(connector
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(connector
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(connector
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(junction (pt 600 624))
(junction (pt 264 312))
(junction (pt 264 632))
3555,6 → 3663,7
(junction (pt 400 1312))
(junction (pt 640 1240))
(junction (pt 640 1408))
(junction (pt 528 856))
(text "BC" (rect 440 120 456 134)(font "Arial" (font_size 8)))
(text "2'b00" (rect 328 120 358 134)(font "Arial" (font_size 8)))
(text "2'b01" (rect 328 280 358 294)(font "Arial" (font_size 8)))
3581,7 → 3690,7
(section (rect 130 0 320 20)(text "MODULE" (rect 2 1 48 13)(font "Arial" ))(text "reg_control" (rect 43 2 146 21)(font "Arial" (font_size 12)(bold)))(border))
(section (rect 0 21 320 40)(text "DESIGNER" (rect 2 0 59 12)(font "Arial" ))(text "Goran Devic" (rect 56 2 151 19)(font "Arial" (font_size 11)))(border))
(section (rect 0 41 240 60)(text "DATE" (rect 2 0 30 12)(font "Arial" ))(text "May 17, 2014, 2016" (rect 56 3 191 19)(font "Arial" (font_size 10)))(border))
(section (rect 241 41 320 60)(text "REV" (rect 2 1 25 13)(font "Arial" ))(text "1.3" (rect 43 3 64 19)(font "Arial" (font_size 10)))(border))
(section (rect 241 41 320 60)(text "REV" (rect 2 1 25 13)(font "Arial" ))(text "1.4" (rect 43 3 64 19)(font "Arial" (font_size 10)))(border))
(drawing
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/trunk/cpu/registers/reg_control.bsf
96,74 → 96,81
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(text "ctl_reg_use_sp" (rect 21 187 109 201)(font "Arial" (font_size 8)))
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(text "ctl_reg_sys_we_hi" (rect 21 203 130 217)(font "Arial" (font_size 8)))
(text "ctl_reg_use_sp" (rect 0 0 88 14)(font "Arial" (font_size 8)))
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(port
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(text "ctl_reg_sys_we_lo" (rect 21 235 130 249)(font "Arial" (font_size 8)))
(text "ctl_reg_sys_we" (rect 0 0 93 14)(font "Arial" (font_size 8)))
(text "ctl_reg_sys_we" (rect 21 235 114 249)(font "Arial" (font_size 8)))
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(text "ctl_reg_sys_hilo[1..0]" (rect 21 251 142 265)(font "Arial" (font_size 8)))
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(text "ctl_reg_sel_ir" (rect 21 283 97 297)(font "Arial" (font_size 8)))
(text "ctl_sw_4d" (rect 0 0 60 14)(font "Arial" (font_size 8)))
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(text "ctl_reg_sel_pc" (rect 21 299 104 313)(font "Arial" (font_size 8)))
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(input)
(text "ctl_reg_sel_wz" (rect 0 0 88 14)(font "Arial" (font_size 8)))
(text "ctl_reg_sel_wz" (rect 21 347 109 361)(font "Arial" (font_size 8)))
(line (pt 0 352)(pt 16 352))
)
(port
(pt 264 32)
(output)
(text "reg_gp_we" (rect 0 0 66 14)(font "Arial" (font_size 8)))
/trunk/cpu/registers/reg_control.v
14,7 → 14,7
 
// PROGRAM "Quartus II 64-Bit"
// VERSION "Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition"
// CREATED "Tue Mar 08 20:46:27 2016"
// CREATED "Thu Dec 08 22:19:25 2016"
 
module reg_control(
ctl_reg_exx,
34,6 → 34,7
ctl_reg_sys_we,
clk,
ctl_sw_4d,
hold_clk_wait,
ctl_reg_gp_hilo,
ctl_reg_gp_sel,
ctl_reg_sys_hilo,
80,6 → 81,7
input wire ctl_reg_sys_we;
input wire clk;
input wire ctl_sw_4d;
input wire hold_clk_wait;
input wire [1:0] ctl_reg_gp_hilo;
input wire [1:0] ctl_reg_gp_sel;
input wire [1:0] ctl_reg_sys_hilo;
111,6 → 113,7
reg bank_exx;
reg bank_hl_de1;
reg bank_hl_de2;
wire n_hold_clk_wait;
wire reg_sys_we_lo_ALTERA_SYNTHESIZED;
wire SYNTHESIZED_WIRE_52;
wire SYNTHESIZED_WIRE_53;
172,7 → 175,7
 
assign reg_sel_ix = SYNTHESIZED_WIRE_56 & use_ix;
 
assign SYNTHESIZED_WIRE_37 = ctl_reg_ex_de_hl & SYNTHESIZED_WIRE_53;
assign SYNTHESIZED_WIRE_50 = ctl_reg_ex_de_hl & SYNTHESIZED_WIRE_53;
 
assign reg_sel_iy = SYNTHESIZED_WIRE_56 & SYNTHESIZED_WIRE_10;
 
180,15 → 183,15
 
assign SYNTHESIZED_WIRE_2 = ~bank_af;
 
assign SYNTHESIZED_WIRE_48 = SYNTHESIZED_WIRE_57 & SYNTHESIZED_WIRE_58;
assign SYNTHESIZED_WIRE_47 = SYNTHESIZED_WIRE_57 & SYNTHESIZED_WIRE_58;
 
assign SYNTHESIZED_WIRE_47 = bank_hl_de2 & SYNTHESIZED_WIRE_59;
assign SYNTHESIZED_WIRE_46 = bank_hl_de2 & SYNTHESIZED_WIRE_59;
 
assign SYNTHESIZED_WIRE_41 = SYNTHESIZED_WIRE_60 & SYNTHESIZED_WIRE_58;
assign SYNTHESIZED_WIRE_39 = SYNTHESIZED_WIRE_60 & SYNTHESIZED_WIRE_58;
 
assign SYNTHESIZED_WIRE_50 = bank_hl_de2 & SYNTHESIZED_WIRE_58;
assign SYNTHESIZED_WIRE_49 = bank_hl_de2 & SYNTHESIZED_WIRE_58;
 
assign SYNTHESIZED_WIRE_49 = SYNTHESIZED_WIRE_57 & SYNTHESIZED_WIRE_59;
assign SYNTHESIZED_WIRE_48 = SYNTHESIZED_WIRE_57 & SYNTHESIZED_WIRE_59;
 
assign reg_sel_de = SYNTHESIZED_WIRE_53 & SYNTHESIZED_WIRE_21;
 
198,13 → 201,13
 
assign reg_sel_hl2 = bank_exx & SYNTHESIZED_WIRE_25;
 
assign SYNTHESIZED_WIRE_40 = bank_hl_de1 & SYNTHESIZED_WIRE_59;
assign SYNTHESIZED_WIRE_38 = bank_hl_de1 & SYNTHESIZED_WIRE_59;
 
assign SYNTHESIZED_WIRE_53 = ~bank_exx;
 
assign SYNTHESIZED_WIRE_46 = bank_hl_de1 & SYNTHESIZED_WIRE_58;
assign SYNTHESIZED_WIRE_45 = bank_hl_de1 & SYNTHESIZED_WIRE_58;
 
assign SYNTHESIZED_WIRE_45 = SYNTHESIZED_WIRE_60 & SYNTHESIZED_WIRE_59;
assign SYNTHESIZED_WIRE_44 = SYNTHESIZED_WIRE_60 & SYNTHESIZED_WIRE_59;
 
assign SYNTHESIZED_WIRE_52 = SYNTHESIZED_WIRE_30 & SYNTHESIZED_WIRE_31;
 
224,34 → 227,45
 
assign SYNTHESIZED_WIRE_56 = SYNTHESIZED_WIRE_61 & use_ixiy;
 
assign SYNTHESIZED_WIRE_44 = ~ctl_reg_gp_sel[0];
assign SYNTHESIZED_WIRE_42 = ~ctl_reg_gp_sel[0];
 
assign SYNTHESIZED_WIRE_39 = ctl_reg_ex_de_hl & bank_exx;
assign SYNTHESIZED_WIRE_43 = ctl_reg_ex_de_hl & bank_exx;
 
assign SYNTHESIZED_WIRE_34 = ~use_ixiy;
 
assign SYNTHESIZED_WIRE_59 = ctl_reg_gp_sel[0] & SYNTHESIZED_WIRE_36;
 
assign SYNTHESIZED_WIRE_10 = ~use_ix;
 
assign SYNTHESIZED_WIRE_57 = ~bank_hl_de2;
 
assign SYNTHESIZED_WIRE_43 = ~reg_sys_we_lo_ALTERA_SYNTHESIZED;
 
 
always@(posedge clk or negedge nreset)
begin
if (!nreset)
begin
bank_hl_de1 <= 0;
bank_af <= 0;
end
else
bank_hl_de1 <= bank_hl_de1 ^ SYNTHESIZED_WIRE_37;
if (n_hold_clk_wait)
begin
bank_af <= bank_af ^ ctl_reg_ex_af;
end
end
 
assign SYNTHESIZED_WIRE_42 = ~SYNTHESIZED_WIRE_38;
assign SYNTHESIZED_WIRE_10 = ~use_ix;
 
assign SYNTHESIZED_WIRE_57 = ~bank_hl_de2;
 
assign SYNTHESIZED_WIRE_41 = ~reg_sys_we_lo_ALTERA_SYNTHESIZED;
 
assign SYNTHESIZED_WIRE_40 = ~SYNTHESIZED_WIRE_37;
 
assign SYNTHESIZED_WIRE_23 = SYNTHESIZED_WIRE_38 | SYNTHESIZED_WIRE_39;
 
assign reg_sw_4d_hi = ctl_sw_4d & SYNTHESIZED_WIRE_40;
 
assign SYNTHESIZED_WIRE_37 = ctl_reg_sys_hilo[1] & SYNTHESIZED_WIRE_41 & ctl_reg_sel_ir;
 
assign SYNTHESIZED_WIRE_61 = SYNTHESIZED_WIRE_42 & ctl_reg_gp_sel[1];
 
 
always@(posedge clk or negedge nreset)
begin
if (!nreset)
259,53 → 273,56
bank_hl_de2 <= 0;
end
else
bank_hl_de2 <= bank_hl_de2 ^ SYNTHESIZED_WIRE_39;
if (n_hold_clk_wait)
begin
bank_hl_de2 <= bank_hl_de2 ^ SYNTHESIZED_WIRE_43;
end
end
 
assign SYNTHESIZED_WIRE_23 = SYNTHESIZED_WIRE_40 | SYNTHESIZED_WIRE_41;
assign SYNTHESIZED_WIRE_21 = SYNTHESIZED_WIRE_44 | SYNTHESIZED_WIRE_45;
 
assign reg_sw_4d_hi = ctl_sw_4d & SYNTHESIZED_WIRE_42;
assign SYNTHESIZED_WIRE_25 = SYNTHESIZED_WIRE_46 | SYNTHESIZED_WIRE_47;
 
assign SYNTHESIZED_WIRE_38 = ctl_reg_sys_hilo[1] & SYNTHESIZED_WIRE_43 & ctl_reg_sel_ir;
assign SYNTHESIZED_WIRE_24 = SYNTHESIZED_WIRE_48 | SYNTHESIZED_WIRE_49;
 
assign SYNTHESIZED_WIRE_61 = SYNTHESIZED_WIRE_44 & ctl_reg_gp_sel[1];
 
assign SYNTHESIZED_WIRE_21 = SYNTHESIZED_WIRE_45 | SYNTHESIZED_WIRE_46;
 
assign SYNTHESIZED_WIRE_25 = SYNTHESIZED_WIRE_47 | SYNTHESIZED_WIRE_48;
 
assign SYNTHESIZED_WIRE_24 = SYNTHESIZED_WIRE_49 | SYNTHESIZED_WIRE_50;
 
assign SYNTHESIZED_WIRE_55 = ctl_reg_gp_sel[0] & ctl_reg_gp_sel[1];
 
assign SYNTHESIZED_WIRE_30 = ~ctl_reg_gp_sel[0];
 
assign SYNTHESIZED_WIRE_31 = ~ctl_reg_gp_sel[1];
 
 
always@(posedge clk or negedge nreset)
begin
if (!nreset)
begin
bank_exx <= 0;
bank_hl_de1 <= 0;
end
else
bank_exx <= bank_exx ^ ctl_reg_exx;
if (n_hold_clk_wait)
begin
bank_hl_de1 <= bank_hl_de1 ^ SYNTHESIZED_WIRE_50;
end
end
 
assign reg_sel_bc2 = SYNTHESIZED_WIRE_52 & bank_exx;
 
 
always@(posedge clk or negedge nreset)
begin
if (!nreset)
begin
bank_af <= 0;
bank_exx <= 0;
end
else
bank_af <= bank_af ^ ctl_reg_ex_af;
if (n_hold_clk_wait)
begin
bank_exx <= bank_exx ^ ctl_reg_exx;
end
end
 
assign SYNTHESIZED_WIRE_55 = ctl_reg_gp_sel[0] & ctl_reg_gp_sel[1];
 
assign SYNTHESIZED_WIRE_30 = ~ctl_reg_gp_sel[0];
 
assign SYNTHESIZED_WIRE_31 = ~ctl_reg_gp_sel[1];
 
assign n_hold_clk_wait = ~hold_clk_wait;
 
assign reg_sel_bc2 = SYNTHESIZED_WIRE_52 & bank_exx;
 
assign reg_sys_we_lo = reg_sys_we_lo_ALTERA_SYNTHESIZED;
 
endmodule
/trunk/cpu/registers/test_registers.sv
49,6 → 49,7
logic ctl_reg_sys_we_sig=0; // Write to system register
logic use_ixiy_sig=0; // Use IX or IY
logic use_ix_sig=0; // Use IX and not IY
logic hold_clk_wait_sig=0; // Hold all transitions
 
logic ctl_reg_exx_sig=0; // Exchange register banks
logic ctl_reg_ex_af_sig=0; // Exchange AF banks
182,6 → 183,7
.ctl_reg_sys_we(ctl_reg_sys_we_sig) , // input ctl_reg_sys_we_sig
.clk(clk) , // input clk
.ctl_sw_4d (ctl_sw_4d_sig) , // input ctl_sw_4d
.hold_clk_wait(hold_clk_wait_sig) , // input hold_clk_wait_sig
.reg_sel_bc(reg_sel_bc_sig) , // output reg_sel_bc_sig
.reg_sel_bc2(reg_sel_bc2_sig) , // output reg_sel_bc2_sig
.reg_sel_ix(reg_sel_ix_sig) , // output reg_sel_ix_sig
/trunk/cpu/top-level-files.txt
1,6 → 1,9
This is a list of A-Z80 top-level files and their dependencies.
These files comprise the A-Z80 CPU proper. Use export.py to copy
them into your project folder.
# This is a list of A-Z80 top-level files and their dependencies.
# These files comprise the A-Z80 CPU proper. Use export.py to copy
# them into your project folder.
#
# Note for the users of Lattice FPGA toolset: instead of data_pins.v
# manually copy and use data_pins_lattice.v file instead.
 
------ Control block -------
control/clk_delay.v
/trunk/cpu/toplevel/coremodules.vh
23,7 → 23,6
.ctl_state_ixiy_clr (ctl_state_ixiy_clr),
.ctl_state_ixiy_we (ctl_state_ixiy_we),
.ctl_state_halt_set (ctl_state_halt_set),
.ctl_state_tbl_clr (ctl_state_tbl_clr),
.ctl_state_tbl_ed_set (ctl_state_tbl_ed_set),
.ctl_state_tbl_cb_set (ctl_state_tbl_cb_set),
.ctl_state_alu (ctl_state_alu),
33,6 → 32,8
.in_intr (in_intr),
.in_nmi (in_nmi),
.nreset (nreset),
.ctl_state_tbl_we (ctl_state_tbl_we),
.hold_clk_wait (hold_clk_wait),
.in_halt (in_halt),
.table_cb (table_cb),
.table_ed (table_ed),
48,11 → 49,11
.ctl_state_ixiy_clr (ctl_state_ixiy_clr),
.ctl_state_ixiy_we (ctl_state_ixiy_we),
.ctl_state_halt_set (ctl_state_halt_set),
.ctl_state_tbl_clr (ctl_state_tbl_clr),
.ctl_state_tbl_ed_set (ctl_state_tbl_ed_set),
.ctl_state_tbl_cb_set (ctl_state_tbl_cb_set),
.ctl_state_alu (ctl_state_alu),
.ctl_repeat_we (ctl_repeat_we),
.ctl_state_tbl_we (ctl_state_tbl_we),
.ctl_iff1_iff2 (ctl_iff1_iff2),
.ctl_iffx_we (ctl_iffx_we),
.ctl_iffx_bit (ctl_iffx_bit),
200,6 → 201,7
.ctl_ir_we (ctl_ir_we),
.clk (clk),
.nreset (nreset),
.hold_clk_wait (hold_clk_wait),
.db (db0[7:0]),
.opcode (opcode)
);
231,6 → 233,7
.M1 (M1),
.T2 (T2),
.fpga_reset (fpga_reset),
.hold_clk_wait (hold_clk_wait),
.clrpc (clrpc),
.nreset (nreset)
);
255,7 → 258,8
.nRD_out (nRD_out),
.nWR_out (nWR_out),
.nIORQ_out (nIORQ_out),
.latch_wait (latch_wait)
.latch_wait (latch_wait),
.wait_m1 (wait_m1)
);
 
sequencer sequencer_(
495,6 → 499,7
.ctl_reg_sys_we (ctl_reg_sys_we),
.clk (clk),
.ctl_sw_4d (ctl_sw_4d),
.hold_clk_wait (hold_clk_wait),
.ctl_reg_gp_hilo (ctl_reg_gp_hilo),
.ctl_reg_gp_sel (ctl_reg_gp_sel),
.ctl_reg_sys_hilo (ctl_reg_sys_hilo),
/trunk/cpu/toplevel/genfuse.py
19,8 → 19,12
# run_tests = -1
# regress = 0
#
# Orthogonal to that, set m1wait to a non-zero value to test nWAIT insertion at
# the first M1 cycle of an instruction. Change it to the number of T-clocks to
# insert.
#
#-------------------------------------------------------------------------------
# Copyright (C) 2014 Goran Devic
# Copyright (C) 2016 Goran Devic
#
# This program is free software; you can redistribute it and/or modify it
# under the terms of the GNU General Public License as published by the Free
40,10 → 44,13
# Number of tests to run; use -1 to run all tests
run_tests = 1
 
# Set this to 1 to use regression test files instead of 'tests.*'
# It will run all regression tests (start_test, run_tests are ignored)
# Set this to 1 to use regression test instead of selected or full 'tests.*'
# Regression test is a shorter set of tests and ignores start_test and run_tests values
regress = 1
 
# Set this to a number of WAIT cycles to add at M1 clock period or 0 not to test nWAIT
m1wait = 0
 
#------------------------------------------------------------------------------
# Determine which test files to use
tests_in = 'fuse/tests.in'
100,12 → 107,11
ftest.write("force dut.reg_file_.reg_gp_we=0;\n")
ftest.write("force dut.reg_control_.ctl_reg_sys_we=0;\n")
ftest.write("force dut.z80_top_ifc_n.fpga_reset=1;\n")
ftest.write("#2\n")
ftest.write("#2 // Start test loop\n\n")
total_clks = total_clks + 2
 
# Read each test from the testdat.in file
while True:
ftest.write("//" + "-" * 80 + "\n")
if len(t1)==0 or run_tests==0:
break
run_tests = run_tests-1
122,7 → 128,7
# AF BC DE HL AF' BC' DE' HL' IX IY SP PC
# I R IFF1 IFF2 IM <halted> <tstates>
name = t1.pop(0)
ftest.write("$fdisplay(f,\"Testing opcode " + name + "\");\n")
ftest.write(" $fdisplay(f,\"Testing opcode " + name + "\");\n")
name = name.split(" ")[0]
r = t1.pop(0).split(' ')
r = list(filter(None, r))
190,9 → 196,9
ftest.write(" force dut.address_latch_.Q=16'h" + r[11] +";\n") # Force PC into the address latch
ftest.write(" release dut.reg_control_.ctl_reg_sys_we;\n")
ftest.write(" release dut.reg_file_.reg_gp_we;\n")
ftest.write("#3\n") # 1T (#2) overlaps the reset cycle
total_clks = total_clks + 3 # We borrow 1T (#2) to to force the PC to be what our test wants...
ftest.write(" release dut.address_latch_.Q;\n")
ftest.write("#2 // Execute: M1/T1 start\n") # 1T (#2) overlaps the reset cycle
ftest.write("#1 release dut.address_latch_.Q;\n")
total_clks = total_clks + 3 # We borrow 1T (#2) to to force the PC to be what our test wants...
ftest.write("#1\n")
total_clks = total_clks + 1
 
215,8 → 221,15
 
ticks = int(s[6]) * 2 - 2 # We return 1T (#2) that we borrowed to set PC
total_clks = total_clks + ticks
ftest.write("#" + str(ticks) + " // Execute\n")
 
# Test WAIT state insertion at the M1 clock cycle
if m1wait:
ftest.write(" z.nWAIT <= 0;\n")
ftest.write("#" + str(m1wait * 2) + " z.nWAIT <= 1; // nWAIT during M1\n")
total_clks = total_clks + m1wait * 2
 
ftest.write("#" + str(ticks) + " // Wait for opcode end\n")
 
ftest.write(" force dut.reg_control_.ctl_reg_sys_we=0;\n")
ftest.write("#2 pc=z.A;\n") # Extra 2T for the next instruction overlap & read PC on the ABus
ftest.write("#2\n") # Complete this instruction
278,10 → 291,13
# Read a list of IO checks that was compiled while parsing the initial condition
while len(check_io)>0:
ftest.write(check_io.pop(0))
ftest.write("#1 // End opcode\n\n")
total_clks = total_clks + 1
 
# Write out the total number of clocks that this set of tests takes to execute
ftest.write("`define TOTAL_CLKS " + str(total_clks) + "\n")
ftest.write("$fdisplay(f,\"=== Tests completed ===\");\n")
ftest.close()
 
# Touch a file that includes 'test_fuse.vh' to ensure it will recompile correctly
os.utime("test_fuse.sv", None)
/trunk/cpu/toplevel/globals.vh
23,11 → 23,11
wire ctl_state_ixiy_clr;
wire ctl_state_ixiy_we;
wire ctl_state_halt_set;
wire ctl_state_tbl_clr;
wire ctl_state_tbl_ed_set;
wire ctl_state_tbl_cb_set;
wire ctl_state_alu;
wire ctl_repeat_we;
wire ctl_state_tbl_we;
wire ctl_iff1_iff2;
wire ctl_iffx_we;
wire ctl_iffx_bit;
159,6 → 159,7
wire nWR_out;
wire nIORQ_out;
wire latch_wait;
wire wait_m1;
 
// Module: control/sequencer.v
wire M1;
/trunk/cpu/toplevel/simulation/modelsim/wave_fuse.do
386,7 → 386,7
add wave -noupdate -group state /test_fuse/dut/decode_state_/ctl_state_ixiy_clr
add wave -noupdate -group state /test_fuse/dut/decode_state_/ctl_state_ixiy_we
add wave -noupdate -group state /test_fuse/dut/decode_state_/ctl_state_halt_set
add wave -noupdate -group state /test_fuse/dut/decode_state_/ctl_state_tbl_clr
add wave -noupdate -group state /test_fuse/dut/decode_state_/ctl_state_tbl_we
add wave -noupdate -group state /test_fuse/dut/decode_state_/ctl_state_tbl_ed_set
add wave -noupdate -group state /test_fuse/dut/decode_state_/ctl_state_tbl_cb_set
add wave -noupdate -group state /test_fuse/dut/decode_state_/ctl_state_alu
/trunk/cpu/toplevel/simulation/modelsim/wave_top.do
386,7 → 386,7
add wave -noupdate -group state /test_top/dut/decode_state_/ctl_state_ixiy_clr
add wave -noupdate -group state /test_top/dut/decode_state_/ctl_state_ixiy_we
add wave -noupdate -group state /test_top/dut/decode_state_/ctl_state_halt_set
add wave -noupdate -group state /test_top/dut/decode_state_/ctl_state_tbl_clr
add wave -noupdate -group state /test_top/dut/decode_state_/ctl_state_tbl_we
add wave -noupdate -group state /test_top/dut/decode_state_/ctl_state_tbl_ed_set
add wave -noupdate -group state /test_top/dut/decode_state_/ctl_state_tbl_cb_set
add wave -noupdate -group state /test_top/dut/decode_state_/ctl_state_alu
/trunk/cpu/toplevel/test_fuse.vh
4,13 → 4,13
force dut.reg_file_.reg_gp_we=0;
force dut.reg_control_.ctl_reg_sys_we=0;
force dut.z80_top_ifc_n.fpga_reset=1;
#2
//--------------------------------------------------------------------------------
#2 // Start test loop
 
force dut.ir_.ctl_ir_we=1;
force dut.ir_.db=0;
#2 release dut.ir_.ctl_ir_we;
release dut.ir_.db;
$fdisplay(f,"Testing opcode 00 NOP");
$fdisplay(f,"Testing opcode 00 NOP");
// Preset af
force dut.reg_file_.b2v_latch_af_lo.we=1;
force dut.reg_file_.b2v_latch_af_hi.we=1;
143,10 → 143,10
force dut.address_latch_.Q=16'h0000;
release dut.reg_control_.ctl_reg_sys_we;
release dut.reg_file_.reg_gp_we;
#3
release dut.address_latch_.Q;
#2 // Execute: M1/T1 start
#1 release dut.address_latch_.Q;
#1
#6 // Execute
#6 // Wait for opcode end
force dut.reg_control_.ctl_reg_sys_we=0;
#2 pc=z.A;
#2
177,12 → 177,13
if (pc!==16'h0001) $fdisplay(f,"* PC=%h !=0001",pc);
if (dut.reg_file_.b2v_latch_ir_lo.latch!==8'h01) $fdisplay(f,"* Reg ir r=%h !=01",dut.reg_file_.b2v_latch_ir_lo.latch);
if (dut.reg_file_.b2v_latch_ir_hi.latch!==8'h00) $fdisplay(f,"* Reg ir i=%h !=00",dut.reg_file_.b2v_latch_ir_hi.latch);
//--------------------------------------------------------------------------------
#1 // End opcode
 
force dut.ir_.ctl_ir_we=1;
force dut.ir_.db=0;
#2 release dut.ir_.ctl_ir_we;
release dut.ir_.db;
$fdisplay(f,"Testing opcode ed67 RRD");
$fdisplay(f,"Testing opcode ed67 RRD");
// Preset af
force dut.reg_file_.b2v_latch_af_lo.we=1;
force dut.reg_file_.b2v_latch_af_hi.we=1;
318,10 → 319,10
force dut.address_latch_.Q=16'h0000;
release dut.reg_control_.ctl_reg_sys_we;
release dut.reg_file_.reg_gp_we;
#3
release dut.address_latch_.Q;
#2 // Execute: M1/T1 start
#1 release dut.address_latch_.Q;
#1
#34 // Execute
#34 // Wait for opcode end
force dut.reg_control_.ctl_reg_sys_we=0;
#2 pc=z.A;
#2
353,12 → 354,13
if (dut.reg_file_.b2v_latch_ir_lo.latch!==8'h02) $fdisplay(f,"* Reg ir r=%h !=02",dut.reg_file_.b2v_latch_ir_lo.latch);
if (dut.reg_file_.b2v_latch_ir_hi.latch!==8'h00) $fdisplay(f,"* Reg ir i=%h !=00",dut.reg_file_.b2v_latch_ir_hi.latch);
if (ram.Mem[47582]!==8'h69) $fdisplay(f,"* Mem[b9de]=%h !=69",ram.Mem[47582]);
//--------------------------------------------------------------------------------
#1 // End opcode
 
force dut.ir_.ctl_ir_we=1;
force dut.ir_.db=0;
#2 release dut.ir_.ctl_ir_we;
release dut.ir_.db;
$fdisplay(f,"Testing opcode ed6f RLD");
$fdisplay(f,"Testing opcode ed6f RLD");
// Preset af
force dut.reg_file_.b2v_latch_af_lo.we=1;
force dut.reg_file_.b2v_latch_af_hi.we=1;
494,10 → 496,10
force dut.address_latch_.Q=16'h0000;
release dut.reg_control_.ctl_reg_sys_we;
release dut.reg_file_.reg_gp_we;
#3
release dut.address_latch_.Q;
#2 // Execute: M1/T1 start
#1 release dut.address_latch_.Q;
#1
#34 // Execute
#34 // Wait for opcode end
force dut.reg_control_.ctl_reg_sys_we=0;
#2 pc=z.A;
#2
529,12 → 531,13
if (dut.reg_file_.b2v_latch_ir_lo.latch!==8'h02) $fdisplay(f,"* Reg ir r=%h !=02",dut.reg_file_.b2v_latch_ir_lo.latch);
if (dut.reg_file_.b2v_latch_ir_hi.latch!==8'h00) $fdisplay(f,"* Reg ir i=%h !=00",dut.reg_file_.b2v_latch_ir_hi.latch);
if (ram.Mem[16444]!==8'h45) $fdisplay(f,"* Mem[403c]=%h !=45",ram.Mem[16444]);
//--------------------------------------------------------------------------------
#1 // End opcode
 
force dut.ir_.ctl_ir_we=1;
force dut.ir_.db=0;
#2 release dut.ir_.ctl_ir_we;
release dut.ir_.db;
$fdisplay(f,"Testing opcode 81 ADD A,C");
$fdisplay(f,"Testing opcode 81 ADD A,C");
// Preset af
force dut.reg_file_.b2v_latch_af_lo.we=1;
force dut.reg_file_.b2v_latch_af_hi.we=1;
669,10 → 672,10
force dut.address_latch_.Q=16'h0000;
release dut.reg_control_.ctl_reg_sys_we;
release dut.reg_file_.reg_gp_we;
#3
release dut.address_latch_.Q;
#2 // Execute: M1/T1 start
#1 release dut.address_latch_.Q;
#1
#6 // Execute
#6 // Wait for opcode end
force dut.reg_control_.ctl_reg_sys_we=0;
#2 pc=z.A;
#2
703,12 → 706,13
if (pc!==16'h0001) $fdisplay(f,"* PC=%h !=0001",pc);
if (dut.reg_file_.b2v_latch_ir_lo.latch!==8'h01) $fdisplay(f,"* Reg ir r=%h !=01",dut.reg_file_.b2v_latch_ir_lo.latch);
if (dut.reg_file_.b2v_latch_ir_hi.latch!==8'h00) $fdisplay(f,"* Reg ir i=%h !=00",dut.reg_file_.b2v_latch_ir_hi.latch);
//--------------------------------------------------------------------------------
#1 // End opcode
 
force dut.ir_.ctl_ir_we=1;
force dut.ir_.db=0;
#2 release dut.ir_.ctl_ir_we;
release dut.ir_.db;
$fdisplay(f,"Testing opcode cb41 BIT 0,C");
$fdisplay(f,"Testing opcode cb41 BIT 0,C");
// Preset af
force dut.reg_file_.b2v_latch_af_lo.we=1;
force dut.reg_file_.b2v_latch_af_hi.we=1;
844,10 → 848,10
force dut.address_latch_.Q=16'h0000;
release dut.reg_control_.ctl_reg_sys_we;
release dut.reg_file_.reg_gp_we;
#3
release dut.address_latch_.Q;
#2 // Execute: M1/T1 start
#1 release dut.address_latch_.Q;
#1
#14 // Execute
#14 // Wait for opcode end
force dut.reg_control_.ctl_reg_sys_we=0;
#2 pc=z.A;
#2
878,12 → 882,13
if (pc!==16'h0002) $fdisplay(f,"* PC=%h !=0002",pc);
if (dut.reg_file_.b2v_latch_ir_lo.latch!==8'h02) $fdisplay(f,"* Reg ir r=%h !=02",dut.reg_file_.b2v_latch_ir_lo.latch);
if (dut.reg_file_.b2v_latch_ir_hi.latch!==8'h00) $fdisplay(f,"* Reg ir i=%h !=00",dut.reg_file_.b2v_latch_ir_hi.latch);
//--------------------------------------------------------------------------------
#1 // End opcode
 
force dut.ir_.ctl_ir_we=1;
force dut.ir_.db=0;
#2 release dut.ir_.ctl_ir_we;
release dut.ir_.db;
$fdisplay(f,"Testing opcode cb93 RES 2,E");
$fdisplay(f,"Testing opcode cb93 RES 2,E");
// Preset af
force dut.reg_file_.b2v_latch_af_lo.we=1;
force dut.reg_file_.b2v_latch_af_hi.we=1;
1019,10 → 1024,10
force dut.address_latch_.Q=16'h0000;
release dut.reg_control_.ctl_reg_sys_we;
release dut.reg_file_.reg_gp_we;
#3
release dut.address_latch_.Q;
#2 // Execute: M1/T1 start
#1 release dut.address_latch_.Q;
#1
#14 // Execute
#14 // Wait for opcode end
force dut.reg_control_.ctl_reg_sys_we=0;
#2 pc=z.A;
#2
1053,12 → 1058,13
if (pc!==16'h0002) $fdisplay(f,"* PC=%h !=0002",pc);
if (dut.reg_file_.b2v_latch_ir_lo.latch!==8'h02) $fdisplay(f,"* Reg ir r=%h !=02",dut.reg_file_.b2v_latch_ir_lo.latch);
if (dut.reg_file_.b2v_latch_ir_hi.latch!==8'h00) $fdisplay(f,"* Reg ir i=%h !=00",dut.reg_file_.b2v_latch_ir_hi.latch);
//--------------------------------------------------------------------------------
#1 // End opcode
 
force dut.ir_.ctl_ir_we=1;
force dut.ir_.db=0;
#2 release dut.ir_.ctl_ir_we;
release dut.ir_.db;
$fdisplay(f,"Testing opcode cbe5 SET 4,L");
$fdisplay(f,"Testing opcode cbe5 SET 4,L");
// Preset af
force dut.reg_file_.b2v_latch_af_lo.we=1;
force dut.reg_file_.b2v_latch_af_hi.we=1;
1194,10 → 1200,10
force dut.address_latch_.Q=16'h0000;
release dut.reg_control_.ctl_reg_sys_we;
release dut.reg_file_.reg_gp_we;
#3
release dut.address_latch_.Q;
#2 // Execute: M1/T1 start
#1 release dut.address_latch_.Q;
#1
#14 // Execute
#14 // Wait for opcode end
force dut.reg_control_.ctl_reg_sys_we=0;
#2 pc=z.A;
#2
1228,12 → 1234,13
if (pc!==16'h0002) $fdisplay(f,"* PC=%h !=0002",pc);
if (dut.reg_file_.b2v_latch_ir_lo.latch!==8'h02) $fdisplay(f,"* Reg ir r=%h !=02",dut.reg_file_.b2v_latch_ir_lo.latch);
if (dut.reg_file_.b2v_latch_ir_hi.latch!==8'h00) $fdisplay(f,"* Reg ir i=%h !=00",dut.reg_file_.b2v_latch_ir_hi.latch);
//--------------------------------------------------------------------------------
#1 // End opcode
 
force dut.ir_.ctl_ir_we=1;
force dut.ir_.db=0;
#2 release dut.ir_.ctl_ir_we;
release dut.ir_.db;
$fdisplay(f,"Testing opcode 8c ADC A,H");
$fdisplay(f,"Testing opcode 8c ADC A,H");
// Preset af
force dut.reg_file_.b2v_latch_af_lo.we=1;
force dut.reg_file_.b2v_latch_af_hi.we=1;
1368,10 → 1375,10
force dut.address_latch_.Q=16'h0000;
release dut.reg_control_.ctl_reg_sys_we;
release dut.reg_file_.reg_gp_we;
#3
release dut.address_latch_.Q;
#2 // Execute: M1/T1 start
#1 release dut.address_latch_.Q;
#1
#6 // Execute
#6 // Wait for opcode end
force dut.reg_control_.ctl_reg_sys_we=0;
#2 pc=z.A;
#2
1402,12 → 1409,13
if (pc!==16'h0001) $fdisplay(f,"* PC=%h !=0001",pc);
if (dut.reg_file_.b2v_latch_ir_lo.latch!==8'h01) $fdisplay(f,"* Reg ir r=%h !=01",dut.reg_file_.b2v_latch_ir_lo.latch);
if (dut.reg_file_.b2v_latch_ir_hi.latch!==8'h00) $fdisplay(f,"* Reg ir i=%h !=00",dut.reg_file_.b2v_latch_ir_hi.latch);
//--------------------------------------------------------------------------------
#1 // End opcode
 
force dut.ir_.ctl_ir_we=1;
force dut.ir_.db=0;
#2 release dut.ir_.ctl_ir_we;
release dut.ir_.db;
$fdisplay(f,"Testing opcode 92 SUB D");
$fdisplay(f,"Testing opcode 92 SUB D");
// Preset af
force dut.reg_file_.b2v_latch_af_lo.we=1;
force dut.reg_file_.b2v_latch_af_hi.we=1;
1542,10 → 1550,10
force dut.address_latch_.Q=16'h0000;
release dut.reg_control_.ctl_reg_sys_we;
release dut.reg_file_.reg_gp_we;
#3
release dut.address_latch_.Q;
#2 // Execute: M1/T1 start
#1 release dut.address_latch_.Q;
#1
#6 // Execute
#6 // Wait for opcode end
force dut.reg_control_.ctl_reg_sys_we=0;
#2 pc=z.A;
#2
1576,12 → 1584,13
if (pc!==16'h0001) $fdisplay(f,"* PC=%h !=0001",pc);
if (dut.reg_file_.b2v_latch_ir_lo.latch!==8'h01) $fdisplay(f,"* Reg ir r=%h !=01",dut.reg_file_.b2v_latch_ir_lo.latch);
if (dut.reg_file_.b2v_latch_ir_hi.latch!==8'h00) $fdisplay(f,"* Reg ir i=%h !=00",dut.reg_file_.b2v_latch_ir_hi.latch);
//--------------------------------------------------------------------------------
#1 // End opcode
 
force dut.ir_.ctl_ir_we=1;
force dut.ir_.db=0;
#2 release dut.ir_.ctl_ir_we;
release dut.ir_.db;
$fdisplay(f,"Testing opcode 9d SBC A,L");
$fdisplay(f,"Testing opcode 9d SBC A,L");
// Preset af
force dut.reg_file_.b2v_latch_af_lo.we=1;
force dut.reg_file_.b2v_latch_af_hi.we=1;
1716,10 → 1725,10
force dut.address_latch_.Q=16'h0000;
release dut.reg_control_.ctl_reg_sys_we;
release dut.reg_file_.reg_gp_we;
#3
release dut.address_latch_.Q;
#2 // Execute: M1/T1 start
#1 release dut.address_latch_.Q;
#1
#6 // Execute
#6 // Wait for opcode end
force dut.reg_control_.ctl_reg_sys_we=0;
#2 pc=z.A;
#2
1750,12 → 1759,13
if (pc!==16'h0001) $fdisplay(f,"* PC=%h !=0001",pc);
if (dut.reg_file_.b2v_latch_ir_lo.latch!==8'h01) $fdisplay(f,"* Reg ir r=%h !=01",dut.reg_file_.b2v_latch_ir_lo.latch);
if (dut.reg_file_.b2v_latch_ir_hi.latch!==8'h00) $fdisplay(f,"* Reg ir i=%h !=00",dut.reg_file_.b2v_latch_ir_hi.latch);
//--------------------------------------------------------------------------------
#1 // End opcode
 
force dut.ir_.ctl_ir_we=1;
force dut.ir_.db=0;
#2 release dut.ir_.ctl_ir_we;
release dut.ir_.db;
$fdisplay(f,"Testing opcode a3 AND E");
$fdisplay(f,"Testing opcode a3 AND E");
// Preset af
force dut.reg_file_.b2v_latch_af_lo.we=1;
force dut.reg_file_.b2v_latch_af_hi.we=1;
1890,10 → 1900,10
force dut.address_latch_.Q=16'h0000;
release dut.reg_control_.ctl_reg_sys_we;
release dut.reg_file_.reg_gp_we;
#3
release dut.address_latch_.Q;
#2 // Execute: M1/T1 start
#1 release dut.address_latch_.Q;
#1
#6 // Execute
#6 // Wait for opcode end
force dut.reg_control_.ctl_reg_sys_we=0;
#2 pc=z.A;
#2
1924,12 → 1934,13
if (pc!==16'h0001) $fdisplay(f,"* PC=%h !=0001",pc);
if (dut.reg_file_.b2v_latch_ir_lo.latch!==8'h01) $fdisplay(f,"* Reg ir r=%h !=01",dut.reg_file_.b2v_latch_ir_lo.latch);
if (dut.reg_file_.b2v_latch_ir_hi.latch!==8'h00) $fdisplay(f,"* Reg ir i=%h !=00",dut.reg_file_.b2v_latch_ir_hi.latch);
//--------------------------------------------------------------------------------
#1 // End opcode
 
force dut.ir_.ctl_ir_we=1;
force dut.ir_.db=0;
#2 release dut.ir_.ctl_ir_we;
release dut.ir_.db;
$fdisplay(f,"Testing opcode ae XOR (HL)");
$fdisplay(f,"Testing opcode ae XOR (HL)");
// Preset af
force dut.reg_file_.b2v_latch_af_lo.we=1;
force dut.reg_file_.b2v_latch_af_hi.we=1;
2064,10 → 2075,10
force dut.address_latch_.Q=16'h0000;
release dut.reg_control_.ctl_reg_sys_we;
release dut.reg_file_.reg_gp_we;
#3
release dut.address_latch_.Q;
#2 // Execute: M1/T1 start
#1 release dut.address_latch_.Q;
#1
#12 // Execute
#12 // Wait for opcode end
force dut.reg_control_.ctl_reg_sys_we=0;
#2 pc=z.A;
#2
2098,12 → 2109,13
if (pc!==16'h0001) $fdisplay(f,"* PC=%h !=0001",pc);
if (dut.reg_file_.b2v_latch_ir_lo.latch!==8'h01) $fdisplay(f,"* Reg ir r=%h !=01",dut.reg_file_.b2v_latch_ir_lo.latch);
if (dut.reg_file_.b2v_latch_ir_hi.latch!==8'h00) $fdisplay(f,"* Reg ir i=%h !=00",dut.reg_file_.b2v_latch_ir_hi.latch);
//--------------------------------------------------------------------------------
#1 // End opcode
 
force dut.ir_.ctl_ir_we=1;
force dut.ir_.db=0;
#2 release dut.ir_.ctl_ir_we;
release dut.ir_.db;
$fdisplay(f,"Testing opcode b4 OR H");
$fdisplay(f,"Testing opcode b4 OR H");
// Preset af
force dut.reg_file_.b2v_latch_af_lo.we=1;
force dut.reg_file_.b2v_latch_af_hi.we=1;
2238,10 → 2250,10
force dut.address_latch_.Q=16'h0000;
release dut.reg_control_.ctl_reg_sys_we;
release dut.reg_file_.reg_gp_we;
#3
release dut.address_latch_.Q;
#2 // Execute: M1/T1 start
#1 release dut.address_latch_.Q;
#1
#6 // Execute
#6 // Wait for opcode end
force dut.reg_control_.ctl_reg_sys_we=0;
#2 pc=z.A;
#2
2272,12 → 2284,13
if (pc!==16'h0001) $fdisplay(f,"* PC=%h !=0001",pc);
if (dut.reg_file_.b2v_latch_ir_lo.latch!==8'h01) $fdisplay(f,"* Reg ir r=%h !=01",dut.reg_file_.b2v_latch_ir_lo.latch);
if (dut.reg_file_.b2v_latch_ir_hi.latch!==8'h00) $fdisplay(f,"* Reg ir i=%h !=00",dut.reg_file_.b2v_latch_ir_hi.latch);
//--------------------------------------------------------------------------------
#1 // End opcode
 
force dut.ir_.ctl_ir_we=1;
force dut.ir_.db=0;
#2 release dut.ir_.ctl_ir_we;
release dut.ir_.db;
$fdisplay(f,"Testing opcode bf CP A");
$fdisplay(f,"Testing opcode bf CP A");
// Preset af
force dut.reg_file_.b2v_latch_af_lo.we=1;
force dut.reg_file_.b2v_latch_af_hi.we=1;
2412,10 → 2425,10
force dut.address_latch_.Q=16'h0000;
release dut.reg_control_.ctl_reg_sys_we;
release dut.reg_file_.reg_gp_we;
#3
release dut.address_latch_.Q;
#2 // Execute: M1/T1 start
#1 release dut.address_latch_.Q;
#1
#6 // Execute
#6 // Wait for opcode end
force dut.reg_control_.ctl_reg_sys_we=0;
#2 pc=z.A;
#2
2446,12 → 2459,13
if (pc!==16'h0001) $fdisplay(f,"* PC=%h !=0001",pc);
if (dut.reg_file_.b2v_latch_ir_lo.latch!==8'h01) $fdisplay(f,"* Reg ir r=%h !=01",dut.reg_file_.b2v_latch_ir_lo.latch);
if (dut.reg_file_.b2v_latch_ir_hi.latch!==8'h00) $fdisplay(f,"* Reg ir i=%h !=00",dut.reg_file_.b2v_latch_ir_hi.latch);
//--------------------------------------------------------------------------------
#1 // End opcode
 
force dut.ir_.ctl_ir_we=1;
force dut.ir_.db=0;
#2 release dut.ir_.ctl_ir_we;
release dut.ir_.db;
$fdisplay(f,"Testing opcode 43 LD B,E");
$fdisplay(f,"Testing opcode 43 LD B,E");
// Preset af
force dut.reg_file_.b2v_latch_af_lo.we=1;
force dut.reg_file_.b2v_latch_af_hi.we=1;
2586,10 → 2600,10
force dut.address_latch_.Q=16'h0000;
release dut.reg_control_.ctl_reg_sys_we;
release dut.reg_file_.reg_gp_we;
#3
release dut.address_latch_.Q;
#2 // Execute: M1/T1 start
#1 release dut.address_latch_.Q;
#1
#6 // Execute
#6 // Wait for opcode end
force dut.reg_control_.ctl_reg_sys_we=0;
#2 pc=z.A;
#2
2620,12 → 2634,13
if (pc!==16'h0001) $fdisplay(f,"* PC=%h !=0001",pc);
if (dut.reg_file_.b2v_latch_ir_lo.latch!==8'h01) $fdisplay(f,"* Reg ir r=%h !=01",dut.reg_file_.b2v_latch_ir_lo.latch);
if (dut.reg_file_.b2v_latch_ir_hi.latch!==8'h00) $fdisplay(f,"* Reg ir i=%h !=00",dut.reg_file_.b2v_latch_ir_hi.latch);
//--------------------------------------------------------------------------------
#1 // End opcode
 
force dut.ir_.ctl_ir_we=1;
force dut.ir_.db=0;
#2 release dut.ir_.ctl_ir_we;
release dut.ir_.db;
$fdisplay(f,"Testing opcode 6e LD L,(HL)");
$fdisplay(f,"Testing opcode 6e LD L,(HL)");
// Preset af
force dut.reg_file_.b2v_latch_af_lo.we=1;
force dut.reg_file_.b2v_latch_af_hi.we=1;
2760,10 → 2775,10
force dut.address_latch_.Q=16'h0000;
release dut.reg_control_.ctl_reg_sys_we;
release dut.reg_file_.reg_gp_we;
#3
release dut.address_latch_.Q;
#2 // Execute: M1/T1 start
#1 release dut.address_latch_.Q;
#1
#12 // Execute
#12 // Wait for opcode end
force dut.reg_control_.ctl_reg_sys_we=0;
#2 pc=z.A;
#2
2794,12 → 2809,13
if (pc!==16'h0001) $fdisplay(f,"* PC=%h !=0001",pc);
if (dut.reg_file_.b2v_latch_ir_lo.latch!==8'h01) $fdisplay(f,"* Reg ir r=%h !=01",dut.reg_file_.b2v_latch_ir_lo.latch);
if (dut.reg_file_.b2v_latch_ir_hi.latch!==8'h00) $fdisplay(f,"* Reg ir i=%h !=00",dut.reg_file_.b2v_latch_ir_hi.latch);
//--------------------------------------------------------------------------------
#1 // End opcode
 
force dut.ir_.ctl_ir_we=1;
force dut.ir_.db=0;
#2 release dut.ir_.ctl_ir_we;
release dut.ir_.db;
$fdisplay(f,"Testing opcode e3 EX (SP),HL");
$fdisplay(f,"Testing opcode e3 EX (SP),HL");
// Preset af
force dut.reg_file_.b2v_latch_af_lo.we=1;
force dut.reg_file_.b2v_latch_af_hi.we=1;
2935,10 → 2951,10
force dut.address_latch_.Q=16'h0000;
release dut.reg_control_.ctl_reg_sys_we;
release dut.reg_file_.reg_gp_we;
#3
release dut.address_latch_.Q;
#2 // Execute: M1/T1 start
#1 release dut.address_latch_.Q;
#1
#36 // Execute
#36 // Wait for opcode end
force dut.reg_control_.ctl_reg_sys_we=0;
#2 pc=z.A;
#2
2971,12 → 2987,13
if (dut.reg_file_.b2v_latch_ir_hi.latch!==8'h00) $fdisplay(f,"* Reg ir i=%h !=00",dut.reg_file_.b2v_latch_ir_hi.latch);
if (ram.Mem[883]!==8'h22) $fdisplay(f,"* Mem[373]=%h !=22",ram.Mem[883]);
if (ram.Mem[884]!==8'h4d) $fdisplay(f,"* Mem[374]=%h !=4d",ram.Mem[884]);
//--------------------------------------------------------------------------------
#1 // End opcode
 
force dut.ir_.ctl_ir_we=1;
force dut.ir_.db=0;
#2 release dut.ir_.ctl_ir_we;
release dut.ir_.db;
$fdisplay(f,"Testing opcode 03 INC BC");
$fdisplay(f,"Testing opcode 03 INC BC");
// Preset af
force dut.reg_file_.b2v_latch_af_lo.we=1;
force dut.reg_file_.b2v_latch_af_hi.we=1;
3109,10 → 3126,10
force dut.address_latch_.Q=16'h0000;
release dut.reg_control_.ctl_reg_sys_we;
release dut.reg_file_.reg_gp_we;
#3
release dut.address_latch_.Q;
#2 // Execute: M1/T1 start
#1 release dut.address_latch_.Q;
#1
#10 // Execute
#10 // Wait for opcode end
force dut.reg_control_.ctl_reg_sys_we=0;
#2 pc=z.A;
#2
3143,12 → 3160,13
if (pc!==16'h0001) $fdisplay(f,"* PC=%h !=0001",pc);
if (dut.reg_file_.b2v_latch_ir_lo.latch!==8'h01) $fdisplay(f,"* Reg ir r=%h !=01",dut.reg_file_.b2v_latch_ir_lo.latch);
if (dut.reg_file_.b2v_latch_ir_hi.latch!==8'h00) $fdisplay(f,"* Reg ir i=%h !=00",dut.reg_file_.b2v_latch_ir_hi.latch);
//--------------------------------------------------------------------------------
#1 // End opcode
 
force dut.ir_.ctl_ir_we=1;
force dut.ir_.db=0;
#2 release dut.ir_.ctl_ir_we;
release dut.ir_.db;
$fdisplay(f,"Testing opcode 3b DEC SP");
$fdisplay(f,"Testing opcode 3b DEC SP");
// Preset af
force dut.reg_file_.b2v_latch_af_lo.we=1;
force dut.reg_file_.b2v_latch_af_hi.we=1;
3281,10 → 3299,10
force dut.address_latch_.Q=16'h0000;
release dut.reg_control_.ctl_reg_sys_we;
release dut.reg_file_.reg_gp_we;
#3
release dut.address_latch_.Q;
#2 // Execute: M1/T1 start
#1 release dut.address_latch_.Q;
#1
#10 // Execute
#10 // Wait for opcode end
force dut.reg_control_.ctl_reg_sys_we=0;
#2 pc=z.A;
#2
3315,12 → 3333,13
if (pc!==16'h0001) $fdisplay(f,"* PC=%h !=0001",pc);
if (dut.reg_file_.b2v_latch_ir_lo.latch!==8'h01) $fdisplay(f,"* Reg ir r=%h !=01",dut.reg_file_.b2v_latch_ir_lo.latch);
if (dut.reg_file_.b2v_latch_ir_hi.latch!==8'h00) $fdisplay(f,"* Reg ir i=%h !=00",dut.reg_file_.b2v_latch_ir_hi.latch);
//--------------------------------------------------------------------------------
#1 // End opcode
 
force dut.ir_.ctl_ir_we=1;
force dut.ir_.db=0;
#2 release dut.ir_.ctl_ir_we;
release dut.ir_.db;
$fdisplay(f,"Testing opcode 07 RLCA");
$fdisplay(f,"Testing opcode 07 RLCA");
// Preset af
force dut.reg_file_.b2v_latch_af_lo.we=1;
force dut.reg_file_.b2v_latch_af_hi.we=1;
3453,10 → 3472,10
force dut.address_latch_.Q=16'h0000;
release dut.reg_control_.ctl_reg_sys_we;
release dut.reg_file_.reg_gp_we;
#3
release dut.address_latch_.Q;
#2 // Execute: M1/T1 start
#1 release dut.address_latch_.Q;
#1
#6 // Execute
#6 // Wait for opcode end
force dut.reg_control_.ctl_reg_sys_we=0;
#2 pc=z.A;
#2
3487,12 → 3506,13
if (pc!==16'h0001) $fdisplay(f,"* PC=%h !=0001",pc);
if (dut.reg_file_.b2v_latch_ir_lo.latch!==8'h01) $fdisplay(f,"* Reg ir r=%h !=01",dut.reg_file_.b2v_latch_ir_lo.latch);
if (dut.reg_file_.b2v_latch_ir_hi.latch!==8'h00) $fdisplay(f,"* Reg ir i=%h !=00",dut.reg_file_.b2v_latch_ir_hi.latch);
//--------------------------------------------------------------------------------
#1 // End opcode
 
force dut.ir_.ctl_ir_we=1;
force dut.ir_.db=0;
#2 release dut.ir_.ctl_ir_we;
release dut.ir_.db;
$fdisplay(f,"Testing opcode 1f RRA");
$fdisplay(f,"Testing opcode 1f RRA");
// Preset af
force dut.reg_file_.b2v_latch_af_lo.we=1;
force dut.reg_file_.b2v_latch_af_hi.we=1;
3625,10 → 3645,10
force dut.address_latch_.Q=16'h0000;
release dut.reg_control_.ctl_reg_sys_we;
release dut.reg_file_.reg_gp_we;
#3
release dut.address_latch_.Q;
#2 // Execute: M1/T1 start
#1 release dut.address_latch_.Q;
#1
#6 // Execute
#6 // Wait for opcode end
force dut.reg_control_.ctl_reg_sys_we=0;
#2 pc=z.A;
#2
3659,12 → 3679,13
if (pc!==16'h0001) $fdisplay(f,"* PC=%h !=0001",pc);
if (dut.reg_file_.b2v_latch_ir_lo.latch!==8'h01) $fdisplay(f,"* Reg ir r=%h !=01",dut.reg_file_.b2v_latch_ir_lo.latch);
if (dut.reg_file_.b2v_latch_ir_hi.latch!==8'h00) $fdisplay(f,"* Reg ir i=%h !=00",dut.reg_file_.b2v_latch_ir_hi.latch);
//--------------------------------------------------------------------------------
#1 // End opcode
 
force dut.ir_.ctl_ir_we=1;
force dut.ir_.db=0;
#2 release dut.ir_.ctl_ir_we;
release dut.ir_.db;
$fdisplay(f,"Testing opcode cb09 RRC C");
$fdisplay(f,"Testing opcode cb09 RRC C");
// Preset af
force dut.reg_file_.b2v_latch_af_lo.we=1;
force dut.reg_file_.b2v_latch_af_hi.we=1;
3800,10 → 3821,10
force dut.address_latch_.Q=16'h0000;
release dut.reg_control_.ctl_reg_sys_we;
release dut.reg_file_.reg_gp_we;
#3
release dut.address_latch_.Q;
#2 // Execute: M1/T1 start
#1 release dut.address_latch_.Q;
#1
#14 // Execute
#14 // Wait for opcode end
force dut.reg_control_.ctl_reg_sys_we=0;
#2 pc=z.A;
#2
3834,12 → 3855,13
if (pc!==16'h0002) $fdisplay(f,"* PC=%h !=0002",pc);
if (dut.reg_file_.b2v_latch_ir_lo.latch!==8'h02) $fdisplay(f,"* Reg ir r=%h !=02",dut.reg_file_.b2v_latch_ir_lo.latch);
if (dut.reg_file_.b2v_latch_ir_hi.latch!==8'h00) $fdisplay(f,"* Reg ir i=%h !=00",dut.reg_file_.b2v_latch_ir_hi.latch);
//--------------------------------------------------------------------------------
#1 // End opcode
 
force dut.ir_.ctl_ir_we=1;
force dut.ir_.db=0;
#2 release dut.ir_.ctl_ir_we;
release dut.ir_.db;
$fdisplay(f,"Testing opcode cb11 RL C");
$fdisplay(f,"Testing opcode cb11 RL C");
// Preset af
force dut.reg_file_.b2v_latch_af_lo.we=1;
force dut.reg_file_.b2v_latch_af_hi.we=1;
3975,10 → 3997,10
force dut.address_latch_.Q=16'h0000;
release dut.reg_control_.ctl_reg_sys_we;
release dut.reg_file_.reg_gp_we;
#3
release dut.address_latch_.Q;
#2 // Execute: M1/T1 start
#1 release dut.address_latch_.Q;
#1
#14 // Execute
#14 // Wait for opcode end
force dut.reg_control_.ctl_reg_sys_we=0;
#2 pc=z.A;
#2
4009,12 → 4031,13
if (pc!==16'h0002) $fdisplay(f,"* PC=%h !=0002",pc);
if (dut.reg_file_.b2v_latch_ir_lo.latch!==8'h02) $fdisplay(f,"* Reg ir r=%h !=02",dut.reg_file_.b2v_latch_ir_lo.latch);
if (dut.reg_file_.b2v_latch_ir_hi.latch!==8'h00) $fdisplay(f,"* Reg ir i=%h !=00",dut.reg_file_.b2v_latch_ir_hi.latch);
//--------------------------------------------------------------------------------
#1 // End opcode
 
force dut.ir_.ctl_ir_we=1;
force dut.ir_.db=0;
#2 release dut.ir_.ctl_ir_we;
release dut.ir_.db;
$fdisplay(f,"Testing opcode cb36 SLL (HL)*");
$fdisplay(f,"Testing opcode cb36 SLL (HL)*");
// Preset af
force dut.reg_file_.b2v_latch_af_lo.we=1;
force dut.reg_file_.b2v_latch_af_hi.we=1;
4150,10 → 4173,10
force dut.address_latch_.Q=16'h0000;
release dut.reg_control_.ctl_reg_sys_we;
release dut.reg_file_.reg_gp_we;
#3
release dut.address_latch_.Q;
#2 // Execute: M1/T1 start
#1 release dut.address_latch_.Q;
#1
#28 // Execute
#28 // Wait for opcode end
force dut.reg_control_.ctl_reg_sys_we=0;
#2 pc=z.A;
#2
4185,12 → 4208,13
if (dut.reg_file_.b2v_latch_ir_lo.latch!==8'h02) $fdisplay(f,"* Reg ir r=%h !=02",dut.reg_file_.b2v_latch_ir_lo.latch);
if (dut.reg_file_.b2v_latch_ir_hi.latch!==8'h00) $fdisplay(f,"* Reg ir i=%h !=00",dut.reg_file_.b2v_latch_ir_hi.latch);
if (ram.Mem[27960]!==8'he3) $fdisplay(f,"* Mem[6d38]=%h !=e3",ram.Mem[27960]);
//--------------------------------------------------------------------------------
#1 // End opcode
 
force dut.ir_.ctl_ir_we=1;
force dut.ir_.db=0;
#2 release dut.ir_.ctl_ir_we;
release dut.ir_.db;
$fdisplay(f,"Testing opcode cb52 BIT 2,D");
$fdisplay(f,"Testing opcode cb52 BIT 2,D");
// Preset af
force dut.reg_file_.b2v_latch_af_lo.we=1;
force dut.reg_file_.b2v_latch_af_hi.we=1;
4326,10 → 4350,10
force dut.address_latch_.Q=16'h0000;
release dut.reg_control_.ctl_reg_sys_we;
release dut.reg_file_.reg_gp_we;
#3
release dut.address_latch_.Q;
#2 // Execute: M1/T1 start
#1 release dut.address_latch_.Q;
#1
#14 // Execute
#14 // Wait for opcode end
force dut.reg_control_.ctl_reg_sys_we=0;
#2 pc=z.A;
#2
4360,12 → 4384,13
if (pc!==16'h0002) $fdisplay(f,"* PC=%h !=0002",pc);
if (dut.reg_file_.b2v_latch_ir_lo.latch!==8'h02) $fdisplay(f,"* Reg ir r=%h !=02",dut.reg_file_.b2v_latch_ir_lo.latch);
if (dut.reg_file_.b2v_latch_ir_hi.latch!==8'h00) $fdisplay(f,"* Reg ir i=%h !=00",dut.reg_file_.b2v_latch_ir_hi.latch);
//--------------------------------------------------------------------------------
#1 // End opcode
 
force dut.ir_.ctl_ir_we=1;
force dut.ir_.db=0;
#2 release dut.ir_.ctl_ir_we;
release dut.ir_.db;
$fdisplay(f,"Testing opcode cb93 RES 2,E");
$fdisplay(f,"Testing opcode cb93 RES 2,E");
// Preset af
force dut.reg_file_.b2v_latch_af_lo.we=1;
force dut.reg_file_.b2v_latch_af_hi.we=1;
4501,10 → 4526,10
force dut.address_latch_.Q=16'h0000;
release dut.reg_control_.ctl_reg_sys_we;
release dut.reg_file_.reg_gp_we;
#3
release dut.address_latch_.Q;
#2 // Execute: M1/T1 start
#1 release dut.address_latch_.Q;
#1
#14 // Execute
#14 // Wait for opcode end
force dut.reg_control_.ctl_reg_sys_we=0;
#2 pc=z.A;
#2
4535,12 → 4560,13
if (pc!==16'h0002) $fdisplay(f,"* PC=%h !=0002",pc);
if (dut.reg_file_.b2v_latch_ir_lo.latch!==8'h02) $fdisplay(f,"* Reg ir r=%h !=02",dut.reg_file_.b2v_latch_ir_lo.latch);
if (dut.reg_file_.b2v_latch_ir_hi.latch!==8'h00) $fdisplay(f,"* Reg ir i=%h !=00",dut.reg_file_.b2v_latch_ir_hi.latch);
//--------------------------------------------------------------------------------
#1 // End opcode
 
force dut.ir_.ctl_ir_we=1;
force dut.ir_.db=0;
#2 release dut.ir_.ctl_ir_we;
release dut.ir_.db;
$fdisplay(f,"Testing opcode cbc4 SET 0,H");
$fdisplay(f,"Testing opcode cbc4 SET 0,H");
// Preset af
force dut.reg_file_.b2v_latch_af_lo.we=1;
force dut.reg_file_.b2v_latch_af_hi.we=1;
4676,10 → 4702,10
force dut.address_latch_.Q=16'h0000;
release dut.reg_control_.ctl_reg_sys_we;
release dut.reg_file_.reg_gp_we;
#3
release dut.address_latch_.Q;
#2 // Execute: M1/T1 start
#1 release dut.address_latch_.Q;
#1
#14 // Execute
#14 // Wait for opcode end
force dut.reg_control_.ctl_reg_sys_we=0;
#2 pc=z.A;
#2
4710,12 → 4736,13
if (pc!==16'h0002) $fdisplay(f,"* PC=%h !=0002",pc);
if (dut.reg_file_.b2v_latch_ir_lo.latch!==8'h02) $fdisplay(f,"* Reg ir r=%h !=02",dut.reg_file_.b2v_latch_ir_lo.latch);
if (dut.reg_file_.b2v_latch_ir_hi.latch!==8'h00) $fdisplay(f,"* Reg ir i=%h !=00",dut.reg_file_.b2v_latch_ir_hi.latch);
//--------------------------------------------------------------------------------
#1 // End opcode
 
force dut.ir_.ctl_ir_we=1;
force dut.ir_.db=0;
#2 release dut.ir_.ctl_ir_we;
release dut.ir_.db;
$fdisplay(f,"Testing opcode dd75 LD (IX+d),L");
$fdisplay(f,"Testing opcode dd75 LD (IX+d),L");
// Preset af
force dut.reg_file_.b2v_latch_af_lo.we=1;
force dut.reg_file_.b2v_latch_af_hi.we=1;
4850,10 → 4877,10
force dut.address_latch_.Q=16'h0000;
release dut.reg_control_.ctl_reg_sys_we;
release dut.reg_file_.reg_gp_we;
#3
release dut.address_latch_.Q;
#2 // Execute: M1/T1 start
#1 release dut.address_latch_.Q;
#1
#36 // Execute
#36 // Wait for opcode end
force dut.reg_control_.ctl_reg_sys_we=0;
#2 pc=z.A;
#2
4885,12 → 4912,13
if (dut.reg_file_.b2v_latch_ir_lo.latch!==8'h02) $fdisplay(f,"* Reg ir r=%h !=02",dut.reg_file_.b2v_latch_ir_lo.latch);
if (dut.reg_file_.b2v_latch_ir_hi.latch!==8'h00) $fdisplay(f,"* Reg ir i=%h !=00",dut.reg_file_.b2v_latch_ir_hi.latch);
if (ram.Mem[44668]!==8'h4f) $fdisplay(f,"* Mem[ae7c]=%h !=4f",ram.Mem[44668]);
//--------------------------------------------------------------------------------
#1 // End opcode
 
force dut.ir_.ctl_ir_we=1;
force dut.ir_.db=0;
#2 release dut.ir_.ctl_ir_we;
release dut.ir_.db;
$fdisplay(f,"Testing opcode dd4e LD C,(IX+d)");
$fdisplay(f,"Testing opcode dd4e LD C,(IX+d)");
// Preset af
force dut.reg_file_.b2v_latch_af_lo.we=1;
force dut.reg_file_.b2v_latch_af_hi.we=1;
5027,10 → 5055,10
force dut.address_latch_.Q=16'h0000;
release dut.reg_control_.ctl_reg_sys_we;
release dut.reg_file_.reg_gp_we;
#3
release dut.address_latch_.Q;
#2 // Execute: M1/T1 start
#1 release dut.address_latch_.Q;
#1
#36 // Execute
#36 // Wait for opcode end
force dut.reg_control_.ctl_reg_sys_we=0;
#2 pc=z.A;
#2
5061,6 → 5089,7
if (pc!==16'h0003) $fdisplay(f,"* PC=%h !=0003",pc);
if (dut.reg_file_.b2v_latch_ir_lo.latch!==8'h02) $fdisplay(f,"* Reg ir r=%h !=02",dut.reg_file_.b2v_latch_ir_lo.latch);
if (dut.reg_file_.b2v_latch_ir_hi.latch!==8'h00) $fdisplay(f,"* Reg ir i=%h !=00",dut.reg_file_.b2v_latch_ir_hi.latch);
//--------------------------------------------------------------------------------
`define TOTAL_CLKS 1559
#1 // End opcode
 
`define TOTAL_CLKS 1588
$fdisplay(f,"=== Tests completed ===");
/trunk/host/basic_de1/basic_de1.qsf
639,6 → 639,7
set_global_assignment -name VERILOG_FILE ../../cpu/registers/reg_file.v
set_global_assignment -name VERILOG_FILE ../../cpu/registers/reg_latch.v
set_global_assignment -name VERILOG_FILE ../common/uart.v
set_global_assignment -name VERILOG_FILE ../common/wait_state.v
set_global_assignment -name VERILOG_FILE basic_de1_fpga.sv
set_global_assignment -name QIP_FILE ram.qip
set_global_assignment -name QIP_FILE pll.qip
/trunk/host/basic_de1/basic_de1_ModelSim.sv
39,7 → 39,7
wire nHALT;
wire nBUSACK;
 
wire nWAIT = 1;
wire nWAIT;
wire nINT = nint;
wire nNMI = nnmi;
wire nBUSRQ = 1;
47,6 → 47,15
wire [15:0] A;
wire [7:0] D;
 
// This is an optional, test feature: add M1/Memory Wait states as described in the Zilog manual
reg nWAIT_M1_sig;
reg nWAIT_Mem_sig;
 
// *** Uncomment one of the following 3 choices ***:
//assign nWAIT = nWAIT_M1_sig; // Add one wait state to an M1 cycle
//assign nWAIT = nWAIT_Mem_sig; // Add one wait state to any memory cycle (M1 + memory read/write)
assign nWAIT = 1; // Do not add wait cycles
 
// ----------------- INTERNAL WIRES -----------------
wire [7:0] RamData; // RamData is a data writer from the RAM module
wire RamWE;
68,6 → 77,18
z80_top_direct_n z80_( .*, .nRESET(reset), .CLK(clk) );
 
//~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
// Instantiate gates to add Wait states to M1 and Memory cycles (for testing)
//~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
wait_state wait_state_inst
(
.CLK(clk),
.nM1(nM1),
.nMREQ((nMREQ === z) ? 1'b1 : nMREQ), // Correct nMREQ from being tri-stated after reset
.nWAIT_M1(nWAIT_M1_sig),
.nWAIT_Mem(nWAIT_Mem_sig)
);
 
//~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
// Instantiate 16Kb of RAM memory
//~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
ram ram_( .address(A[13:0]), .clock(clk), .data(D[7:0]), .wren(RamWE), .q(RamData[7:0]) );
/trunk/host/basic_de1/basic_de1_fpga.sv
59,7 → 59,7
wire nHALT;
wire nBUSACK;
 
wire nWAIT = 1;
wire nWAIT;
wire nBUSRQ = 1;
wire nINT = KEY1;
wire nNMI = KEY2;
67,6 → 67,15
wire [15:0] A;
wire [7:0] D;
 
// This is an optional, test feature: add M1/Memory Wait states as described in the Zilog manual
reg nWAIT_M1_sig;
reg nWAIT_Mem_sig;
 
// *** Uncomment one of the following 3 choices ***:
//assign nWAIT = nWAIT_M1_sig; // Add one wait state to an M1 cycle
//assign nWAIT = nWAIT_Mem_sig; // Add one wait state to any memory cycle (M1 + memory read/write)
assign nWAIT = 1; // Do not add wait cycles
 
//~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
// Instantiate PLL
//~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
124,6 → 133,18
z80_top_direct_n z80_( .*, .nRESET(reset), .CLK(clk_cpu) );
 
//~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
// Instantiate gates to add Wait states to M1 and Memory cycles (for testing)
//~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
wait_state wait_state_inst
(
.CLK(clk_cpu),
.nM1(nM1),
.nMREQ(nMREQ),
.nWAIT_M1(nWAIT_M1_sig),
.nWAIT_Mem(nWAIT_Mem_sig)
);
 
//~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
// Instantiate 16Kb of RAM memory
//~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
ram ram_( .address(A[13:0]), .clock(pll_clk), .data(D[7:0]), .wren(RamWE), .q(RamData[7:0]) );
/trunk/host/basic_de1/simulation/modelsim/test_host.mpf
441,7 → 441,7
Project_Version = 6
Project_DefaultLib = work
Project_SortMethod = unused
Project_Files_Count = 43
Project_Files_Count = 44
Project_File_0 = $ROOT/cpu/alu/alu.v
Project_File_P_0 = compile_order 11 compile_to work cover_branch 0 cover_cond 0 cover_covercells 0 cover_excludedefault 0 cover_expr 0 cover_exttoggle 0 cover_fsm 0 cover_nofec 0 cover_noshort 0 cover_optlevel 3 cover_stmt 0 cover_toggle 0 dont_compile 0 file_type verilog folder cpu group_id 0 last_compile 1 ood 0 toggle - vlog_0InOptions {} vlog_1995compat 0 vlog_disableopt 0 vlog_enable0In 0 vlog_hazard 0 vlog_nodebug 0 vlog_noload 0 vlog_options {} vlog_protect 0 vlog_showsource 0 vlog_upper 0 voptflow 1
Project_File_1 = $ROOT/cpu/alu/alu_bit_select.v
528,6 → 528,8
Project_File_P_41 = compile_order 38 compile_to work cover_branch 0 cover_cond 0 cover_covercells 0 cover_excludedefault 0 cover_expr 0 cover_exttoggle 0 cover_fsm 0 cover_nofec 0 cover_noshort 0 cover_optlevel 3 cover_stmt 0 cover_toggle 0 dont_compile 0 file_type systemverilog folder {Top Level} group_id 0 last_compile 1 ood 0 toggle - vlog_0InOptions {} vlog_1995compat SV vlog_disableopt 0 vlog_enable0In 0 vlog_hazard 0 vlog_nodebug 0 vlog_noload 0 vlog_options {} vlog_protect 0 vlog_showsource 0 vlog_upper 0 voptflow 1
Project_File_42 = $ROOT/host/common/uart.v
Project_File_P_42 = compile_order 42 compile_to work cover_branch 0 cover_cond 0 cover_covercells 0 cover_excludedefault 0 cover_expr 0 cover_exttoggle 0 cover_fsm 0 cover_nofec 0 cover_noshort 0 cover_optlevel 3 cover_stmt 0 cover_toggle 0 dont_compile 0 file_type verilog folder uart group_id 0 last_compile 1 ood 0 toggle - vlog_0InOptions {} vlog_1995compat 0 vlog_disableopt 0 vlog_enable0In 0 vlog_hazard 0 vlog_nodebug 0 vlog_noload 0 vlog_options {} vlog_protect 0 vlog_showsource 0 vlog_upper 0 voptflow 1
Project_File_43 = $ROOT/host/common/wait_state.v
Project_File_P_43 = compile_order 43 compile_to work cover_branch 0 cover_cond 0 cover_covercells 0 cover_excludedefault 0 cover_expr 0 cover_exttoggle 0 cover_fsm 0 cover_nofec 0 cover_noshort 0 cover_optlevel 3 cover_stmt 0 cover_toggle 0 dont_compile 0 file_type verilog folder {Top Level} group_id 0 last_compile 1 ood 0 toggle - vlog_0InOptions {} vlog_1995compat 0 vlog_disableopt 0 vlog_enable0In 0 vlog_hazard 0 vlog_nodebug 0 vlog_noload 0 vlog_options {} vlog_protect 0 vlog_showsource 0 vlog_upper 0 voptflow 1
Project_Sim_Count = 1
Project_Sim_0 = test_host
Project_Sim_P_0 = timing default -t ps -sdfnoerror 0 -nofileshare 0 +no_pulse_msg 0 -Lf {} Generics {} +notimingchecks 0 ok 1 folder {Top Level} +pulse_e {} additional_dus work.test_bench_host -assertfile {} -std_output {} -L altera_mf_ver -nopsl 0 -nosva 0 +pulse_r {} -absentisempty 0 -assertcover 0 -multisource_delay {} OtherArgs {} -vital2.2b 0 is_vopt_flow 0 -memprof 0 -noglitch 0 -0in_options {} selected_du {} -sdf {} -hazards 0 -0in 0 +plusarg {} -coverage 0 vopt_env 1 -wlf {} -assertdebug 0 -std_input {} -sdfnowarn 0
/trunk/host/basic_de1/simulation/modelsim/wave_host.do
41,6 → 41,8
} /test_bench_host/host_/D
add wave -noupdate -expand -group {host
} /test_bench_host/host_/RamData
add wave -noupdate /test_bench_host/host_/nWAIT_M1_sig
add wave -noupdate /test_bench_host/host_/nWAIT_Mem_sig
add wave -noupdate -group {RAM
} /test_bench_host/host_/ram_/address
add wave -noupdate -group {RAM
/trunk/host/common/wait_state.bdf
0,0 → 1,492
/*
WARNING: Do NOT edit the input and output ports in this file in a text
editor if you plan to continue editing the block that represents it in
the Block Editor! File corruption is VERY likely to occur.
*/
/*
Copyright (C) 1991-2013 Altera Corporation
Your use of Altera Corporation's design tools, logic functions
and other software and tools, and its AMPP partner logic
functions, and any output files from any of the foregoing
(including device programming or simulation files), and any
associated documentation or information are expressly subject
to the terms and conditions of the Altera Program License
Subscription Agreement, Altera MegaCore Function License
Agreement, or other applicable license agreement, including,
without limitation, that your use is for the sole purpose of
programming logic devices manufactured by Altera and sold by
Altera or its authorized distributors. Please refer to the
applicable agreement for further details.
*/
(header "graphic" (version "1.4"))
(pin
(input)
(rect 64 216 240 232)
(text "INPUT" (rect 133 0 161 10)(font "Arial" (font_size 6)))
(text "CLK" (rect 9 0 30 12)(font "Arial" ))
(pt 176 8)
(drawing
(line (pt 92 12)(pt 117 12))
(line (pt 92 4)(pt 117 4))
(line (pt 121 8)(pt 176 8))
(line (pt 92 12)(pt 92 4))
(line (pt 117 4)(pt 121 8))
(line (pt 117 12)(pt 121 8))
)
(text "VCC" (rect 136 7 156 17)(font "Arial" (font_size 6)))
)
(pin
(input)
(rect 64 136 240 152)
(text "INPUT" (rect 133 0 161 10)(font "Arial" (font_size 6)))
(text "nM1" (rect 9 0 29 12)(font "Arial" ))
(pt 176 8)
(drawing
(line (pt 92 12)(pt 117 12))
(line (pt 92 4)(pt 117 4))
(line (pt 121 8)(pt 176 8))
(line (pt 92 12)(pt 92 4))
(line (pt 117 4)(pt 121 8))
(line (pt 117 12)(pt 121 8))
)
(text "VCC" (rect 136 7 156 17)(font "Arial" (font_size 6)))
)
(pin
(input)
(rect 64 376 240 392)
(text "INPUT" (rect 133 0 161 10)(font "Arial" (font_size 6)))
(text "nMREQ" (rect 9 0 46 12)(font "Arial" ))
(pt 176 8)
(drawing
(line (pt 92 12)(pt 117 12))
(line (pt 92 4)(pt 117 4))
(line (pt 121 8)(pt 176 8))
(line (pt 92 12)(pt 92 4))
(line (pt 117 4)(pt 121 8))
(line (pt 117 12)(pt 121 8))
)
(text "VCC" (rect 136 7 156 17)(font "Arial" (font_size 6)))
)
(pin
(output)
(rect 608 72 784 88)
(text "OUTPUT" (rect 1 0 39 10)(font "Arial" (font_size 6)))
(text "nWAIT_M1" (rect 90 0 143 12)(font "Arial" ))
(pt 0 8)
(drawing
(line (pt 0 8)(pt 52 8))
(line (pt 52 4)(pt 78 4))
(line (pt 52 12)(pt 78 12))
(line (pt 52 12)(pt 52 4))
(line (pt 78 4)(pt 82 8))
(line (pt 82 8)(pt 78 12))
(line (pt 78 12)(pt 82 8))
)
)
(pin
(output)
(rect 608 312 784 328)
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(pt 64 24)
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(pt 152 400)
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(junction (pt 256 224))
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(junction (pt 368 144))
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(text "Memory Speed Control, Zilog Manual" (rect 72 40 324 56)(font "Arial" (font_size 10))(border))
(text "Adding One Wait State to an M1 Cycle" (rect 536 168 802 184)(font "Arial" (font_size 10)))
(text "Adding One Wait State to Any Memory Cycle" (rect 528 408 839 424)(font "Arial" (font_size 10)))
(line (pt 64 272)(pt 784 272)(color 0 255 0))
/trunk/host/common/wait_state.bsf
0,0 → 1,64
/*
WARNING: Do NOT edit the input and output ports in this file in a text
editor if you plan to continue editing the block that represents it in
the Block Editor! File corruption is VERY likely to occur.
*/
/*
Copyright (C) 1991-2013 Altera Corporation
Your use of Altera Corporation's design tools, logic functions
and other software and tools, and its AMPP partner logic
functions, and any output files from any of the foregoing
(including device programming or simulation files), and any
associated documentation or information are expressly subject
to the terms and conditions of the Altera Program License
Subscription Agreement, Altera MegaCore Function License
Agreement, or other applicable license agreement, including,
without limitation, that your use is for the sole purpose of
programming logic devices manufactured by Altera and sold by
Altera or its authorized distributors. Please refer to the
applicable agreement for further details.
*/
(header "symbol" (version "1.2"))
(symbol
(rect 16 16 184 112)
(text "wait_state" (rect 5 0 65 14)(font "Arial" (font_size 8)))
(text "inst" (rect 8 80 25 92)(font "Arial" ))
(port
(pt 0 32)
(input)
(text "nM1" (rect 0 0 23 14)(font "Arial" (font_size 8)))
(text "nM1" (rect 21 27 44 41)(font "Arial" (font_size 8)))
(line (pt 0 32)(pt 16 32))
)
(port
(pt 0 48)
(input)
(text "CLK" (rect 0 0 23 14)(font "Arial" (font_size 8)))
(text "CLK" (rect 21 43 44 57)(font "Arial" (font_size 8)))
(line (pt 0 48)(pt 16 48))
)
(port
(pt 0 64)
(input)
(text "nMREQ" (rect 0 0 41 14)(font "Arial" (font_size 8)))
(text "nMREQ" (rect 21 59 62 73)(font "Arial" (font_size 8)))
(line (pt 0 64)(pt 16 64))
)
(port
(pt 168 32)
(output)
(text "nWAIT_M1" (rect 0 0 61 14)(font "Arial" (font_size 8)))
(text "nWAIT_M1" (rect 86 27 147 41)(font "Arial" (font_size 8)))
(line (pt 168 32)(pt 152 32))
)
(port
(pt 168 48)
(output)
(text "nWAIT_Mem" (rect 0 0 70 14)(font "Arial" (font_size 8)))
(text "nWAIT_Mem" (rect 77 43 147 57)(font "Arial" (font_size 8)))
(line (pt 168 48)(pt 152 48))
)
(drawing
(rectangle (rect 16 16 152 80))
)
)
/trunk/host/common/wait_state.v
0,0 → 1,86
// Copyright (C) 1991-2013 Altera Corporation
// Your use of Altera Corporation's design tools, logic functions
// and other software and tools, and its AMPP partner logic
// functions, and any output files from any of the foregoing
// (including device programming or simulation files), and any
// associated documentation or information are expressly subject
// to the terms and conditions of the Altera Program License
// Subscription Agreement, Altera MegaCore Function License
// Agreement, or other applicable license agreement, including,
// without limitation, that your use is for the sole purpose of
// programming logic devices manufactured by Altera and sold by
// Altera or its authorized distributors. Please refer to the
// applicable agreement for further details.
 
// PROGRAM "Quartus II 64-Bit"
// VERSION "Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition"
// CREATED "Thu Dec 08 00:16:50 2016"
 
module wait_state(
CLK,
nM1,
nMREQ,
nWAIT_M1,
nWAIT_Mem
);
 
 
input wire CLK;
input wire nM1;
input wire nMREQ;
output wire nWAIT_M1;
output wire nWAIT_Mem;
 
reg SYNTHESIZED_WIRE_1;
reg DFF_inst3;
reg DFF_inst2;
reg DFF_inst5;
wire SYNTHESIZED_WIRE_0;
 
assign nWAIT_M1 = DFF_inst2;
 
 
 
assign SYNTHESIZED_WIRE_0 = ~SYNTHESIZED_WIRE_1;
 
 
always@(posedge CLK or negedge DFF_inst3)
begin
if (!DFF_inst3)
begin
DFF_inst2 <= 1;
end
else
begin
DFF_inst2 <= nM1;
end
end
 
 
always@(posedge CLK)
begin
begin
DFF_inst3 <= DFF_inst2;
end
end
 
 
always@(posedge CLK)
begin
begin
SYNTHESIZED_WIRE_1 <= nMREQ;
end
end
 
 
always@(posedge CLK)
begin
begin
DFF_inst5 <= SYNTHESIZED_WIRE_1;
end
end
 
assign nWAIT_Mem = ~(DFF_inst5 & SYNTHESIZED_WIRE_0);
 
 
endmodule
/trunk/host/zxspectrum_de1/rom/combined.rom Cannot display: file marked as a binary type. svn:mime-type = application/octet-stream
/trunk/host/zxspectrum_de1/ula/ula.sv
147,7 → 147,7
ula_data = 8'hFF;
// Regular IO at every odd address: line-in and keyboard
if (A[0]==0) begin
ula_data = { 1'b0, pcm_inl[14] | pcm_inr[14], 1'b0, key_row[4:0] };
ula_data = { 1'b1, pcm_inl[14] | pcm_inr[14], 1'b1, key_row[4:0] };
end
end
 
/trunk/host/zxspectrum_de1/ula/zx_kbd.sv
54,9 → 54,9
//~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
//
//~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
reg [4:0] keys [0:7]; // 8 rows of 5 bits each
reg [4:0] keys [0:7]; // 8 rows of 5 bits each: contains 0 for a pressed key at a specific location, 1 otherwise
 
reg released; // Tracks "released" scan code (F0)
reg released; // Tracks "released" scan code (F0): contains 0 when a key is pressed, 1 otherwise
reg extended; // Tracks "extended" scan code (E0)
reg shifted; // Tracks local "shifted" state
 
91,9 → 91,9
keys[7] <= '1;
end else
if (scan_code_ready) begin
if (scan_code==8'hE0)
if (scan_code==8'hE0) // Extended code prefix byte
extended <= 1;
else if (scan_code==8'hF0)
else if (scan_code==8'hF0) // Break code prefix byte
released <= 1;
else begin
// Cancel release/extended flags for the next clock
123,7 → 123,6
end
else begin
// For each PS/2 scan-code, set the ZX keyboard matrix state
// 'released' contains 0 when a key is pressed; 1 otherwise
case (scan_code)
8'h12: shifted <= !released; // Local SHIFT key (left)
8'h59: shifted <= !released; // Local SHIFT key (right)
185,76 → 184,43
keys[0][0] <= released; // CAPS SHIFT
keys[7][0] <= released; // SPACE
end
// With shifted keys, we need to make inactive (set to 1) other corresponding key
// Otherwise, it will stay active if the shift was released first
8'h4E: begin // - or (shifted) _
if (!shifted) begin
keys[7][1] <= released; // SYMBOL SHIFT (Red)
keys[6][3] <= released; // J
keys[7][1] <= released; // SYMBOL SHIFT (Red)
keys[4][0] <= shifted ? released : 1; // 0
keys[6][3] <= shifted ? 1 : released; // J
end
else begin
keys[7][1] <= released; // SYMBOL SHIFT (Red)
keys[4][0] <= released; // 0
end
end
8'h55: begin // = or (shifted) +
if (!shifted) begin
keys[7][1] <= released; // SYMBOL SHIFT (Red)
keys[6][1] <= released; // L
keys[7][1] <= released; // SYMBOL SHIFT (Red)
keys[6][2] <= shifted ? released : 1; // K
keys[6][1] <= shifted ? 1 : released; // L
end
else begin
keys[7][1] <= released; // SYMBOL SHIFT (Red)
keys[6][2] <= released; // K
end
end
8'h52: begin // ' or (shifted) "
if (!shifted) begin
keys[7][1] <= released; // SYMBOL SHIFT (Red)
keys[4][3] <= released; // 7
keys[7][1] <= released; // SYMBOL SHIFT (Red)
keys[5][0] <= shifted ? released : 1; // P
keys[4][3] <= shifted ? 1 : released; // 7
end
else begin
keys[7][1] <= released; // SYMBOL SHIFT (Red)
keys[5][0] <= released; // P
end
end
8'h4C: begin // ; or (shifted) :
if (!shifted) begin
keys[7][1] <= released; // SYMBOL SHIFT (Red)
keys[5][1] <= released; // O
keys[7][1] <= released; // SYMBOL SHIFT (Red)
keys[0][1] <= shifted ? released : 1; // Z
keys[5][1] <= shifted ? 1 : released; // O
end
else begin
keys[7][1] <= released; // SYMBOL SHIFT (Red)
keys[0][1] <= released; // Z
end
end
8'h41: begin // , or (shifted) <
if (!shifted) begin
keys[7][1] <= released; // SYMBOL SHIFT (Red)
keys[7][3] <= released; // N
keys[7][1] <= released; // SYMBOL SHIFT (Red)
keys[2][3] <= shifted ? released : 1; // R
keys[7][3] <= shifted ? 1 : released; // N
end
else begin
keys[7][1] <= released; // SYMBOL SHIFT (Red)
keys[2][3] <= released; // R
end
end
8'h49: begin // . or (shifted) >
if (!shifted) begin
keys[7][1] <= released; // SYMBOL SHIFT (Red)
keys[7][2] <= released; // M
keys[7][1] <= released; // SYMBOL SHIFT (Red)
keys[2][4] <= shifted ? released : 1; // T
keys[7][2] <= shifted ? 1 : released; // M
end
else begin
keys[7][1] <= released; // SYMBOL SHIFT (Red)
keys[2][4] <= released; // T
end
end
8'h4A: begin // / or (shifted) ?
if (!shifted) begin
keys[7][1] <= released; // SYMBOL SHIFT (Red)
keys[0][4] <= released; // V
keys[7][1] <= released; // SYMBOL SHIFT (Red)
keys[0][3] <= shifted ? released : 1; // C
keys[0][4] <= shifted ? 1 : released; // V
end
else begin
keys[7][1] <= released; // SYMBOL SHIFT (Red)
keys[0][3] <= released; // C
end
end
endcase
end
end

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