URL
https://opencores.org/ocsvn/a-z80/a-z80/trunk
Subversion Repositories a-z80
Compare Revisions
- This comparison shows the changes necessary to convert path
/a-z80
- from Rev 6 to Rev 7
- ↔ Reverse comparison
Rev 6 → Rev 7
/trunk/cpu/control/timing_macros.i
42,6 → 42,7
ZF setM1=flags_zf; // Used in DJNZ |
BR setM1=nonRep | !repeat_en; |
BRZ setM1=nonRep | !repeat_en | flags_zf; |
BZ setM1=nonRep | flags_zf; |
INT setM1=!(in_intr & im2); // RST38 interrupt extension |
|
//----------------------------------------------------------------------------------------- |
/trunk/cpu/control/Timings.csv
847,10 → 847,10
#043H T9 AB:000 DB:-- RD IORQ 2 4 fIORead mw d < R alu >s0 bus S NEG_OP2 |
#044H T10 AB:000 DB:-- 3 1 fMWrite HL W |
#045H T11 AB:000 DB:B1 MREQ 3 2 fMWrite HL op3 R |
#046H T12 AB:000 DB:B1 MREQ WR 3 3 fMWrite 1 BRZ B >s0 L XOR |
#047H T13 AB:000 DB:-- 4 1 PC - W |
#046H T12 AB:000 DB:B1 MREQ WR 3 3 fMWrite 1 BZ |
#047H T13 AB:000 DB:-- 4 1 PC W |
#048H T14 AB:000 DB:-- 4 2 PC - R |
#049H T15 AB:000 DB:-- 4 3 PC - W |
#049H T15 AB:000 DB:-- 4 3 PC W |
#050H T16 AB:000 DB:-- 4 4 PC - R |
#051H T17 AB:000 DB:-- 4 5 1 1 |
#end |
867,10 → 867,10
#043H T9 AB:000 DB:-- 3 1 fIOWrite BC W |
#044H T10 AB:000 DB:21 WR IORQ 3 2 fIOWrite d < R alu >s0 bus L ADD * S |
#045H T11 AB:000 DB:21 WR IORQ 3 3 fIOWrite alu < res H ADD * |
#046H T12 AB:000 DB:21 WR IORQ 3 4 fIOWrite 1 BRZ B > >s0 L XOR |
#047H T13 AB:000 DB:-- 4 1 PC - W |
#046H T12 AB:000 DB:21 WR IORQ 3 4 fIOWrite 1 BZ |
#047H T13 AB:000 DB:-- 4 1 PC W |
#048H T14 AB:000 DB:-- 4 2 PC - R |
#049H T15 AB:000 DB:-- 4 3 PC - W |
#049H T15 AB:000 DB:-- 4 3 PC W |
#050H T16 AB:000 DB:-- 4 4 PC - R |
#051H T17 AB:000 DB:-- 4 5 1 1 |
#end |
/trunk/cpu/control/exec_matrix.vh
2989,14 → 2989,9
ctl_reg_gp_we=1; ctl_reg_gp_sel=`GP_REG_HL; ctl_reg_gp_hilo=2'b11; ctl_sw_4u=1; /* Write 16-bit HL, enable SW4 upstream */ |
ctl_inc_cy=pc_inc; ctl_inc_dec=op3; /* Decrement if op3 is set; increment otherwise */ |
ctl_bus_inc_oe=1; /* Output enable incrementer to the register bus */ end |
if (M3 && T3) begin fMWrite=1; nextM=1; setM1=nonRep | !repeat_en | flags_zf; |
ctl_reg_gp_sel=`GP_REG_BC; ctl_reg_gp_hilo=2'b10; |
ctl_alu_shift_oe=!ctl_alu_bs_oe; /* Shifter unit without shift-enable */ |
ctl_alu_op_low=1; /* Activate ALU operation on low nibble */ |
ctl_alu_core_R=1; ctl_alu_core_V=0; ctl_alu_core_S=0; ctl_flags_cf_set=1; ctl_flags_cf_cpl=1; end |
if (M3 && T3) begin fMWrite=1; nextM=1; setM1=nonRep | flags_zf; end |
if (M4 && T1) begin |
ctl_reg_sel_pc=1; ctl_reg_sys_hilo=2'b11; /* Select 16-bit PC */ |
ctl_inc_cy=pc_inc; ctl_inc_dec=1; /* Decrement */ |
ctl_al_we=1; /* Write a value from the register bus to the address latch */ end |
if (M4 && T2) begin |
ctl_reg_sys_we=1; ctl_reg_sel_pc=1; ctl_reg_sys_hilo=2'b11; pc_inc=!(in_halt | in_intr | in_nmi); /* Write 16-bit PC and control incrementer */ |
3004,7 → 2999,6
ctl_bus_inc_oe=1; /* Output enable incrementer to the register bus */ end |
if (M4 && T3) begin |
ctl_reg_sel_pc=1; ctl_reg_sys_hilo=2'b11; /* Select 16-bit PC */ |
ctl_inc_cy=pc_inc; ctl_inc_dec=1; /* Decrement */ |
ctl_al_we=1; /* Write a value from the register bus to the address latch */ end |
if (M4 && T4) begin |
ctl_reg_sys_we=1; ctl_reg_sel_pc=1; ctl_reg_sys_hilo=2'b11; pc_inc=!(in_halt | in_intr | in_nmi); /* Write 16-bit PC and control incrementer */ |
3118,15 → 3112,9
ctl_alu_core_hf=1; |
end |
ctl_flags_cf_we=1; end |
if (M3 && T4) begin fIOWrite=1; nextM=1; setM1=nonRep | !repeat_en | flags_zf; |
ctl_reg_gp_sel=`GP_REG_BC; ctl_reg_gp_hilo=2'b10; |
ctl_reg_out_hi=1; ctl_reg_out_lo=1; /* From the register file into the ALU */ |
ctl_alu_shift_oe=!ctl_alu_bs_oe; /* Shifter unit without shift-enable */ |
ctl_alu_op_low=1; /* Activate ALU operation on low nibble */ |
ctl_alu_core_R=1; ctl_alu_core_V=0; ctl_alu_core_S=0; ctl_flags_cf_set=1; ctl_flags_cf_cpl=1; end |
if (M3 && T4) begin fIOWrite=1; nextM=1; setM1=nonRep | flags_zf; end |
if (M4 && T1) begin |
ctl_reg_sel_pc=1; ctl_reg_sys_hilo=2'b11; /* Select 16-bit PC */ |
ctl_inc_cy=pc_inc; ctl_inc_dec=1; /* Decrement */ |
ctl_al_we=1; /* Write a value from the register bus to the address latch */ end |
if (M4 && T2) begin |
ctl_reg_sys_we=1; ctl_reg_sel_pc=1; ctl_reg_sys_hilo=2'b11; pc_inc=!(in_halt | in_intr | in_nmi); /* Write 16-bit PC and control incrementer */ |
3134,7 → 3122,6
ctl_bus_inc_oe=1; /* Output enable incrementer to the register bus */ end |
if (M4 && T3) begin |
ctl_reg_sel_pc=1; ctl_reg_sys_hilo=2'b11; /* Select 16-bit PC */ |
ctl_inc_cy=pc_inc; ctl_inc_dec=1; /* Decrement */ |
ctl_al_we=1; /* Write a value from the register bus to the address latch */ end |
if (M4 && T4) begin |
ctl_reg_sys_we=1; ctl_reg_sel_pc=1; ctl_reg_sys_hilo=2'b11; pc_inc=!(in_halt | in_intr | in_nmi); /* Write 16-bit PC and control incrementer */ |
/trunk/cpu/control/Timings.xlsm
Cannot display: file marked as a binary type.
svn:mime-type = application/octet-stream
/trunk/cpu/deploy/exec_matrix.vh
2989,14 → 2989,9
ctl_reg_gp_we=1; ctl_reg_gp_sel=`GP_REG_HL; ctl_reg_gp_hilo=2'b11; ctl_sw_4u=1; /* Write 16-bit HL, enable SW4 upstream */ |
ctl_inc_cy=pc_inc; ctl_inc_dec=op3; /* Decrement if op3 is set; increment otherwise */ |
ctl_bus_inc_oe=1; /* Output enable incrementer to the register bus */ end |
if (M3 && T3) begin fMWrite=1; nextM=1; setM1=nonRep | !repeat_en | flags_zf; |
ctl_reg_gp_sel=`GP_REG_BC; ctl_reg_gp_hilo=2'b10; |
ctl_alu_shift_oe=!ctl_alu_bs_oe; /* Shifter unit without shift-enable */ |
ctl_alu_op_low=1; /* Activate ALU operation on low nibble */ |
ctl_alu_core_R=1; ctl_alu_core_V=0; ctl_alu_core_S=0; ctl_flags_cf_set=1; ctl_flags_cf_cpl=1; end |
if (M3 && T3) begin fMWrite=1; nextM=1; setM1=nonRep | flags_zf; end |
if (M4 && T1) begin |
ctl_reg_sel_pc=1; ctl_reg_sys_hilo=2'b11; /* Select 16-bit PC */ |
ctl_inc_cy=pc_inc; ctl_inc_dec=1; /* Decrement */ |
ctl_al_we=1; /* Write a value from the register bus to the address latch */ end |
if (M4 && T2) begin |
ctl_reg_sys_we=1; ctl_reg_sel_pc=1; ctl_reg_sys_hilo=2'b11; pc_inc=!(in_halt | in_intr | in_nmi); /* Write 16-bit PC and control incrementer */ |
3004,7 → 2999,6
ctl_bus_inc_oe=1; /* Output enable incrementer to the register bus */ end |
if (M4 && T3) begin |
ctl_reg_sel_pc=1; ctl_reg_sys_hilo=2'b11; /* Select 16-bit PC */ |
ctl_inc_cy=pc_inc; ctl_inc_dec=1; /* Decrement */ |
ctl_al_we=1; /* Write a value from the register bus to the address latch */ end |
if (M4 && T4) begin |
ctl_reg_sys_we=1; ctl_reg_sel_pc=1; ctl_reg_sys_hilo=2'b11; pc_inc=!(in_halt | in_intr | in_nmi); /* Write 16-bit PC and control incrementer */ |
3118,15 → 3112,9
ctl_alu_core_hf=1; |
end |
ctl_flags_cf_we=1; end |
if (M3 && T4) begin fIOWrite=1; nextM=1; setM1=nonRep | !repeat_en | flags_zf; |
ctl_reg_gp_sel=`GP_REG_BC; ctl_reg_gp_hilo=2'b10; |
ctl_reg_out_hi=1; ctl_reg_out_lo=1; /* From the register file into the ALU */ |
ctl_alu_shift_oe=!ctl_alu_bs_oe; /* Shifter unit without shift-enable */ |
ctl_alu_op_low=1; /* Activate ALU operation on low nibble */ |
ctl_alu_core_R=1; ctl_alu_core_V=0; ctl_alu_core_S=0; ctl_flags_cf_set=1; ctl_flags_cf_cpl=1; end |
if (M3 && T4) begin fIOWrite=1; nextM=1; setM1=nonRep | flags_zf; end |
if (M4 && T1) begin |
ctl_reg_sel_pc=1; ctl_reg_sys_hilo=2'b11; /* Select 16-bit PC */ |
ctl_inc_cy=pc_inc; ctl_inc_dec=1; /* Decrement */ |
ctl_al_we=1; /* Write a value from the register bus to the address latch */ end |
if (M4 && T2) begin |
ctl_reg_sys_we=1; ctl_reg_sel_pc=1; ctl_reg_sys_hilo=2'b11; pc_inc=!(in_halt | in_intr | in_nmi); /* Write 16-bit PC and control incrementer */ |
3134,7 → 3122,6
ctl_bus_inc_oe=1; /* Output enable incrementer to the register bus */ end |
if (M4 && T3) begin |
ctl_reg_sel_pc=1; ctl_reg_sys_hilo=2'b11; /* Select 16-bit PC */ |
ctl_inc_cy=pc_inc; ctl_inc_dec=1; /* Decrement */ |
ctl_al_we=1; /* Write a value from the register bus to the address latch */ end |
if (M4 && T4) begin |
ctl_reg_sys_we=1; ctl_reg_sel_pc=1; ctl_reg_sys_hilo=2'b11; pc_inc=!(in_halt | in_intr | in_nmi); /* Write 16-bit PC and control incrementer */ |