URL
https://opencores.org/ocsvn/ahb2wishbone/ahb2wishbone/trunk
Subversion Repositories ahb2wishbone
Compare Revisions
- This comparison shows the changes necessary to convert path
/
- from Rev 5 to Rev 6
- ↔ Reverse comparison
Rev 5 → Rev 6
/trunk/src/ahb2wb.v
100,8 → 100,9
hresp <= 2'b00; |
cyc_o <= 'b0; |
stb_o <= 'b0; |
addr_temp <= 'b0; |
hwrite_temp <= 'b0; |
addr_temp <= 'bx; |
hwrite_temp <= 'bx; |
dat_o <='bx; |
end |
else if(hready & hsel) begin |
case (hburst) |
147,7 → 148,7
always@(hwrite_temp or hwdata or dat_i or ack_i or hresetn or stb_o ) begin |
|
if (!hresetn) begin |
hready <= 'b1; |
hready <= 'b1; |
end |
else begin |
if (stb_o) |
/trunk/svtb/Readme.doc
Cannot display: file marked as a binary type.
svn:mime-type = application/octet-stream
trunk/svtb/Readme.doc
Property changes :
Added: svn:mime-type
## -0,0 +1 ##
+application/octet-stream
\ No newline at end of property
Index: trunk/svtb/avm_svtb/ahb_wb_responder.svh
===================================================================
--- trunk/svtb/avm_svtb/ahb_wb_responder.svh (nonexistent)
+++ trunk/svtb/avm_svtb/ahb_wb_responder.svh (revision 6)
@@ -0,0 +1,89 @@
+//////////////////////////////////////////////////////////////////////////////////////////////////////////////////
+//*****************************************************************************************************************
+// Copyright (c) 2007 TooMuch Semiconductor Solutions Pvt Ltd.
+//
+//File name : ahb_wb_responder.svh
+//Designer : Sanjay kumar
+//Date : 3rd Aug'2007
+//Description : ahb_wb_responder:Class to respond for the request sent by AHB Master and to generate
+// wait state by Wishbone slave.
+//Revision : 1.0
+//*****************************************************************************************************************
+///////////////////////////////////////////////////////////////////////////////////////////////////////////////////
+
+import avm_pkg::*;
+import global::*;
+
+class ahb_wb_responder extends avm_threaded_component;
+
+int cnt;
+virtual ahb_wb_if pin_if;
+
+ function new(string name ,avm_named_component parent);
+ super.new(name,parent);
+ pin_if =null;
+ endfunction
+
+
+task run;
+ forever
+ begin
+ @(pin_if.slave_bw.adr_o or pin_if.slave_bw.we_o);
+ if(!pin_if.master_ab.hresetn)
+ begin
+ pin_if.slave_bw.ack_i='b0;
+ pin_if.slave_bw.dat_i='bx;
+ end
+ else
+ if(! pin_if.slave_bw.we_o)
+ pin_if.slave_bw.dat_i=pin_if.slave_bw.adr_o;
+ end
+endtask
+
+// wait state asserted by slave
+task wait_state_by_slave;
+ pin_if.slave_bw.ack_i='b1;
+ do
+ begin
+ @(posedge pin_if.master_ab.hclk);
+ cnt++;
+ end
+ while (cnt <= 7);
+
+ #2 pin_if.slave_bw.ack_i='b0; // 8 clock cycle asserted
+ //avm_report_message("Responder: Wait state asserted in Write mode ","by slave");
+ cnt=0;
+ do
+ begin
+ @(posedge pin_if.master_ab.hclk);
+ cnt++;
+ end
+ while (cnt <= 4);
+ #2 pin_if.slave_bw.ack_i='b1; // 5 clock cycle deasserted
+ //avm_report_message("Responder: Wait state deasserted in write mode ","by slave");
+ cnt=0;
+ do
+ begin
+ @(posedge pin_if.master_ab.hclk);
+ cnt++;
+ end
+ while (cnt <= 44);
+
+ #2 pin_if.slave_bw.ack_i='b0; // 25 clock cycle asserted
+ //avm_report_message("Responder: Wait state asserted in Read mode ","by slave");
+ cnt=0;
+ do
+ begin
+ @(posedge pin_if.master_ab.hclk);
+ cnt++;
+ end
+ while (cnt <= 4);
+ #2 pin_if.slave_bw.ack_i='b1; // 5 clock cycle deasserted
+ //avm_report_message("Responder: Wait state deasserted in Read mode ","by slave");
+endtask
+
+
+endclass
+
+
+
Index: trunk/svtb/avm_svtb/ahb_wb_master.sv
===================================================================
--- trunk/svtb/avm_svtb/ahb_wb_master.sv (nonexistent)
+++ trunk/svtb/avm_svtb/ahb_wb_master.sv (revision 6)
@@ -0,0 +1,54 @@
+//////////////////////////////////////////////////////////////////////////////////////////////////////////////////
+//*****************************************************************************************************************
+// Copyright (c) 2007 TooMuch Semiconductor Solutions Pvt Ltd.
+//
+//File name : ahb_wb_master.sv
+//Designer : Sanjay kumar
+//Date : 3rd Aug'2007
+//Description : stimulus_gen:This module perform reset and initial signal setup for the testbench.
+//Revision : 1.0
+//*****************************************************************************************************************
+///////////////////////////////////////////////////////////////////////////////////////////////////////////////////
+
+import global::*;
+`timescale 1 ns/1 ps
+
+module stimulus_gen( ahb_wb_if.master_ab m_ab,
+ input bit clk,
+ input bit reset);
+
+
+//******************************************
+// assign input clk and reset to stimulus gen
+//******************************************
+
+ assign m_ab.hclk = clk;
+ assign m_ab.hresetn = reset;
+
+always@(posedge m_ab.hclk)
+ if (!m_ab.hresetn)
+ begin
+ m_ab.htrans='b00;
+ m_ab.haddr='bx;
+ m_ab.hwdata='bx;
+ end
+
+
+//******************************************
+// initial signal setups
+//******************************************
+task initial_setup;
+ begin
+ @(posedge m_ab.hclk);
+ #2 m_ab.hsel ='b1; // slave selected (only one)
+ m_ab.hburst ='b000; // single transfer
+ m_ab.hsize ='b010; // 32 bit size bursting
+ m_ab.hwrite ='b0;
+ m_ab.htrans ='b10;
+ end
+endtask
+
+
+
+endmodule
+
Index: trunk/svtb/avm_svtb/ahb_wb_scoreboard.svh
===================================================================
--- trunk/svtb/avm_svtb/ahb_wb_scoreboard.svh (nonexistent)
+++ trunk/svtb/avm_svtb/ahb_wb_scoreboard.svh (revision 6)
@@ -0,0 +1,127 @@
+//////////////////////////////////////////////////////////////////////////////////////////////////////////////////
+//*****************************************************************************************************************
+// Copyright (c) 2007 TooMuch Semiconductor Solutions Pvt Ltd.
+//
+//File name : ahb_wb_scoreboard.svh
+//Designer : Sanjay kumar
+//Date : 3rd Aug'2007
+//Description : ahb_wb_:Class to receive monitor packet from the publisher(monitor) and check for
+// protocol matching.
+//Revision : 1.0
+//*****************************************************************************************************************
+///////////////////////////////////////////////////////////////////////////////////////////////////////////////////
+
+import avm_pkg::*;
+import global::*;
+
+class ahb_wb_scoreboard extends avm_threaded_component;
+
+analysis_fifo#(monitor_pkt) ap_fifo; // analysis port fifo
+analysis_if#(monitor_pkt) ap_if; // analysis port interface
+// local variables
+logic [AWIDTH-1:0]adr1;
+logic [AWIDTH-1:0]adr2;
+logic [DWIDTH-1:0]dat1;
+logic [DWIDTH-1:0]dat2;
+// monitor packet
+monitor_pkt m_pkt;
+
+virtual ahb_wb_if pin_if;
+
+ function new(string name ,avm_named_component parent);
+ super.new(name,parent);
+ ap_fifo =new("ap_fifo",this);
+ ap_if =null;
+ pin_if =null;
+ //avm_report_severity_action(MESSAGE,NO_ACTION);
+ endfunction
+
+// connecting analysis fifo to the analysis interface
+function void export_connections();
+ ap_if = ap_fifo.analysis_export;
+endfunction
+
+
+task run;
+ forever
+ begin
+ ap_fifo.get(m_pkt);
+ if(m_pkt.sel && (m_pkt.mode == 'b10)) //No wait state
+ if(m_pkt.wr) //write mode
+ if(m_pkt.flag1) // first clock no comaprison only sampling the values
+ adr1=m_pkt.adr1;
+ else
+ if(m_pkt.flag2) // first clock after after wait state
+ begin
+ if((( adr1==m_pkt.adr1) && (dat1==m_pkt.dat1) && (adr2==m_pkt.adr2) && (dat2==m_pkt.dat2)) || (( adr1 === m_pkt.adr2 ) && (m_pkt.dat1 === m_pkt.dat2)));
+ //avm_report_message("Scoreboard: Write Passed","after wait state");
+ else
+ avm_report_warning("Scoreboard: Error in write after wait state",display_pkt(m_pkt));
+ adr1=m_pkt.adr1; // Holding the previous address
+ end
+ else
+
+ begin
+ if(( adr1 === m_pkt.adr2 ) && (m_pkt.dat1 === m_pkt.dat2));
+ //avm_report_message("Scoreboard: Write Passed","without wait state");
+ else
+ begin
+ avm_report_warning("Scoreboard: Error in write without wait state",display_pkt(m_pkt));
+ end
+ adr1=m_pkt.adr1;
+ end
+ else// read mode
+ if(m_pkt.flag1) // first clock no comaprison only sampling the values
+ adr1=m_pkt.adr1;
+ else
+ if(m_pkt.flag2) // first clock after after wait state
+ begin
+ if((( adr1==m_pkt.adr1) && (dat1==m_pkt.dat1) && (adr2==m_pkt.adr2) && (dat2==m_pkt.dat2)) || (( adr1 === m_pkt.adr2 ) && (m_pkt.dat1 === m_pkt.dat2)));
+ //avm_report_message("Scoreboard: Read Passed","after wait state");
+ else
+ avm_report_warning("Scoreboard: Error in read after wait state",display_pkt(m_pkt));
+ adr1=m_pkt.adr1;
+ end
+
+ else
+ begin
+ if(( adr1 === m_pkt.adr2 ) && (m_pkt.dat1 === m_pkt.dat2)); // comparing unknown values too
+ //avm_report_message("Scoreboard: Read Passed","without wait state");
+ else
+ begin
+ avm_report_warning("Scoreboard: Error in read without wait state",display_pkt(m_pkt));
+ end
+ adr1=m_pkt.adr1;
+ end
+ else // wait state by slave or master
+ if(m_pkt.flag2) // latch the value
+ begin
+ adr1=m_pkt.adr1;
+ dat1=m_pkt.dat1;
+ adr2=m_pkt.adr2;
+ dat2=m_pkt.dat2;
+ end
+ else
+ if(( adr1==m_pkt.adr1) && (dat1==m_pkt.dat1) && (adr2==m_pkt.adr2) && (dat2==m_pkt.dat2));
+ //$display("Passed wait");
+ //avm_report_message("Scoreboard: Passed","with wait state");
+ else
+ begin
+ avm_report_warning("Scoreboard: Error in with wait state",display_pkt(m_pkt));
+ end
+
+ end
+endtask
+
+// function to display values at any instant :)
+function string display_pkt(input monitor_pkt m);
+ string s;
+ $sformat(s,"current_adr1=%0d,adr1=%0d,adr2=%0d,dat1=%0d,dat2=%0d,wr=%0b,mode=%0b,sel=%0b,f1=%b,f2=%b",adr1,m.adr1,m.adr2,m.dat1,m.dat2,m.wr,m.mode,m.sel,m.flag1,m.flag2);
+ return s;
+endfunction
+
+
+endclass
+
+
+
Index: trunk/svtb/avm_svtb/ahb_wb_stim_gen.svh
===================================================================
--- trunk/svtb/avm_svtb/ahb_wb_stim_gen.svh (nonexistent)
+++ trunk/svtb/avm_svtb/ahb_wb_stim_gen.svh (revision 6)
@@ -0,0 +1,105 @@
+//////////////////////////////////////////////////////////////////////////////////////////////////////////////////
+//*****************************************************************************************************************
+// Copyright (c) 2007 TooMuch Semiconductor Solutions Pvt Ltd.
+//
+//File name : ahb_wb_stim_gen.svh
+//Designer : Sanjay kumar
+//Date : 3rd Aug'2007
+//Description : ahb_wb_stim_gen:Class to generata write and read packet with wait state by master.
+//Revision : 1.0
+//*****************************************************************************************************************
+///////////////////////////////////////////////////////////////////////////////////////////////////////////////////
+
+import avm_pkg::*;
+import global::*;
+
+class ahb_wb_stim_gen extends avm_named_component;
+
+// communication port
+avm_blocking_put_port#( ahb_req_pkt) initiator_port;
+tlm_fifo #(ahb_req_pkt) fifo;
+
+ function new(string name ,avm_named_component parent);
+ super.new(name,parent);
+ initiator_port=new("initiatot_port",this);
+ fifo =new("fifo",this);
+ endfunction
+
+task stimulus(input int count= 45);
+ ahb_req_pkt p;
+ //(write operation) write data and addr. to fifo
+ for(int i=0; i15 && i<21)// busy mode
+ begin
+ p.mode='b01;
+ p.wr='b1;
+ end
+ else if(i>26 && i<31) // idle mode
+ begin
+ p.mode='b00;
+ p.wr='b1;
+ end
+ else if(i>30 && i<36) // Sequential mode
+ begin
+ p.mode='b11;
+ p.wr='b1;
+ end
+ else // Non sequential mode
+ begin
+ p.mode='b10;
+ p.adr=$random;
+ p.dat=$random;
+ p.wr='b1;
+ end
+ write_to_pipe(p);
+ end
+ //(read operation) write address to fifo for read
+ for(int i=0; i10 && i<16) // busy mode
+ begin
+ p.mode='b01;
+ p.wr='b0;
+ end
+ else if(i>20 && i<26) // idle mode
+ begin
+ p.mode='b00;
+ p.wr='b0;
+ end
+ else if(i>25 && i<31) // Sequential mode
+ begin
+ p.mode='b11;
+ p.wr='b0;
+ end
+ else //Non Sequential mode
+ begin
+ p.mode='b10;
+ p.adr=$random;
+ p.wr='b0;
+ end
+ write_to_pipe(p);
+ end
+ // write operation
+ for(int i=0; i<(count-30) ;i++)
+ begin
+ if(i>=0 && i<(count-30))
+ begin
+ p.mode='b10;
+ p.adr=$random;
+ p.dat=$random;
+ p.wr='b1;
+ end
+ write_to_pipe(p);
+ end
+endtask
+
+// task to push transaction in the fifo
+task write_to_pipe(ahb_req_pkt p);
+ initiator_port.put(p);
+ //avm_report_message("Stim_gen: Packet pushed into fifo",global::convert2string(p));
+
+endtask
+
+
+endclass
Index: trunk/svtb/avm_svtb/global.sv
===================================================================
--- trunk/svtb/avm_svtb/global.sv (nonexistent)
+++ trunk/svtb/avm_svtb/global.sv (revision 6)
@@ -0,0 +1,39 @@
+// package decleration
+package global;
+
+parameter int DWIDTH =32;
+parameter int AWIDTH =16;
+parameter int cyc_prd = 10;
+
+typedef struct {
+ rand logic [AWIDTH-1:0]adr;
+ rand logic [DWIDTH-1:0]dat;
+ logic [1:0] mode; // htrans
+ logic wr; // hwrite
+} ahb_req_pkt;
+
+typedef struct {
+ rand logic [DWIDTH-1:0]dat;
+ logic rdy;// hready
+} ahb_res_pkt;
+
+typedef struct {
+ bit flag1;
+ bit flag2;
+ logic wr;
+ logic sel;
+ logic [1:0]mode;
+ logic [AWIDTH-1:0]adr1;
+ logic [AWIDTH-1:0]adr2;
+ logic [DWIDTH-1:0]dat1;
+ logic [DWIDTH-1:0]dat2;
+} monitor_pkt;
+// convert to strings
+function string convert2string(ahb_req_pkt p);
+string s;
+ $sformat(s,"adr:%0d dat:%0d mst_mode:%0d Wr_Rd:%0d",p.adr,p.dat,p.mode,p.wr);
+ return s;
+endfunction
+
+
+endpackage
Index: trunk/svtb/avm_svtb/ahb_wb_monitor.svh
===================================================================
--- trunk/svtb/avm_svtb/ahb_wb_monitor.svh (nonexistent)
+++ trunk/svtb/avm_svtb/ahb_wb_monitor.svh (revision 6)
@@ -0,0 +1,185 @@
+///////////////////////////////////////////////////////////////////////////////////////////////////////////////////
+//*****************************************************************************************************************
+// Copyright (c) 2007 TooMuch Semiconductor Solutions Pvt Ltd.
+//
+//File name : ahb_wb_monitor.svh
+//Designer : Sanjay kumar
+//Date : 3rd Aug'2007
+//Description : ahb_wb_monitor:Class to monitor transaction on interface and send a copy of monitor
+// packets to each subscribers(scoreboard and coverage).
+//Revision : 1.0
+//*****************************************************************************************************************
+///////////////////////////////////////////////////////////////////////////////////////////////////////////////////
+
+import avm_pkg::*;
+import global::*;
+
+class ahb_wb_monitor extends avm_threaded_component;
+
+avm_analysis_port#(monitor_pkt) ap_sb; // analysis port
+monitor_pkt m_pkt; // instance of packet
+
+local bit flag1;
+local bit flag2;
+
+virtual ahb_wb_if pin_if;
+
+ function new(string name ,avm_named_component parent);
+ super.new(name,parent);
+ ap_sb = new("ap_sb",this);
+ pin_if =null;
+ endfunction
+// task to monitor event on read/write signal
+task rdwr;
+ forever
+ begin
+ @(pin_if.monitor.hwrite);
+ flag1='b1;
+ end
+endtask
+// task to monitor event on hready or htrans (wait state)
+task wait_ms;
+ forever
+ begin
+ @(pin_if.monitor.hready or pin_if.monitor.htrans);
+ flag2='b1;
+ end
+endtask
+
+task main_run;
+ forever
+ begin
+ @(posedge pin_if.monitor.hclk);
+ if((pin_if.monitor.hready) && (pin_if.monitor.htrans == 'b10)) //No wait state
+ begin
+ if(pin_if.monitor.hwrite) //write mode
+ begin
+ if(flag1) // first clock
+ begin
+ m_pkt.adr1=pin_if.monitor.haddr;
+ m_pkt.wr='b1;
+ m_pkt.sel=pin_if.monitor.hready;
+ m_pkt.mode=pin_if.monitor.htrans;
+ m_pkt.flag1='b1;
+ // write packet to scoreboard
+ ap_sb.write(m_pkt);
+ flag1='b0;
+ end
+ else
+ begin
+ m_pkt.adr1=pin_if.monitor.haddr;
+ m_pkt.dat1=pin_if.monitor.hwdata;
+ m_pkt.adr2=pin_if.monitor.adr_o;
+ m_pkt.dat2=pin_if.monitor.dat_o;
+ m_pkt.wr='b1;
+ m_pkt.sel=pin_if.monitor.hready;
+ m_pkt.mode=pin_if.monitor.htrans;
+ m_pkt.flag1='b0;
+ m_pkt.flag2=flag2;
+ ap_sb.write(m_pkt);
+ end
+ end
+ else// read mode
+ begin
+ if(flag1) // first clock
+ begin
+ m_pkt.adr1=pin_if.monitor.haddr;
+ m_pkt.wr='b0;
+ m_pkt.sel=pin_if.monitor.hready;
+ m_pkt.mode=pin_if.monitor.htrans;
+ m_pkt.flag1='b1;
+ //write packet to scoreboard
+ ap_sb.write(m_pkt);
+ flag1='b0;
+ end
+ else
+ begin
+ m_pkt.adr1=pin_if.monitor.haddr;
+ m_pkt.dat1=pin_if.monitor.hrdata;
+ m_pkt.adr2=pin_if.monitor.adr_o;
+ m_pkt.dat2=pin_if.monitor.dat_i;
+ m_pkt.wr='b0;
+ m_pkt.sel=pin_if.monitor.hready;
+ m_pkt.mode=pin_if.monitor.htrans;
+ m_pkt.flag1='b0;
+ m_pkt.flag2=flag2;
+ // write packet to scoreboard
+ ap_sb.write(m_pkt);
+ end
+ end
+ end
+ else // wait state by slave or master
+ begin
+ if(pin_if.monitor.hwrite) // write mode
+ begin
+ if(flag2) // latch the value
+ begin
+ m_pkt.adr1=pin_if.monitor.haddr;
+ m_pkt.dat1=pin_if.monitor.hwdata;
+ m_pkt.adr2=pin_if.monitor.adr_o;
+ m_pkt.dat2=pin_if.monitor.dat_o;
+ m_pkt.wr='b1;
+ m_pkt.sel=pin_if.monitor.hready;
+ m_pkt.mode=pin_if.monitor.htrans;
+ m_pkt.flag2='b1;
+ ap_sb.write(m_pkt);
+ flag2='b0;
+ end
+ else
+ begin
+ m_pkt.adr1=pin_if.monitor.haddr;
+ m_pkt.dat1=pin_if.monitor.hwdata;
+ m_pkt.adr2=pin_if.monitor.adr_o;
+ m_pkt.dat2=pin_if.monitor.dat_o;
+ m_pkt.wr='b1;
+ m_pkt.sel=pin_if.monitor.hready;
+ m_pkt.mode=pin_if.monitor.htrans;
+ m_pkt.flag2='b0;
+ ap_sb.write(m_pkt);
+ end
+ end
+ else
+ begin
+ if(flag2) // latch the value
+ begin
+ m_pkt.adr1=pin_if.monitor.haddr;
+ m_pkt.dat1=pin_if.monitor.hrdata;
+ m_pkt.adr2=pin_if.monitor.adr_o;
+ m_pkt.dat2=pin_if.monitor.dat_i;
+ m_pkt.wr='b0;
+ m_pkt.sel=pin_if.monitor.hready;
+ m_pkt.mode=pin_if.monitor.htrans;
+ m_pkt.flag2='b1;
+ ap_sb.write(m_pkt);
+ flag2='b0;
+ end
+ else
+ begin
+ m_pkt.adr1=pin_if.monitor.haddr;
+ m_pkt.dat1=pin_if.monitor.hrdata;
+ m_pkt.adr2=pin_if.monitor.adr_o;
+ m_pkt.dat2=pin_if.monitor.dat_i;
+ m_pkt.wr='b0;
+ m_pkt.sel=pin_if.monitor.hready;
+ m_pkt.mode=pin_if.monitor.htrans;
+ m_pkt.flag2='b0;
+ ap_sb.write(m_pkt);
+ end
+ end
+ end
+ end
+endtask
+
+// run all task simultanoe task
+task run;
+ fork
+ rdwr();
+ wait_ms();
+ main_run();
+ join
+endtask
+
+endclass
+
+
+
Index: trunk/svtb/avm_svtb/ahb_wb_env.svh
===================================================================
--- trunk/svtb/avm_svtb/ahb_wb_env.svh (nonexistent)
+++ trunk/svtb/avm_svtb/ahb_wb_env.svh (revision 6)
@@ -0,0 +1,74 @@
+//////////////////////////////////////////////////////////////////////////////////////////////////////////////////
+//*****************************************************************************************************************
+// Copyright (c) 2007 TooMuch Semiconductor Solutions Pvt Ltd.
+//
+//File name : ahb_wb_env.svh
+//Designer : Sanjay kumar
+//Date : 3rd Aug'2007
+//Description : ahb_wb_env:Enviornment class to connect all the analysis and operational components.
+//Revision : 1.0
+//*****************************************************************************************************************
+///////////////////////////////////////////////////////////////////////////////////////////////////////////////////
+
+// env class
+import avm_pkg::*;
+import ahb_wb_pkg::*;
+import global::*;
+
+class ahb_wb_env extends avm_env;
+
+virtual ahb_wb_if pin_if;// interface
+
+// operational components
+ahb_wb_stim_gen stim_gen;
+ahb_wb_driver driver;
+ahb_wb_responder responder;
+
+// analysis components
+ahb_wb_monitor monitor;
+ahb_wb_scoreboard scoreboard;
+ahb_wb_coverage coverage;
+
+// tlm fifo
+tlm_fifo #(ahb_req_pkt) fifo;
+
+avm_analysis_port#(monitor_pkt) e_ap;
+ function new (virtual ahb_wb_if pin);
+ stim_gen =new("stim_gen",this);
+ driver =new("driver",this);
+ responder =new("responder",this);
+ monitor =new("monitor",this);
+ scoreboard =new("scoreboard",this);
+ coverage =new("coverage",this);
+ fifo =new("fifo",this);
+ e_ap =new("e_ap",this);
+ pin_if =pin;
+ monitor.ap_sb =e_ap;
+ endfunction
+
+ function void connect();
+ stim_gen.initiator_port.connect(fifo.blocking_put_export);
+ driver.request_port.connect(fifo.nonblocking_get_export);
+ monitor.ap_sb.register(scoreboard.ap_if);
+ monitor.ap_sb.register(coverage.ap_if);
+ endfunction
+
+ function void import_connections();
+ driver.pin_if = pin_if;
+ responder.pin_if = pin_if;
+ monitor.pin_if = pin_if;
+ endfunction
+
+
+ task run;
+ fork
+ stim_gen.stimulus();
+ responder.wait_state_by_slave();
+ #625;
+ join
+ endtask
+
+endclass
+
+
+
Index: trunk/svtb/avm_svtb/ahb_wb_interface.sv
===================================================================
--- trunk/svtb/avm_svtb/ahb_wb_interface.sv (nonexistent)
+++ trunk/svtb/avm_svtb/ahb_wb_interface.sv (revision 6)
@@ -0,0 +1,110 @@
+//////////////////////////////////////////////////////////////////////////////////////////////////////////////////
+//*****************************************************************************************************************
+// Copyright (c) 2007 TooMuch Semiconductor Solutions Pvt Ltd.
+//
+//File name : ahb_wb_interface.sv
+//Designer : Sanjay kumar
+//Date : 3rd Aug'2007
+//Description : ahb_wb_if: System verilog Interface with the AHB side master/slave,
+// Wishbone side master/slave and monitor.
+//Revision : 1.0
+//*****************************************************************************************************************
+///////////////////////////////////////////////////////////////////////////////////////////////////////////////////
+
+// interface for the stimulus generator and DUT
+import global::*;
+`timescale 1 ns/1 ps
+interface ahb_wb_if;
+//master to bridge
+ logic hclk;
+ logic hresetn;
+ logic [AWIDTH-1:0]haddr;
+ logic [DWIDTH-1:0]hwdata;
+ logic [1:0]htrans;
+ logic [2:0]hburst;
+ logic [2:0]hsize;
+ logic hwrite;
+ logic hsel;
+ logic hready;
+ logic [DWIDTH-1:0]hrdata;
+ logic [1:0]hresp;
+//bridge to slave
+ logic clk_i;
+ logic rst_i;
+ logic cyc_o;
+ logic stb_o;
+ logic we_o;
+ logic [DWIDTH-1:0]dat_o;
+ logic [AWIDTH-1:0]adr_o;
+ logic ack_i;
+ logic [DWIDTH-1:0]dat_i;
+modport master_ab ( output hclk,
+ output hresetn,
+ output haddr,
+ output hwdata,
+ output htrans,
+ output hburst,
+ output hsize,
+ output hwrite,
+ output hsel,
+ input hready,
+ input hrdata,
+ input hresp
+ );
+modport slave_ab ( input hclk,
+ input hresetn,
+ input haddr,
+ input hwdata,
+ input htrans,
+ input hburst,
+ input hsize,
+ input hwrite,
+ input hsel,
+ output hready,
+ output hrdata,
+ output hresp
+ );
+modport master_bw ( output cyc_o,
+ output stb_o,
+ output we_o,
+ output dat_o,
+ output adr_o,
+ input ack_i,
+ input dat_i,
+ input clk_i,
+ input rst_i
+ );
+modport slave_bw ( input cyc_o,
+ input stb_o,
+ input we_o,
+ input dat_o,
+ input adr_o,
+ output ack_i,
+ output dat_i,
+ output clk_i,
+ output rst_i
+ );
+modport monitor ( // signals from master to bridge
+ input hclk,
+ input hresetn,
+ input haddr,
+ input hwdata,
+ input htrans,
+ input hburst,
+ input hsize,
+ input hwrite,
+ input hsel,
+ input hready,
+ input hrdata,
+ input hresp,
+ // signals from bridge to slave
+ input cyc_o,
+ input stb_o,
+ input we_o,
+ input dat_o,
+ input adr_o,
+ input ack_i,
+ input dat_i,
+ input clk_i,
+ input rst_i );
+endinterface
Index: trunk/svtb/avm_svtb/ahb_wb_top.sv
===================================================================
--- trunk/svtb/avm_svtb/ahb_wb_top.sv (nonexistent)
+++ trunk/svtb/avm_svtb/ahb_wb_top.sv (revision 6)
@@ -0,0 +1,61 @@
+// top module
+`include "../../src/ahb2wb.v"
+`timescale 1ns/ 1ps
+
+import ahb_wb_pkg::*;
+import global::*;
+
+module ahb_wb_top;
+
+logic clk ='b0;
+logic reset ='b1;
+
+ ahb_wb_if inf1(); // interface instance from ahb to bridge
+ stimulus_gen TB_M(inf1.master_ab,clk,reset); // AHB master instance
+
+ ahb2wb DUT ( // interface connection from AHB(stimulus gen) to bridge
+ .hclk(inf1.slave_ab.hclk),
+ .hresetn(inf1.slave_ab.hresetn),
+ .haddr(inf1.slave_ab.haddr),
+ .hwdata(inf1.slave_ab.hwdata),
+ .htrans(inf1.slave_ab.htrans),
+ .hburst(inf1.slave_ab.hburst),
+ .hsize(inf1.slave_ab.hsize),
+ .hwrite(inf1.slave_ab.hwrite),
+ .hsel(inf1.slave_ab.hsel),
+ .hready(inf1.slave_ab.hready),
+ .hrdata(inf1.slave_ab.hrdata),
+ .hresp(inf1.slave_ab.hresp),
+ // interface connection from bridge to wishbone(memory)
+ .cyc_o(inf1.master_bw.cyc_o),
+ .stb_o(inf1.master_bw.stb_o),
+ .we_o(inf1.master_bw.we_o),
+ .dat_o(inf1.master_bw.dat_o),
+ .adr_o(inf1.master_bw.adr_o),
+ .ack_i(inf1.master_bw.ack_i),
+ .dat_i(inf1.master_bw.dat_i),
+ .clk_i(inf1.master_bw.clk_i),
+ .rst_i(inf1.master_bw.rst_i));
+ ahb_wb_env env; // enviornment class
+
+// reset generation
+initial
+ begin
+ env = new(inf1);
+ $display ("\n@%0d:Testcase begin",$time);
+ #13 reset='b0;
+ #33 reset ='b1;
+ $display ("\n@%0d:Reset done",$time);
+ TB_M.initial_setup();
+ $display ("\n@%0d:Initial setup done",$time);
+ env.do_test();
+ $display ("\n@%0d do_test over",$time);
+ $finish;
+
+ end
+
+//clock generation
+initial
+ forever
+ #(cyc_prd/2) clk = ~clk;
+endmodule
Index: trunk/svtb/avm_svtb/ahb_wb_coverage.svh
===================================================================
--- trunk/svtb/avm_svtb/ahb_wb_coverage.svh (nonexistent)
+++ trunk/svtb/avm_svtb/ahb_wb_coverage.svh (revision 6)
@@ -0,0 +1,73 @@
+//////////////////////////////////////////////////////////////////////////////////////////////////////////////////
+//*****************************************************************************************************************
+// Copyright (c) 2007 TooMuch Semiconductor Solutions Pvt Ltd.
+//
+//File name : ahb_wb_coverage.svh
+//Designer : Sanjay kumar
+//Date : 3rd Aug'2007
+//Description : ahb_wb_coverage:Class to receive monitor packets from publisher(monitor) and check
+// for Functional coverage.
+//Revision : 1.0
+//*****************************************************************************************************************
+///////////////////////////////////////////////////////////////////////////////////////////////////////////////////
+
+import avm_pkg::*;
+import global::*;
+
+class ahb_wb_coverage extends avm_threaded_component;
+
+analysis_fifo#(monitor_pkt) ap_fifo; // analysis port fifo
+analysis_if#(monitor_pkt) ap_if; // analysis port interface
+
+// local variables
+logic [AWIDTH-1:0]adr1;
+logic [AWIDTH-1:0]adr2;
+logic [DWIDTH-1:0]dat1;
+logic [DWIDTH-1:0]dat2;
+bit sel,wr;
+bit [1:0]mode;
+
+// monitor packet
+monitor_pkt m_pkt;
+
+// coverage group
+covergroup cov_wr;
+ write_read: coverpoint wr; // cover read/write
+ wr_with_wait_mst: cross wr,mode;// cover read/write on wait state by master
+ wr_with_wait_slv: cross wr,sel;// cover read/write on wait state by slave
+
+endgroup
+
+ function new(string name ,avm_named_component parent);
+ super.new(name,parent);
+ ap_fifo =new("ap_fifo",this);
+ ap_if =null;
+ cov_wr=new;
+ endfunction
+
+// connecting analysis fifo to the analysis interface
+function void export_connections();
+ ap_if = ap_fifo.analysis_export;
+endfunction
+
+
+
+
+task run;
+ forever
+ begin
+ ap_fifo.get(m_pkt); // receiving monitor_pkt from monitor
+ // sampling the values of pkt to local variables
+ sel=m_pkt.sel;
+ wr=m_pkt.wr;
+ mode=m_pkt.mode;
+ // sample the coverpoints
+ cov_wr.sample();
+
+ end
+endtask
+
+endclass
+
+
+
Index: trunk/svtb/avm_svtb/ahb_wb_driver.svh
===================================================================
--- trunk/svtb/avm_svtb/ahb_wb_driver.svh (nonexistent)
+++ trunk/svtb/avm_svtb/ahb_wb_driver.svh (revision 6)
@@ -0,0 +1,59 @@
+//////////////////////////////////////////////////////////////////////////////////////////////////////////////////
+//*****************************************************************************************************************
+// Copyright (c) 2007 TooMuch Semiconductor Solutions Pvt Ltd.
+//
+//File name : ahb_wb_driver.svh
+//Designer : Sanjay kumar
+//Date : 3rd Aug'2007
+//Description : ahb_wb_driver:Class to receive packets from the tlm fifo and passed it to the
+// interface of the AHB to Wishbone bridge.
+//Revision : 1.0
+//*****************************************************************************************************************
+///////////////////////////////////////////////////////////////////////////////////////////////////////////////////
+
+import avm_pkg::*;
+import global::*;
+
+class ahb_wb_driver extends avm_threaded_component;
+
+// communication ports
+avm_nonblocking_get_port #(ahb_req_pkt) request_port;
+tlm_fifo #(ahb_req_pkt) fifo;
+
+virtual ahb_wb_if pin_if;
+
+ function new(string name ,avm_named_component parent);
+ super.new(name,parent);
+ request_port =new("request_port",this);
+ fifo =new("fifo",this);
+ pin_if =null;
+ endfunction
+
+task run;
+ ahb_req_pkt req;
+ ahb_res_pkt res;
+ forever
+ begin
+ @(posedge pin_if.master_ab.hclk);
+ if(pin_if.master_ab.hready && pin_if.master_ab.hresetn)
+ begin
+ if(request_port.try_get(req))
+ write_to_bus(req);
+ end
+ end
+endtask
+
+
+// write data to bus
+virtual task write_to_bus(input ahb_req_pkt req);
+ #2 pin_if.master_ab.htrans=req.mode;
+ pin_if.master_ab.hwrite=req.wr;
+ pin_if.master_ab.haddr =req.adr;
+ pin_if.master_ab.hwdata=req.dat;
+ //avm_report_message("Driver:Packet on interface",global::convert2string(req));
+endtask
+
+endclass
+
+
+
Index: trunk/svtb/sim_svtb/cov_run.all
===================================================================
--- trunk/svtb/sim_svtb/cov_run.all (nonexistent)
+++ trunk/svtb/sim_svtb/cov_run.all (revision 6)
@@ -0,0 +1,7 @@
+rm -rf ./work
+vlib work
+vlog -f compile_sv.f
+rm cover_rpt.ucdb cover_rpt.out
+vsim -c ahb_wb_top -do "run 1110ns ; fcover save cover_rpt.ucdb; vcover report -cvg -details cover_rpt.ucdb | tee cover_rpt.out; exit"
+gvim cover_rpt.out
+
trunk/svtb/sim_svtb/cov_run.all
Property changes :
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: trunk/svtb/sim_svtb/compile_sv.f
===================================================================
--- trunk/svtb/sim_svtb/compile_sv.f (nonexistent)
+++ trunk/svtb/sim_svtb/compile_sv.f (revision 6)
@@ -0,0 +1,8 @@
++incdir+libraries/systemverilog/avm
+libraries/systemverilog/avm/avm_pkg.sv
++incdir+.
+../avm_svtb/global.sv
+../avm_svtb/ahb_wb_interface.sv
+./ahb_wb_pkg.sv
+../avm_svtb/ahb_wb_master.sv
+../avm_svtb/ahb_wb_top.sv
Index: trunk/svtb/sim_svtb/clean.all
===================================================================
--- trunk/svtb/sim_svtb/clean.all (nonexistent)
+++ trunk/svtb/sim_svtb/clean.all (revision 6)
@@ -0,0 +1 @@
+rm -rf cover_rpt.* vsim.wlf work transcript
trunk/svtb/sim_svtb/clean.all
Property changes :
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: trunk/svtb/sim_svtb/ahb_wb_pkg.sv
===================================================================
--- trunk/svtb/sim_svtb/ahb_wb_pkg.sv (nonexistent)
+++ trunk/svtb/sim_svtb/ahb_wb_pkg.sv (revision 6)
@@ -0,0 +1,12 @@
+`timescale 1 ns/1 ps
+package ahb_wb_pkg;
+import global::*;
+ `include "../avm_svtb/ahb_wb_stim_gen.svh"
+ `include "../avm_svtb/ahb_wb_driver.svh"
+ `include "../avm_svtb/ahb_wb_responder.svh"
+ `include "../avm_svtb/ahb_wb_monitor.svh"
+ `include "../avm_svtb/ahb_wb_scoreboard.svh"
+ `include "../avm_svtb/ahb_wb_coverage.svh"
+ `include "../avm_svtb/ahb_wb_env.svh"
+endpackage
+
Index: trunk/svtb/sim_svtb/run.all
===================================================================
--- trunk/svtb/sim_svtb/run.all (nonexistent)
+++ trunk/svtb/sim_svtb/run.all (revision 6)
@@ -0,0 +1,5 @@
+rm -rf ./work
+vlib work
+vlog -f compile_sv.f
+vsim -c ahb_wb_top -do "run -all"
+
trunk/svtb/sim_svtb/run.all
Property changes :
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property