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URL https://opencores.org/ocsvn/altor32/altor32/trunk

Subversion Repositories altor32

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Rev 22 → Rev 23

/altor32/trunk/sw/bootloader/xmodem.h
1,25 → 1,25
#ifndef __XMODEM_H__
#define __XMODEM_H__
#ifndef __XMODEM_H__
#define __XMODEM_H__
 
//-----------------------------------------------------------------
// Defines
//-----------------------------------------------------------------
 
// Support 128 byte transfers
#define XMODEM_BUFFER_SIZE 128
 
// Support 1024 byte transfers
//#define XMODEM_BUFFER_SIZE 1024
 
// xmodem timeout/retry parameters
#define XMODEM_TIMEOUT_DELAY 1000
#define XMODEM_RETRY_LIMIT 16
 
//-----------------------------------------------------------------
// Prototypes
//-----------------------------------------------------------------
void xmodem_init(int (*sputc)(char c), int (*sgetc)(void));
int xmodem_receive( int (*write)(unsigned char* buffer, int size) );
 
#endif // __XMODEM_H__
 
//-----------------------------------------------------------------
// Defines
//-----------------------------------------------------------------
 
// Support 128 byte transfers
#define XMODEM_BUFFER_SIZE 128
 
// Support 1024 byte transfers
//#define XMODEM_BUFFER_SIZE 1024
 
// xmodem timeout/retry parameters
#define XMODEM_TIMEOUT_DELAY 1000
#define XMODEM_RETRY_LIMIT 16
 
//-----------------------------------------------------------------
// Prototypes
//-----------------------------------------------------------------
void xmodem_init(int (*sputc)(char c), int (*sgetc)(void));
int xmodem_receive( int (*write)(unsigned char* buffer, int size) );
 
#endif // __XMODEM_H__
 
/altor32/trunk/sw/bootloader/boot_serial.c
1,7 → 1,6
//-----------------------------------------------------------------------------
//-----------------------------------------------------------------------------
// AltOR32
// Alternative Lightweight OpenRisc
// Alternative Lightweight OpenRISC
// Ultra-Embedded.com
// Copyright 2011 - 2012
//
13,23 → 12,22
// applications.
//-----------------------------------------------------------------------------
//
// This file is part of AltOR32 OpenRisc Simulator.
// This file is part of AltOR32 Alternative Lightweight OpenRISC project.
//
// AltOR32 OpenRisc Simulator is free software; you can redistribute it and/or
// modify it under the terms of the GNU General Public License as published by
// the Free Software Foundation; either version 2 of the License, or
// (at your option) any later version.
// AltOR32 is free software; you can redistribute it and/or modify it under
// the terms of the GNU General Public License as published by the Free Software
// Foundation; either version 2 of the License, or (at your option) any later
// version.
//
// AltOR32 OpenRisc Simulator is distributed in the hope that it will be useful,
// but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
// GNU General Public License for more details.
// AltOR32 is distributed in the hope that it will be useful, but WITHOUT ANY
// WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS
// FOR A PARTICULAR PURPOSE. See the GNU General Public License for more
// details.
//
// You should have received a copy of the GNU General Public License
// along with AltOR32 OpenRisc Simulator; if not, write to the Free Software
// Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
// along with AltOR32; if not, write to the Free Software Foundation, Inc.,
// 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
//-----------------------------------------------------------------------------
//-----------------------------------------------------------------------------
#include "serial.h"
#include "boot_serial.h"
#include "xmodem.h"
39,7 → 37,7
//-----------------------------------------------------------------
// Defines:
//-----------------------------------------------------------------
#define FLASH_SECTOR_SIZE SPIFLASH_BLOCKSIZE
#define FLASH_SECTOR_SIZE SPIFLASH_BLOCKSIZE
 
//-----------------------------------------------------------------
// Locals:
/altor32/trunk/sw/bootloader/assert.h
1,10 → 1,10
#ifndef __ASSERT_H__
#define __ASSERT_H__
 
extern void assert_handler(const char * type, const char *reason, const char *file, int line);
 
#define assert(exp) do { if (!(exp)) assert_handler("ASSERT", #exp, __FILE__, __LINE__ ); } while (0)
#define panic(reason) do { assert_handler("PANIC", #reason, __FILE__, __LINE__ ); } while (0)
 
#endif
 
#ifndef __ASSERT_H__
#define __ASSERT_H__
 
extern void assert_handler(const char * type, const char *reason, const char *file, int line);
 
#define assert(exp) do { if (!(exp)) assert_handler("ASSERT", #exp, __FILE__, __LINE__ ); } while (0)
#define panic(reason) do { assert_handler("PANIC", #reason, __FILE__, __LINE__ ); } while (0)
 
#endif
 
/altor32/trunk/sw/bootloader/boot_serial.h
1,18 → 1,18
#ifndef __BOOT_SERIAL_H__
#define __BOOT_SERIAL_H__
 
//-----------------------------------------------------------------
// Defines
//-----------------------------------------------------------------
 
//-----------------------------------------------------------------
// Types
//-----------------------------------------------------------------
 
//-----------------------------------------------------------------
// Prototypes
//-----------------------------------------------------------------
void boot_serial(unsigned long target, int flash);
 
 
#endif //__BOOT_SERIAL_H__
#ifndef __BOOT_SERIAL_H__
#define __BOOT_SERIAL_H__
 
//-----------------------------------------------------------------
// Defines
//-----------------------------------------------------------------
 
//-----------------------------------------------------------------
// Types
//-----------------------------------------------------------------
 
//-----------------------------------------------------------------
// Prototypes
//-----------------------------------------------------------------
void boot_serial(unsigned long target, int flash);
 
 
#endif //__BOOT_SERIAL_H__
/altor32/trunk/sw/bootloader/spi_flash.c
1,341 → 1,339
//-----------------------------------------------------------------------------
//-----------------------------------------------------------------------------
//-----------------------------------------------------------------------------
// AltOR32
// Alternative Lightweight OpenRisc
// Alternative Lightweight OpenRISC
// Ultra-Embedded.com
// Copyright 2011 - 2012
//
// Email: admin@ultra-embedded.com
//
// License: GPL
// Please contact the above address if you would like a version of this
// software with a more permissive license for use in closed source commercial
// applications.
//-----------------------------------------------------------------------------
//
// This file is part of AltOR32 OpenRisc Simulator.
//
// AltOR32 OpenRisc Simulator is free software; you can redistribute it and/or
// modify it under the terms of the GNU General Public License as published by
// the Free Software Foundation; either version 2 of the License, or
// (at your option) any later version.
//
// AltOR32 OpenRisc Simulator is distributed in the hope that it will be useful,
// but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
// GNU General Public License for more details.
//
// You should have received a copy of the GNU General Public License
// along with AltOR32 OpenRisc Simulator; if not, write to the Free Software
// Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
//-----------------------------------------------------------------------------
//-----------------------------------------------------------------------------
#include "assert.h"
#include "mem_map.h"
#include "spi_flash.h"
 
//-------------------------------------------------------------
// Defines:
//-------------------------------------------------------------
 
// Chip select control
#define SPIFLASH_CS_HIGH SPI_PROM_CTRL = SPI_PROM_CS
#define SPIFLASH_CS_LOW SPI_PROM_CTRL = 0
 
// ID addresses
#define SPIFLASH_MAN_ADDR 0x00
#define SPIFLASH_DEV_ADDR 0x01
 
// Instructions
#define SPIFLASH_OP_WRSR 0x01
#define SPIFLASH_OP_PROGRAM 0x02
#define SPIFLASH_OP_READ 0x03
#define SPIFLASH_OP_RDSR 0x05
#define SPIFLASH_STAT_BUSY (1 << 0)
#define SPIFLASH_STAT_WEL (1 << 1)
#define SPIFLASH_STAT_BP0 (1 << 2)
#define SPIFLASH_STAT_BP1 (1 << 3)
#define SPIFLASH_STAT_BP2 (1 << 4)
#define SPIFLASH_STAT_BP3 (1 << 5)
#define SPIFLASH_STAT_AAI (1 << 6)
#define SPIFLASH_STAT_BPL (1 << 7)
#define SPIFLASH_OP_WREN 0x06
#define SPIFLASH_OP_ERASESECTOR 0x20
#define SPIFLASH_OP_ERASECHIP 0x60
#define SPIFLASH_OP_RDID 0x9F
#define SPIFLASH_OP_AAIP 0xAD
 
typedef enum
{
SPI_FLASH_GENERIC,
SPI_FLASH_SST25VF040B,
SPI_FLASH_AT25DF041A
} tSpiDevice;
 
//-------------------------------------------------------------
// Locals:
//-------------------------------------------------------------
static tSpiDevice _device = SPI_FLASH_GENERIC;
 
//-------------------------------------------------------------
// spiflash_writebyte:
//-------------------------------------------------------------
static void spiflash_writebyte(unsigned char data)
{
SPI_PROM_DATA = data;
while (SPI_PROM_STAT & SPI_PROM_BUSY);
}
//-------------------------------------------------------------
// spiflash_readbyte:
//-------------------------------------------------------------
static unsigned char spiflash_readbyte(void)
{
SPI_PROM_DATA = 0xFF;
while (SPI_PROM_STAT & SPI_PROM_BUSY);
return SPI_PROM_DATA;
}
//-------------------------------------------------------------
// spiflash_command:
//-------------------------------------------------------------
static void spiflash_command(unsigned char command, unsigned long address)
{
spiflash_writebyte(command);
spiflash_writebyte(address >> 16);
spiflash_writebyte(address >> 8);
spiflash_writebyte(address >> 0);
}
//-------------------------------------------------------------
// spiflash_readid:
//-------------------------------------------------------------
static unsigned char spiflash_readid(unsigned long address)
{
unsigned long i;
unsigned char id;
 
SPIFLASH_CS_LOW;
 
spiflash_writebyte(SPIFLASH_OP_RDID);
for (i=0;i<=address;i++)
{
id = spiflash_readbyte();
}
 
SPIFLASH_CS_HIGH;
 
return id;
}
//-------------------------------------------------------------
// spiflash_readstatus:
//-------------------------------------------------------------
static unsigned char spiflash_readstatus(void)
{
unsigned char stat;
 
SPIFLASH_CS_LOW;
 
spiflash_writebyte(SPIFLASH_OP_RDSR);
stat = spiflash_readbyte();
 
SPIFLASH_CS_HIGH;
 
return stat;
}
//-------------------------------------------------------------
// spiflash_writeenable:
//-------------------------------------------------------------
static void spiflash_writeenable(void)
{
SPIFLASH_CS_LOW;
spiflash_writebyte(SPIFLASH_OP_WREN);
SPIFLASH_CS_HIGH;
}
//-------------------------------------------------------------
// spiflash_writestatus:
//-------------------------------------------------------------
static void spiflash_writestatus(unsigned char value)
{
// Execute write enable command
spiflash_writeenable();
 
SPIFLASH_CS_LOW;
spiflash_writebyte(SPIFLASH_OP_WRSR);
spiflash_writebyte(value);
SPIFLASH_CS_HIGH;
}
//-------------------------------------------------------------
// spiflash_programbyte:
//-------------------------------------------------------------
static void spiflash_programbyte(unsigned long address, unsigned char data)
{
// Execute write enable command
spiflash_writeenable();
 
// Program a word at a specific address
SPIFLASH_CS_LOW;
spiflash_command(SPIFLASH_OP_PROGRAM, address);
spiflash_writebyte(data);
SPIFLASH_CS_HIGH;
 
// Wait until operation completed
while (spiflash_readstatus() & SPIFLASH_STAT_BUSY)
;
}
//-------------------------------------------------------------
// spiflash_programpage:
//-------------------------------------------------------------
static void spiflash_programpage(unsigned long address, unsigned char *data, unsigned int size)
{
int i;
 
// Execute write enable command
spiflash_writeenable();
 
// Program a word at a specific address
SPIFLASH_CS_LOW;
 
spiflash_command(SPIFLASH_OP_PROGRAM, address);
 
for (i=0;i<size;i++)
spiflash_writebyte(data[i]);
 
SPIFLASH_CS_HIGH;
 
// Wait until operation completed
while (spiflash_readstatus() & SPIFLASH_STAT_BUSY)
;
}
 
//-------------------------------------------------------------
// External API
//-------------------------------------------------------------
 
//-------------------------------------------------------------
// spiflash_init:
//-------------------------------------------------------------
int spiflash_init(void)
{
int res;
unsigned char id;
 
// Do dummy reads first
spiflash_readstatus();
spiflash_readid(SPIFLASH_DEV_ADDR);
 
// Check device ID
switch ((id = spiflash_readid(SPIFLASH_MAN_ADDR)))
{
// Atmel
case 0x1F:
id = spiflash_readid(SPIFLASH_DEV_ADDR);
res = ( id == 0x44 );
assert( res && "Unknown device ID" );
_device = SPI_FLASH_AT25DF041A;
break;
// SST
case 0xBF:
id = spiflash_readid(SPIFLASH_DEV_ADDR);
res = ( id == 0x25 );
assert( res && "Unknown device ID" );
_device = SPI_FLASH_SST25VF040B;
break;
default:
res = 0;
assert(res && "Unknown manufacturer ID");
break;
}
 
// Enable device writes
spiflash_writestatus(0);
return res;
}
//-------------------------------------------------------------
// spiflash_readblock:
//-------------------------------------------------------------
int spiflash_readblock(unsigned long address, unsigned char *buf, int length)
{
int i;
 
SPIFLASH_CS_LOW;
 
spiflash_command(SPIFLASH_OP_READ, address);
 
for (i=0;i<length;i++)
buf[i] = spiflash_readbyte();
 
SPIFLASH_CS_HIGH;
 
return 0;
}
//-------------------------------------------------------------
// spiflash_writeblock:
//-------------------------------------------------------------
int spiflash_writeblock(unsigned long address, unsigned char *buf, int length)
{
int i, j;
 
// Sector boundary? Erase sector
if ((address & (SPIFLASH_SECTORSIZE - 1)) == 0)
spiflash_eraseblock(address);
 
for (i=0;i<length;i+=SPIFLASH_PAGESIZE)
{
int size = length - i;
 
if (size > SPIFLASH_PAGESIZE)
size = SPIFLASH_PAGESIZE;
 
// Byte program device
if (_device == SPI_FLASH_SST25VF040B)
{
for (j=0;j<size;j++)
spiflash_programbyte(address + j, buf[j]);
}
// Block program device
else
spiflash_programpage(address, buf, size);
 
address += SPIFLASH_PAGESIZE;
buf += SPIFLASH_PAGESIZE;
}
 
return 0;
}
//-------------------------------------------------------------
// spiflash_eraseblock:
//-------------------------------------------------------------
int spiflash_eraseblock(unsigned long address)
{
// Enable write mode
spiflash_writeenable();
 
// Erase sector
SPIFLASH_CS_LOW;
spiflash_command(SPIFLASH_OP_ERASESECTOR, address);
SPIFLASH_CS_HIGH;
 
// Wait until operation completed
while (spiflash_readstatus() & SPIFLASH_STAT_BUSY)
;
 
return 0;
}
//-------------------------------------------------------------
// spiflash_erasechip:
//-------------------------------------------------------------
int spiflash_erasechip(void)
{
// Enable write mode
spiflash_writeenable();
 
// Erase chip
SPIFLASH_CS_LOW;
spiflash_writebyte(SPIFLASH_OP_ERASECHIP);
SPIFLASH_CS_HIGH;
 
// Wait until operation completed
while (spiflash_readstatus() & SPIFLASH_STAT_BUSY)
;
 
return 0;
}
 
// Copyright 2011 - 2012
//
// Email: admin@ultra-embedded.com
//
// License: GPL
// Please contact the above address if you would like a version of this
// software with a more permissive license for use in closed source commercial
// applications.
//-----------------------------------------------------------------------------
//
// This file is part of AltOR32 Alternative Lightweight OpenRISC project.
//
// AltOR32 is free software; you can redistribute it and/or modify it under
// the terms of the GNU General Public License as published by the Free Software
// Foundation; either version 2 of the License, or (at your option) any later
// version.
//
// AltOR32 is distributed in the hope that it will be useful, but WITHOUT ANY
// WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS
// FOR A PARTICULAR PURPOSE. See the GNU General Public License for more
// details.
//
// You should have received a copy of the GNU General Public License
// along with AltOR32; if not, write to the Free Software Foundation, Inc.,
// 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
//-----------------------------------------------------------------------------
#include "assert.h"
#include "mem_map.h"
#include "spi_flash.h"
 
//-------------------------------------------------------------
// Defines:
//-------------------------------------------------------------
 
// Chip select control
#define SPIFLASH_CS_HIGH SPI_PROM_CTRL = SPI_PROM_CS
#define SPIFLASH_CS_LOW SPI_PROM_CTRL = 0
 
// ID addresses
#define SPIFLASH_MAN_ADDR 0x00
#define SPIFLASH_DEV_ADDR 0x01
 
// Instructions
#define SPIFLASH_OP_WRSR 0x01
#define SPIFLASH_OP_PROGRAM 0x02
#define SPIFLASH_OP_READ 0x03
#define SPIFLASH_OP_RDSR 0x05
#define SPIFLASH_STAT_BUSY (1 << 0)
#define SPIFLASH_STAT_WEL (1 << 1)
#define SPIFLASH_STAT_BP0 (1 << 2)
#define SPIFLASH_STAT_BP1 (1 << 3)
#define SPIFLASH_STAT_BP2 (1 << 4)
#define SPIFLASH_STAT_BP3 (1 << 5)
#define SPIFLASH_STAT_AAI (1 << 6)
#define SPIFLASH_STAT_BPL (1 << 7)
#define SPIFLASH_OP_WREN 0x06
#define SPIFLASH_OP_ERASESECTOR 0x20
#define SPIFLASH_OP_ERASECHIP 0x60
#define SPIFLASH_OP_RDID 0x9F
#define SPIFLASH_OP_AAIP 0xAD
 
typedef enum
{
SPI_FLASH_GENERIC,
SPI_FLASH_SST25VF040B,
SPI_FLASH_AT25DF041A
} tSpiDevice;
 
//-------------------------------------------------------------
// Locals:
//-------------------------------------------------------------
static tSpiDevice _device = SPI_FLASH_GENERIC;
 
//-------------------------------------------------------------
// spiflash_writebyte:
//-------------------------------------------------------------
static void spiflash_writebyte(unsigned char data)
{
SPI_PROM_DATA = data;
while (SPI_PROM_STAT & SPI_PROM_BUSY);
}
//-------------------------------------------------------------
// spiflash_readbyte:
//-------------------------------------------------------------
static unsigned char spiflash_readbyte(void)
{
SPI_PROM_DATA = 0xFF;
while (SPI_PROM_STAT & SPI_PROM_BUSY);
return SPI_PROM_DATA;
}
//-------------------------------------------------------------
// spiflash_command:
//-------------------------------------------------------------
static void spiflash_command(unsigned char command, unsigned long address)
{
spiflash_writebyte(command);
spiflash_writebyte(address >> 16);
spiflash_writebyte(address >> 8);
spiflash_writebyte(address >> 0);
}
//-------------------------------------------------------------
// spiflash_readid:
//-------------------------------------------------------------
static unsigned char spiflash_readid(unsigned long address)
{
unsigned long i;
unsigned char id;
 
SPIFLASH_CS_LOW;
 
spiflash_writebyte(SPIFLASH_OP_RDID);
for (i=0;i<=address;i++)
{
id = spiflash_readbyte();
}
 
SPIFLASH_CS_HIGH;
 
return id;
}
//-------------------------------------------------------------
// spiflash_readstatus:
//-------------------------------------------------------------
static unsigned char spiflash_readstatus(void)
{
unsigned char stat;
 
SPIFLASH_CS_LOW;
 
spiflash_writebyte(SPIFLASH_OP_RDSR);
stat = spiflash_readbyte();
 
SPIFLASH_CS_HIGH;
 
return stat;
}
//-------------------------------------------------------------
// spiflash_writeenable:
//-------------------------------------------------------------
static void spiflash_writeenable(void)
{
SPIFLASH_CS_LOW;
spiflash_writebyte(SPIFLASH_OP_WREN);
SPIFLASH_CS_HIGH;
}
//-------------------------------------------------------------
// spiflash_writestatus:
//-------------------------------------------------------------
static void spiflash_writestatus(unsigned char value)
{
// Execute write enable command
spiflash_writeenable();
 
SPIFLASH_CS_LOW;
spiflash_writebyte(SPIFLASH_OP_WRSR);
spiflash_writebyte(value);
SPIFLASH_CS_HIGH;
}
//-------------------------------------------------------------
// spiflash_programbyte:
//-------------------------------------------------------------
static void spiflash_programbyte(unsigned long address, unsigned char data)
{
// Execute write enable command
spiflash_writeenable();
 
// Program a word at a specific address
SPIFLASH_CS_LOW;
spiflash_command(SPIFLASH_OP_PROGRAM, address);
spiflash_writebyte(data);
SPIFLASH_CS_HIGH;
 
// Wait until operation completed
while (spiflash_readstatus() & SPIFLASH_STAT_BUSY)
;
}
//-------------------------------------------------------------
// spiflash_programpage:
//-------------------------------------------------------------
static void spiflash_programpage(unsigned long address, unsigned char *data, unsigned int size)
{
int i;
 
// Execute write enable command
spiflash_writeenable();
 
// Program a word at a specific address
SPIFLASH_CS_LOW;
 
spiflash_command(SPIFLASH_OP_PROGRAM, address);
 
for (i=0;i<size;i++)
spiflash_writebyte(data[i]);
 
SPIFLASH_CS_HIGH;
 
// Wait until operation completed
while (spiflash_readstatus() & SPIFLASH_STAT_BUSY)
;
}
 
//-------------------------------------------------------------
// External API
//-------------------------------------------------------------
 
//-------------------------------------------------------------
// spiflash_init:
//-------------------------------------------------------------
int spiflash_init(void)
{
int res;
unsigned char id;
 
// Do dummy reads first
spiflash_readstatus();
spiflash_readid(SPIFLASH_DEV_ADDR);
 
// Check device ID
switch ((id = spiflash_readid(SPIFLASH_MAN_ADDR)))
{
// Atmel
case 0x1F:
id = spiflash_readid(SPIFLASH_DEV_ADDR);
res = ( id == 0x44 );
assert( res && "Unknown device ID" );
_device = SPI_FLASH_AT25DF041A;
break;
// SST
case 0xBF:
id = spiflash_readid(SPIFLASH_DEV_ADDR);
res = ( id == 0x25 );
assert( res && "Unknown device ID" );
_device = SPI_FLASH_SST25VF040B;
break;
default:
res = 0;
assert(res && "Unknown manufacturer ID");
break;
}
 
// Enable device writes
spiflash_writestatus(0);
return res;
}
//-------------------------------------------------------------
// spiflash_readblock:
//-------------------------------------------------------------
int spiflash_readblock(unsigned long address, unsigned char *buf, int length)
{
int i;
 
SPIFLASH_CS_LOW;
 
spiflash_command(SPIFLASH_OP_READ, address);
 
for (i=0;i<length;i++)
buf[i] = spiflash_readbyte();
 
SPIFLASH_CS_HIGH;
 
return 0;
}
//-------------------------------------------------------------
// spiflash_writeblock:
//-------------------------------------------------------------
int spiflash_writeblock(unsigned long address, unsigned char *buf, int length)
{
int i, j;
 
// Sector boundary? Erase sector
if ((address & (SPIFLASH_SECTORSIZE - 1)) == 0)
spiflash_eraseblock(address);
 
for (i=0;i<length;i+=SPIFLASH_PAGESIZE)
{
int size = length - i;
 
if (size > SPIFLASH_PAGESIZE)
size = SPIFLASH_PAGESIZE;
 
// Byte program device
if (_device == SPI_FLASH_SST25VF040B)
{
for (j=0;j<size;j++)
spiflash_programbyte(address + j, buf[j]);
}
// Block program device
else
spiflash_programpage(address, buf, size);
 
address += SPIFLASH_PAGESIZE;
buf += SPIFLASH_PAGESIZE;
}
 
return 0;
}
//-------------------------------------------------------------
// spiflash_eraseblock:
//-------------------------------------------------------------
int spiflash_eraseblock(unsigned long address)
{
// Enable write mode
spiflash_writeenable();
 
// Erase sector
SPIFLASH_CS_LOW;
spiflash_command(SPIFLASH_OP_ERASESECTOR, address);
SPIFLASH_CS_HIGH;
 
// Wait until operation completed
while (spiflash_readstatus() & SPIFLASH_STAT_BUSY)
;
 
return 0;
}
//-------------------------------------------------------------
// spiflash_erasechip:
//-------------------------------------------------------------
int spiflash_erasechip(void)
{
// Enable write mode
spiflash_writeenable();
 
// Erase chip
SPIFLASH_CS_LOW;
spiflash_writebyte(SPIFLASH_OP_ERASECHIP);
SPIFLASH_CS_HIGH;
 
// Wait until operation completed
while (spiflash_readstatus() & SPIFLASH_STAT_BUSY)
;
 
return 0;
}
 
/altor32/trunk/sw/bootloader/spi_flash.h
1,25 → 1,25
#ifndef __SPI_FLASH_H__
#define __SPI_FLASH_H__
 
//-----------------------------------------------------------------
// Defines:
//-----------------------------------------------------------------
#define SPIFLASH_PAGESIZE (256)
#define SPIFLASH_BLOCKSIZE (4 * 1024)
#define SPIFLASH_SECTORSIZE (SPIFLASH_BLOCKSIZE)
#define SPIFLASH_SIZE (512 * 1024) // 4Mbit
#define SPIFLASH_FPGA_OFFSET (0)
#define SPIFLASH_FPGA_SIZE (352 * 1024)
#define SPIFLASH_APP_OFFSET (SPIFLASH_FPGA_SIZE)
#define SPIFLASH_APP_SIZE (SPIFLASH_SIZE - SPIFLASH_APP_OFFSET)
 
//-----------------------------------------------------------------
// Prototypes:
//-----------------------------------------------------------------
int spiflash_init(void);
int spiflash_readblock(unsigned long address, unsigned char *buf, int length);
int spiflash_writeblock(unsigned long address, unsigned char *buf, int length);
int spiflash_eraseblock(unsigned long address);
int spiflash_erasechip(void);
 
#endif // __SPI_FLASH_H__
#ifndef __SPI_FLASH_H__
#define __SPI_FLASH_H__
 
//-----------------------------------------------------------------
// Defines:
//-----------------------------------------------------------------
#define SPIFLASH_PAGESIZE (256)
#define SPIFLASH_BLOCKSIZE (4 * 1024)
#define SPIFLASH_SECTORSIZE (SPIFLASH_BLOCKSIZE)
#define SPIFLASH_SIZE (512 * 1024) // 4Mbit
#define SPIFLASH_FPGA_OFFSET (0)
#define SPIFLASH_FPGA_SIZE (352 * 1024)
#define SPIFLASH_APP_OFFSET (SPIFLASH_FPGA_SIZE)
#define SPIFLASH_APP_SIZE (SPIFLASH_SIZE - SPIFLASH_APP_OFFSET)
 
//-----------------------------------------------------------------
// Prototypes:
//-----------------------------------------------------------------
int spiflash_init(void);
int spiflash_readblock(unsigned long address, unsigned char *buf, int length);
int spiflash_writeblock(unsigned long address, unsigned char *buf, int length);
int spiflash_eraseblock(unsigned long address);
int spiflash_erasechip(void);
 
#endif // __SPI_FLASH_H__
/altor32/trunk/sw/bootloader/serial.c
1,7 → 1,6
//-----------------------------------------------------------------------------
//-----------------------------------------------------------------------------
// AltOR32
// Alternative Lightweight OpenRisc
// Alternative Lightweight OpenRISC
// Ultra-Embedded.com
// Copyright 2011 - 2012
//
13,23 → 12,22
// applications.
//-----------------------------------------------------------------------------
//
// This file is part of AltOR32 OpenRisc Simulator.
// This file is part of AltOR32 Alternative Lightweight OpenRISC project.
//
// AltOR32 OpenRisc Simulator is free software; you can redistribute it and/or
// modify it under the terms of the GNU General Public License as published by
// the Free Software Foundation; either version 2 of the License, or
// (at your option) any later version.
// AltOR32 is free software; you can redistribute it and/or modify it under
// the terms of the GNU General Public License as published by the Free Software
// Foundation; either version 2 of the License, or (at your option) any later
// version.
//
// AltOR32 OpenRisc Simulator is distributed in the hope that it will be useful,
// but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
// GNU General Public License for more details.
// AltOR32 is distributed in the hope that it will be useful, but WITHOUT ANY
// WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS
// FOR A PARTICULAR PURPOSE. See the GNU General Public License for more
// details.
//
// You should have received a copy of the GNU General Public License
// along with AltOR32 OpenRisc Simulator; if not, write to the Free Software
// Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
// along with AltOR32; if not, write to the Free Software Foundation, Inc.,
// 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
//-----------------------------------------------------------------------------
//-----------------------------------------------------------------------------
#include "mem_map.h"
#include "serial.h"
 
36,11 → 34,11
//-----------------------------------------------------------------
// Registers
//-----------------------------------------------------------------
#define UART_RX_AVAIL (1<<0)
#define UART_TX_AVAIL (1<<1)
#define UART_RX_FULL (1<<2)
#define UART_TX_BUSY (1<<3)
#define UART_RX_ERROR (1<<4)
#define UART_RX_AVAIL (1<<0)
#define UART_TX_AVAIL (1<<1)
#define UART_RX_FULL (1<<2)
#define UART_TX_BUSY (1<<3)
#define UART_RX_ERROR (1<<4)
 
//-------------------------------------------------------------
// serial_init:
/altor32/trunk/sw/bootloader/boot_flash.c
1,7 → 1,6
//-----------------------------------------------------------------------------
//-----------------------------------------------------------------------------
// AltOR32
// Alternative Lightweight OpenRisc
// Alternative Lightweight OpenRISC
// Ultra-Embedded.com
// Copyright 2011 - 2012
//
13,23 → 12,22
// applications.
//-----------------------------------------------------------------------------
//
// This file is part of AltOR32 OpenRisc Simulator.
// This file is part of AltOR32 Alternative Lightweight OpenRISC project.
//
// AltOR32 OpenRisc Simulator is free software; you can redistribute it and/or
// modify it under the terms of the GNU General Public License as published by
// the Free Software Foundation; either version 2 of the License, or
// (at your option) any later version.
// AltOR32 is free software; you can redistribute it and/or modify it under
// the terms of the GNU General Public License as published by the Free Software
// Foundation; either version 2 of the License, or (at your option) any later
// version.
//
// AltOR32 OpenRisc Simulator is distributed in the hope that it will be useful,
// but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
// GNU General Public License for more details.
// AltOR32 is distributed in the hope that it will be useful, but WITHOUT ANY
// WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS
// FOR A PARTICULAR PURPOSE. See the GNU General Public License for more
// details.
//
// You should have received a copy of the GNU General Public License
// along with AltOR32 OpenRisc Simulator; if not, write to the Free Software
// Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
// along with AltOR32; if not, write to the Free Software Foundation, Inc.,
// 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
//-----------------------------------------------------------------------------
//-----------------------------------------------------------------------------
#include "assert.h"
#include "spi_flash.h"
#include "boot_flash.h"
38,7 → 36,7
//-----------------------------------------------------------------
// Defines:
//-----------------------------------------------------------------
#define BOOTFLASH_BLOCK_SIZE SPIFLASH_BLOCKSIZE
#define BOOTFLASH_BLOCK_SIZE SPIFLASH_BLOCKSIZE
 
//-----------------------------------------------------------------
// Locals:
49,7 → 47,7
// bootflash:
//-------------------------------------------------------------
int bootflash(unsigned long target)
{
{
unsigned char *ptr = (unsigned char *)(target);
unsigned int length;
unsigned int pos = 0;
/altor32/trunk/sw/bootloader/boot_header.h
1,20 → 1,20
#ifndef __BOOT_HEADER_H__
#define __BOOT_HEADER_H__
 
//-----------------------------------------------------------------
// Defines:
//-----------------------------------------------------------------
#define BOOT_HDR_SIZE sizeof(struct boot_header)
#define BOOT_HDR_MAGIC 0xb00710ad
 
//-----------------------------------------------------------------
// Types:
//-----------------------------------------------------------------
struct boot_header
{
unsigned int jmp_code[2];
unsigned int magic;
unsigned int file_length;
};
 
#endif // __BOOT_HEADER_H__
#ifndef __BOOT_HEADER_H__
#define __BOOT_HEADER_H__
 
//-----------------------------------------------------------------
// Defines:
//-----------------------------------------------------------------
#define BOOT_HDR_SIZE sizeof(struct boot_header)
#define BOOT_HDR_MAGIC 0xb00710ad
 
//-----------------------------------------------------------------
// Types:
//-----------------------------------------------------------------
struct boot_header
{
unsigned int jmp_code[2];
unsigned int magic;
unsigned int file_length;
};
 
#endif // __BOOT_HEADER_H__
/altor32/trunk/sw/bootloader/mem_map.h
4,17 → 4,17
//-----------------------------------------------------------------
// Defines:
//-----------------------------------------------------------------
#define INT_BASE 0x00000000
#define INT_APP_BASE 0x00002000
#define EXT_BASE 0x10000000
#define IO_BASE 0x20000000
#define INT_BASE 0x00000000
#define INT_APP_BASE 0x00002000
#define EXT_BASE 0x10000000
#define IO_BASE 0x20000000
 
//-----------------------------------------------------------------
// Macros:
//-----------------------------------------------------------------
#define REG8 (volatile unsigned char*)
#define REG16 (volatile unsigned short*)
#define REG32 (volatile unsigned int*)
#define REG8 (volatile unsigned char*)
#define REG16 (volatile unsigned short*)
#define REG32 (volatile unsigned int*)
 
//-----------------------------------------------------------------
// Peripheral Base Addresses
35,26 → 35,26
// Peripheral Registers
//-----------------------------------------------------------------
 
#define UART_USR (*(REG32 (UART_BASE + 0x4)))
#define UART_UDR (*(REG32 (UART_BASE + 0x8)))
#define UART_USR (*(REG32 (UART_BASE + 0x4)))
#define UART_UDR (*(REG32 (UART_BASE + 0x8)))
 
#define TIMER_VAL (*(REG32 (TIMER_BASE + 0x0)))
#define SYS_CLK_COUNT (*(REG32 (TIMER_BASE + 0x4)))
#define TIMER_VAL (*(REG32 (TIMER_BASE + 0x0)))
#define SYS_CLK_COUNT (*(REG32 (TIMER_BASE + 0x4)))
 
#define IRQ_MASK (*(REG32 (INTR_BASE + 0x00)))
#define IRQ_MASK_SET (*(REG32 (INTR_BASE + 0x00)))
#define IRQ_MASK_CLR (*(REG32 (INTR_BASE + 0x04)))
#define IRQ_STATUS (*(REG32 (INTR_BASE + 0x08)))
#define IRQ_SYSTICK (IRQ_TIMER_SYSTICK)
#define IRQ_UART_RX_AVAIL (IRQ_UART_RX)
#define IRQ_PIT (IRQ_TIMER_HIRES)
#define IRQ_SW (3)
#define EXT_INT_OFFSET (8)
#define IRQ_MASK (*(REG32 (INTR_BASE + 0x00)))
#define IRQ_MASK_SET (*(REG32 (INTR_BASE + 0x00)))
#define IRQ_MASK_CLR (*(REG32 (INTR_BASE + 0x04)))
#define IRQ_STATUS (*(REG32 (INTR_BASE + 0x08)))
#define IRQ_SYSTICK (IRQ_TIMER_SYSTICK)
#define IRQ_UART_RX_AVAIL (IRQ_UART_RX)
#define IRQ_PIT (IRQ_TIMER_HIRES)
#define IRQ_SW (3)
#define EXT_INT_OFFSET (8)
 
#define SPI_PROM_CTRL (*(REG32 (SPI_FLASH_BASE + 0x00)))
#define SPI_PROM_CS (1 << 0)
#define SPI_PROM_STAT (*(REG32 (SPI_FLASH_BASE + 0x00)))
#define SPI_PROM_BUSY (1 << 0)
#define SPI_PROM_DATA (*(REG32 (SPI_FLASH_BASE + 0x04)))
#define SPI_PROM_CTRL (*(REG32 (SPI_FLASH_BASE + 0x00)))
#define SPI_PROM_CS (1 << 0)
#define SPI_PROM_STAT (*(REG32 (SPI_FLASH_BASE + 0x00)))
#define SPI_PROM_BUSY (1 << 0)
#define SPI_PROM_DATA (*(REG32 (SPI_FLASH_BASE + 0x04)))
 
#endif
/altor32/trunk/sw/bootloader/timer.c
1,7 → 1,6
//-----------------------------------------------------------------------------
//-----------------------------------------------------------------------------
// AltOR32
// Alternative Lightweight OpenRisc
// Alternative Lightweight OpenRISC
// Ultra-Embedded.com
// Copyright 2011 - 2012
//
13,23 → 12,22
// applications.
//-----------------------------------------------------------------------------
//
// This file is part of AltOR32 OpenRisc Simulator.
// This file is part of AltOR32 Alternative Lightweight OpenRISC project.
//
// AltOR32 OpenRisc Simulator is free software; you can redistribute it and/or
// modify it under the terms of the GNU General Public License as published by
// the Free Software Foundation; either version 2 of the License, or
// (at your option) any later version.
// AltOR32 is free software; you can redistribute it and/or modify it under
// the terms of the GNU General Public License as published by the Free Software
// Foundation; either version 2 of the License, or (at your option) any later
// version.
//
// AltOR32 OpenRisc Simulator is distributed in the hope that it will be useful,
// but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
// GNU General Public License for more details.
// AltOR32 is distributed in the hope that it will be useful, but WITHOUT ANY
// WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS
// FOR A PARTICULAR PURPOSE. See the GNU General Public License for more
// details.
//
// You should have received a copy of the GNU General Public License
// along with AltOR32 OpenRisc Simulator; if not, write to the Free Software
// Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
// along with AltOR32; if not, write to the Free Software Foundation, Inc.,
// 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
//-----------------------------------------------------------------------------
//-----------------------------------------------------------------------------
#include "timer.h"
 
//--------------------------------------------------------------------------
/altor32/trunk/sw/bootloader/main.c
1,7 → 1,6
//-----------------------------------------------------------------------------
//-----------------------------------------------------------------------------
// AltOR32
// Alternative Lightweight OpenRisc
// Alternative Lightweight OpenRISC
// Ultra-Embedded.com
// Copyright 2011 - 2012
//
13,23 → 12,22
// applications.
//-----------------------------------------------------------------------------
//
// This file is part of AltOR32 OpenRisc Simulator.
// This file is part of AltOR32 Alternative Lightweight OpenRISC project.
//
// AltOR32 OpenRisc Simulator is free software; you can redistribute it and/or
// modify it under the terms of the GNU General Public License as published by
// the Free Software Foundation; either version 2 of the License, or
// (at your option) any later version.
// AltOR32 is free software; you can redistribute it and/or modify it under
// the terms of the GNU General Public License as published by the Free Software
// Foundation; either version 2 of the License, or (at your option) any later
// version.
//
// AltOR32 OpenRisc Simulator is distributed in the hope that it will be useful,
// but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
// GNU General Public License for more details.
// AltOR32 is distributed in the hope that it will be useful, but WITHOUT ANY
// WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS
// FOR A PARTICULAR PURPOSE. See the GNU General Public License for more
// details.
//
// You should have received a copy of the GNU General Public License
// along with AltOR32 OpenRisc Simulator; if not, write to the Free Software
// Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
// along with AltOR32; if not, write to the Free Software Foundation, Inc.,
// 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
//-----------------------------------------------------------------------------
//-----------------------------------------------------------------------------
#include "timer.h"
#include "serial.h"
#include "boot_serial.h"
51,11 → 49,11
typedef int (*fnptr)(void);
fnptr app_start;
 
app_start = (fnptr)(addr);
app_start();
app_start = (fnptr)(addr);
app_start();
 
while (1)
;
while (1)
;
}
//-----------------------------------------------------------------
// main:
78,40 → 76,40
serial_putstr("<F> PROM (FPGA)\n");
 
tStart = timer_now();
while (timer_diff(timer_now(), tStart) < BOOT_TIMEOUT || no_flash_boot == 1)
{
int ch = serial_getchar();
if (ch == 'I')
{
serial_putstr("Internal (BRAM) X-modem boot...\n");
boot_serial(INT_APP_BASE, 0);
while (timer_diff(timer_now(), tStart) < BOOT_TIMEOUT || no_flash_boot == 1)
{
int ch = serial_getchar();
if (ch == 'I')
{
serial_putstr("Internal (BRAM) X-modem boot...\n");
boot_serial(INT_APP_BASE, 0);
 
// Jump to application reset vector
application_boot(INT_APP_BASE + 0x100);
}
else if (ch == 'E')
{
serial_putstr("External X-modem boot...\n");
boot_serial(EXT_BASE, 0);
}
else if (ch == 'E')
{
serial_putstr("External X-modem boot...\n");
boot_serial(EXT_BASE, 0);
 
// Jump to application reset vector
application_boot(EXT_BASE + 0x100);
}
else if (ch == 'A')
{
serial_putstr("PROM (App) X-modem flash...\n");
boot_serial(SPIFLASH_APP_OFFSET, 1);
}
else if (ch == 'A')
{
serial_putstr("PROM (App) X-modem flash...\n");
boot_serial(SPIFLASH_APP_OFFSET, 1);
no_flash_boot = 1;
continue;
}
else if (ch == 'F')
{
serial_putstr("PROM (FPGA) X-modem flash...\n");
boot_serial(SPIFLASH_FPGA_OFFSET, 1);
}
else if (ch == 'F')
{
serial_putstr("PROM (FPGA) X-modem flash...\n");
boot_serial(SPIFLASH_FPGA_OFFSET, 1);
no_flash_boot = 1;
continue;
}
}
}
}
 
serial_putstr("Boot from PROM (App)...\n");
 
118,7 → 116,7
// Auto boot SPI PROM image if available
if (bootflash(BOOT_FLASH_TARGET))
{
// Normal boot
// Normal boot
application_boot(BOOT_FLASH_TARGET + 0x100);
}
// No image available, wait for X-modem image
/altor32/trunk/sw/bootloader/serial.h
1,15 → 1,15
#ifndef __SERIAL_H__
#define __SERIAL_H__
 
//-----------------------------------------------------------------
// Prototypes:
//-----------------------------------------------------------------
void serial_init (void);
int serial_putchar(char ch);
int serial_getchar(void);
int serial_haschar();
void serial_putstr(char *str);
void serial_putnum( int n );
void serial_printstrnum(char *str1, unsigned int hexnum, char *str2);
 
#endif // __SERIAL_H__
#ifndef __SERIAL_H__
#define __SERIAL_H__
 
//-----------------------------------------------------------------
// Prototypes:
//-----------------------------------------------------------------
void serial_init (void);
int serial_putchar(char ch);
int serial_getchar(void);
int serial_haschar();
void serial_putstr(char *str);
void serial_putnum( int n );
void serial_printstrnum(char *str1, unsigned int hexnum, char *str2);
 
#endif // __SERIAL_H__
/altor32/trunk/sw/bootloader/timer.h
1,21 → 1,21
#ifndef __TIMER_H__
#define __TIMER_H__
 
#include "mem_map.h"
 
//-----------------------------------------------------------------
// Defines:
//-----------------------------------------------------------------
typedef unsigned long t_time;
 
//-----------------------------------------------------------------
// Prototypes:
//-----------------------------------------------------------------
 
// General timer
void timer_init(void);
static t_time timer_now(void) { return TIMER_VAL; }
static long timer_diff(t_time a, t_time b) { return (long)(a - b); }
void timer_sleep(int timeMs);
 
#endif
#ifndef __TIMER_H__
#define __TIMER_H__
 
#include "mem_map.h"
 
//-----------------------------------------------------------------
// Defines:
//-----------------------------------------------------------------
typedef unsigned long t_time;
 
//-----------------------------------------------------------------
// Prototypes:
//-----------------------------------------------------------------
 
// General timer
void timer_init(void);
static t_time timer_now(void) { return TIMER_VAL; }
static long timer_diff(t_time a, t_time b) { return (long)(a - b); }
void timer_sleep(int timeMs);
 
#endif
/altor32/trunk/sw/bootloader/boot_flash.h
1,9 → 1,9
#ifndef __BOOT_FLASH_H__
#define __BOOT_FLASH_H__
 
//-----------------------------------------------------------------
// Prototypes:
//-----------------------------------------------------------------
int bootflash(unsigned long target);
 
#endif // __BOOT_FLASH_H__
#ifndef __BOOT_FLASH_H__
#define __BOOT_FLASH_H__
 
//-----------------------------------------------------------------
// Prototypes:
//-----------------------------------------------------------------
int bootflash(unsigned long target);
 
#endif // __BOOT_FLASH_H__
/altor32/trunk/sw/bootloader/xmodem.c
1,7 → 1,6
//-----------------------------------------------------------------------------
//-----------------------------------------------------------------------------
// AltOR32
// Alternative Lightweight OpenRisc
// Alternative Lightweight OpenRISC
// Ultra-Embedded.com
// Copyright 2011 - 2012
//
13,23 → 12,22
// applications.
//-----------------------------------------------------------------------------
//
// This file is part of AltOR32 OpenRisc Simulator.
// This file is part of AltOR32 Alternative Lightweight OpenRISC project.
//
// AltOR32 OpenRisc Simulator is free software; you can redistribute it and/or
// modify it under the terms of the GNU General Public License as published by
// the Free Software Foundation; either version 2 of the License, or
// (at your option) any later version.
// AltOR32 is free software; you can redistribute it and/or modify it under
// the terms of the GNU General Public License as published by the Free Software
// Foundation; either version 2 of the License, or (at your option) any later
// version.
//
// AltOR32 OpenRisc Simulator is distributed in the hope that it will be useful,
// but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
// GNU General Public License for more details.
// AltOR32 is distributed in the hope that it will be useful, but WITHOUT ANY
// WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS
// FOR A PARTICULAR PURPOSE. See the GNU General Public License for more
// details.
//
// You should have received a copy of the GNU General Public License
// along with AltOR32 OpenRisc Simulator; if not, write to the Free Software
// Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
// along with AltOR32; if not, write to the Free Software Foundation, Inc.,
// 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
//-----------------------------------------------------------------------------
//-----------------------------------------------------------------------------
#include <string.h>
#include "xmodem.h"
#include "timer.h"
37,16 → 35,16
//-----------------------------------------------------------------
// Defines
//-----------------------------------------------------------------
#define XMODEM_HDR_SIZE 6
#define XMODEM_HDR_SIZE 6
 
// Control character codes
#define SOH 0x01
#define STX 0x02
#define EOT 0x04
#define ACK 0x06
#define NAK 0x15
#define CAN 0x18
#define CTRLZ 0x1A
#define SOH 0x01
#define STX 0x02
#define EOT 0x04
#define ACK 0x06
#define NAK 0x15
#define CAN 0x18
#define CTRLZ 0x1A
 
#define XMODEM_CRC_REQ 'C'
 
235,7 → 233,7
}
//-----------------------------------------------------------------
// calc_crc_16: Calculate 16 bit CRC used by XModem(CRC)
// Polynomial x^16 + x^12 + x^5 + 1 (0x1021)
// Polynomial x^16 + x^12 + x^5 + 1 (0x1021)
//-----------------------------------------------------------------
static unsigned short calc_crc_16(unsigned char *data, int length)
{
268,7 → 266,7
{
unsigned char sum = 0;
while (length)
while (length)
{
sum += *data++;
length--;

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