URL
https://opencores.org/ocsvn/altor32/altor32/trunk
Subversion Repositories altor32
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- This comparison shows the changes necessary to convert path
/altor32/trunk/rtl/cpu
- from Rev 37 to Rev 39
- ↔ Reverse comparison
Rev 37 → Rev 39
/altor32_defs.v
145,25 → 145,25
//----------------------------------------------------------------- |
// SR Register bits |
//----------------------------------------------------------------- |
`define OR32_SR_SM 0 |
`define OR32_SR_TEE 1 |
`define OR32_SR_IEE 2 |
`define OR32_SR_DCE 3 |
`define OR32_SR_ICE 4 |
`define OR32_SR_DME 5 |
`define OR32_SR_IME 6 |
`define OR32_SR_LEE 7 |
`define OR32_SR_CE 8 |
`define OR32_SR_F 9 |
`define OR32_SR_CY 10 |
`define OR32_SR_OV 11 |
`define OR32_SR_OVE 12 |
`define OR32_SR_DSX 13 |
`define OR32_SR_EPH 14 |
`define OR32_SR_FO 15 |
`define OR32_SR_TED 16 |
`define OR32_SR_ICACHE_FLUSH 17 |
`define OR32_SR_DCACHE_FLUSH 18 |
`define SR_SM 0 |
`define SR_TEE 1 |
`define SR_IEE 2 |
`define SR_DCE 3 |
`define SR_ICE 4 |
`define SR_DME 5 |
`define SR_IME 6 |
`define SR_LEE 7 |
`define SR_CE 8 |
`define SR_F 9 |
`define SR_CY 10 |
`define SR_OV 11 |
`define SR_OVE 12 |
`define SR_DSX 13 |
`define SR_EPH 14 |
`define SR_FO 15 |
`define SR_SUMRA 16 |
`define SR_ICACHE_FLUSH 17 |
`define SR_DCACHE_FLUSH 18 |
|
//----------------------------------------------------------------- |
// OR32 Vectors |
/altor32_exec.v
198,6 → 198,9
// Delayed NMI |
reg nmi_q; |
|
// Exception/Interrupt was last instruction |
reg exc_last_q; |
|
// SIM PUTC |
`ifdef SIM_EXT_PUTC |
reg [7:0] putc_q; |
214,7 → 217,7
// Operands |
.a_i(ex_alu_a_q), |
.b_i(ex_alu_b_q), |
.c_i(sr_q[`OR32_SR_CY]), |
.c_i(sr_q[`SR_CY]), |
|
// Result |
.p_o(ex_result_w), |
496,11 → 499,11
|
// Update SR.F |
if (alu_flag_update_w) |
next_sr_r[`OR32_SR_F] = compare_result_r; |
next_sr_r[`SR_F] = compare_result_r; |
|
// Latch carry if updated |
if (alu_carry_update_w) |
next_sr_r[`OR32_SR_CY] = alu_carry_out_w; |
next_sr_r[`SR_CY] = alu_carry_out_w; |
|
// If valid instruction, check if SR needs updating |
if (execute_inst_r & ~stall_inst_r) |
515,8 → 518,8
next_sr_r = reg_rb_r; |
|
// Don't store cache flush requests |
next_sr_r[`OR32_SR_ICACHE_FLUSH] = 1'b0; |
next_sr_r[`OR32_SR_DCACHE_FLUSH] = 1'b0; |
next_sr_r[`SR_ICACHE_FLUSH] = 1'b0; |
next_sr_r[`SR_DCACHE_FLUSH] = 1'b0; |
end |
default: |
; |
540,21 → 543,31
begin |
next_epc_r = epc_q; |
next_esr_r = esr_q; |
// Instruction after interrupt, update SR.F |
if (exc_last_q && alu_flag_update_w) |
next_esr_r[`SR_F] = compare_result_r; |
|
// Instruction after interrupt, latch carry if updated |
if (exc_last_q && alu_carry_update_w) |
next_esr_r[`SR_CY] = alu_carry_out_w; |
|
case (1'b1) |
inst_mtspr_w: // l.mtspr |
if (execute_inst_r & ~stall_inst_r) |
begin |
case (mxspr_uint16_r) |
// EPCR - EPC Exception saved PC |
`SPR_REG_EPCR: next_epc_r = reg_rb_r; |
case (1'b1) |
inst_mtspr_w: // l.mtspr |
begin |
case (mxspr_uint16_r) |
// EPCR - EPC Exception saved PC |
`SPR_REG_EPCR: next_epc_r = reg_rb_r; |
|
// ESR - Exception saved SR |
`SPR_REG_ESR: next_esr_r = reg_rb_r; |
endcase |
// ESR - Exception saved SR |
`SPR_REG_ESR: next_esr_r = reg_rb_r; |
endcase |
end |
default: |
; |
endcase |
end |
default: |
; |
endcase |
end |
|
//----------------------------------------------------------------- |
958,10 → 971,10
|
case (1'b1) |
inst_bf_w: // l.bf |
branch_r = next_sr_r[`OR32_SR_F]; |
branch_r = next_sr_r[`SR_F]; |
|
inst_bnf_w: // l.bnf |
branch_r = ~next_sr_r[`OR32_SR_F]; |
branch_r = ~next_sr_r[`SR_F]; |
|
inst_j_w: // l.j |
branch_r = 1'b1; |
1177,6 → 1190,7
begin |
pc_branch_q <= 32'h00000000; |
pc_fetch_q <= 1'b0; |
exc_last_q <= 1'b0; |
|
// Status registers |
epc_q <= 32'h00000000; |
1195,10 → 1209,16
|
// Reset branch request |
pc_fetch_q <= 1'b0; |
exc_last_q <= 1'b0; |
|
// Update SR |
sr_q <= next_sr_r; |
|
// Update EPC / ESR which may have been updated by an |
// MTSPR write / flag update in instruction after interrupt |
epc_q <= next_epc_r; |
esr_q <= next_esr_r; |
|
// Instruction ready |
if (execute_inst_r & ~stall_inst_r) |
begin |
1218,6 → 1238,7
else |
pc_branch_q <= ISR_VECTOR + `VECTOR_BUS_ERROR; |
pc_fetch_q <= 1'b1; |
exc_last_q <= 1'b1; |
|
fault_o <= 1'b1; |
end |
1233,7 → 1254,8
|
// Set PC to exception vector |
pc_branch_q <= branch_target_r; |
pc_fetch_q <= 1'b1; |
pc_fetch_q <= 1'b1; |
exc_last_q <= 1'b1; |
|
`ifdef CONF_CORE_DEBUG |
$display(" Exception 0x%08x", branch_target_r); |
1259,6 → 1281,7
// Set PC to exception vector |
pc_branch_q <= ISR_VECTOR + `VECTOR_NMI; |
pc_fetch_q <= 1'b1; |
exc_last_q <= 1'b1; |
|
`ifdef CONF_CORE_DEBUG |
$display(" NMI 0x%08x", ISR_VECTOR + `VECTOR_NMI); |
1265,7 → 1288,7
`endif |
end |
// External interrupt |
else if (intr_i && next_sr_r[`OR32_SR_IEE]) |
else if (intr_i && next_sr_r[`SR_IEE]) |
begin |
// Save PC of next instruction & SR |
if (branch_r) |
1282,6 → 1305,7
// Set PC to external interrupt vector |
pc_branch_q <= ISR_VECTOR + `VECTOR_EXTINT; |
pc_fetch_q <= 1'b1; |
exc_last_q <= 1'b1; |
|
`ifdef CONF_CORE_DEBUG |
$display(" External Interrupt 0x%08x", ISR_VECTOR + `VECTOR_EXTINT); |
1298,14 → 1322,6
$display(" Branch to 0x%08x", branch_target_r); |
`endif |
end |
// Non branch |
else |
begin |
// Update EPC / ESR which may have been updated |
// by an MTSPR write |
epc_q <= next_epc_r; |
esr_q <= next_esr_r; |
end |
end |
end |
end |
1528,8 → 1544,8
`SPR_REG_SR: |
begin |
// Cache flush request? |
icache_flush_o <= reg_rb_r[`OR32_SR_ICACHE_FLUSH]; |
dcache_flush_o <= reg_rb_r[`OR32_SR_DCACHE_FLUSH]; |
icache_flush_o <= reg_rb_r[`SR_ICACHE_FLUSH]; |
dcache_flush_o <= reg_rb_r[`SR_DCACHE_FLUSH]; |
end |
endcase |
end |