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URL https://opencores.org/ocsvn/altor32/altor32/trunk

Subversion Repositories altor32

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  • This comparison shows the changes necessary to convert path 
    /altor32/trunk/rtl/peripheral
    from Rev 27 to Rev 32
    ↔ Reverse comparison
  •

Rev 27 → Rev 32

/intr_periph.v
65,8 → 65,8
addr_i,
data_o,
data_i,
wr_i,
rd_i
we_i,
stb_i
);
 
//-----------------------------------------------------------------
94,8 → 94,8
input [7:0] addr_i /*verilator public*/;
output [31:0] data_o /*verilator public*/;
input [31:0] data_i /*verilator public*/;
input [3:0] wr_i /*verilator public*/;
input rd_i /*verilator public*/;
input we_i /*verilator public*/;
input stb_i /*verilator public*/;
 
//-----------------------------------------------------------------
// Registers / Wires
175,7 → 175,7
intr_o <= ((v_irq_status & irq_mask) != {(INTERRUPT_COUNT){1'b0}}) ? 1'b1 : 1'b0;
 
// Write Cycle
if (wr_i != 4'b0000)
if (we_i & stb_i)
begin
case (addr_i)
 
198,33 → 198,22
//-----------------------------------------------------------------
// Peripheral Register Read
//-----------------------------------------------------------------
always @ (posedge rst_i or posedge clk_i )
always @ *
begin
if (rst_i == 1'b1)
begin
data_o <= 32'h00000000;
end
else
begin
// Read cycle?
if (rd_i == 1'b1)
begin
case (addr_i[7:0])
case (addr_i[7:0])
 
`IRQ_MASK_SET :
data_o <= {{(32-INTERRUPT_COUNT){1'b0}}, irq_mask};
`IRQ_MASK_SET :
data_o = {{(32-INTERRUPT_COUNT){1'b0}}, irq_mask};
 
`IRQ_MASK_CLR :
data_o <= {{(32-INTERRUPT_COUNT){1'b0}}, irq_mask};
`IRQ_MASK_CLR :
data_o = {{(32-INTERRUPT_COUNT){1'b0}}, irq_mask};
 
`IRQ_STATUS :
data_o <= {{(32-INTERRUPT_COUNT){1'b0}}, irq_status};
`IRQ_STATUS :
data_o = {{(32-INTERRUPT_COUNT){1'b0}}, irq_status};
 
default :
data_o <= 32'h00000000;
endcase
end
end
default :
data_o = 32'h00000000;
endcase
end
 
endmodule
/timer_periph.v
57,8 → 57,8
addr_i,
data_o,
data_i,
wr_i,
rd_i
we_i,
stb_i
);
 
//-----------------------------------------------------------------
81,8 → 81,8
input [7:0] addr_i /*verilator public*/;
output [31:0] data_o /*verilator public*/;
input [31:0] data_i /*verilator public*/;
input [3:0] wr_i /*verilator public*/;
input rd_i /*verilator public*/;
input we_i /*verilator public*/;
input stb_i /*verilator public*/;
 
//-----------------------------------------------------------------
// Registers / Wires
231,7 → 231,7
else
begin
// Write Cycle
if (wr_i != 4'b0000)
if (we_i & stb_i)
begin
case (addr_i)
 
248,32 → 248,21
//-----------------------------------------------------------------
// Peripheral Register Read
//-----------------------------------------------------------------
always @ (posedge rst_i or posedge clk_i )
always @ *
begin
if (rst_i == 1'b1)
begin
data_o <= 32'h00000000;
end
else
begin
// Read cycle?
if (rd_i == 1'b1)
begin
case (addr_i[7:0])
case (addr_i[7:0])
 
// 32-bit systick/1ms counter
`TIMER_SYSTICK_VAL :
data_o <= systick_count;
// 32-bit systick/1ms counter
`TIMER_SYSTICK_VAL :
data_o = systick_count;
 
// Hi res timer (clock rate)
`TIMER_HIRES :
data_o <= hr_timer_cnt;
// Hi res timer (clock rate)
`TIMER_HIRES :
data_o = hr_timer_cnt;
 
default :
data_o <= 32'h00000000;
endcase
end
end
default :
data_o = 32'h00000000;
endcase
end
 
endmodule

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