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URL https://opencores.org/ocsvn/altor32/altor32/trunk

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  • This comparison shows the changes necessary to convert path 
    /altor32/trunk
    from Rev 15 to Rev 16
    ↔ Reverse comparison
  •

Rev 15 → Rev 16

/rtl/sim_verilator/top.v
121,8 → 121,8
.UART_BAUD(115200),
.EXTERNAL_INTERRUPTS(1),
.CORE_ID(32'h00000000),
.BOOT_VECTOR(32'h00002000),
.ISR_VECTOR(32'h0000203C)
.BOOT_VECTOR(32'h00000000),
.ISR_VECTOR(32'h00000000)
)
u1_cpu
(
146,6 → 146,14
.int_mem_rd_o(/*open */),
.int_mem_pause_i(1'b0),
// External Memory
.ext_mem_addr_o(/*open */),
.ext_mem_data_o(/*open */),
.ext_mem_data_i(32'h00000000),
.ext_mem_wr_o(/*open */),
.ext_mem_rd_o(/*open */),
.ext_mem_pause_i(1'b0),
// External I/O or Memory
.ext_io_addr_o(/*open */),
.ext_io_data_o(/*open */),
/rtl/core_pipelined/altor32.v
72,7 → 72,8
//-----------------------------------------------------------------
// Params
//-----------------------------------------------------------------
parameter [31:0] BOOT_VECTOR = 32'h00000100;
parameter [31:0] BOOT_VECTOR = 32'h00000000;
parameter [31:0] ISR_VECTOR = 32'h00000000;
 
//-----------------------------------------------------------------
// I/O
343,7 → 344,7
begin
if (rst_i == 1'b1)
begin
r_pc <= BOOT_VECTOR;
r_pc <= BOOT_VECTOR + `VECTOR_RESET;
r_epc <= 32'h00000000;
r_sr <= 32'h00000000;
677,7 → 678,7
begin
fault_o <= 1'b1;
v_exception = 1'b1;
v_vector = `VECTOR_ILLEGAL_INST;
v_vector = ISR_VECTOR + `VECTOR_ILLEGAL_INST;
end
endcase
end
785,7 → 786,7
begin
fault_o <= 1'b1;
v_exception = 1'b1;
v_vector = `VECTOR_ILLEGAL_INST;
v_vector = ISR_VECTOR + `VECTOR_ILLEGAL_INST;
end
endcase
end
815,7 → 816,7
begin
fault_o <= 1'b1;
v_exception = 1'b1;
v_vector = `VECTOR_ILLEGAL_INST;
v_vector = ISR_VECTOR + `VECTOR_ILLEGAL_INST;
end
endcase
end
879,7 → 880,7
begin
fault_o <= 1'b1;
v_exception = 1'b1;
v_vector = `VECTOR_ILLEGAL_INST;
v_vector = ISR_VECTOR + `VECTOR_ILLEGAL_INST;
end
endcase
end
1088,7 → 1089,7
begin
fault_o <= 1'b1;
v_exception = 1'b1;
v_vector = `VECTOR_ILLEGAL_INST;
v_vector = ISR_VECTOR + `VECTOR_ILLEGAL_INST;
end
endcase
end
1137,13 → 1138,13
`INST_OR32_SYS: // l.sys
begin
v_exception = 1'b1;
v_vector = `VECTOR_SYSCALL;
v_vector = ISR_VECTOR + `VECTOR_SYSCALL;
end
`INST_OR32_TRAP: // l.trap
begin
v_exception = 1'b1;
v_vector = `VECTOR_TRAP;
v_vector = ISR_VECTOR + `VECTOR_TRAP;
break_o <= 1'b1;
end
1151,7 → 1152,7
begin
fault_o <= 1'b1;
v_exception = 1'b1;
v_vector = `VECTOR_ILLEGAL_INST;
v_vector = ISR_VECTOR + `VECTOR_ILLEGAL_INST;
end
endcase
end
1168,7 → 1169,7
begin
fault_o <= 1'b1;
v_exception = 1'b1;
v_vector = `VECTOR_ILLEGAL_INST;
v_vector = ISR_VECTOR + `VECTOR_ILLEGAL_INST;
end
endcase
1291,7 → 1292,7
v_sr = 0;
// Set PC to external interrupt vector
v_pc = `VECTOR_EXTINT;
v_pc = ISR_VECTOR + `VECTOR_EXTINT;
r_pc <= v_pc;
// Do not execute next instruction which will be PC + 4.
/rtl/soc/alt_soc.v
70,6 → 70,14
int_mem_rd_o,
int_mem_pause_i,
// External Memory
ext_mem_addr_o,
ext_mem_data_o,
ext_mem_data_i,
ext_mem_wr_o,
ext_mem_rd_o,
ext_mem_pause_i,
// External IO
ext_io_addr_o,
ext_io_data_o,
120,6 → 128,12
output [3:0] int_mem_wr_o /*verilator public*/;
output int_mem_rd_o /*verilator public*/;
input int_mem_pause_i /*verilator public*/;
output [31:0] ext_mem_addr_o /*verilator public*/;
output [31:0] ext_mem_data_o /*verilator public*/;
input [31:0] ext_mem_data_i /*verilator public*/;
output [3:0] ext_mem_wr_o /*verilator public*/;
output ext_mem_rd_o /*verilator public*/;
input ext_mem_pause_i /*verilator public*/;
output [31:0] ext_io_addr_o /*verilator public*/;
output [31:0] ext_io_data_o /*verilator public*/;
input [31:0] ext_io_data_i /*verilator public*/;
137,20 → 151,18
//-----------------------------------------------------------------
// Registers
//-----------------------------------------------------------------
reg [31:0] v_irq_status;
reg [2:0] r_mem_sel;
wire [31:0] cpu_address;
wire [3:0] cpu_byte_we;
wire cpu_oe;
wire [31:0] cpu_data_w;
reg [31:0] cpu_data_r;
reg cpu_pause;
wire [31:0] cpu_data_r;
wire cpu_pause;
 
reg [31:0] io_address;
reg [31:0] io_data_w;
wire [31:0] io_address;
wire [31:0] io_data_w;
wire [31:0] io_data_r;
reg [3:0] io_wr;
reg io_rd;
wire [3:0] io_wr;
wire io_rd;
 
// IRQ Status
wire intr_in;
157,14 → 169,18
 
// Output Signals
wire uart_tx_o;
reg [31:0] int_mem_addr_o;
reg [31:0] int_mem_data_o;
reg [3:0] int_mem_wr_o;
reg int_mem_rd_o;
reg [31:0] ext_io_addr_o;
reg [31:0] ext_io_data_o;
reg [3:0] ext_io_wr_o;
reg ext_io_rd_o;
wire [31:0] int_mem_addr_o;
wire [31:0] int_mem_data_o;
wire [3:0] int_mem_wr_o;
wire int_mem_rd_o;
wire [31:0] ext_io_addr_o;
wire [31:0] ext_io_data_o;
wire [3:0] ext_io_wr_o;
wire ext_io_rd_o;
wire [31:0] ext_mem_addr_o;
wire [31:0] ext_mem_data_o;
wire [3:0] ext_mem_wr_o;
wire ext_mem_rd_o;
wire flash_cs_o;
wire flash_si_o;
wire flash_sck_o;
203,6 → 219,10
 
// MPX CPU
altor32
#(
.BOOT_VECTOR(BOOT_VECTOR),
.ISR_VECTOR(ISR_VECTOR)
)
u1_cpu
(
.clk_i(clk_i),
220,6 → 240,60
.dbg_pc_o(dbg_pc_o)
);
 
mem_mux
#(
.BOOT_VECTOR(BOOT_VECTOR)
)
u2_mux
(
.clk_i(clk_i),
.rst_i(rst_i),
// Input
.mem_addr_i(cpu_address),
.mem_data_i(cpu_data_w),
.mem_data_o(cpu_data_r),
.mem_wr_i(cpu_byte_we),
.mem_rd_i(cpu_oe),
.mem_pause_o(cpu_pause),
// Outputs
.out0_addr_o(int_mem_addr_o),
.out0_data_o(int_mem_data_o),
.out0_data_i(int_mem_data_i),
.out0_wr_o(int_mem_wr_o),
.out0_rd_o(int_mem_rd_o),
.out0_pause_i(int_mem_pause_i),
.out1_addr_o(ext_mem_addr_o),
.out1_data_o(ext_mem_data_o),
.out1_data_i(ext_mem_data_i),
.out1_wr_o(ext_mem_wr_o),
.out1_rd_o(ext_mem_rd_o),
.out1_pause_i(ext_mem_pause_i),
.out2_addr_o(io_address),
.out2_data_o(io_data_w),
.out2_data_i(io_data_r),
.out2_wr_o(io_wr),
.out2_rd_o(io_rd),
.out2_pause_i(1'b0),
.out3_addr_o(ext_io_addr_o),
.out3_data_o(ext_io_data_o),
.out3_data_i(ext_io_data_i),
.out3_wr_o(ext_io_wr_o),
.out3_rd_o(ext_io_rd_o),
.out3_pause_i(ext_io_pause_i),
.out4_addr_o(/*open*/),
.out4_data_o(/*open*/),
.out4_data_i(32'h00000000),
.out4_wr_o(/*open*/),
.out4_rd_o(/*open*/),
.out4_pause_i(1'b0)
);
 
// Peripheral Interconnect
soc_pif
u2_soc
388,142 → 462,6
);
 
//-----------------------------------------------------------------
// Memory Map
//-----------------------------------------------------------------
always @ (cpu_address or cpu_byte_we or cpu_oe or cpu_data_w )
begin
case (cpu_address[30:28])
// Block RAM
`MEM_REGION_INTERNAL :
begin
int_mem_addr_o = cpu_address;
int_mem_wr_o = cpu_byte_we;
int_mem_rd_o = cpu_oe;
int_mem_data_o = cpu_data_w;
io_address = 32'h00000000;
io_wr = 4'b0000;
io_rd = 1'b0;
io_data_w = 32'h00000000;
ext_io_addr_o = 32'h00000000;
ext_io_wr_o = 4'b0000;
ext_io_rd_o = 1'b0;
ext_io_data_o = 32'h00000000;
end
// Core I/O peripherals
`MEM_REGION_CORE_IO :
begin
io_address = cpu_address;
io_wr = cpu_byte_we;
io_rd = cpu_oe;
io_data_w = cpu_data_w;
int_mem_addr_o = 32'h00000000;
int_mem_wr_o = 4'b0000;
int_mem_rd_o = 1'b0;
int_mem_data_o = 32'h00000000;
ext_io_addr_o = 32'h00000000;
ext_io_wr_o = 4'b0000;
ext_io_rd_o = 1'b0;
ext_io_data_o = 32'h00000000;
end
// Extended I/O peripherals
`MEM_REGION_EXT_IO :
begin
ext_io_addr_o = cpu_address;
ext_io_wr_o = cpu_byte_we;
ext_io_rd_o = cpu_oe;
ext_io_data_o = cpu_data_w;
int_mem_addr_o = 32'h00000000;
int_mem_wr_o = 4'b0000;
int_mem_rd_o = 1'b0;
int_mem_data_o = 32'h00000000;
io_address = 32'h00000000;
io_wr = 4'b0000;
io_rd = 1'b0;
io_data_w = 32'h00000000;
end
default :
begin
io_address = 32'h00000000;
io_wr = 4'b0000;
io_rd = 1'b0;
io_data_w = 32'h00000000;
int_mem_addr_o = 32'h00000000;
int_mem_wr_o = 4'b0000;
int_mem_rd_o = 1'b0;
int_mem_data_o = 32'h00000000;
ext_io_addr_o = 32'h00000000;
ext_io_wr_o = 4'b0000;
ext_io_rd_o = 1'b0;
ext_io_data_o = 32'h00000000;
end
endcase
end
//-----------------------------------------------------------------
// Read Port
//-----------------------------------------------------------------
always @ (r_mem_sel or int_mem_data_i or io_data_r or ext_io_data_i or int_mem_pause_i or ext_io_pause_i)
begin
case (r_mem_sel)
// Block RAM
`MEM_REGION_INTERNAL :
begin
cpu_data_r = int_mem_data_i;
cpu_pause = int_mem_pause_i;
end
// Core I/O peripherals
`MEM_REGION_CORE_IO :
begin
cpu_data_r = io_data_r;
cpu_pause = 1'b0;
end
// Extended I/O peripherals
`MEM_REGION_EXT_IO :
begin
cpu_data_r = ext_io_data_i;
cpu_pause = ext_io_pause_i;
end
default :
begin
cpu_data_r = 32'h00000000;
cpu_pause = 1'b0;
end
endcase
end
//-----------------------------------------------------------------
// Registered device select
//-----------------------------------------------------------------
reg [31:0] v_mem_sel;
always @ (posedge clk_i or posedge rst_i )
begin
if (rst_i == 1'b1)
begin
v_mem_sel = BOOT_VECTOR;
r_mem_sel <= v_mem_sel[30:28];
end
else
r_mem_sel <= cpu_address[30:28];
end
//-----------------------------------------------------------------
// External Interface
//-----------------------------------------------------------------
// Debug UART
/rtl/soc/mem_mux.v
0,0 → 1,415
//-----------------------------------------------------------------
// AltOR32
// Alternative Lightweight OpenRisc
// V0.1
// Ultra-Embedded.com
// Copyright 2011 - 2012
//
// Email: admin@ultra-embedded.com
//
// License: LGPL
//
// If you would like a version with a different license for use
// in commercial projects please contact the above email address
// for more details.
//-----------------------------------------------------------------
//
// Copyright (C) 2011 - 2012 Ultra-Embedded.com
//
// This source file may be used and distributed without
// restriction provided that this copyright statement is not
// removed from the file and that any derivative work contains
// the original copyright notice and the associated disclaimer.
//
// This source file is free software; you can redistribute it
// and/or modify it under the terms of the GNU Lesser General
// Public License as published by the Free Software Foundation;
// either version 2.1 of the License, or (at your option) any
// later version.
//
// This source is distributed in the hope that it will be
// useful, but WITHOUT ANY WARRANTY; without even the implied
// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR
// PURPOSE. See the GNU Lesser General Public License for more
// details.
//
// You should have received a copy of the GNU Lesser General
// Public License along with this source; if not, write to the
// Free Software Foundation, Inc., 59 Temple Place, Suite 330,
// Boston, MA 02111-1307 USA
//-----------------------------------------------------------------
 
//-----------------------------------------------------------------
// Module:
//-----------------------------------------------------------------
module mem_mux
(
// General
clk_i,
rst_i,
// Input
mem_addr_i,
mem_data_i,
mem_data_o,
mem_wr_i,
mem_rd_i,
mem_pause_o,
// Outputs
out0_addr_o,
out0_data_o,
out0_data_i,
out0_wr_o,
out0_rd_o,
out0_pause_i,
out1_addr_o,
out1_data_o,
out1_data_i,
out1_wr_o,
out1_rd_o,
out1_pause_i,
out2_addr_o,
out2_data_o,
out2_data_i,
out2_wr_o,
out2_rd_o,
out2_pause_i,
out3_addr_o,
out3_data_o,
out3_data_i,
out3_wr_o,
out3_rd_o,
out3_pause_i,
out4_addr_o,
out4_data_o,
out4_data_i,
out4_wr_o,
out4_rd_o,
out4_pause_i
);
 
//-----------------------------------------------------------------
// Params
//-----------------------------------------------------------------
parameter BOOT_VECTOR = 0;
//-----------------------------------------------------------------
// I/O
//-----------------------------------------------------------------
input clk_i /*verilator public*/;
input rst_i /*verilator public*/;
input [31:0] mem_addr_i /*verilator public*/;
input [31:0] mem_data_i /*verilator public*/;
output [31:0] mem_data_o /*verilator public*/;
input [3:0] mem_wr_i /*verilator public*/;
input mem_rd_i /*verilator public*/;
output mem_pause_o /*verilator public*/;
output [31:0] out0_addr_o /*verilator public*/;
output [31:0] out0_data_o /*verilator public*/;
input [31:0] out0_data_i /*verilator public*/;
output [3:0] out0_wr_o /*verilator public*/;
output out0_rd_o /*verilator public*/;
input out0_pause_i /*verilator public*/;
output [31:0] out1_addr_o /*verilator public*/;
output [31:0] out1_data_o /*verilator public*/;
input [31:0] out1_data_i /*verilator public*/;
output [3:0] out1_wr_o /*verilator public*/;
output out1_rd_o /*verilator public*/;
input out1_pause_i /*verilator public*/;
output [31:0] out2_addr_o /*verilator public*/;
output [31:0] out2_data_o /*verilator public*/;
input [31:0] out2_data_i /*verilator public*/;
output [3:0] out2_wr_o /*verilator public*/;
output out2_rd_o /*verilator public*/;
input out2_pause_i /*verilator public*/;
output [31:0] out3_addr_o /*verilator public*/;
output [31:0] out3_data_o /*verilator public*/;
input [31:0] out3_data_i /*verilator public*/;
output [3:0] out3_wr_o /*verilator public*/;
output out3_rd_o /*verilator public*/;
input out3_pause_i /*verilator public*/;
output [31:0] out4_addr_o /*verilator public*/;
output [31:0] out4_data_o /*verilator public*/;
input [31:0] out4_data_i /*verilator public*/;
output [3:0] out4_wr_o /*verilator public*/;
output out4_rd_o /*verilator public*/;
input out4_pause_i /*verilator public*/;
 
//-----------------------------------------------------------------
// Registers
//-----------------------------------------------------------------
reg [2:0] r_mem_sel;
 
// Output Signals
reg mem_pause_o;
reg [31:0] mem_data_o;
reg [31:0] out0_addr_o;
reg [31:0] out0_data_o;
reg [3:0] out0_wr_o;
reg out0_rd_o;
reg [31:0] out1_addr_o;
reg [31:0] out1_data_o;
reg [3:0] out1_wr_o;
reg out1_rd_o;
reg [31:0] out2_addr_o;
reg [31:0] out2_data_o;
reg [3:0] out2_wr_o;
reg out2_rd_o;
reg [31:0] out3_addr_o;
reg [31:0] out3_data_o;
reg [3:0] out3_wr_o;
reg out3_rd_o;
reg [31:0] out4_addr_o;
reg [31:0] out4_data_o;
reg [3:0] out4_wr_o;
reg out4_rd_o;
 
//-----------------------------------------------------------------
// Memory Map
//-----------------------------------------------------------------
always @ (mem_addr_i or mem_wr_i or mem_rd_i or mem_data_i )
begin
case (mem_addr_i[30:28])
3'b000 :
begin
out0_addr_o = mem_addr_i;
out0_wr_o = mem_wr_i;
out0_rd_o = mem_rd_i;
out0_data_o = mem_data_i;
out1_addr_o = 32'h00000000;
out1_wr_o = 4'b0000;
out1_rd_o = 1'b0;
out1_data_o = 32'h00000000;
out2_addr_o = 32'h00000000;
out2_wr_o = 4'b0000;
out2_rd_o = 1'b0;
out2_data_o = 32'h00000000;
out3_addr_o = 32'h00000000;
out3_wr_o = 4'b0000;
out3_rd_o = 1'b0;
out3_data_o = 32'h00000000;
out4_addr_o = 32'h00000000;
out4_wr_o = 4'b0000;
out4_rd_o = 1'b0;
out4_data_o = 32'h00000000;
end
3'b001 :
begin
out0_addr_o = 32'h00000000;
out0_wr_o = 4'b0000;
out0_rd_o = 1'b0;
out0_data_o = 32'h00000000;
out1_addr_o = mem_addr_i;
out1_wr_o = mem_wr_i;
out1_rd_o = mem_rd_i;
out1_data_o = mem_data_i;
out2_addr_o = 32'h00000000;
out2_wr_o = 4'b0000;
out2_rd_o = 1'b0;
out2_data_o = 32'h00000000;
out3_addr_o = 32'h00000000;
out3_wr_o = 4'b0000;
out3_rd_o = 1'b0;
out3_data_o = 32'h00000000;
out4_addr_o = 32'h00000000;
out4_wr_o = 4'b0000;
out4_rd_o = 1'b0;
out4_data_o = 32'h00000000;
end
3'b010 :
begin
out0_addr_o = 32'h00000000;
out0_wr_o = 4'b0000;
out0_rd_o = 1'b0;
out0_data_o = 32'h00000000;
out1_addr_o = 32'h00000000;
out1_wr_o = 4'b0000;
out1_rd_o = 1'b0;
out1_data_o = 32'h00000000;
out2_addr_o = mem_addr_i;
out2_wr_o = mem_wr_i;
out2_rd_o = mem_rd_i;
out2_data_o = mem_data_i;
out3_addr_o = 32'h00000000;
out3_wr_o = 4'b0000;
out3_rd_o = 1'b0;
out3_data_o = 32'h00000000;
out4_addr_o = 32'h00000000;
out4_wr_o = 4'b0000;
out4_rd_o = 1'b0;
out4_data_o = 32'h00000000;
end
3'b011 :
begin
out0_addr_o = 32'h00000000;
out0_wr_o = 4'b0000;
out0_rd_o = 1'b0;
out0_data_o = 32'h00000000;
out1_addr_o = 32'h00000000;
out1_wr_o = 4'b0000;
out1_rd_o = 1'b0;
out1_data_o = 32'h00000000;
out2_addr_o = 32'h00000000;
out2_wr_o = 4'b0000;
out2_rd_o = 1'b0;
out2_data_o = 32'h00000000;
out3_addr_o = mem_addr_i;
out3_wr_o = mem_wr_i;
out3_rd_o = mem_rd_i;
out3_data_o = mem_data_i;
out4_addr_o = 32'h00000000;
out4_wr_o = 4'b0000;
out4_rd_o = 1'b0;
out4_data_o = 32'h00000000;
end
3'b100 :
begin
out0_addr_o = 32'h00000000;
out0_wr_o = 4'b0000;
out0_rd_o = 1'b0;
out0_data_o = 32'h00000000;
out1_addr_o = 32'h00000000;
out1_wr_o = 4'b0000;
out1_rd_o = 1'b0;
out1_data_o = 32'h00000000;
out2_addr_o = 32'h00000000;
out2_wr_o = 4'b0000;
out2_rd_o = 1'b0;
out2_data_o = 32'h00000000;
out3_addr_o = 32'h00000000;
out3_wr_o = 4'b0000;
out3_rd_o = 1'b0;
out3_data_o = 32'h00000000;
out4_addr_o = mem_addr_i;
out4_wr_o = mem_wr_i;
out4_rd_o = mem_rd_i;
out4_data_o = mem_data_i;
end
default :
begin
out0_addr_o = 32'h00000000;
out0_wr_o = 4'b0000;
out0_rd_o = 1'b0;
out0_data_o = 32'h00000000;
out1_addr_o = 32'h00000000;
out1_wr_o = 4'b0000;
out1_rd_o = 1'b0;
out1_data_o = 32'h00000000;
out2_addr_o = 32'h00000000;
out2_wr_o = 4'b0000;
out2_rd_o = 1'b0;
out2_data_o = 32'h00000000;
out3_addr_o = 32'h00000000;
out3_wr_o = 4'b0000;
out3_rd_o = 1'b0;
out3_data_o = 32'h00000000;
out4_addr_o = 32'h00000000;
out4_wr_o = 4'b0000;
out4_rd_o = 1'b0;
out4_data_o = 32'h00000000;
end
endcase
end
//-----------------------------------------------------------------
// Read Port
//-----------------------------------------------------------------
always @ ( r_mem_sel or
out0_data_i or out0_pause_i or
out1_data_i or out1_pause_i or
out2_data_i or out2_pause_i or
out3_data_i or out3_pause_i or
out4_data_i or out4_pause_i )
begin
case (r_mem_sel)
3'b000 :
begin
mem_data_o = out0_data_i;
mem_pause_o = out0_pause_i;
end
3'b001 :
begin
mem_data_o = out1_data_i;
mem_pause_o = out1_pause_i;
end
3'b010 :
begin
mem_data_o = out2_data_i;
mem_pause_o = out2_pause_i;
end
3'b011 :
begin
mem_data_o = out3_data_i;
mem_pause_o = out3_pause_i;
end
3'b100 :
begin
mem_data_o = out4_data_i;
mem_pause_o = out4_pause_i;
end
default :
begin
mem_data_o = 32'h00000000;
mem_pause_o = 1'b0;
end
endcase
end
//-----------------------------------------------------------------
// Registered device select
//-----------------------------------------------------------------
reg [31:0] v_mem_sel;
always @ (posedge clk_i or posedge rst_i )
begin
if (rst_i == 1'b1)
begin
v_mem_sel = BOOT_VECTOR;
r_mem_sel <= v_mem_sel[30:28];
end
else
r_mem_sel <= mem_addr_i[30:28];
end
endmodule
/fpga/papilio_xc3s250e/top.vhd
179,12 → 179,14
datab_o => open
);
 
-- MPX CPU SOC
-- CPU SOC
U3_CPU: alt_soc
generic map
(
CLK_KHZ => (CPU_MHZ * 1000),
UART_BAUD => 115200,
BOOT_VECTOR => X"00000000",
ISR_VECTOR => X"00002000",
EXTERNAL_INTERRUPTS => 1
)
port map
217,6 → 219,14
ext_io_rd_o => io_rd,
ext_io_pause_i => '0',
-- External Memory
ext_mem_addr_o => open,
ext_mem_data_o => open,
ext_mem_data_i => X"00000000",
ext_mem_wr_o => open,
ext_mem_rd_o => open,
ext_mem_pause_i => '0',
-- SPI Flash
flash_cs_o => flash_cs,
flash_si_o => flash_si,
/fpga/papilio_xc3s250e/fpga_papilio_xc3s250e.bit Cannot display: file marked as a binary type. svn:mime-type = application/octet-stream
/fpga/papilio_xc3s250e/components.vhd
55,9 → 55,8
UART_BAUD : integer := 115200;
SPI_FLASH_CLK_KHZ : integer := 12288 / 2;
EXTERNAL_INTERRUPTS : integer := 1;
CORE_ID : std_logic_vector := X"00000000";
BOOT_VECTOR : std_logic_vector := X"00000000";
ISR_VECTOR : std_logic_vector := X"0000003C"
ISR_VECTOR : std_logic_vector := X"00000000"
);
port
(
71,28 → 70,36
 
-- UART
uart_tx_o : out std_logic;
uart_rx_i : in std_logic;
uart_rx_i : in std_logic;
-- BootRAM
int_mem_addr_o : out std_logic_vector(32-1 downto 0);
int_mem_data_o : out std_logic_vector(32-1 downto 0);
int_mem_data_i : in std_logic_vector(32-1 downto 0);
int_mem_wr_o : out std_logic_vector(3 downto 0);
int_mem_rd_o : out std_logic;
int_mem_addr_o : out std_logic_vector(32-1 downto 0);
int_mem_data_o : out std_logic_vector(32-1 downto 0);
int_mem_data_i : in std_logic_vector(32-1 downto 0);
int_mem_wr_o : out std_logic_vector(3 downto 0);
int_mem_rd_o : out std_logic;
int_mem_pause_i : in std_logic;
-- External Memory
ext_mem_addr_o : out std_logic_vector(32-1 downto 0);
ext_mem_data_o : out std_logic_vector(32-1 downto 0);
ext_mem_data_i : in std_logic_vector(32-1 downto 0);
ext_mem_wr_o : out std_logic_vector(3 downto 0);
ext_mem_rd_o : out std_logic;
ext_mem_pause_i : in std_logic;
-- External IO
ext_io_addr_o : out std_logic_vector(32-1 downto 0);
ext_io_data_o : out std_logic_vector(32-1 downto 0);
ext_io_data_i : in std_logic_vector(32-1 downto 0);
ext_io_wr_o : out std_logic_vector(3 downto 0);
ext_io_rd_o : out std_logic;
ext_io_pause_i : in std_logic;
ext_io_addr_o : out std_logic_vector(32-1 downto 0);
ext_io_data_o : out std_logic_vector(32-1 downto 0);
ext_io_data_i : in std_logic_vector(32-1 downto 0);
ext_io_wr_o : out std_logic_vector(3 downto 0);
ext_io_rd_o : out std_logic;
ext_io_pause_i : in std_logic;
-- SPI Flash
flash_cs_o : out std_logic;
flash_si_o : out std_logic;
flash_so_i : in std_logic;
flash_so_i : in std_logic;
flash_sck_o : out std_logic;
-- Debug Access
/fpga/papilio_xc3s250e/project.xise
21,7 → 21,7
</file>
<file xil_pn:name="components.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="2"/>
<association xil_pn:name="Implementation" xil_pn:seqID="13"/>
<association xil_pn:name="Implementation" xil_pn:seqID="14"/>
</file>
<file xil_pn:name="fpga.ucf" xil_pn:type="FILE_UCF">
<association xil_pn:name="Implementation" xil_pn:seqID="0"/>
28,11 → 28,11
</file>
<file xil_pn:name="program.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="4"/>
<association xil_pn:name="Implementation" xil_pn:seqID="12"/>
<association xil_pn:name="Implementation" xil_pn:seqID="13"/>
</file>
<file xil_pn:name="top.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="5"/>
<association xil_pn:name="Implementation" xil_pn:seqID="14"/>
<association xil_pn:name="Implementation" xil_pn:seqID="15"/>
</file>
<file xil_pn:name="../../rtl/peripheral/spi_master.v" xil_pn:type="FILE_VERILOG">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="14"/>
44,11 → 44,11
</file>
<file xil_pn:name="../../rtl/soc/alt_soc.v" xil_pn:type="FILE_VERILOG">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="233"/>
<association xil_pn:name="Implementation" xil_pn:seqID="11"/>
<association xil_pn:name="Implementation" xil_pn:seqID="12"/>
</file>
<file xil_pn:name="../../rtl/core_pipelined/altor32.v" xil_pn:type="FILE_VERILOG">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="21"/>
<association xil_pn:name="Implementation" xil_pn:seqID="10"/>
<association xil_pn:name="Implementation" xil_pn:seqID="11"/>
</file>
<file xil_pn:name="../../rtl/core_pipelined/altor32_alu.v" xil_pn:type="FILE_VERILOG">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="22"/>
60,24 → 60,28
</file>
<file xil_pn:name="../../rtl/peripheral/intr_periph.v" xil_pn:type="FILE_VERILOG">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="68"/>
<association xil_pn:name="Implementation" xil_pn:seqID="9"/>
<association xil_pn:name="Implementation" xil_pn:seqID="10"/>
</file>
<file xil_pn:name="../../rtl/peripheral/spim_periph.v" xil_pn:type="FILE_VERILOG">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="70"/>
<association xil_pn:name="Implementation" xil_pn:seqID="8"/>
<association xil_pn:name="Implementation" xil_pn:seqID="9"/>
</file>
<file xil_pn:name="../../rtl/peripheral/timer_periph.v" xil_pn:type="FILE_VERILOG">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="72"/>
<association xil_pn:name="Implementation" xil_pn:seqID="7"/>
<association xil_pn:name="Implementation" xil_pn:seqID="8"/>
</file>
<file xil_pn:name="../../rtl/peripheral/uart_periph.v" xil_pn:type="FILE_VERILOG">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="74"/>
<association xil_pn:name="Implementation" xil_pn:seqID="6"/>
<association xil_pn:name="Implementation" xil_pn:seqID="7"/>
</file>
<file xil_pn:name="../../rtl/soc/soc_pif.v" xil_pn:type="FILE_VERILOG">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="75"/>
<association xil_pn:name="Implementation" xil_pn:seqID="5"/>
</file>
<file xil_pn:name="../../rtl/soc/mem_mux.v" xil_pn:type="FILE_VERILOG">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="76"/>
<association xil_pn:name="Implementation" xil_pn:seqID="6"/>
</file>
</files>
 
<properties>
386,12 → 390,12
<!-- include files. -->
<file xil_pn:name="../../rtl/core_pipelined/altor32_defs.v" xil_pn:type="FILE_VERILOG"/>
<file xil_pn:name="../../rtl/core_pipelined/altor32_funcs.v" xil_pn:type="FILE_VERILOG"/>
<file xil_pn:name="../../rtl/soc/alt_soc_defs.v" xil_pn:type="FILE_VERILOG"/>
<file xil_pn:name="../../rtl/soc/alt_soc_conf.v" xil_pn:type="FILE_VERILOG"/>
<file xil_pn:name="../../rtl/peripheral/intr_defs.v" xil_pn:type="FILE_VERILOG"/>
<file xil_pn:name="../../rtl/peripheral/spim_defs.v" xil_pn:type="FILE_VERILOG"/>
<file xil_pn:name="../../rtl/peripheral/timer_defs.v" xil_pn:type="FILE_VERILOG"/>
<file xil_pn:name="../../rtl/peripheral/uart_defs.v" xil_pn:type="FILE_VERILOG"/>
<file xil_pn:name="../../rtl/soc/alt_soc_defs.v" xil_pn:type="FILE_VERILOG"/>
<file xil_pn:name="../../rtl/soc/alt_soc_conf.v" xil_pn:type="FILE_VERILOG"/>
</autoManagedFiles>
 
</project>

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