URL
https://opencores.org/ocsvn/altor32/altor32/trunk
Subversion Repositories altor32
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- This comparison shows the changes necessary to convert path
/altor32/trunk
- from Rev 18 to Rev 19
- ↔ Reverse comparison
Rev 18 → Rev 19
/rtl/soc/soc_pif.v
104,17 → 104,6
periph7_wr_o, |
periph7_rd_o |
); |
|
//----------------------------------------------------------------- |
// Params |
//----------------------------------------------------------------- |
parameter [31:0] CLK_KHZ = 12288; |
parameter [31:0] UART_BAUD = 115200; |
parameter [31:0] SPI_FLASH_CLK_KHZ = (12288/2); |
parameter [31:0] EXTERNAL_INTERRUPTS = 1; |
parameter CORE_ID = 0; |
parameter BOOT_VECTOR = 0; |
parameter ISR_VECTOR = 0; |
|
//----------------------------------------------------------------- |
// I/O |
/rtl/peripheral/intr_defs.v
44,7 → 44,6
// Registers |
//----------------------------------------------------------------- |
`define IRQ_MASK_SET 8'h00 |
`define IRQ_MASK_STATUS 8'h04 |
`define IRQ_MASK_CLR 8'h08 |
`define IRQ_STATUS 8'h0C |
`define IRQ_MASK_CLR 8'h04 |
`define IRQ_STATUS 8'h08 |
`define IRQ_EXT_FIRST (8) |
/rtl/peripheral/intr_periph.v
216,7 → 216,7
data_o <= irq_mask; |
|
`IRQ_STATUS : |
data_o <= (irq_status & irq_mask); |
data_o <= irq_status; |
|
default : |
data_o <= 32'h00000000; |
/sw/bootloader/mem_map.h
41,10 → 41,10
#define TIMER_VAL (*(REG32 (TIMER_BASE + 0x0))) |
#define SYS_CLK_COUNT (*(REG32 (TIMER_BASE + 0x4))) |
|
#define IRQ_MASK (*(REG32 (INTR_BASE + 0x00))) |
#define IRQ_MASK_SET (*(REG32 (INTR_BASE + 0x00))) |
#define IRQ_MASK_STATUS (*(REG32 (INTR_BASE + 0x04))) |
#define IRQ_MASK_CLR (*(REG32 (INTR_BASE + 0x08))) |
#define IRQ_STATUS (*(REG32 (INTR_BASE + 0x0C))) |
#define IRQ_MASK_CLR (*(REG32 (INTR_BASE + 0x04))) |
#define IRQ_STATUS (*(REG32 (INTR_BASE + 0x08))) |
#define IRQ_SYSTICK (IRQ_TIMER_SYSTICK) |
#define IRQ_UART_RX_AVAIL (IRQ_UART_RX) |
#define IRQ_PIT (IRQ_TIMER_HIRES) |
/fpga/papilio_xc3s250e/sw/mem_map.h
41,10 → 41,10
#define TIMER_VAL (*(REG32 (TIMER_BASE + 0x0))) |
#define SYS_CLK_COUNT (*(REG32 (TIMER_BASE + 0x4))) |
|
#define IRQ_MASK (*(REG32 (INTR_BASE + 0x00))) |
#define IRQ_MASK_SET (*(REG32 (INTR_BASE + 0x00))) |
#define IRQ_MASK_STATUS (*(REG32 (INTR_BASE + 0x04))) |
#define IRQ_MASK_CLR (*(REG32 (INTR_BASE + 0x08))) |
#define IRQ_STATUS (*(REG32 (INTR_BASE + 0x0C))) |
#define IRQ_MASK_CLR (*(REG32 (INTR_BASE + 0x04))) |
#define IRQ_STATUS (*(REG32 (INTR_BASE + 0x08))) |
#define IRQ_SYSTICK (IRQ_TIMER_SYSTICK) |
#define IRQ_UART_RX_AVAIL (IRQ_UART_RX) |
#define IRQ_PIT (IRQ_TIMER_HIRES) |