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URL https://opencores.org/ocsvn/altor32/altor32/trunk

Subversion Repositories altor32

Compare Revisions

  • This comparison shows the changes necessary to convert path 
    /altor32
    from Rev 11 to Rev 12
    ↔ Reverse comparison
  •

Rev 11 → Rev 12

/trunk/rtl/sim_verilator/top.v
143,7 → 143,8
.int_mem_data_o(int_mem_data_o),
.int_mem_data_i(int_mem_data_i),
.int_mem_wr_o(int_mem_wr_o),
.int_mem_rd_o(/*open */),
.int_mem_rd_o(/*open */),
.int_mem_pause_i(1'b0),
// External I/O or Memory
.ext_io_addr_o(/*open */),
/trunk/rtl/sim_verilator/makefile
9,6 → 9,9
# Waveform trace disabled by default
TRACE?= 0
 
# Enable debug output
DEBUG?= 0
 
# Top module (without .v extension)
TOP_MODULE = top
 
27,6 → 30,10
VERILATOR_OPTS += --trace
endif
 
ifeq ($(DEBUG),1)
VERILATOR_OPTS += +define+CONF_CORE_DEBUG+
endif
 
all: run
compile: clean
/trunk/rtl/core_simple/altor32.v
244,20 → 244,17
r_rb <= 5'b00000;
end
// Instruction fetch cycle
else if ((en_i == 1'b1) && (mem_pause_i == 1'b0))
else if ((en_i == 1'b1) && (r_state == STATE_FETCH))
begin
if (r_state == STATE_FETCH)
begin
// Decode opcode in-order to perform register accesses
r_opcode <= mem_data_in_i;
r_rd <= mem_data_in_i[25:21];
r_ra <= mem_data_in_i[20:16];
r_rb <= mem_data_in_i[15:11];
// Decode opcode in-order to perform register accesses
r_opcode <= mem_data_in_i;
r_rd <= mem_data_in_i[25:21];
r_ra <= mem_data_in_i[20:16];
r_rb <= mem_data_in_i[15:11];
`ifdef CONF_CORE_DEBUG
$display("%08x: Fetch 0x%08x", r_pc, mem_data_in_i);
$display("%08x: Fetch 0x%08x", r_pc, mem_data_in_i);
`endif
end
end
end
 
322,8 → 319,8
break_o <= 1'b0;
r_mem_access <= 1'b0;
end
// Enabled & memory not busy
else if ((en_i == 1'b1) && (mem_pause_i == 1'b0))
// Enabled
else if (en_i == 1'b1)
begin
r_mem_access <= 1'b0;
330,6 → 327,15
mem_rd <= 1'b0;
mem_wr <= 4'b0000;
break_o <= 1'b0;
// Memory stalls are not supported by this version of the core
if (mem_pause_i == 1'b1)
begin
fault_o <= 1'b1;
`ifdef CONF_CORE_DEBUG
$display("Memory pause not supported on this implementation!");
`endif
end
// Execute stage?
if (r_state == STATE_EXECUTE)
1014,12 → 1020,6
end
end
end
// Memory paused?
else if (en_i == 1'b1)
begin
mem_rd <= 1'b0;
mem_wr <= 4'b0000;
end
end
 
//-------------------------------------------------------------------
1034,11 → 1034,13
begin
r_writeback <= 1'b1;
end
else
// Enabled
else if (en_i == 1'b1)
begin
r_writeback <= 1'b0;
if ((en_i == 1'b1) && (mem_pause_i == 1'b0) && (r_state == STATE_WRITEBACK))
// Writeback stage?
if (r_state == STATE_WRITEBACK)
begin
wb_v_reg_result = r_reg_result;
1149,8 → 1151,7
begin
r_state <= STATE_RESET;
end
else
if (en_i == 1'b1 && mem_pause_i == 1'b0)
else if (en_i == 1'b1)
begin
case (r_state)
STATE_RESET :
1189,7 → 1190,7
assign mem_addr_o = (r_mem_access == 1'b1) ? mem_addr : r_pc;
assign mem_data_out_o = (r_mem_access == 1'b1) ? mem_data_out : 32'h00000000;
assign mem_rd_o = (r_mem_access == 1'b1) ? mem_rd : 1'b1;
assign mem_wr_o = (mem_pause_i == 1'b0) ? mem_wr : 4'b0000;
assign mem_wr_o = mem_wr;
 
assign dbg_pc_o = r_pc;
 
/trunk/rtl/soc/alt_soc.v
68,6 → 68,7
int_mem_data_i,
int_mem_wr_o,
int_mem_rd_o,
int_mem_pause_i,
// External IO
ext_io_addr_o,
118,6 → 119,7
input [31:0] int_mem_data_i /*verilator public*/;
output [3:0] int_mem_wr_o /*verilator public*/;
output int_mem_rd_o /*verilator public*/;
input int_mem_pause_i /*verilator public*/;
output [31:0] ext_io_addr_o /*verilator public*/;
output [31:0] ext_io_data_o /*verilator public*/;
input [31:0] ext_io_data_i /*verilator public*/;
628,7 → 630,7
//-----------------------------------------------------------------
// Read Port
//-----------------------------------------------------------------
always @ (r_mem_sel or int_mem_data_i or io_data_r or ext_io_data_i)
always @ (r_mem_sel or int_mem_data_i or io_data_r or ext_io_data_i or int_mem_pause_i or ext_io_pause_i)
begin
case (r_mem_sel)
636,7 → 638,7
`MEM_REGION_INTERNAL :
begin
cpu_data_r = int_mem_data_i;
cpu_pause = 1'b0;
cpu_pause = int_mem_pause_i;
end
// Core I/O peripherals
650,7 → 652,7
`MEM_REGION_EXT_IO :
begin
cpu_data_r = ext_io_data_i;
cpu_pause = 1'b0;
cpu_pause = ext_io_pause_i;
end
default :
/trunk/fpga/papilio_xc3s250e/top.vhd
50,7 → 50,7
(
OSC_MHZ : integer := 32;
-- Target CPU MHz (must be a multiple of 2)
CPU_MHZ : integer := 60
CPU_MHZ : integer := 58
);
port
(
220,6 → 220,7
int_mem_data_i => bram_mem_data_r,
int_mem_wr_o => bram_mem_wr,
int_mem_rd_o => open,
int_mem_pause_i => '0',
 
-- External IO
ext_io_addr_o => io_address,
/trunk/fpga/papilio_xc3s250e/components.vhd
51,55 → 51,56
component alt_soc
generic
(
CLK_KHZ : integer := 12288;
UART_BAUD : integer := 115200;
SPI_FLASH_CLK_KHZ : integer := 12288 / 2;
EXTERNAL_INTERRUPTS : integer := 1;
CORE_ID : std_logic_vector := X"00000000";
BOOT_VECTOR : std_logic_vector := X"00000000";
ISR_VECTOR : std_logic_vector := X"0000003C"
CLK_KHZ : integer := 12288;
UART_BAUD : integer := 115200;
SPI_FLASH_CLK_KHZ : integer := 12288 / 2;
EXTERNAL_INTERRUPTS : integer := 1;
CORE_ID : std_logic_vector := X"00000000";
BOOT_VECTOR : std_logic_vector := X"00000000";
ISR_VECTOR : std_logic_vector := X"0000003C"
);
port
(
-- General - clocking & rst_i
clk_i : in std_logic;
rst_i : in std_logic;
en_i : in std_logic;
ext_intr_i : in std_logic_vector(EXTERNAL_INTERRUPTS-1 downto 0);
fault_o : out std_logic;
break_o : out std_logic;
-- General - clocking & rst_i
clk_i : in std_logic;
rst_i : in std_logic;
en_i : in std_logic;
ext_intr_i : in std_logic_vector(EXTERNAL_INTERRUPTS-1 downto 0);
fault_o : out std_logic;
break_o : out std_logic;
 
-- UART
uart_tx_o : out std_logic;
uart_rx_i : in std_logic;
-- BootRAM
int_mem_addr_o : out std_logic_vector(32-1 downto 0);
int_mem_data_o : out std_logic_vector(32-1 downto 0);
int_mem_data_i : in std_logic_vector(32-1 downto 0);
int_mem_wr_o : out std_logic_vector(3 downto 0);
int_mem_rd_o : out std_logic;
-- External IO
ext_io_addr_o : out std_logic_vector(32-1 downto 0);
ext_io_data_o : out std_logic_vector(32-1 downto 0);
ext_io_data_i : in std_logic_vector(32-1 downto 0);
ext_io_wr_o : out std_logic_vector(3 downto 0);
ext_io_rd_o : out std_logic;
ext_io_pause_i : in std_logic;
-- SPI Flash
flash_cs_o : out std_logic;
flash_si_o : out std_logic;
flash_so_i : in std_logic;
flash_sck_o : out std_logic;
-- Debug Access
dbg_pc_o : out std_logic_vector(31 downto 0);
-- Debug UART Output
dbg_uart_data_o : out std_logic_vector(7 downto 0);
dbg_uart_wr_o : out std_logic
-- UART
uart_tx_o : out std_logic;
uart_rx_i : in std_logic;
-- BootRAM
int_mem_addr_o : out std_logic_vector(32-1 downto 0);
int_mem_data_o : out std_logic_vector(32-1 downto 0);
int_mem_data_i : in std_logic_vector(32-1 downto 0);
int_mem_wr_o : out std_logic_vector(3 downto 0);
int_mem_rd_o : out std_logic;
int_mem_pause_i : in std_logic;
-- External IO
ext_io_addr_o : out std_logic_vector(32-1 downto 0);
ext_io_data_o : out std_logic_vector(32-1 downto 0);
ext_io_data_i : in std_logic_vector(32-1 downto 0);
ext_io_wr_o : out std_logic_vector(3 downto 0);
ext_io_rd_o : out std_logic;
ext_io_pause_i : in std_logic;
-- SPI Flash
flash_cs_o : out std_logic;
flash_si_o : out std_logic;
flash_so_i : in std_logic;
flash_sck_o : out std_logic;
-- Debug Access
dbg_pc_o : out std_logic_vector(31 downto 0);
-- Debug UART Output
dbg_uart_data_o : out std_logic_vector(7 downto 0);
dbg_uart_wr_o : out std_logic
);
end component;
 
106,19 → 107,19
component ClockDCM is
generic
(
CLK_IN_MHZ : integer := 32;
CLK_OUT_MHZ : integer := 64
CLK_IN_MHZ : integer := 32;
CLK_OUT_MHZ : integer := 64
);
port
(
CLKIN_IN : in std_logic;
CLKFX_OUT : out std_logic;
CLKIN_IBUFG_OUT : out std_logic
CLKIN_IN : in std_logic;
CLKFX_OUT : out std_logic;
CLKIN_IBUFG_OUT : out std_logic
);
end component;
 
end peripherals;
package body peripherals is
end; --package body
/trunk/fpga/papilio_xc3s250e/project.xise
34,10 → 34,6
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="5"/>
<association xil_pn:name="Implementation" xil_pn:seqID="10"/>
</file>
<file xil_pn:name="../../rtl/soc/mpx_soc.v" xil_pn:type="FILE_VERILOG"/>
<file xil_pn:name="../../rtl/altor32/altor32.v" xil_pn:type="FILE_VERILOG"/>
<file xil_pn:name="../../rtl/altor32/altor32_alu.v" xil_pn:type="FILE_VERILOG"/>
<file xil_pn:name="../../rtl/altor32/altor32_regfile_xil.v" xil_pn:type="FILE_VERILOG"/>
<file xil_pn:name="../../rtl/peripheral/spi_master.v" xil_pn:type="FILE_VERILOG">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="14"/>
<association xil_pn:name="Implementation" xil_pn:seqID="4"/>
51,15 → 47,15
<association xil_pn:name="Implementation" xil_pn:seqID="6"/>
</file>
<file xil_pn:name="../../rtl/core_simple/altor32.v" xil_pn:type="FILE_VERILOG">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="68"/>
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="21"/>
<association xil_pn:name="Implementation" xil_pn:seqID="5"/>
</file>
<file xil_pn:name="../../rtl/core_simple/altor32_alu.v" xil_pn:type="FILE_VERILOG">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="69"/>
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="22"/>
<association xil_pn:name="Implementation" xil_pn:seqID="2"/>
</file>
<file xil_pn:name="../../rtl/core_simple/altor32_regfile_xil.v" xil_pn:type="FILE_VERILOG">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="72"/>
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="23"/>
<association xil_pn:name="Implementation" xil_pn:seqID="1"/>
</file>
</files>
116,6 → 112,7
<property xil_pn:name="Enable BitStream Compression" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Enable Cyclic Redundancy Checking (CRC)" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Enable Debugging of Serial Mode BitStream" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Enable Hardware Co-Simulation" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Enable Internal Done Pipe" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Enable Message Filtering" xil_pn:value="true" xil_pn:valueState="non-default"/>
<property xil_pn:name="Enable Outputs (Output Events)" xil_pn:value="Default (5)" xil_pn:valueState="default"/>
367,10 → 364,10
<!-- Do not hand-edit this section, as it will be overwritten when the -->
<!-- project is analyzed based on files automatically identified as -->
<!-- include files. -->
<file xil_pn:name="../../rtl/core_simple/altor32_defs.v" xil_pn:type="FILE_VERILOG"/>
<file xil_pn:name="../../rtl/core_simple/altor32_funcs.v" xil_pn:type="FILE_VERILOG"/>
<file xil_pn:name="../../rtl/soc/alt_soc_defs.v" xil_pn:type="FILE_VERILOG"/>
<file xil_pn:name="../../rtl/soc/alt_soc_conf.v" xil_pn:type="FILE_VERILOG"/>
<file xil_pn:name="../../rtl/core_simple/altor32_defs.v" xil_pn:type="FILE_VERILOG"/>
<file xil_pn:name="../../rtl/core_simple/altor32_funcs.v" xil_pn:type="FILE_VERILOG"/>
</autoManagedFiles>
 
</project>

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