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Rev 14 → Rev 15

/trunk/rtl/core_pipelined/altor32.v
576,7 → 576,7
v_shift_imm = {26'b00,v_imm[5:0]};
// MTSPR/MFSPR operand
v_mxspr_imm = (v_reg_ra[15:0] | {5'b000000,v_mem_data_in[10:0]});
v_mxspr_imm = (v_reg_ra[15:0] | {5'b00000,v_mem_data_in[10:0]});
// Zero result
v_reg_result = 32'h00000000;
/trunk/rtl/soc/soc_pif.v
0,0 → 1,707
//-----------------------------------------------------------------
// AltOR32
// Alternative Lightweight OpenRisc
// V0.1
// Ultra-Embedded.com
// Copyright 2011 - 2012
//
// Email: admin@ultra-embedded.com
//
// License: LGPL
//
// If you would like a version with a different license for use
// in commercial projects please contact the above email address
// for more details.
//-----------------------------------------------------------------
//
// Copyright (C) 2011 - 2012 Ultra-Embedded.com
//
// This source file may be used and distributed without
// restriction provided that this copyright statement is not
// removed from the file and that any derivative work contains
// the original copyright notice and the associated disclaimer.
//
// This source file is free software; you can redistribute it
// and/or modify it under the terms of the GNU Lesser General
// Public License as published by the Free Software Foundation;
// either version 2.1 of the License, or (at your option) any
// later version.
//
// This source is distributed in the hope that it will be
// useful, but WITHOUT ANY WARRANTY; without even the implied
// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR
// PURPOSE. See the GNU Lesser General Public License for more
// details.
//
// You should have received a copy of the GNU Lesser General
// Public License along with this source; if not, write to the
// Free Software Foundation, Inc., 59 Temple Place, Suite 330,
// Boston, MA 02111-1307 USA
//-----------------------------------------------------------------
 
//-----------------------------------------------------------------
// Module:
//-----------------------------------------------------------------
module soc_pif
(
// General - Clocking & Reset
clk_i,
rst_i,
 
// I/O bus
io_addr_i,
io_data_i,
io_data_o,
io_wr_i,
io_rd_i,
// Peripherals
periph0_addr_o,
periph0_data_o,
periph0_data_i,
periph0_wr_o,
periph0_rd_o,
periph1_addr_o,
periph1_data_o,
periph1_data_i,
periph1_wr_o,
periph1_rd_o,
periph2_addr_o,
periph2_data_o,
periph2_data_i,
periph2_wr_o,
periph2_rd_o,
periph3_addr_o,
periph3_data_o,
periph3_data_i,
periph3_wr_o,
periph3_rd_o,
periph4_addr_o,
periph4_data_o,
periph4_data_i,
periph4_wr_o,
periph4_rd_o,
periph5_addr_o,
periph5_data_o,
periph5_data_i,
periph5_wr_o,
periph5_rd_o,
periph6_addr_o,
periph6_data_o,
periph6_data_i,
periph6_wr_o,
periph6_rd_o,
periph7_addr_o,
periph7_data_o,
periph7_data_i,
periph7_wr_o,
periph7_rd_o
);
 
//-----------------------------------------------------------------
// Params
//-----------------------------------------------------------------
parameter [31:0] CLK_KHZ = 12288;
parameter [31:0] UART_BAUD = 115200;
parameter [31:0] SPI_FLASH_CLK_KHZ = (12288/2);
parameter [31:0] EXTERNAL_INTERRUPTS = 1;
parameter CORE_ID = 0;
parameter BOOT_VECTOR = 0;
parameter ISR_VECTOR = 0;
//-----------------------------------------------------------------
// I/O
//-----------------------------------------------------------------
input clk_i /*verilator public*/;
input rst_i /*verilator public*/;
 
input [31:0] io_addr_i /*verilator public*/;
output [31:0] io_data_o /*verilator public*/;
input [31:0] io_data_i /*verilator public*/;
input [3:0] io_wr_i /*verilator public*/;
input io_rd_i /*verilator public*/;
 
output [7:0] periph0_addr_o /*verilator public*/;
output [31:0] periph0_data_o /*verilator public*/;
input [31:0] periph0_data_i /*verilator public*/;
output [3:0] periph0_wr_o /*verilator public*/;
output periph0_rd_o /*verilator public*/;
 
output [7:0] periph1_addr_o /*verilator public*/;
output [31:0] periph1_data_o /*verilator public*/;
input [31:0] periph1_data_i /*verilator public*/;
output [3:0] periph1_wr_o /*verilator public*/;
output periph1_rd_o /*verilator public*/;
 
output [7:0] periph2_addr_o /*verilator public*/;
output [31:0] periph2_data_o /*verilator public*/;
input [31:0] periph2_data_i /*verilator public*/;
output [3:0] periph2_wr_o /*verilator public*/;
output periph2_rd_o /*verilator public*/;
 
output [7:0] periph3_addr_o /*verilator public*/;
output [31:0] periph3_data_o /*verilator public*/;
input [31:0] periph3_data_i /*verilator public*/;
output [3:0] periph3_wr_o /*verilator public*/;
output periph3_rd_o /*verilator public*/;
 
output [7:0] periph4_addr_o /*verilator public*/;
output [31:0] periph4_data_o /*verilator public*/;
input [31:0] periph4_data_i /*verilator public*/;
output [3:0] periph4_wr_o /*verilator public*/;
output periph4_rd_o /*verilator public*/;
 
output [7:0] periph5_addr_o /*verilator public*/;
output [31:0] periph5_data_o /*verilator public*/;
input [31:0] periph5_data_i /*verilator public*/;
output [3:0] periph5_wr_o /*verilator public*/;
output periph5_rd_o /*verilator public*/;
 
output [7:0] periph6_addr_o /*verilator public*/;
output [31:0] periph6_data_o /*verilator public*/;
input [31:0] periph6_data_i /*verilator public*/;
output [3:0] periph6_wr_o /*verilator public*/;
output periph6_rd_o /*verilator public*/;
 
output [7:0] periph7_addr_o /*verilator public*/;
output [31:0] periph7_data_o /*verilator public*/;
input [31:0] periph7_data_i /*verilator public*/;
output [3:0] periph7_wr_o /*verilator public*/;
output periph7_rd_o /*verilator public*/;
 
//-----------------------------------------------------------------
// Registers
//-----------------------------------------------------------------
reg [3:0] r_mem_sel;
 
reg [31:0] io_data_o;
 
reg [7:0] periph0_addr_o;
reg [31:0] periph0_data_o;
reg [3:0] periph0_wr_o;
reg periph0_rd_o;
 
reg [7:0] periph1_addr_o;
reg [31:0] periph1_data_o;
reg [3:0] periph1_wr_o;
reg periph1_rd_o;
 
reg [7:0] periph2_addr_o;
reg [31:0] periph2_data_o;
reg [3:0] periph2_wr_o;
reg periph2_rd_o;
 
reg [7:0] periph3_addr_o;
reg [31:0] periph3_data_o;
reg [3:0] periph3_wr_o;
reg periph3_rd_o;
 
reg [7:0] periph4_addr_o;
reg [31:0] periph4_data_o;
reg [3:0] periph4_wr_o;
reg periph4_rd_o;
 
reg [7:0] periph5_addr_o;
reg [31:0] periph5_data_o;
reg [3:0] periph5_wr_o;
reg periph5_rd_o;
 
reg [7:0] periph6_addr_o;
reg [31:0] periph6_data_o;
reg [3:0] periph6_wr_o;
reg periph6_rd_o;
 
reg [7:0] periph7_addr_o;
reg [31:0] periph7_data_o;
reg [3:0] periph7_wr_o;
reg periph7_rd_o;
 
//-----------------------------------------------------------------
// Memory Map
//-----------------------------------------------------------------
always @ (io_addr_i or io_wr_i or io_rd_i or io_data_i)
begin
// Decode 4-bit peripheral select
case (io_addr_i[11:8])
// Peripheral 0
4'h0 :
begin
 
periph0_addr_o = io_addr_i[7:0];
periph0_wr_o = io_wr_i;
periph0_rd_o = io_rd_i;
periph0_data_o = io_data_i;
periph1_addr_o = 8'h00;
periph1_wr_o = 4'b0000;
periph1_rd_o = 1'b0;
periph1_data_o = 32'h00000000;
periph2_addr_o = 8'h00;
periph2_wr_o = 4'b0000;
periph2_rd_o = 1'b0;
periph2_data_o = 32'h00000000;
periph3_addr_o = 8'h00;
periph3_wr_o = 4'b0000;
periph3_rd_o = 1'b0;
periph3_data_o = 32'h00000000;
periph4_addr_o = 8'h00;
periph4_wr_o = 4'b0000;
periph4_rd_o = 1'b0;
periph4_data_o = 32'h00000000;
 
periph5_addr_o = 8'h00;
periph5_wr_o = 4'b0000;
periph5_rd_o = 1'b0;
periph5_data_o = 32'h00000000;
 
periph6_addr_o = 8'h00;
periph6_wr_o = 4'b0000;
periph6_rd_o = 1'b0;
periph6_data_o = 32'h00000000;
 
periph7_addr_o = 8'h00;
periph7_wr_o = 4'b0000;
periph7_rd_o = 1'b0;
periph7_data_o = 32'h00000000;
 
end
// Peripheral 1
4'h1 :
begin
periph0_addr_o = 8'h00;
periph0_wr_o = 4'b0000;
periph0_rd_o = 1'b0;
periph0_data_o = 32'h00000000;
periph1_addr_o = io_addr_i[7:0];
periph1_wr_o = io_wr_i;
periph1_rd_o = io_rd_i;
periph1_data_o = io_data_i;
periph2_addr_o = 8'h00;
periph2_wr_o = 4'b0000;
periph2_rd_o = 1'b0;
periph2_data_o = 32'h00000000;
periph3_addr_o = 8'h00;
periph3_wr_o = 4'b0000;
periph3_rd_o = 1'b0;
periph3_data_o = 32'h00000000;
periph4_addr_o = 8'h00;
periph4_wr_o = 4'b0000;
periph4_rd_o = 1'b0;
periph4_data_o = 32'h00000000;
 
periph5_addr_o = 8'h00;
periph5_wr_o = 4'b0000;
periph5_rd_o = 1'b0;
periph5_data_o = 32'h00000000;
 
periph6_addr_o = 8'h00;
periph6_wr_o = 4'b0000;
periph6_rd_o = 1'b0;
periph6_data_o = 32'h00000000;
 
periph7_addr_o = 8'h00;
periph7_wr_o = 4'b0000;
periph7_rd_o = 1'b0;
periph7_data_o = 32'h00000000;
end
// Peripheral 2
4'h2 :
begin
periph0_addr_o = 8'h00;
periph0_wr_o = 4'b0000;
periph0_rd_o = 1'b0;
periph0_data_o = 32'h00000000;
periph1_addr_o = 8'h00;
periph1_wr_o = 4'b0000;
periph1_rd_o = 1'b0;
periph1_data_o = 32'h00000000;
periph2_addr_o = io_addr_i[7:0];
periph2_wr_o = io_wr_i;
periph2_rd_o = io_rd_i;
periph2_data_o = io_data_i;
periph3_addr_o = 8'h00;
periph3_wr_o = 4'b0000;
periph3_rd_o = 1'b0;
periph3_data_o = 32'h00000000;
periph4_addr_o = 8'h00;
periph4_wr_o = 4'b0000;
periph4_rd_o = 1'b0;
periph4_data_o = 32'h00000000;
 
periph5_addr_o = 8'h00;
periph5_wr_o = 4'b0000;
periph5_rd_o = 1'b0;
periph5_data_o = 32'h00000000;
 
periph6_addr_o = 8'h00;
periph6_wr_o = 4'b0000;
periph6_rd_o = 1'b0;
periph6_data_o = 32'h00000000;
 
periph7_addr_o = 8'h00;
periph7_wr_o = 4'b0000;
periph7_rd_o = 1'b0;
periph7_data_o = 32'h00000000;
end
// Peripheral 3
4'h3 :
begin
periph0_addr_o = 8'h00;
periph0_wr_o = 4'b0000;
periph0_rd_o = 1'b0;
periph0_data_o = 32'h00000000;
periph1_addr_o = 8'h00;
periph1_wr_o = 4'b0000;
periph1_rd_o = 1'b0;
periph1_data_o = 32'h00000000;
periph2_addr_o = 8'h00;
periph2_wr_o = 4'b0000;
periph2_rd_o = 1'b0;
periph2_data_o = 32'h00000000;
periph3_addr_o = io_addr_i[7:0];
periph3_wr_o = io_wr_i;
periph3_rd_o = io_rd_i;
periph3_data_o = io_data_i;
periph4_addr_o = 8'h00;
periph4_wr_o = 4'b0000;
periph4_rd_o = 1'b0;
periph4_data_o = 32'h00000000;
 
periph5_addr_o = 8'h00;
periph5_wr_o = 4'b0000;
periph5_rd_o = 1'b0;
periph5_data_o = 32'h00000000;
 
periph6_addr_o = 8'h00;
periph6_wr_o = 4'b0000;
periph6_rd_o = 1'b0;
periph6_data_o = 32'h00000000;
 
periph7_addr_o = 8'h00;
periph7_wr_o = 4'b0000;
periph7_rd_o = 1'b0;
periph7_data_o = 32'h00000000;
end
// Peripheral 4
4'h4 :
begin
periph0_addr_o = 8'h00;
periph0_wr_o = 4'b0000;
periph0_rd_o = 1'b0;
periph0_data_o = 32'h00000000;
periph1_addr_o = 8'h00;
periph1_wr_o = 4'b0000;
periph1_rd_o = 1'b0;
periph1_data_o = 32'h00000000;
periph2_addr_o = 8'h00;
periph2_wr_o = 4'b0000;
periph2_rd_o = 1'b0;
periph2_data_o = 32'h00000000;
periph3_addr_o = 8'h00;
periph3_wr_o = 4'b0000;
periph3_rd_o = 1'b0;
periph3_data_o = 32'h00000000;
periph4_addr_o = io_addr_i[7:0];
periph4_wr_o = io_wr_i;
periph4_rd_o = io_rd_i;
periph4_data_o = io_data_i;
 
periph5_addr_o = 8'h00;
periph5_wr_o = 4'b0000;
periph5_rd_o = 1'b0;
periph5_data_o = 32'h00000000;
 
periph6_addr_o = 8'h00;
periph6_wr_o = 4'b0000;
periph6_rd_o = 1'b0;
periph6_data_o = 32'h00000000;
 
periph7_addr_o = 8'h00;
periph7_wr_o = 4'b0000;
periph7_rd_o = 1'b0;
periph7_data_o = 32'h00000000;
end
// Peripheral 5
4'h5 :
begin
periph0_addr_o = 8'h00;
periph0_wr_o = 4'b0000;
periph0_rd_o = 1'b0;
periph0_data_o = 32'h00000000;
periph1_addr_o = 8'h00;
periph1_wr_o = 4'b0000;
periph1_rd_o = 1'b0;
periph1_data_o = 32'h00000000;
periph2_addr_o = 8'h00;
periph2_wr_o = 4'b0000;
periph2_rd_o = 1'b0;
periph2_data_o = 32'h00000000;
periph3_addr_o = 8'h00;
periph3_wr_o = 4'b0000;
periph3_rd_o = 1'b0;
periph3_data_o = 32'h00000000;
periph4_addr_o = 8'h00;
periph4_wr_o = 4'b0000;
periph4_rd_o = 1'b0;
periph4_data_o = 32'h00000000;
 
periph5_addr_o = io_addr_i[7:0];
periph5_wr_o = io_wr_i;
periph5_rd_o = io_rd_i;
periph5_data_o = io_data_i;
 
periph6_addr_o = 8'h00;
periph6_wr_o = 4'b0000;
periph6_rd_o = 1'b0;
periph6_data_o = 32'h00000000;
 
periph7_addr_o = 8'h00;
periph7_wr_o = 4'b0000;
periph7_rd_o = 1'b0;
periph7_data_o = 32'h00000000;
end
// Peripheral 6
4'h6 :
begin
periph0_addr_o = 8'h00;
periph0_wr_o = 4'b0000;
periph0_rd_o = 1'b0;
periph0_data_o = 32'h00000000;
periph1_addr_o = 8'h00;
periph1_wr_o = 4'b0000;
periph1_rd_o = 1'b0;
periph1_data_o = 32'h00000000;
periph2_addr_o = 8'h00;
periph2_wr_o = 4'b0000;
periph2_rd_o = 1'b0;
periph2_data_o = 32'h00000000;
periph3_addr_o = 8'h00;
periph3_wr_o = 4'b0000;
periph3_rd_o = 1'b0;
periph3_data_o = 32'h00000000;
periph4_addr_o = 8'h00;
periph4_wr_o = 4'b0000;
periph4_rd_o = 1'b0;
periph4_data_o = 32'h00000000;
 
periph5_addr_o = 8'h00;
periph5_wr_o = 4'b0000;
periph5_rd_o = 1'b0;
periph5_data_o = 32'h00000000;
 
periph6_addr_o = io_addr_i[7:0];
periph6_wr_o = io_wr_i;
periph6_rd_o = io_rd_i;
periph6_data_o = io_data_i;
 
periph7_addr_o = 8'h00;
periph7_wr_o = 4'b0000;
periph7_rd_o = 1'b0;
periph7_data_o = 32'h00000000;
end
// Peripheral 7
4'h7 :
begin
periph0_addr_o = 8'h00;
periph0_wr_o = 4'b0000;
periph0_rd_o = 1'b0;
periph0_data_o = 32'h00000000;
periph1_addr_o = 8'h00;
periph1_wr_o = 4'b0000;
periph1_rd_o = 1'b0;
periph1_data_o = 32'h00000000;
periph2_addr_o = 8'h00;
periph2_wr_o = 4'b0000;
periph2_rd_o = 1'b0;
periph2_data_o = 32'h00000000;
periph3_addr_o = 8'h00;
periph3_wr_o = 4'b0000;
periph3_rd_o = 1'b0;
periph3_data_o = 32'h00000000;
periph4_addr_o = 8'h00;
periph4_wr_o = 4'b0000;
periph4_rd_o = 1'b0;
periph4_data_o = 32'h00000000;
 
periph5_addr_o = 8'h00;
periph5_wr_o = 4'b0000;
periph5_rd_o = 1'b0;
periph5_data_o = 32'h00000000;
 
periph6_addr_o = 8'h00;
periph6_wr_o = 4'b0000;
periph6_rd_o = 1'b0;
periph6_data_o = 32'h00000000;
 
periph7_addr_o = io_addr_i[7:0];
periph7_wr_o = io_wr_i;
periph7_rd_o = io_rd_i;
periph7_data_o = io_data_i;
end
default :
begin
periph0_addr_o = 8'h00;
periph0_wr_o = 4'b0000;
periph0_rd_o = 1'b0;
periph0_data_o = 32'h00000000;
periph1_addr_o = 8'h00;
periph1_wr_o = 4'b0000;
periph1_rd_o = 1'b0;
periph1_data_o = 32'h00000000;
periph2_addr_o = 8'h00;
periph2_wr_o = 4'b0000;
periph2_rd_o = 1'b0;
periph2_data_o = 32'h00000000;
periph3_addr_o = 8'h00;
periph3_wr_o = 4'b0000;
periph3_rd_o = 1'b0;
periph3_data_o = 32'h00000000;
periph4_addr_o = 8'h00;
periph4_wr_o = 4'b0000;
periph4_rd_o = 1'b0;
periph4_data_o = 32'h00000000;
 
periph5_addr_o = 8'h00;
periph5_wr_o = 4'b0000;
periph5_rd_o = 1'b0;
periph5_data_o = 32'h00000000;
 
periph6_addr_o = 8'h00;
periph6_wr_o = 4'b0000;
periph6_rd_o = 1'b0;
periph6_data_o = 32'h00000000;
 
periph7_addr_o = 8'h00;
periph7_wr_o = 4'b0000;
periph7_rd_o = 1'b0;
periph7_data_o = 32'h00000000;
end
endcase
end
//-----------------------------------------------------------------
// Read Port
//-----------------------------------------------------------------
always @ (r_mem_sel or periph0_data_i or periph1_data_i or periph2_data_i or
periph3_data_i or periph4_data_i or periph5_data_i or periph6_data_i or periph7_data_i)
begin
case (r_mem_sel)
// Peripheral 0
4'h0 :
begin
io_data_o = periph0_data_i;
end
// Peripheral 1
4'h1 :
begin
io_data_o = periph1_data_i;
end
// Peripheral 2
4'h2 :
begin
io_data_o = periph2_data_i;
end
// Peripheral 3
4'h3 :
begin
io_data_o = periph3_data_i;
end
// Peripheral 4
4'h4 :
begin
io_data_o = periph4_data_i;
end
// Peripheral 5
4'h5 :
begin
io_data_o = periph5_data_i;
end
// Peripheral 6
4'h6 :
begin
io_data_o = periph6_data_i;
end
// Peripheral 7
4'h7 :
begin
io_data_o = periph7_data_i;
end
default :
begin
io_data_o = 32'h00000000;
end
endcase
end
//-----------------------------------------------------------------
// Registered peripheral select
//-----------------------------------------------------------------
always @ (posedge clk_i or posedge rst_i)
begin
if (rst_i == 1'b1)
r_mem_sel <= 4'h0;
else
r_mem_sel <= io_addr_i[11:8];
end
 
endmodule
/trunk/rtl/soc/alt_soc.v
137,8 → 137,6
//-----------------------------------------------------------------
// Registers
//-----------------------------------------------------------------
wire alt_reset;
 
reg [31:0] v_irq_status;
reg [2:0] r_mem_sel;
wire [31:0] cpu_address;
150,50 → 148,13
 
reg [31:0] io_address;
reg [31:0] io_data_w;
reg [31:0] io_data_r;
wire [31:0] io_data_r;
reg [3:0] io_wr;
reg io_rd;
 
// UART
reg [7:0] uart_tx_data;
wire [7:0] uart_rx_data;
reg uart_wr;
reg uart_rd;
wire uart_tx_busy;
wire uart_rx_avail;
 
// Systick Timer
reg systick_intr;
reg [31:0] systick_count;
reg [31:0] systick_clk_count;
 
// Hi-res system clock tick counter
reg [31:0] hr_timer_cnt;
reg [31:0] hr_timer_match;
 
// IRQ Status
wire intr_in;
reg [31:0] irq_status;
reg [31:0] irq_mask;
 
// Watchdog
`ifdef SOC_CONF_ENABLE_WATCHDOG
reg watchdog_enable;
reg [15:0] watchdog_threshold;
reg watchdog_expired;
reg watchdog_load;
reg [15:0] watchdog_counter;
reg watchdog_alt_reset;
`endif
 
// SPI Flash
`ifdef SOC_CONF_ENABLE_SPI_FLASH
reg spi_flash_start;
wire spi_flash_busy;
reg [7:0] spi_flash_data_wr;
wire [7:0] spi_flash_data_rd;
`endif
 
// Output Signals
wire uart_tx_o;
reg [31:0] int_mem_addr_o;
204,10 → 165,38
reg [31:0] ext_io_data_o;
reg [3:0] ext_io_wr_o;
reg ext_io_rd_o;
reg flash_cs_o;
wire flash_cs_o;
wire flash_si_o;
wire flash_sck_o;
 
// Peripheral Interface
wire [7:0] uart_addr;
wire [31:0] uart_data_o;
wire [31:0] uart_data_i;
wire [3:0] uart_wr;
wire uart_rd;
wire uart_intr;
 
wire [7:0] spi_addr;
wire [31:0] spi_data_o;
wire [31:0] spi_data_i;
wire [3:0] spi_wr;
wire spi_rd;
 
wire [7:0] timer_addr;
wire [31:0] timer_data_o;
wire [31:0] timer_data_i;
wire [3:0] timer_wr;
wire timer_rd;
wire timer_intr_systick;
wire timer_intr_hires;
 
wire [7:0] intr_addr;
wire [31:0] intr_data_o;
wire [31:0] intr_data_i;
wire [3:0] intr_wr;
wire intr_rd;
 
//-----------------------------------------------------------------
// Instantiation
//-----------------------------------------------------------------
217,7 → 206,7
u1_cpu
(
.clk_i(clk_i),
.rst_i(alt_reset),
.rst_i(rst_i),
.en_i(en_i),
.intr_i(intr_in),
.fault_o(fault_o),
231,8 → 220,81
.dbg_pc_o(dbg_pc_o)
);
 
// Peripheral Interconnect
soc_pif
u2_soc
(
// General - Clocking & Reset
.clk_i(clk_i),
.rst_i(rst_i),
 
// I/O bus
.io_addr_i(io_address),
.io_data_i(io_data_w),
.io_data_o(io_data_r),
.io_wr_i(io_wr),
.io_rd_i(io_rd),
// Peripherals
.periph0_addr_o(uart_addr),
.periph0_data_o(uart_data_o),
.periph0_data_i(uart_data_i),
.periph0_wr_o(uart_wr),
.periph0_rd_o(uart_rd),
.periph1_addr_o(timer_addr),
.periph1_data_o(timer_data_o),
.periph1_data_i(timer_data_i),
.periph1_wr_o(timer_wr),
.periph1_rd_o(timer_rd),
.periph2_addr_o(intr_addr),
.periph2_data_o(intr_data_o),
.periph2_data_i(intr_data_i),
.periph2_wr_o(intr_wr),
.periph2_rd_o(intr_rd),
`ifdef SOC_CONF_ENABLE_SPI_FLASH
.periph3_addr_o(spi_addr),
.periph3_data_o(spi_data_o),
.periph3_data_i(spi_data_i),
.periph3_wr_o(spi_wr),
.periph3_rd_o(spi_rd),
`else
.periph3_addr_o(/*open*/),
.periph3_data_o(/*open*/),
.periph3_data_i(32'h00000000),
.periph3_wr_o(/*open*/),
.periph3_rd_o(/*open*/),
`endif
.periph4_addr_o(/*open*/),
.periph4_data_o(/*open*/),
.periph4_data_i(32'h00000000),
.periph4_wr_o(/*open*/),
.periph4_rd_o(/*open*/),
.periph5_addr_o(/*open*/),
.periph5_data_o(/*open*/),
.periph5_data_i(32'h00000000),
.periph5_wr_o(/*open*/),
.periph5_rd_o(/*open*/),
.periph6_addr_o(/*open*/),
.periph6_data_o(/*open*/),
.periph6_data_i(32'h00000000),
.periph6_wr_o(/*open*/),
.periph6_rd_o(/*open*/),
.periph7_addr_o(/*open*/),
.periph7_data_o(/*open*/),
.periph7_data_i(32'h00000000),
.periph7_wr_o(/*open*/),
.periph7_rd_o(/*open*/)
);
 
// UART
uart
uart_periph
#(
.UART_DIVISOR(((CLK_KHZ * 1000) / UART_BAUD))
)
240,22 → 302,21
(
.clk_i(clk_i),
.rst_i(rst_i),
.data_i(uart_tx_data),
.data_o(uart_rx_data),
.intr_o(uart_intr),
.addr_i(uart_addr),
.data_o(uart_data_i),
.data_i(uart_data_o),
.wr_i(uart_wr),
.rd_i(uart_rd),
.tx_busy_o(uart_tx_busy),
.rx_ready_o(uart_rx_avail),
.rxd_i(uart_rx_i),
.txd_o(uart_tx_o)
.rd_i(uart_rd),
.rx_i(uart_rx_i),
.tx_o(uart_tx_o)
);
 
`ifdef SOC_CONF_ENABLE_SPI_FLASH
// SPI Flash Master
spi_master
spim_periph
#(
.CLK_DIV(CLK_KHZ / SPI_FLASH_CLK_KHZ),
.TRANSFER_WIDTH(8)
.CLK_DIV(CLK_KHZ / SPI_FLASH_CLK_KHZ)
)
u4_spi_flash
(
262,16 → 323,16
// Clocking / Reset
.clk_i(clk_i),
.rst_i(rst_i),
// Control & Status
.start_i(spi_flash_start),
.done_o(/*open */),
.busy_o(spi_flash_busy),
// Data
.data_i(spi_flash_data_wr),
.data_o(spi_flash_data_rd),
.intr_o(/*open*/),
// Peripheral I/O
.addr_i(spi_addr),
.data_o(spi_data_i),
.data_i(spi_data_o),
.wr_i(spi_wr),
.rd_i(spi_rd),
// SPI interface
.spi_clk_o(flash_sck_o),
.spi_ss_o(/*open */),
.spi_ss_o(flash_cs_o),
.spi_mosi_o(flash_si_o),
.spi_miso_i(flash_so_i)
);
282,267 → 343,50
assign flash_sck_o = 1'b0;
`endif
 
//-----------------------------------------------------------------
// I/O Handlers
//-----------------------------------------------------------------
always @ (posedge rst_i or posedge clk_i )
begin
if (rst_i == 1'b1)
begin
// UART
uart_tx_data <= 8'h00;
uart_wr <= 1'b0;
// Interrupt Status
irq_status <= 32'h00000000;
irq_mask <= 32'h00000000;
hr_timer_cnt <= 32'h00000000;
hr_timer_match <= 32'h00000000;
// SPI Flash (Configuration PROM)
`ifdef SOC_CONF_ENABLE_SPI_FLASH
flash_cs_o <= 1'b1;
spi_flash_start <= 1'b0;
spi_flash_data_wr<= 8'h00;
`endif
// Watchdog
`ifdef SOC_CONF_ENABLE_WATCHDOG
watchdog_enable <= 1'b0;
watchdog_load <= 1'b0;
watchdog_threshold <= 16'h0000;
`endif
end
else
begin
uart_wr <= 1'b0;
`ifdef SOC_CONF_ENABLE_SPI_FLASH
spi_flash_start <= 1'b0;
`endif
`ifdef SOC_CONF_ENABLE_WATCHDOG
watchdog_load <= 1'b0;
`endif
// Get current IRQ status
v_irq_status = irq_status;
// Clock tick counter
hr_timer_cnt <= (hr_timer_cnt + 1);
// Systick IRQ?
if (systick_intr == 1'b1)
v_irq_status[`IRQ_SYSTICK] = 1'b1;
// UART IRQ?
if (uart_rx_avail == 1'b1)
v_irq_status[`IRQ_UART_RX_AVAIL] = 1'b1;
// Hi-res Timer IRQ [IRQ6]
if ((hr_timer_match != 32'h00000000) && (hr_timer_match == hr_timer_cnt))
v_irq_status[`IRQ_PIT] = 1'b1;
// External interrupts
begin : ext_ints_loop
integer i;
for (i=0; i< EXTERNAL_INTERRUPTS; i=i+1)
begin
if (ext_intr_i[i] == 1'b1)
v_irq_status[(`IRQ_EXT_FIRST + i)] = 1'b1;
end
end
// Update IRQ status
irq_status <= v_irq_status;
// IO Write Cycle
if (io_wr != 4'b0000)
case (io_address[7:0])
`UART_UDR :
begin
uart_tx_data <= io_data_w[7:0];
uart_wr <= 1'b1;
end
`IRQ_MASK_SET :
irq_mask <= (irq_mask | io_data_w);
`IRQ_MASK_CLR :
irq_mask <= (irq_mask & ~ (io_data_w));
`IRQ_STATUS : // (IRQ Acknowledge)
irq_status <= (v_irq_status & ~ (io_data_w));
`ifdef SOC_CONF_ENABLE_WATCHDOG
`WATCHDOG_CTRL :
begin
// Enable watchdog if non-zero
if (io_data_w[15:0] != 16'h0000)
watchdog_enable <= 1'b1;
else
watchdog_enable <= 1'b0;
timer_periph
#(
.CLK_KHZ(CLK_KHZ)
)
u5_timer
(
.clk_i(clk_i),
.rst_i(rst_i),
.intr_systick_o(timer_intr_systick),
.intr_hires_o(timer_intr_hires),
.addr_i(timer_addr),
.data_o(timer_data_i),
.data_i(timer_data_o),
.wr_i(timer_wr),
.rd_i(timer_rd)
);
 
// Store threshold for timeout (16-bit x 1ms)
watchdog_threshold <= io_data_w[15:0];
watchdog_load <= 1'b1;
end
`endif
`SYS_CLK_COUNT :
hr_timer_match <= io_data_w;
`ifdef SOC_CONF_ENABLE_SPI_FLASH
`SPI_PROM_CTRL :
begin
flash_cs_o <= io_data_w[0];
end
`SPI_PROM_DATA :
begin
spi_flash_data_wr <= io_data_w[7:0];
spi_flash_start <= 1'b1;
end
`endif
default :
;
endcase
end
end
// IO memory space READ handler
always @ (posedge rst_i or posedge clk_i )
begin
if (rst_i == 1'b1)
begin
io_data_r <= 32'h00000000;
uart_rd <= 1'b0;
end
else
begin
uart_rd <= 1'b0;
// Read cycle?
if (io_rd == 1'b1)
case (io_address[7:0])
`CORE_ID :
io_data_r <= CORE_ID;
`UART_USR :
io_data_r <= {27'h0000000, 1'b0, uart_tx_busy, 1'b0, 1'b0, uart_rx_avail};
`UART_UDR :
begin
io_data_r <= {24'h000000,uart_rx_data};
uart_rd <= 1'b1;
end
`TIMER_VAL : // (32-bit 1ms counter)
io_data_r <= systick_count;
`IRQ_MASK_SET :
io_data_r <= irq_mask;
`IRQ_MASK_CLR :
io_data_r <= irq_mask;
`IRQ_STATUS :
io_data_r <= (irq_status & irq_mask);
`ifdef SOC_CONF_ENABLE_WATCHDOG
`WATCHDOG_CTRL :
io_data_r <= {15'h000000, watchdog_expired, watchdog_counter};
`endif
`SYS_CLK_COUNT :
io_data_r <= hr_timer_cnt;
`ifdef SOC_CONF_ENABLE_SPI_FLASH
`SPI_PROM_STAT :
io_data_r <= {31'h00000000, spi_flash_busy};
`SPI_PROM_DATA :
io_data_r <= {24'h000000, spi_flash_data_rd};
`endif
default :
io_data_r <= 32'h00000000;
endcase
end
end
// SysTick Timer (1 ms resolution)
always @ (posedge rst_i or posedge clk_i )
begin
if (rst_i == 1'b1)
begin
systick_count <= 32'h00000000;
systick_clk_count <= 32'h00000000;
systick_intr <= 1'b0;
end
else
begin
systick_intr <= 1'b0;
if (systick_clk_count == CLK_KHZ)
begin
systick_count <= (systick_count + 1);
systick_intr <= 1'b1;
systick_clk_count <= 32'h00000000;
end
else
systick_clk_count <= (systick_clk_count + 1);
end
end
intr_periph
#(
.EXTERNAL_INTERRUPTS(EXTERNAL_INTERRUPTS)
)
u6_intr
(
.clk_i(clk_i),
.rst_i(rst_i),
.intr_o(intr_in),
.intr0_i(uart_intr),
.intr1_i(timer_intr_systick),
.intr2_i(timer_intr_hires),
.intr3_i(/*open*/),
.intr4_i(/*open*/),
.intr5_i(/*open*/),
.intr6_i(/*open*/),
.intr7_i(/*open*/),
.intr_ext_i(ext_intr_i),
.addr_i(intr_addr),
.data_o(intr_data_i),
.data_i(intr_data_o),
.wr_i(intr_wr),
.rd_i(intr_rd)
);
 
// Watchdog
`ifdef SOC_CONF_ENABLE_WATCHDOG
always @ (posedge rst_i or posedge clk_i )
begin
if (rst_i == 1'b1)
begin
watchdog_counter <= 16'h0000;
watchdog_expired <= 1'b0;
watchdog_alt_reset <= 1'b0;
end
else
begin
 
// On 1ms tick - decrement watchdog if enabled
if (systick_intr == 1'b1)
if (watchdog_enable == 1'b1)
begin
// Count down or expire if 0
if (watchdog_counter != 16'h0000)
watchdog_counter <= (watchdog_counter - 1);
else
begin
// Clear reset if already high
watchdog_alt_reset <= 1'b0;
// If not already expired, start reset sequence
if (watchdog_expired != 1'b1)
begin
watchdog_expired <= 1'b1;
watchdog_alt_reset <= 1'b1;
// Hold reset high for a couple of ms
watchdog_counter <= 16'h002;
end
end
end
 
// If watchdog reset signalled, reset counter with new threshold value
if (watchdog_load == 1'b1)
begin
watchdog_counter <= watchdog_threshold;
watchdog_expired <= 1'b0;
end
end
end
`endif
 
//-----------------------------------------------------------------
// Memory Map
//-----------------------------------------------------------------
668,9 → 512,9
//-----------------------------------------------------------------
reg [31:0] v_mem_sel;
always @ (posedge clk_i or posedge alt_reset )
always @ (posedge clk_i or posedge rst_i )
begin
if (alt_reset == 1'b1)
if (rst_i == 1'b1)
begin
v_mem_sel = BOOT_VECTOR;
r_mem_sel <= v_mem_sel[30:28];
680,20 → 524,10
end
//-----------------------------------------------------------------
// Combinatorial Logic
//-----------------------------------------------------------------
assign intr_in = ((irq_mask & irq_status) != 32'h00000000) ? 1'b1 : 1'b0;
`ifdef SOC_CONF_ENABLE_WATCHDOG
assign alt_reset = (rst_i | watchdog_alt_reset);
`else
assign alt_reset = rst_i;
`endif
 
//-----------------------------------------------------------------
// External Interface
//-----------------------------------------------------------------
// Debug UART
assign dbg_uart_data_o = uart_tx_data;
assign dbg_uart_wr_o = uart_wr;
assign dbg_uart_data_o = uart_data_o[7:0];
assign dbg_uart_wr_o = (uart_wr != 4'b0000) ? 1'b1 : 1'b0;
 
endmodule
/trunk/rtl/soc/alt_soc_defs.v
47,33 → 47,22
`define MEM_REGION_CORE_IO 3'b010
`define MEM_REGION_EXT_IO 3'b011
 
`define INT_BASE 32'h00000000
`define EXT_BASE 32'h10000000
`define IO_BASE 32'h20000000
`define EXT_IO_BASE 32'h30000000
 
//-----------------------------------------------------------------
// I/O
// Peripheral Base Addresses
//-----------------------------------------------------------------
`define UART_BASE 32'h20000000
`define TIMER_BASE 32'h20000100
`define INTR_BASE 32'h20000200
`define SPI_FLASH_BASE 32'h20000300
 
// General
`define CORE_ID 8'h00
 
// Basic Peripherals
`define UART_USR 8'h04
`define UART_UDR 8'h08
`define TIMER_VAL 8'h10
`define IRQ_MASK_SET 8'h14
`define IRQ_MASK_STATUS 8'h14
`define IRQ_MASK_CLR 8'h18
`define IRQ_STATUS 8'h1C
`define IRQ_SYSTICK (0)
`define IRQ_UART_RX_AVAIL (1)
`define IRQ_SW (2)
`define IRQ_PIT (6)
`define IRQ_EXT_FIRST (8)
`define WATCHDOG_CTRL 8'h20
`define WATCHDOG_EXPIRED (16)
`define SYS_CLK_COUNT 8'h60
 
// SPI Configuration PROM
`define SPI_PROM_CTRL 8'h70
`define SPI_PROM_STAT 8'h70
`define SPI_PROM_DATA 8'h74
//-----------------------------------------------------------------
// Interrupts
//-----------------------------------------------------------------
`define IRQ_UART_RX 0
`define IRQ_TIMER_SYSTICK 1
`define IRQ_TIMER_HIRES 2
/trunk/rtl/soc/alt_soc_conf.v
42,5 → 42,4
//-----------------------------------------------------------------
// Configuration
//-----------------------------------------------------------------
//`define SOC_CONF_ENABLE_WATCHDOG
`define SOC_CONF_ENABLE_SPI_FLASH
/trunk/rtl/peripheral/uart_defs.v
0,0 → 1,49
//-----------------------------------------------------------------
// AltOR32
// Alternative Lightweight OpenRisc
// V0.1
// Ultra-Embedded.com
// Copyright 2011 - 2012
//
// Email: admin@ultra-embedded.com
//
// License: LGPL
//
// If you would like a version with a different license for use
// in commercial projects please contact the above email address
// for more details.
//-----------------------------------------------------------------
//
// Copyright (C) 2011 - 2012 Ultra-Embedded.com
//
// This source file may be used and distributed without
// restriction provided that this copyright statement is not
// removed from the file and that any derivative work contains
// the original copyright notice and the associated disclaimer.
//
// This source file is free software; you can redistribute it
// and/or modify it under the terms of the GNU Lesser General
// Public License as published by the Free Software Foundation;
// either version 2.1 of the License, or (at your option) any
// later version.
//
// This source is distributed in the hope that it will be
// useful, but WITHOUT ANY WARRANTY; without even the implied
// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR
// PURPOSE. See the GNU Lesser General Public License for more
// details.
//
// You should have received a copy of the GNU Lesser General
// Public License along with this source; if not, write to the
// Free Software Foundation, Inc., 59 Temple Place, Suite 330,
// Boston, MA 02111-1307 USA
//-----------------------------------------------------------------
 
 
//-----------------------------------------------------------------
// Registers
//-----------------------------------------------------------------
 
// Basic Peripherals
`define UART_USR 8'h04
`define UART_UDR 8'h08
/trunk/rtl/peripheral/intr_defs.v
0,0 → 1,50
//-----------------------------------------------------------------
// AltOR32
// Alternative Lightweight OpenRisc
// V0.1
// Ultra-Embedded.com
// Copyright 2011 - 2012
//
// Email: admin@ultra-embedded.com
//
// License: LGPL
//
// If you would like a version with a different license for use
// in commercial projects please contact the above email address
// for more details.
//-----------------------------------------------------------------
//
// Copyright (C) 2011 - 2012 Ultra-Embedded.com
//
// This source file may be used and distributed without
// restriction provided that this copyright statement is not
// removed from the file and that any derivative work contains
// the original copyright notice and the associated disclaimer.
//
// This source file is free software; you can redistribute it
// and/or modify it under the terms of the GNU Lesser General
// Public License as published by the Free Software Foundation;
// either version 2.1 of the License, or (at your option) any
// later version.
//
// This source is distributed in the hope that it will be
// useful, but WITHOUT ANY WARRANTY; without even the implied
// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR
// PURPOSE. See the GNU Lesser General Public License for more
// details.
//
// You should have received a copy of the GNU Lesser General
// Public License along with this source; if not, write to the
// Free Software Foundation, Inc., 59 Temple Place, Suite 330,
// Boston, MA 02111-1307 USA
//-----------------------------------------------------------------
 
 
//-----------------------------------------------------------------
// Registers
//-----------------------------------------------------------------
`define IRQ_MASK_SET 8'h00
`define IRQ_MASK_STATUS 8'h04
`define IRQ_MASK_CLR 8'h08
`define IRQ_STATUS 8'h0C
`define IRQ_EXT_FIRST (8)
/trunk/rtl/peripheral/spim_periph.v
0,0 → 1,203
//-----------------------------------------------------------------
// AltOR32
// Alternative Lightweight OpenRisc
// V0.1
// Ultra-Embedded.com
// Copyright 2011 - 2012
//
// Email: admin@ultra-embedded.com
//
// License: LGPL
//
// If you would like a version with a different license for use
// in commercial projects please contact the above email address
// for more details.
//-----------------------------------------------------------------
//
// Copyright (C) 2011 - 2012 Ultra-Embedded.com
//
// This source file may be used and distributed without
// restriction provided that this copyright statement is not
// removed from the file and that any derivative work contains
// the original copyright notice and the associated disclaimer.
//
// This source file is free software; you can redistribute it
// and/or modify it under the terms of the GNU Lesser General
// Public License as published by the Free Software Foundation;
// either version 2.1 of the License, or (at your option) any
// later version.
//
// This source is distributed in the hope that it will be
// useful, but WITHOUT ANY WARRANTY; without even the implied
// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR
// PURPOSE. See the GNU Lesser General Public License for more
// details.
//
// You should have received a copy of the GNU Lesser General
// Public License along with this source; if not, write to the
// Free Software Foundation, Inc., 59 Temple Place, Suite 330,
// Boston, MA 02111-1307 USA
//-----------------------------------------------------------------
 
//-----------------------------------------------------------------
// Includes
//-----------------------------------------------------------------
`include "spim_defs.v"
 
//-----------------------------------------------------------------
// Module:
//-----------------------------------------------------------------
module spim_periph
(
// General - Clocking & Reset
clk_i,
rst_i,
intr_o,
// SPI Bus
spi_clk_o,
spi_ss_o,
spi_mosi_o,
spi_miso_i,
// Peripheral bus
addr_i,
data_o,
data_i,
wr_i,
rd_i
);
 
//-----------------------------------------------------------------
// Params
//-----------------------------------------------------------------
parameter [31:0] CLK_DIV = 32;
//-----------------------------------------------------------------
// I/O
//-----------------------------------------------------------------
input clk_i /*verilator public*/;
input rst_i /*verilator public*/;
output intr_o /*verilator public*/;
 
output spi_clk_o /*verilator public*/;
output spi_ss_o /*verilator public*/;
output spi_mosi_o /*verilator public*/;
input spi_miso_i /*verilator public*/;
 
input [7:0] addr_i /*verilator public*/;
output [31:0] data_o /*verilator public*/;
input [31:0] data_i /*verilator public*/;
input [3:0] wr_i /*verilator public*/;
input rd_i /*verilator public*/;
 
 
//-----------------------------------------------------------------
// Registers / Wires
//-----------------------------------------------------------------
reg [31:0] data_o;
reg spi_ss_o;
reg spi_start;
wire spi_busy;
reg [7:0] spi_data_wr;
wire [7:0] spi_data_rd;
 
//-----------------------------------------------------------------
// Instantiation
//-----------------------------------------------------------------
 
// SPI Master
spi_master
#(
.CLK_DIV(CLK_DIV),
.TRANSFER_WIDTH(8)
)
u1_spi_master
(
// Clocking / Reset
.clk_i(clk_i),
.rst_i(rst_i),
// Control & Status
.start_i(spi_start),
.done_o(intr_o),
.busy_o(spi_busy),
// Data
.data_i(spi_data_wr),
.data_o(spi_data_rd),
// SPI interface
.spi_clk_o(spi_clk_o),
.spi_ss_o(/*open */),
.spi_mosi_o(spi_mosi_o),
.spi_miso_i(spi_miso_i)
);
 
//-----------------------------------------------------------------
// Peripheral Register Write
//-----------------------------------------------------------------
always @ (posedge rst_i or posedge clk_i )
begin
if (rst_i == 1'b1)
begin
spi_ss_o <= 1'b1;
spi_start <= 1'b0;
spi_data_wr <= 8'h00;
end
else
begin
spi_start <= 1'b0;
// Write Cycle
if (wr_i != 4'b0000)
begin
case (addr_i)
`SPI_MASTER_CTRL :
begin
spi_ss_o <= data_i[0];
end
`SPI_MASTER_DATA :
begin
spi_data_wr <= data_i[7:0];
spi_start <= 1'b1;
end
default :
;
endcase
end
end
end
 
//-----------------------------------------------------------------
// Peripheral Register Read
//-----------------------------------------------------------------
always @ (posedge rst_i or posedge clk_i )
begin
if (rst_i == 1'b1)
begin
data_o <= 32'h00000000;
end
else
begin
// Read cycle?
if (rd_i == 1'b1)
begin
case (addr_i[7:0])
`SPI_MASTER_STAT :
data_o <= {31'h00000000, spi_busy};
`SPI_MASTER_DATA :
data_o <= {24'h000000, spi_data_rd};
default :
data_o <= 32'h00000000;
endcase
end
end
end
 
endmodule
/trunk/rtl/peripheral/timer_defs.v
0,0 → 1,47
//-----------------------------------------------------------------
// AltOR32
// Alternative Lightweight OpenRisc
// V0.1
// Ultra-Embedded.com
// Copyright 2011 - 2012
//
// Email: admin@ultra-embedded.com
//
// License: LGPL
//
// If you would like a version with a different license for use
// in commercial projects please contact the above email address
// for more details.
//-----------------------------------------------------------------
//
// Copyright (C) 2011 - 2012 Ultra-Embedded.com
//
// This source file may be used and distributed without
// restriction provided that this copyright statement is not
// removed from the file and that any derivative work contains
// the original copyright notice and the associated disclaimer.
//
// This source file is free software; you can redistribute it
// and/or modify it under the terms of the GNU Lesser General
// Public License as published by the Free Software Foundation;
// either version 2.1 of the License, or (at your option) any
// later version.
//
// This source is distributed in the hope that it will be
// useful, but WITHOUT ANY WARRANTY; without even the implied
// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR
// PURPOSE. See the GNU Lesser General Public License for more
// details.
//
// You should have received a copy of the GNU Lesser General
// Public License along with this source; if not, write to the
// Free Software Foundation, Inc., 59 Temple Place, Suite 330,
// Boston, MA 02111-1307 USA
//-----------------------------------------------------------------
 
 
//-----------------------------------------------------------------
// Registers
//-----------------------------------------------------------------
`define TIMER_SYSTICK_VAL 8'h00
`define TIMER_HIRES 8'h04
/trunk/rtl/peripheral/uart_periph.v
0,0 → 1,199
//-----------------------------------------------------------------
// AltOR32
// Alternative Lightweight OpenRisc
// V0.1
// Ultra-Embedded.com
// Copyright 2011 - 2012
//
// Email: admin@ultra-embedded.com
//
// License: LGPL
//
// If you would like a version with a different license for use
// in commercial projects please contact the above email address
// for more details.
//-----------------------------------------------------------------
//
// Copyright (C) 2011 - 2012 Ultra-Embedded.com
//
// This source file may be used and distributed without
// restriction provided that this copyright statement is not
// removed from the file and that any derivative work contains
// the original copyright notice and the associated disclaimer.
//
// This source file is free software; you can redistribute it
// and/or modify it under the terms of the GNU Lesser General
// Public License as published by the Free Software Foundation;
// either version 2.1 of the License, or (at your option) any
// later version.
//
// This source is distributed in the hope that it will be
// useful, but WITHOUT ANY WARRANTY; without even the implied
// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR
// PURPOSE. See the GNU Lesser General Public License for more
// details.
//
// You should have received a copy of the GNU Lesser General
// Public License along with this source; if not, write to the
// Free Software Foundation, Inc., 59 Temple Place, Suite 330,
// Boston, MA 02111-1307 USA
//-----------------------------------------------------------------
 
//-----------------------------------------------------------------
// Includes
//-----------------------------------------------------------------
`include "uart_defs.v"
 
//-----------------------------------------------------------------
// Module:
//-----------------------------------------------------------------
module uart_periph
(
// General - Clocking & Reset
clk_i,
rst_i,
intr_o,
// UART
tx_o,
rx_i,
// Peripheral bus
addr_i,
data_o,
data_i,
wr_i,
rd_i
);
 
//-----------------------------------------------------------------
// Params
//-----------------------------------------------------------------
parameter [31:0] UART_DIVISOR = 1;
//-----------------------------------------------------------------
// I/O
//-----------------------------------------------------------------
input clk_i /*verilator public*/;
input rst_i /*verilator public*/;
output intr_o /*verilator public*/;
 
output tx_o /*verilator public*/;
input rx_i /*verilator public*/;
 
input [7:0] addr_i /*verilator public*/;
output [31:0] data_o /*verilator public*/;
input [31:0] data_i /*verilator public*/;
input [3:0] wr_i /*verilator public*/;
input rd_i /*verilator public*/;
 
//-----------------------------------------------------------------
// Registers / Wires
//-----------------------------------------------------------------
reg [31:0] data_o;
 
// UART
reg [7:0] uart_tx_data;
wire [7:0] uart_rx_data;
reg uart_wr;
reg uart_rd;
wire uart_tx_busy;
wire uart_rx_avail;
 
//-----------------------------------------------------------------
// Instantiation
//-----------------------------------------------------------------
 
// UART
uart
#(
.UART_DIVISOR(UART_DIVISOR)
)
u1_uart
(
.clk_i(clk_i),
.rst_i(rst_i),
.data_i(uart_tx_data),
.data_o(uart_rx_data),
.wr_i(uart_wr),
.rd_i(uart_rd),
.tx_busy_o(uart_tx_busy),
.rx_ready_o(uart_rx_avail),
.rxd_i(rx_i),
.txd_o(tx_o)
);
 
//-----------------------------------------------------------------
// Peripheral Register Write
//-----------------------------------------------------------------
always @ (posedge rst_i or posedge clk_i )
begin
if (rst_i == 1'b1)
begin
uart_tx_data <= 8'h00;
uart_wr <= 1'b0;
end
else
begin
uart_wr <= 1'b0;
// Write Cycle
if (wr_i != 4'b0000)
begin
case (addr_i)
`UART_UDR :
begin
uart_tx_data <= data_i[7:0];
uart_wr <= 1'b1;
end
default :
;
endcase
end
end
end
 
//-----------------------------------------------------------------
// Peripheral Register Read
//-----------------------------------------------------------------
always @ (posedge rst_i or posedge clk_i )
begin
if (rst_i == 1'b1)
begin
data_o <= 32'h00000000;
uart_rd <= 1'b0;
end
else
begin
uart_rd <= 1'b0;
// Read cycle?
if (rd_i == 1'b1)
begin
case (addr_i[7:0])
`UART_USR :
data_o <= {27'h0000000, 1'b0, uart_tx_busy, 1'b0, 1'b0, uart_rx_avail};
`UART_UDR :
begin
data_o <= {24'h000000,uart_rx_data};
uart_rd <= 1'b1;
end
default :
data_o <= 32'h00000000;
endcase
end
end
end
//-----------------------------------------------------------------
// Combinatorial Logic
//-----------------------------------------------------------------
assign intr_o = uart_rx_avail;
 
endmodule
/trunk/rtl/peripheral/intr_periph.v
0,0 → 1,233
//-----------------------------------------------------------------
// AltOR32
// Alternative Lightweight OpenRisc
// V0.1
// Ultra-Embedded.com
// Copyright 2011 - 2012
//
// Email: admin@ultra-embedded.com
//
// License: LGPL
//
// If you would like a version with a different license for use
// in commercial projects please contact the above email address
// for more details.
//-----------------------------------------------------------------
//
// Copyright (C) 2011 - 2012 Ultra-Embedded.com
//
// This source file may be used and distributed without
// restriction provided that this copyright statement is not
// removed from the file and that any derivative work contains
// the original copyright notice and the associated disclaimer.
//
// This source file is free software; you can redistribute it
// and/or modify it under the terms of the GNU Lesser General
// Public License as published by the Free Software Foundation;
// either version 2.1 of the License, or (at your option) any
// later version.
//
// This source is distributed in the hope that it will be
// useful, but WITHOUT ANY WARRANTY; without even the implied
// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR
// PURPOSE. See the GNU Lesser General Public License for more
// details.
//
// You should have received a copy of the GNU Lesser General
// Public License along with this source; if not, write to the
// Free Software Foundation, Inc., 59 Temple Place, Suite 330,
// Boston, MA 02111-1307 USA
//-----------------------------------------------------------------
 
//-----------------------------------------------------------------
// Includes
//-----------------------------------------------------------------
`include "intr_defs.v"
 
//-----------------------------------------------------------------
// Module:
//-----------------------------------------------------------------
module intr_periph
(
// General - Clocking & Reset
clk_i,
rst_i,
intr_o,
// Interrupts
intr0_i,
intr1_i,
intr2_i,
intr3_i,
intr4_i,
intr5_i,
intr6_i,
intr7_i,
intr_ext_i,
// Peripheral bus
addr_i,
data_o,
data_i,
wr_i,
rd_i
);
 
//-----------------------------------------------------------------
// Params
//-----------------------------------------------------------------
parameter [31:0] EXTERNAL_INTERRUPTS = 1;
//-----------------------------------------------------------------
// I/O
//-----------------------------------------------------------------
input clk_i /*verilator public*/;
input rst_i /*verilator public*/;
output intr_o /*verilator public*/;
 
input intr0_i /*verilator public*/;
input intr1_i /*verilator public*/;
input intr2_i /*verilator public*/;
input intr3_i /*verilator public*/;
input intr4_i /*verilator public*/;
input intr5_i /*verilator public*/;
input intr6_i /*verilator public*/;
input intr7_i /*verilator public*/;
input [(EXTERNAL_INTERRUPTS - 1):0] intr_ext_i /*verilator public*/;
input [7:0] addr_i /*verilator public*/;
output [31:0] data_o /*verilator public*/;
input [31:0] data_i /*verilator public*/;
input [3:0] wr_i /*verilator public*/;
input rd_i /*verilator public*/;
 
//-----------------------------------------------------------------
// Registers / Wires
//-----------------------------------------------------------------
reg [31:0] data_o;
 
// IRQ Status
wire intr_in;
reg [31:0] irq_status;
reg [31:0] irq_mask;
reg [31:0] v_irq_status;
 
//-----------------------------------------------------------------
// Peripheral Register Write
//-----------------------------------------------------------------
always @ (posedge rst_i or posedge clk_i )
begin
if (rst_i == 1'b1)
begin
irq_status <= 32'h00000000;
irq_mask <= 32'h00000000;
end
else
begin
// Get current IRQ status
v_irq_status = irq_status;
// IRQ0
if (intr0_i == 1'b1)
v_irq_status[0] = 1'b1;
// IRQ1
if (intr1_i == 1'b1)
v_irq_status[1] = 1'b1;
// IRQ2
if (intr2_i == 1'b1)
v_irq_status[2] = 1'b1;
// IRQ3
if (intr3_i == 1'b1)
v_irq_status[3] = 1'b1;
// IRQ4
if (intr4_i == 1'b1)
v_irq_status[4] = 1'b1;
// IRQ5
if (intr5_i == 1'b1)
v_irq_status[5] = 1'b1;
// IRQ6
if (intr6_i == 1'b1)
v_irq_status[6] = 1'b1;
// IRQ7
if (intr7_i == 1'b1)
v_irq_status[7] = 1'b1;
// External interrupts
begin : ext_ints_loop
integer i;
for (i=0; i< EXTERNAL_INTERRUPTS; i=i+1)
begin
if (intr_ext_i[i] == 1'b1)
v_irq_status[(`IRQ_EXT_FIRST + i)] = 1'b1;
end
end
// Update IRQ status
irq_status <= v_irq_status;
// Write Cycle
if (wr_i != 4'b0000)
begin
case (addr_i)
`IRQ_MASK_SET :
irq_mask <= (irq_mask | data_i);
`IRQ_MASK_CLR :
irq_mask <= (irq_mask & ~ (data_i));
`IRQ_STATUS : // (IRQ Acknowledge)
irq_status <= (v_irq_status & ~ (data_i));
default :
;
endcase
end
end
end
 
//-----------------------------------------------------------------
// Peripheral Register Read
//-----------------------------------------------------------------
always @ (posedge rst_i or posedge clk_i )
begin
if (rst_i == 1'b1)
begin
data_o <= 32'h00000000;
end
else
begin
// Read cycle?
if (rd_i == 1'b1)
begin
case (addr_i[7:0])
`IRQ_MASK_SET :
data_o <= irq_mask;
`IRQ_MASK_CLR :
data_o <= irq_mask;
`IRQ_STATUS :
data_o <= (irq_status & irq_mask);
default :
data_o <= 32'h00000000;
endcase
end
end
end
//-----------------------------------------------------------------
// Combinatorial Logic
//-----------------------------------------------------------------
assign intr_o = ((irq_mask & irq_status) != 32'h00000000) ? 1'b1 : 1'b0;
 
endmodule
/trunk/rtl/peripheral/timer_periph.v
0,0 → 1,207
//-----------------------------------------------------------------
// AltOR32
// Alternative Lightweight OpenRisc
// V0.1
// Ultra-Embedded.com
// Copyright 2011 - 2012
//
// Email: admin@ultra-embedded.com
//
// License: LGPL
//
// If you would like a version with a different license for use
// in commercial projects please contact the above email address
// for more details.
//-----------------------------------------------------------------
//
// Copyright (C) 2011 - 2012 Ultra-Embedded.com
//
// This source file may be used and distributed without
// restriction provided that this copyright statement is not
// removed from the file and that any derivative work contains
// the original copyright notice and the associated disclaimer.
//
// This source file is free software; you can redistribute it
// and/or modify it under the terms of the GNU Lesser General
// Public License as published by the Free Software Foundation;
// either version 2.1 of the License, or (at your option) any
// later version.
//
// This source is distributed in the hope that it will be
// useful, but WITHOUT ANY WARRANTY; without even the implied
// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR
// PURPOSE. See the GNU Lesser General Public License for more
// details.
//
// You should have received a copy of the GNU Lesser General
// Public License along with this source; if not, write to the
// Free Software Foundation, Inc., 59 Temple Place, Suite 330,
// Boston, MA 02111-1307 USA
//-----------------------------------------------------------------
 
//-----------------------------------------------------------------
// Includes
//-----------------------------------------------------------------
`include "timer_defs.v"
 
//-----------------------------------------------------------------
// Module:
//-----------------------------------------------------------------
module timer_periph
(
// General - Clocking & Reset
clk_i,
rst_i,
// Interrupts
intr_systick_o,
intr_hires_o,
// Peripheral bus
addr_i,
data_o,
data_i,
wr_i,
rd_i
);
 
//-----------------------------------------------------------------
// Params
//-----------------------------------------------------------------
parameter [31:0] CLK_KHZ = 12288;
//-----------------------------------------------------------------
// I/O
//-----------------------------------------------------------------
input clk_i /*verilator public*/;
input rst_i /*verilator public*/;
 
output intr_systick_o /*verilator public*/;
output intr_hires_o /*verilator public*/;
 
input [7:0] addr_i /*verilator public*/;
output [31:0] data_o /*verilator public*/;
input [31:0] data_i /*verilator public*/;
input [3:0] wr_i /*verilator public*/;
input rd_i /*verilator public*/;
 
//-----------------------------------------------------------------
// Registers / Wires
//-----------------------------------------------------------------
 
reg [31:0] data_o;
 
// Systick Timer
reg systick_intr;
reg [31:0] systick_count;
reg [31:0] systick_clk_count;
 
// Hi-res system clock tick counter
reg hr_timer_intr;
reg [31:0] hr_timer_cnt;
reg [31:0] hr_timer_match;
 
//-----------------------------------------------------------------
// Implementation
//-----------------------------------------------------------------
 
// SysTick Timer (1 ms resolution)
always @ (posedge rst_i or posedge clk_i )
begin
if (rst_i == 1'b1)
begin
systick_count <= 32'h00000000;
systick_clk_count <= 32'h00000000;
systick_intr <= 1'b0;
end
else
begin
systick_intr <= 1'b0;
if (systick_clk_count == CLK_KHZ)
begin
systick_count <= (systick_count + 1);
systick_intr <= 1'b1;
systick_clk_count <= 32'h00000000;
end
else
systick_clk_count <= (systick_clk_count + 1);
end
end
 
//-----------------------------------------------------------------
// Peripheral Register Write
//-----------------------------------------------------------------
always @ (posedge rst_i or posedge clk_i )
begin
if (rst_i == 1'b1)
begin
hr_timer_cnt <= 32'h00000000;
hr_timer_match <= 32'h00000000;
hr_timer_intr <= 1'b0;
end
else
begin
hr_timer_intr <= 1'b0;
// Clock tick counter
hr_timer_cnt <= (hr_timer_cnt + 1);
// Hi-res Timer IRQ
if ((hr_timer_match != 32'h00000000) && (hr_timer_match == hr_timer_cnt))
hr_timer_intr <= 1'b1;
// Write Cycle
if (wr_i != 4'b0000)
begin
case (addr_i)
`TIMER_HIRES :
hr_timer_match <= data_i;
default :
;
endcase
end
end
end
 
//-----------------------------------------------------------------
// Peripheral Register Read
//-----------------------------------------------------------------
always @ (posedge rst_i or posedge clk_i )
begin
if (rst_i == 1'b1)
begin
data_o <= 32'h00000000;
end
else
begin
// Read cycle?
if (rd_i == 1'b1)
begin
case (addr_i[7:0])
// 32-bit systick/1ms counter
`TIMER_SYSTICK_VAL :
data_o <= systick_count;
// Hi res timer (clock rate)
`TIMER_HIRES :
data_o <= hr_timer_cnt;
default :
data_o <= 32'h00000000;
endcase
end
end
end
//-----------------------------------------------------------------
// Combinatorial Logic
//-----------------------------------------------------------------
assign intr_systick_o = systick_intr;
assign intr_hires_o = hr_timer_intr;
 
endmodule
/trunk/rtl/peripheral/spim_defs.v
0,0 → 1,48
//-----------------------------------------------------------------
// AltOR32
// Alternative Lightweight OpenRisc
// V0.1
// Ultra-Embedded.com
// Copyright 2011 - 2012
//
// Email: admin@ultra-embedded.com
//
// License: LGPL
//
// If you would like a version with a different license for use
// in commercial projects please contact the above email address
// for more details.
//-----------------------------------------------------------------
//
// Copyright (C) 2011 - 2012 Ultra-Embedded.com
//
// This source file may be used and distributed without
// restriction provided that this copyright statement is not
// removed from the file and that any derivative work contains
// the original copyright notice and the associated disclaimer.
//
// This source file is free software; you can redistribute it
// and/or modify it under the terms of the GNU Lesser General
// Public License as published by the Free Software Foundation;
// either version 2.1 of the License, or (at your option) any
// later version.
//
// This source is distributed in the hope that it will be
// useful, but WITHOUT ANY WARRANTY; without even the implied
// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR
// PURPOSE. See the GNU Lesser General Public License for more
// details.
//
// You should have received a copy of the GNU Lesser General
// Public License along with this source; if not, write to the
// Free Software Foundation, Inc., 59 Temple Place, Suite 330,
// Boston, MA 02111-1307 USA
//-----------------------------------------------------------------
 
 
//-----------------------------------------------------------------
// Registers
//-----------------------------------------------------------------
`define SPI_MASTER_CTRL 8'h00
`define SPI_MASTER_STAT 8'h00
`define SPI_MASTER_DATA 8'h04
/trunk/sw/bootloader/mem_map.h
17,37 → 17,44
#define REG32 (volatile unsigned int*)
 
//-----------------------------------------------------------------
// I/O:
// Peripheral Base Addresses
//-----------------------------------------------------------------
#define UART_BASE 0x20000000
#define TIMER_BASE 0x20000100
#define INTR_BASE 0x20000200
#define SPI_FLASH_BASE 0x20000300
 
// General
#define CORE_ID (*(REG32 (IO_BASE + 0x0)))
//-----------------------------------------------------------------
// Interrupts
//-----------------------------------------------------------------
#define IRQ_UART_RX 0
#define IRQ_TIMER_SYSTICK 1
#define IRQ_TIMER_HIRES 2
 
// Basic Peripherals
#define UART_USR (*(REG32 (IO_BASE + 0x4)))
#define UART_UDR (*(REG32 (IO_BASE + 0x8)))
#define TIMER_VAL (*(REG32 (IO_BASE + 0x10)))
#define IRQ_MASK_SET (*(REG32 (IO_BASE + 0x14)))
#define IRQ_MASK_STATUS (*(REG32 (IO_BASE + 0x14)))
#define IRQ_MASK_CLR (*(REG32 (IO_BASE + 0x18)))
#define IRQ_STATUS (*(REG32 (IO_BASE + 0x1C)))
#define IRQ_SYSTICK (0)
#define IRQ_UART_RX_AVAIL (1)
#define IRQ_SW (2)
#define IRQ_PIT (6)
#define EXT_INT_OFFSET (8)
//-----------------------------------------------------------------
// Peripheral Registers
//-----------------------------------------------------------------
 
// [Optional] Watchdog
#define WATCHDOG_CTRL (*(REG32 (IO_BASE + 0x20)))
#define WATCHDOG_EXPIRED (16)
#define UART_USR (*(REG32 (UART_BASE + 0x4)))
#define UART_UDR (*(REG32 (UART_BASE + 0x8)))
 
#define SYS_CLK_COUNT (*(REG32 (IO_BASE + 0x60)))
#define TIMER_VAL (*(REG32 (TIMER_BASE + 0x0)))
#define SYS_CLK_COUNT (*(REG32 (TIMER_BASE + 0x4)))
 
// SPI Configuration PROM
#define SPI_PROM_CTRL (*(REG32 (IO_BASE + 0x70)))
#define IRQ_MASK_SET (*(REG32 (INTR_BASE + 0x00)))
#define IRQ_MASK_STATUS (*(REG32 (INTR_BASE + 0x04)))
#define IRQ_MASK_CLR (*(REG32 (INTR_BASE + 0x08)))
#define IRQ_STATUS (*(REG32 (INTR_BASE + 0x0C)))
#define IRQ_SYSTICK (IRQ_TIMER_SYSTICK)
#define IRQ_UART_RX_AVAIL (IRQ_UART_RX)
#define IRQ_PIT (IRQ_TIMER_HIRES)
#define IRQ_SW (3)
#define EXT_INT_OFFSET (8)
 
#define SPI_PROM_CTRL (*(REG32 (SPI_FLASH_BASE + 0x00)))
#define SPI_PROM_CS (1 << 0)
#define SPI_PROM_STAT (*(REG32 (IO_BASE + 0x70)))
#define SPI_PROM_STAT (*(REG32 (SPI_FLASH_BASE + 0x00)))
#define SPI_PROM_BUSY (1 << 0)
#define SPI_PROM_DATA (*(REG32 (IO_BASE + 0x74)))
#define SPI_PROM_DATA (*(REG32 (SPI_FLASH_BASE + 0x04)))
 
#endif
/trunk/fpga/papilio_xc3s250e/top.vhd
50,7 → 50,7
(
OSC_MHZ : integer := 32;
-- Target CPU MHz (must be a multiple of 2)
CPU_MHZ : integer := 58
CPU_MHZ : integer := 32
);
port
(
154,21 → 154,8
-----------------------------------------------
-- Instantiation
-----------------------------------------------
cpu_clk <= clk;
 
-- DCM Clock Generator
U1_DCM: ClockDCM
generic map
(
CLK_IN_MHZ => OSC_MHZ,
CLK_OUT_MHZ => CPU_MHZ
)
port map
(
CLKIN_IN => clk,
CLKFX_OUT => cpu_clk,
CLKIN_IBUFG_OUT => open
);
 
-- 24KB Block RAM (0x0000 - 0x6000)
U2_RAM: ram
generic map
/trunk/fpga/papilio_xc3s250e/fpga_papilio_xc3s250e.bit Cannot display: file marked as a binary type. svn:mime-type = application/octet-stream
/trunk/fpga/papilio_xc3s250e/program.vhd
159,7 → 159,7
INIT_12 => X"9ca810bce0e0a8189d9d13bc848644868584859c9d0ce4a88418aa04a89caa9c",
INIT_13 => X"84150fbd15488586a99ca8d7d71918d7d78644868584859d9ce213e484e104a8",
INIT_14 => X"9c85d7d7d7d7d7d7d7d7d7aad71ad7d444a818d4a81886448584859c150fbce0",
INIT_15 => X"48e1d49fd4199c9e9f13bc84a818874487878786868686858485a99c9e0cbcab",
INIT_15 => X"48a9d49f9fd4199e9c13bc84a818874487878786868686858485a99c9e0cbcab",
INIT_16 => X"d8d49fa8841810bc10bc108503150cbdbbbb9f150fbce084bc0cbd15488586a8",
INIT_17 => X"181910bc8410e4a48cac8c84bb13e59fbb9f07150fbce084180cbd154885869e",
INIT_18 => X"13e4a818a413bc9caca413bde0b8180cbc9ce0009c9db88ca5e1a9b98c8d9ca8",
190,7 → 190,7
INIT_31 => X"0a740a9c44859d1507d49c9c44859c9d0015001513e49d9ce10ce4b89cb810e4",
INIT_32 => X"414f0a74206f2072452e6f652d4d286e6e29464f3e0a414f3e0a72453c61743e",
INIT_33 => X"6e222000530a502061766720200a2928526f74002e6c652d4128522e73206f20",
INIT_34 => X"0000000000000000000000000000004465636e6e6b20736361696e6f2e496920",
INIT_34 => X"0000000000000000000000000000000000002075666d6f552672686673496920",
INIT_35 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_36 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_37 => X"0000000000000000000000000000000000000000000000000000000000000000",
248,7 → 248,7
INIT_12 => X"409000a2456e4240c060ff05b2410001c1412121600022635260440062a00321",
INIT_13 => X"6e00ff8b0000620ece2142e1e1c040e1e1410001c14121602110ff45b2ce00a2",
INIT_14 => X"2174e1e1e1e1e1e1e1e1e194e180e10300636005a5a00100c141212100ff4363",
INIT_15 => X"00ce014001c060c000ff03624240c100814101c1814101c141217621c0000bc3",
INIT_15 => X"00ce01400001c0c060ff03624240c100814101c1814101c141217621c0000bc3",
INIT_16 => X"04018584a180001a000b0074ff00005818181800ff44848e0b008b0000620e7a",
INIT_17 => X"a000000481002484668486c118ffb2401818ff00ff44848ec0008b0000620e40",
INIT_18 => X"ff28c6c084ff25a58787ff66e4c4c00025a58400a008c6c86b6b086ba56580a5",
279,7 → 279,7
INIT_31 => X"0052422100216700ff0121210021e56000000000ff8929e6630024a5806b0023",
INIT_32 => X"704d002e6264586e782e6f6d6d294261740a504d2000704d20006e78456c6520",
INIT_33 => X"6f552672450052696261656961002e414f6d20422e616d6d29464f0a68666458",
INIT_34 => X"00000000000000000000000000000022727475206e222000735f2f6d2e446364",
INIT_34 => X"00000000000000000000000000000000000049726161776e26652e6c70446364",
INIT_35 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_36 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_37 => X"0000000000000000000000000000000000000000000000000000000000000000",
318,7 → 318,7
generic map (
INIT_00 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_01 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_02 => X"0000000000000000000000000000000000000000000100ff28001d001a001c00",
INIT_02 => X"0000000000000000000000000000000000000000000100ff28001c001a001c00",
INIT_03 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_04 => X"0000000000000000000000000000000000000000000000000000000000000008",
INIT_05 => X"0000000000000000000000000000000000000000000000000000000000000000",
328,7 → 328,7
INIT_09 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0C => X"0000190200190200190200180200000280020000ff1887174f00209777000008",
INIT_0C => X"0000190200190200190200180200000280020100ff1887174f00209777000008",
INIT_0D => X"00001901000000ff0000001902000000ff000000000000000002000000002780",
INIT_0E => X"000020001901000000582100002019010000000058011000001019010000ff00",
INIT_0F => X"0000303000001a0000000000ff00771a4f00170000000000582100ff19010000",
335,9 → 335,9
INIT_10 => X"184f1a770017ff48ff0010ff1800000003001a0000ff48ffff0010002038ff10",
INIT_11 => X"1a774f9787000017ff48ffff0000ff0020000700001a000e0e000020ff1a0000",
INIT_12 => X"10000010701080000000ff0000ff48ffffffff000000181000b00002800000ff",
INIT_13 => X"0000ff000058000000ff1a874f20007717ff48ffffffff000010ff7000100200",
INIT_13 => X"0000ff000058000001ff1a874f20007717ff48ffffffff000010ff7000100200",
INIT_14 => X"ff00e7d7c7978777174ff71ab700a720481a00181a00ff48ffffff0000ff0380",
INIT_15 => X"58c01800b020000000ff00001a00ff48ffffffffffffffffffff0000ff000000",
INIT_15 => X"5801180000b0200000ff00001a00ff48ffffffffffffffffffff0000ff000000",
INIT_16 => X"5820001a0000000000000000ff0000000000ff00ff0380000000000058000000",
INIT_17 => X"00000000000018000000000000ffe00000ffff00ff0380000000000058000000",
INIT_18 => X"ff301a00ffff00ff10ffff002000000000ff300000000000ff281a000000001a",
348,27 → 348,27
INIT_1D => X"000000004f170048000020004800000000000000ff2000ff00ffff48ff0000ff",
INIT_1E => X"001045431041381036341000ffa7978777324f3017ff48ff0000ff000000ffff",
INIT_1F => X"00180080ff0000180000000000ff000058020000005800020000000000001000",
INIT_20 => X"18000020004800ff203000000020004800ff18ff48ffffffffff0000ff80ffff",
INIT_21 => X"0000002000000020ff000000280000000020ff000000280000000020ff000000",
INIT_22 => X"ff30000000ff000000600000000020ff00000030ff10000000001720004800ff",
INIT_23 => X"00000020ff0000002800000020ff00000020ff10000000001720ff4800180000",
INIT_24 => X"00280000002000fd001a1a190000000000000000ff00ffffff174fff48001800",
INIT_25 => X"00ffff48ff00100000ff00000018000020ff000000280020182800ff00000028",
INIT_20 => X"18030320004800ff203000000120004800ff18ff48ffffffffff0000ff80ffff",
INIT_21 => X"0000002003000320ff000000280003030020ff000000280003030020ff000000",
INIT_22 => X"ff30000000ff000000600003030020ff00000030ff10000300031720004800ff",
INIT_23 => X"00000320ff0000002803000320ff00000020ff10000300031720ff4800180000",
INIT_24 => X"00280303002000fd001a1a190000000000000000ff00ffffff174fff48001800",
INIT_25 => X"00ffff48ff00100000ff00000018030320ff000000280320182800ff00000028",
INIT_26 => X"fd1a1919000020ff1a000000000000ff000000ff20ff1a000000000000ff0000",
INIT_27 => X"00000000ff28ff004f000000000087772000971700ff00fd1a1919000000ff00",
INIT_28 => X"0000001720ff48ffffffff00180000002040ff10000038ff0000006000000000",
INIT_27 => X"03000000ff28ff004f000000030087772000971700ff00fd1a1919000000ff00",
INIT_28 => X"0003031720ff48ffffffff00180003002040ff10000038ff0000006000000000",
INIT_29 => X"774f17ff48ffff0000ff000000ff7000fe28700000ff00000018ff000020774f",
INIT_2A => X"01c00001c000c00000000000002000000028000020180ffff7e7d7c7b7a79787",
INIT_2A => X"01c00001c000c00000030003002000000028000020180ffff7e7d7c7b7a79787",
INIT_2B => X"00ff0000003000300000000000fe700000d000ff000000282000000000001a00",
INIT_2C => X"ff00ff48ffffffffffffffffffff000000ffc0000100ff000000fed000ff8000",
INIT_2D => X"000000fed000ff000000e0002000fe30280000ff00000018f028000000700000",
INIT_2E => X"00ff00000028ff1000004f0000172000ff00ff00ff00ffc0000170ff800000ff",
INIT_2F => X"002800005800000048ffff48ff0000ff000000fe1800ff000000280000201828",
INIT_2D => X"000000fed000ff000000e0032000fe30280000ff00000018f028000000700000",
INIT_2E => X"00ff00000028ff1000034f0003172000ff00ff00ff00ffc0000170ff800000ff",
INIT_2F => X"002800005800000048ffff48ff0000ff000000fe1800ff000000280300201828",
INIT_30 => X"0000784018000078008000006800000000ff40183000000048ff800000400028",
INIT_31 => X"3c4f6f0048000000ff48ff004800000000000000ff6800002000880000000020",
INIT_32 => X"7020502e6f652d61740a74206f20526c65004720503c7020503c61743e0a7249",
INIT_33 => X"776e266552414f6e6c69206d704e2e704d20666f2e73206f20504d002e6c652d",
INIT_34 => X"000000000000000000000000000000002075666d6f5526726866736d2f226565",
INIT_34 => X"0000000000000000000000000000000000004465636e6e6b2073636169226565",
INIT_35 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_36 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_37 => X"0000000000000000000000000000000000000000000000000000000000000000",
407,7 → 407,7
generic map (
INIT_00 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_01 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_02 => X"0000000000000000000000000000000000000000003804fe000000005000f000",
INIT_02 => X"0000000000000000000000000000000000000000003804fe0000f0004000e000",
INIT_03 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_04 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_05 => X"0000000000000000000000000000000000000000000000000000000000000000",
417,47 → 417,47
INIT_09 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0C => X"00002a1e001a21000c2400fe270000f5002c1000ecf4f4ecfc0500f8f0000000",
INIT_0C => X"00002a1e001a21000c2400fe270000f5002c0000ecf4f4ecfc0500f8f0000000",
INIT_0D => X"5b0076fe010000e70064009307010000f0460d41184526490004003601040f02",
INIT_0E => X"0700005cb1e000000000000047003bea000000000000000053005cf60000de00",
INIT_0F => X"010000000009580000001600f400f854fc00f40000000000000000afcad80100",
INIT_10 => X"00fc50f800f4f800f40000fc000c00002e00580000f800f4fc0c00000000fb00",
INIT_11 => X"5cf0fcf8f40500ecf800f4fc0c00fb000063b400005861a840000000f4540000",
INIT_0F => X"010000000009480000001600f400f844fc00f40000000000000000afcad80100",
INIT_10 => X"00fc40f800f4f800f40000fc000c00002e00480000f800f4fc0c00000000fb00",
INIT_11 => X"4cf0fcf8f40500ecf800f4fc0c00fb000063b400004861a840000000f4440000",
INIT_12 => X"00000300020000050001f7000cf800f4f0ecfc14000900ad080700a8001000ec",
INIT_13 => X"0000fb000000000010f070f8fc0000f4f0f800f4f0ecfc011400f3000c008b00",
INIT_14 => X"c800f4f0ece0dcd8d4fcf86ce800e400007000006c00f800f4f0fc1000f7e702",
INIT_15 => X"000408430400010010ee00007000f800f4f0ece8e4e0dcd8d4fc0038ff100000",
INIT_16 => X"0000827404007a435b187400ec00a3009818ff00f7e70200040f000000000000",
INIT_13 => X"0000fb000000000000f060f8fc0000f4f0f800f4f0ecfc011400f3000c008b00",
INIT_14 => X"c800f4f0ece0dcd8d4fcf85ce800e400006000005c00f800f4f0fc1000f7e702",
INIT_15 => X"000008431004000001ee00006000f800f4f0ece8e4e0dcd8d4fc0038ff100000",
INIT_16 => X"0000826404007a435b187400ec00a3009818ff00f7e70200040f000000000000",
INIT_17 => X"00005f00042900ff01ff020098de001518ff8200f7e702000044000000000000",
INIT_18 => X"e900f700fff800ff21fff9000010000d00ff050608010800ff00770884830074",
INIT_19 => X"18f70000000043a1e7020000080000c500b30000740100a998491815ff084b00",
INIT_1A => X"0077040000878300000474010038540000000600000026385e060000ff2d4399",
INIT_1B => X"26180000180000180000fffb065e00ffff08140008b9008300fffa00f7010000",
INIT_1C => X"000800000408000400f8110a98fc18f80000083300ff06011008000077800038",
INIT_18 => X"e900e700fff800ff21fff9000010000d00ff050608010800ff00670884830064",
INIT_19 => X"18f70000000043a1e7020000080000c500b30000640100a998491815ff084b00",
INIT_1A => X"0067040000878300000464010038540000000600000026385e060000ff2d4399",
INIT_1B => X"26180000180000180000fffb065e00ffff08140008b9008300fffa00e7010000",
INIT_1C => X"000800000408000400f8110a98fc18f80000083300ff06011008000067800038",
INIT_1D => X"08000000fcf80100000400000000080300010004ff0000f00deaf800fc0800fd",
INIT_1E => X"002c46442842392437352000b4f8f4f0ec33fc31e8f800fc0800fc000001cff8",
INIT_1F => X"00000800ff0001002d00060000f5000100080a0000000a4d000020000000302d",
INIT_20 => X"00707400000000fd000200001000000001d602f800f4f0ece8fc4c00fc00ff90",
INIT_21 => X"0001000070ff7400fd00010000ff70744800fd00010000ff70745000fd000100",
INIT_22 => X"f700010000fd00010000007074ff00fd00010000fc009f740070fc00000000fd",
INIT_23 => X"01007400fd0001000070ff7400fd00010000fc0005740070fc00fc00040001ff",
INIT_24 => X"0600747000000053f20c22ea0000003cbf301f00b901bbf8dff8fcfc000400ff",
INIT_25 => X"0186f800fc08000100fd00010000707400fd000100007400000001fd00010000",
INIT_26 => X"0c0cf1ea000000c2fc01000010005fffff25017800d0fc02000015005fffff44",
INIT_27 => X"741100002100ec03fc0000007000f4f00000f8ec00eced030cf1ea000000e7e6",
INIT_28 => X"007074f400f800f4f0ecfc14000070010000f700010000fd000100000000ff00",
INIT_20 => X"00000400000000fd000200000000000001d602f800f4f0ece8fc4c00fc00ff90",
INIT_21 => X"0001000000ff0400fd00010000ff00044800fd00010000ff00045000fd000100",
INIT_22 => X"f700010000fd00010000000004ff00fd00010000fc009f040000fc00000000fd",
INIT_23 => X"01000400fd0001000000ff0400fd00010000fc0005040000fc00fc00040001ff",
INIT_24 => X"0600040000000053f30c18ea0000003cbf301f00b901bbf8dff8fcfc000400ff",
INIT_25 => X"0186f800fc08000100fd00010000000400fd000100000400000001fd00010000",
INIT_26 => X"0c0cf1ea000000c2ec01000010005fffff25017800d0ec02000015005fffff44",
INIT_27 => X"041100002100ec03fc0000000000f4f00000f8ec00ecee030cf1ea000000e7e7",
INIT_28 => X"000004f400f800f4f0ecfc14000000010000f700010000fd000100000000ff00",
INIT_29 => X"d8fcd4f800f4fc0c00fc000100340000ed00002001fd00010000f4060000f8fc",
INIT_2A => X"00000300000402080070007401003f00000080000804ffc8f8f4f0ece8e4e0dc",
INIT_2B => X"00fd00010000000000000f0000aa0000020000fd000100000006003a0100fc00",
INIT_2A => X"00000300000402080000000401003f00000080000804ffc8f8f4f0ece8e4e0dc",
INIT_2B => X"00fd00010000000000000f0000aa0000020000fd000100000006003a0100ec00",
INIT_2C => X"ec00f800f4f0ece8e4e0dcd8d4fc003808cb00000000fc000100e10000f60001",
INIT_2D => X"000100aa0000fd000100007400006b00000201fd000100000000000600000000",
INIT_2E => X"01fd00010000f8000674fc0070f8000081004e38c6089000000000df000100fc",
INIT_2F => X"320000360000000000fcf800fc0800fc0001007a0001fd000100007460000000",
INIT_2D => X"000100aa0000fd000100000400006b00000201fd000100000000000600000000",
INIT_2E => X"01fd00010000f8000604fc0000f8000081004e38c6089000000000df000100fc",
INIT_2F => X"320000360000000000fcf800fc0800fc0001007a0001fd000100000460000000",
INIT_30 => X"005f0302045f01030000001e0000014101f90004005f000103ff00200d002e00",
INIT_31 => X"494d6f0400000000bf00fc040000000103000500ed0001000403000101010300",
INIT_32 => X"2928522e6f6d6d6c65002e6264584120724941285246292852416c6520006e6e",
INIT_33 => X"6e6b207354534d20656c6161706f2e702050726f0a686664584720502e616d6d",
INIT_34 => X"0000000000000000000000000000000049726161776e26652e6c706f63002076",
INIT_34 => X"00000000000000000000000000000000000022727475206e222000735f002076",
INIT_35 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_36 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_37 => X"0000000000000000000000000000000000000000000000000000000000000000",
/trunk/fpga/papilio_xc3s250e/sw/mem_map.h
17,38 → 17,45
#define REG32 (volatile unsigned int*)
 
//-----------------------------------------------------------------
// I/O:
// Peripheral Base Addresses
//-----------------------------------------------------------------
#define UART_BASE 0x20000000
#define TIMER_BASE 0x20000100
#define INTR_BASE 0x20000200
#define SPI_FLASH_BASE 0x20000300
 
// General
#define CORE_ID (*(REG32 (IO_BASE + 0x0)))
//-----------------------------------------------------------------
// Interrupts
//-----------------------------------------------------------------
#define IRQ_UART_RX 0
#define IRQ_TIMER_SYSTICK 1
#define IRQ_TIMER_HIRES 2
 
// Basic Peripherals
#define UART_USR (*(REG32 (IO_BASE + 0x4)))
#define UART_UDR (*(REG32 (IO_BASE + 0x8)))
#define TIMER_VAL (*(REG32 (IO_BASE + 0x10)))
#define IRQ_MASK_SET (*(REG32 (IO_BASE + 0x14)))
#define IRQ_MASK_STATUS (*(REG32 (IO_BASE + 0x14)))
#define IRQ_MASK_CLR (*(REG32 (IO_BASE + 0x18)))
#define IRQ_STATUS (*(REG32 (IO_BASE + 0x1C)))
#define IRQ_SYSTICK (0)
#define IRQ_UART_RX_AVAIL (1)
#define IRQ_SW (2)
#define IRQ_PIT (6)
#define EXT_INT_OFFSET (8)
//-----------------------------------------------------------------
// Peripheral Registers
//-----------------------------------------------------------------
 
// [Optional] Watchdog
#define WATCHDOG_CTRL (*(REG32 (IO_BASE + 0x20)))
#define WATCHDOG_EXPIRED (16)
#define UART_USR (*(REG32 (UART_BASE + 0x4)))
#define UART_UDR (*(REG32 (UART_BASE + 0x8)))
 
#define SYS_CLK_COUNT (*(REG32 (IO_BASE + 0x60)))
#define TIMER_VAL (*(REG32 (TIMER_BASE + 0x0)))
#define SYS_CLK_COUNT (*(REG32 (TIMER_BASE + 0x4)))
 
// [Optional] SPI Configuration PROM
#define SPI_PROM_CTRL (*(REG32 (IO_BASE + 0x70)))
#define IRQ_MASK_SET (*(REG32 (INTR_BASE + 0x00)))
#define IRQ_MASK_STATUS (*(REG32 (INTR_BASE + 0x04)))
#define IRQ_MASK_CLR (*(REG32 (INTR_BASE + 0x08)))
#define IRQ_STATUS (*(REG32 (INTR_BASE + 0x0C)))
#define IRQ_SYSTICK (IRQ_TIMER_SYSTICK)
#define IRQ_UART_RX_AVAIL (IRQ_UART_RX)
#define IRQ_PIT (IRQ_TIMER_HIRES)
#define IRQ_SW (3)
#define EXT_INT_OFFSET (8)
 
#define SPI_PROM_CTRL (*(REG32 (SPI_FLASH_BASE + 0x00)))
#define SPI_PROM_CS (1 << 0)
#define SPI_PROM_STAT (*(REG32 (IO_BASE + 0x70)))
#define SPI_PROM_STAT (*(REG32 (SPI_FLASH_BASE + 0x00)))
#define SPI_PROM_BUSY (1 << 0)
#define SPI_PROM_DATA (*(REG32 (IO_BASE + 0x74)))
#define SPI_PROM_DATA (*(REG32 (SPI_FLASH_BASE + 0x04)))
 
//-----------------------------------------------------------------
// Extended Peripherals
/trunk/fpga/papilio_xc3s250e/project.xise
17,11 → 17,11
<files>
<file xil_pn:name="ClockDCM.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="1"/>
<association xil_pn:name="Implementation" xil_pn:seqID="9"/>
<association xil_pn:name="Implementation" xil_pn:seqID="0"/>
</file>
<file xil_pn:name="components.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="2"/>
<association xil_pn:name="Implementation" xil_pn:seqID="8"/>
<association xil_pn:name="Implementation" xil_pn:seqID="13"/>
</file>
<file xil_pn:name="fpga.ucf" xil_pn:type="FILE_UCF">
<association xil_pn:name="Implementation" xil_pn:seqID="0"/>
28,36 → 28,56
</file>
<file xil_pn:name="program.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="4"/>
<association xil_pn:name="Implementation" xil_pn:seqID="7"/>
<association xil_pn:name="Implementation" xil_pn:seqID="12"/>
</file>
<file xil_pn:name="top.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="5"/>
<association xil_pn:name="Implementation" xil_pn:seqID="10"/>
<association xil_pn:name="Implementation" xil_pn:seqID="14"/>
</file>
<file xil_pn:name="../../rtl/peripheral/spi_master.v" xil_pn:type="FILE_VERILOG">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="14"/>
<association xil_pn:name="Implementation" xil_pn:seqID="4"/>
<association xil_pn:name="Implementation" xil_pn:seqID="2"/>
</file>
<file xil_pn:name="../../rtl/peripheral/uart.v" xil_pn:type="FILE_VERILOG">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="15"/>
<association xil_pn:name="Implementation" xil_pn:seqID="3"/>
<association xil_pn:name="Implementation" xil_pn:seqID="1"/>
</file>
<file xil_pn:name="../../rtl/soc/alt_soc.v" xil_pn:type="FILE_VERILOG">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="233"/>
<association xil_pn:name="Implementation" xil_pn:seqID="6"/>
<association xil_pn:name="Implementation" xil_pn:seqID="11"/>
</file>
<file xil_pn:name="../../rtl/core_simple/altor32.v" xil_pn:type="FILE_VERILOG">
<file xil_pn:name="../../rtl/core_pipelined/altor32.v" xil_pn:type="FILE_VERILOG">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="21"/>
<association xil_pn:name="Implementation" xil_pn:seqID="5"/>
<association xil_pn:name="Implementation" xil_pn:seqID="10"/>
</file>
<file xil_pn:name="../../rtl/core_simple/altor32_alu.v" xil_pn:type="FILE_VERILOG">
<file xil_pn:name="../../rtl/core_pipelined/altor32_alu.v" xil_pn:type="FILE_VERILOG">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="22"/>
<association xil_pn:name="Implementation" xil_pn:seqID="2"/>
<association xil_pn:name="Implementation" xil_pn:seqID="4"/>
</file>
<file xil_pn:name="../../rtl/core_simple/altor32_regfile_xil.v" xil_pn:type="FILE_VERILOG">
<file xil_pn:name="../../rtl/core_pipelined/altor32_regfile_xil.v" xil_pn:type="FILE_VERILOG">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="23"/>
<association xil_pn:name="Implementation" xil_pn:seqID="1"/>
<association xil_pn:name="Implementation" xil_pn:seqID="3"/>
</file>
<file xil_pn:name="../../rtl/peripheral/intr_periph.v" xil_pn:type="FILE_VERILOG">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="68"/>
<association xil_pn:name="Implementation" xil_pn:seqID="9"/>
</file>
<file xil_pn:name="../../rtl/peripheral/spim_periph.v" xil_pn:type="FILE_VERILOG">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="70"/>
<association xil_pn:name="Implementation" xil_pn:seqID="8"/>
</file>
<file xil_pn:name="../../rtl/peripheral/timer_periph.v" xil_pn:type="FILE_VERILOG">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="72"/>
<association xil_pn:name="Implementation" xil_pn:seqID="7"/>
</file>
<file xil_pn:name="../../rtl/peripheral/uart_periph.v" xil_pn:type="FILE_VERILOG">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="74"/>
<association xil_pn:name="Implementation" xil_pn:seqID="6"/>
</file>
<file xil_pn:name="../../rtl/soc/soc_pif.v" xil_pn:type="FILE_VERILOG">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="75"/>
<association xil_pn:name="Implementation" xil_pn:seqID="5"/>
</file>
</files>
 
<properties>
364,10 → 384,14
<!-- Do not hand-edit this section, as it will be overwritten when the -->
<!-- project is analyzed based on files automatically identified as -->
<!-- include files. -->
<file xil_pn:name="../../rtl/core_simple/altor32_defs.v" xil_pn:type="FILE_VERILOG"/>
<file xil_pn:name="../../rtl/core_simple/altor32_funcs.v" xil_pn:type="FILE_VERILOG"/>
<file xil_pn:name="../../rtl/core_pipelined/altor32_defs.v" xil_pn:type="FILE_VERILOG"/>
<file xil_pn:name="../../rtl/core_pipelined/altor32_funcs.v" xil_pn:type="FILE_VERILOG"/>
<file xil_pn:name="../../rtl/soc/alt_soc_defs.v" xil_pn:type="FILE_VERILOG"/>
<file xil_pn:name="../../rtl/soc/alt_soc_conf.v" xil_pn:type="FILE_VERILOG"/>
<file xil_pn:name="../../rtl/peripheral/intr_defs.v" xil_pn:type="FILE_VERILOG"/>
<file xil_pn:name="../../rtl/peripheral/spim_defs.v" xil_pn:type="FILE_VERILOG"/>
<file xil_pn:name="../../rtl/peripheral/timer_defs.v" xil_pn:type="FILE_VERILOG"/>
<file xil_pn:name="../../rtl/peripheral/uart_defs.v" xil_pn:type="FILE_VERILOG"/>
</autoManagedFiles>
 
</project>

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