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    /amber
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Rev 63 → Rev 64

/trunk/sw/tools
trunk/sw/tools Property changes : Modified: svn:ignore ## -2,4 +2,5 ## amber-mem-ascii amber-func-jumps amber-bin2mem +amber-pkt2mem amber-ascii-mem Index: trunk/sw/boot-loader-ethmac =================================================================== --- trunk/sw/boot-loader-ethmac (revision 63) +++ trunk/sw/boot-loader-ethmac (revision 64)
trunk/sw/boot-loader-ethmac Property changes : Added: svn:ignore ## -0,0 +1,6 ## +boot-loader-ethmac_memparams32.v +boot-loader-ethmac.map +boot-loader-ethmac.mem +boot-loader-ethmac.dis +boot-loader-ethmac_memparams128.v +boot-loader-ethmac.elf Index: trunk/sw/boot-loader/fpga-version.h =================================================================== --- trunk/sw/boot-loader/fpga-version.h (revision 63) +++ trunk/sw/boot-loader/fpga-version.h (revision 64) @@ -1 +1 @@ -#define AMBER_FPGA_VERSION "20091124203711" +#define AMBER_FPGA_VERSION "20130428143120" Index: trunk/hw/isim =================================================================== --- trunk/hw/isim (revision 63) +++ trunk/hw/isim (revision 64)
trunk/hw/isim Property changes : Added: svn:ignore ## -0,0 +1,8 ## +*.log +isim +fuse.xmsgs +pkt_to_amber_ack.txt +amber-test.exe +amber.dis +fuseRelaunch.cmd +*.wdb Index: trunk/hw/vlog/system/system.v =================================================================== --- trunk/hw/vlog/system/system.v (revision 63) +++ trunk/hw/vlog/system/system.v (revision 64) @@ -47,10 +47,6 @@ input brd_clk_n, input brd_clk_p, -`ifdef XILINX_VIRTEX6_FPGA -input sys_clk_p, -input sys_clk_n, -`endif // UART 0 Interface input i_uart0_rts, @@ -73,12 +69,10 @@ inout [1:0] ddr3_dqs_n, output ddr3_ck_p, output ddr3_ck_n, -`ifdef XILINX_VIRTEX6_FPGA -output ddr3_cs_n, -`endif + `ifdef XILINX_SPARTAN6_FPGA inout mcb3_rzq, -inout mcb3_zio, +//inout mcb3_zio, `endif @@ -126,24 +120,6 @@ wire test_mem_ctrl; wire system_rdy; -// ====================================== -// Xilinx Virtex-6 DDR3 Controller connections -// ====================================== -`ifdef XILINX_VIRTEX6_FPGA -wire phy_init_done1; -wire xv6_cmd_en; -wire [2:0] xv6_cmd_instr; -wire [26:0] xv6_cmd_byte_addr; -wire xv6_cmd_full; -wire xv6_wr_full; -wire xv6_wr_en; -wire xv6_wr_end; -wire [7:0] xv6_wr_mask; -wire [63:0] xv6_wr_data; -wire [63:0] xv6_rd_data; -wire xv6_rd_data_valid; -wire xv6_ddr3_clk; -`endif // ====================================== // Ethmac MII @@ -592,7 +568,7 @@ // ------------------------------------------------------------- // Instantiate Xilinx Spartan-6 FPGA MCB-DDR3 Controller // ------------------------------------------------------------- - mcb_ddr3 u_mcb_ddr3 ( + ddr3 u_ddr3 ( // DDR3 signals .mcb3_dram_dq ( ddr3_dq ), @@ -607,7 +583,7 @@ .mcb3_dram_udm ( ddr3_dm[1] ), .mcb3_dram_dm ( ddr3_dm[0] ), .mcb3_rzq ( mcb3_rzq ), - .mcb3_zio ( mcb3_zio ), +// .mcb3_zio ( mcb3_zio ), .mcb3_dram_udqs ( ddr3_dqs_p[1] ), .mcb3_dram_dqs ( ddr3_dqs_p[0] ), .mcb3_dram_udqs_n ( ddr3_dqs_n[1] ), @@ -615,9 +591,10 @@ .mcb3_dram_ck ( ddr3_ck_p ), .mcb3_dram_ck_n ( ddr3_ck_n ), - .sys_clk_ibufg ( clk_200 ), - .c3_sys_rst_n ( brd_rst ), - + .c3_sys_clk ( clk_200 ), + .c3_sys_rst_i ( brd_rst ), // active-high + .c3_clk0 ( ), + .c3_rst0 ( ), .c3_calib_done ( phy_init_done ), .c3_p0_cmd_clk ( sys_clk ), @@ -653,106 +630,7 @@ `endif -`ifdef XILINX_VIRTEX6_FPGA - // ------------------------------------------------------------- - // Instantiate Wishbone to Xilinx Spartan-6 DDR3 Bridge - // ------------------------------------------------------------- - // The clock crossing fifo for virtex-6 is insode the bridge - // module - wb_xv6_ddr3_bridge #( - .WB_DWIDTH ( WB_DWIDTH ), - .WB_SWIDTH ( WB_SWIDTH ) - ) - u_wb_xv6_ddr3_bridge ( - .i_sys_clk ( sys_clk ), - .i_ddr_clk ( xv6_ddr3_clk ), - .o_ddr_cmd_en ( xv6_cmd_en ), - .o_ddr_cmd_instr ( xv6_cmd_instr ), - .o_ddr_cmd_byte_addr ( xv6_cmd_byte_addr ), - .i_ddr_cmd_full ( xv6_cmd_full ), - - .i_ddr_wr_full ( xv6_wr_full ), - .o_ddr_wr_en ( xv6_wr_en ), - .o_ddr_wr_end ( xv6_wr_end ), - .o_ddr_wr_mask ( xv6_wr_mask ), - .o_ddr_wr_data ( xv6_wr_data ), - - .i_ddr_rd_data ( xv6_rd_data ), - .i_ddr_rd_valid ( xv6_rd_data_valid ), - - .i_phy_init_done ( phy_init_done1 ), - .o_phy_init_done ( phy_init_done ), // delayed version - - .i_mem_ctrl ( test_mem_ctrl ), - .i_wb_adr ( s_wb_adr [2] ), - .i_wb_sel ( s_wb_sel [2] ), - .i_wb_we ( s_wb_we [2] ), - .o_wb_dat ( s_wb_dat_r[2] ), - .i_wb_dat ( s_wb_dat_w[2] ), - .i_wb_cyc ( s_wb_cyc [2] ), - .i_wb_stb ( s_wb_stb [2] ), - .o_wb_ack ( s_wb_ack [2] ), - .o_wb_err ( s_wb_err [2] ) - ); - - - // ------------------------------------------------------------- - // Instantiate Xilinx Virtex-6 FPGA DDR3 Controller - // ------------------------------------------------------------- - xv6_ddr3 - #( // - Skip the memory initilization sequence, - .SIM_INIT_OPTION ("SKIP_PU_DLY" ), - // - Skip the delay Calibration process - .SIM_CAL_OPTION ("FAST_CAL" ), - .RST_ACT_LOW ( 0 ) - ) - u_xv6_ddr3 ( - // DDR3 signals - .ddr3_dq ( ddr3_dq ), - .ddr3_addr ( ddr3_addr ), - .ddr3_ba ( ddr3_ba ), - .ddr3_ras_n ( ddr3_ras_n ), - .ddr3_cas_n ( ddr3_cas_n ), - .ddr3_we_n ( ddr3_we_n ), - .ddr3_odt ( ddr3_odt ), - .ddr3_reset_n ( ddr3_reset_n ), - .ddr3_cke ( ddr3_cke ), - .ddr3_dm ( ddr3_dm ), - .ddr3_dqs_p ( ddr3_dqs_p ), - .ddr3_dqs_n ( ddr3_dqs_n ), - .ddr3_ck_p ( ddr3_ck_p ), - .ddr3_ck_n ( ddr3_ck_n ), - .ddr3_cs_n ( ddr3_cs_n ), - - // DDR clock - .sys_clk_p ( sys_clk_p ), - .sys_clk_n ( sys_clk_n ), - .clk_ref ( clk_200 ), - .sys_rst ( brd_rst ), - .tb_rst ( ), - .tb_clk ( xv6_ddr3_clk ), - .phy_init_done ( phy_init_done1 ), - - .app_en ( xv6_cmd_en ), - .app_cmd ( xv6_cmd_instr ), - .tg_addr ( xv6_cmd_byte_addr ), - .app_full ( xv6_cmd_full ), - - .app_wdf_wren ( xv6_wr_en ), - .app_wdf_mask ( xv6_wr_mask ), - .app_wdf_data ( xv6_wr_data ), - .app_wdf_end ( xv6_wr_end ), - .app_wdf_full ( xv6_wr_full ), - - .app_rd_data ( xv6_rd_data ), - .app_rd_data_valid ( xv6_rd_data_valid ) - ); - -`endif - - - // ------------------------------------------------------------- // Instantiate Wishbone Arbiter // -------------------------------------------------------------
/trunk/hw/vlog/xs6_ddr3/ddr3.xco
0,0 → 1,49
##############################################################
#
# Xilinx Core Generator version 14.5
# Date: Sun Apr 28 12:02:09 2013
#
##############################################################
#
# This file contains the customisation parameters for a
# Xilinx CORE Generator IP GUI. It is strongly recommended
# that you do not manually alter this file as it may cause
# unexpected and unsupported behavior.
#
##############################################################
#
# Generated from component: xilinx.com:ip:mig:3.92
#
##############################################################
#
# BEGIN Project Options
SET addpads = false
SET asysymbol = true
SET busformat = BusFormatAngleBracketNotRipped
SET createndf = false
SET designentry = Verilog
SET device = xc6slx45t
SET devicefamily = spartan6
SET flowvendor = Other
SET formalverification = false
SET foundationsym = false
SET implementationfiletype = Ngc
SET package = fgg484
SET removerpms = false
SET simulationfiles = Structural
SET speedgrade = -3
SET verilogsim = true
SET vhdlsim = false
# END Project Options
# BEGIN Select
SELECT MIG_Virtex-6_and_Spartan-6 family Xilinx,_Inc. 3.92
# END Select
# BEGIN Parameters
CSET component_name=ddr3
CSET xml_input_file=./ddr3/user_design/mig.prj
# END Parameters
# BEGIN Extra information
MISC pkg_timestamp=2013-03-27T03:45:13Z
# END Extra information
GENERATE
# CRC: 75718c29
/trunk/hw/vlog/xs6_ddr3/coregen_sp605.cgp
0,0 → 1,22
# Date: Sun Apr 28 11:01:18 2013
 
SET addpads = false
SET asysymbol = true
SET busformat = BusFormatAngleBracketNotRipped
SET createndf = false
SET designentry = Verilog
SET device = xc6slx45t
SET devicefamily = spartan6
SET flowvendor = Other
SET formalverification = false
SET foundationsym = false
SET implementationfiletype = Ngc
SET package = fgg484
SET removerpms = false
SET simulationfiles = Structural
SET speedgrade = -3
SET verilogsim = true
SET vhdlsim = false
SET workingdirectory = ./tmp/
 
# CRC: 78bed5b0
/trunk/hw/vlog/xs6_ddr3/README.txt
1,7 → 1,15
*** Steps to create the Spartan-6 DDR3 memory interface for the SP605 development board.
These instructions are based on using Xilinx ISE 11.5
These instructions are based on using Xilinx ISE 14.5
 
Use Coregen/MIG 3.3 to create the controller.
Run coregen
Open the project hw/vlog/xs6_ddr3/coregen_sp605.cgp
Under Project IP, select the Core Name "MIG Virtex-6 and Spartan-6",
right mouse on it and select Regenerate 9Under Original Project Settings)
Answer Yes to 'Do you wish to continue?' twice. The core generation process then runs in a few seconds.
Exit coregen.
 
 
This is the controller configuration, for reference.
- Component Name: ddr3
- Bank 3 Memory Type DDR3 SDRAM
- Frequency: 400MHz
10,30 → 18,39
- Memory Address Mapping Selection: Row, Bank, Column
 
 
Once the controller is generated copy all the Verilog files from the user_design/rtl directory to $AMBER_BASE/hw/vlog/xs6_ddr3.
Once the controller is generated copy all the Verilog files from the
hw/vlog/xs6_ddr3/user_design/rtl and hw/vlog/xs6_ddr3/user_design/rtl/mcb_controller
directories to $AMBER_BASE/hw/vlog/xs6_ddr3. Then make the following modifications
 
Then make the following modifications
1. ddr3
line 167 change
localparam C3_CLKFBOUT_MULT = 2;
to
localparam C3_CLKFBOUT_MULT = 4;
2. infrastructure.v
Comment out line 126, (* KEEP = "TRUE" *) wire sys_clk_ibufg;
Comment out the IBUFG instance u_ibufg_sys_clk on lines 156 to 160.
Change the CLKIN1 signal on line 202 from sys_clk_ibufg to sys_clk.
 
1. ddr3.v
Rename this module to mcb_ddr3.v.
Replace the inputs c3_sys_clk_p, c3_sys_clk_n with sys_clk_ibufg.
Delete the outputs c3_clk0 and c3_rst0.
There is already an IBUFGDS on that signal in clocks_resets.v so the
one in infrastructure.v is not needed.
 
2. memc3_infrastructure.v
Replace the inputs sys_clk_p, sys_clk_n with sys_clk_ibufg.
Delete the outputs clk0 and rst0.
Delete the line with (* KEEP = "TRUE" *) wire sys_clk_ibufg;
 
Change the localparam from
localparam CLK_PERIOD_NS = C_MEMCLK_PERIOD / 1000.0;
to
localparam CLK_PERIOD_NS = C_MEMCLK_PERIOD / 500.0;
In order to use Impact on CentOS 6, you need to install a USB driver.
sudo yum install libusb-devel
Then download and make the usb driver from http://rmdir.de/~michael/xilinx/
Once its successfully compiled run setup_pcusb to add the device IDs to the Xilinx installation.
 
Delete the generate statement from lines 124 to 154
You also need to install the fxload package
sudo rpm -i fxload-2008_10_13-3.el6.i686.rpm
And reboot after installing it.
 
On the PLL_ADV instantiation,
Change the parameter CLKFBOUT_MULT from 2 to 4.
Disconnect the CLKOUT2 output
Then power on the SP605 board and connect its USB-JTAG port to your PC.
Then run impact as follows
export LD_PRELOAD=/your-path/libusb-driver.so
impact
Impact should now be able to auto-detect the FPFA card. Right click on the FPGA and select the bitfile to load into it.
 
Delete the U_BUFG_CLK0 instantiation.
Delete the rst0_sync_r logic.
 
/trunk/hw/vlog/xs6_ddr3/ddr3/user_design/mig.prj
0,0 → 1,63
<?xml version="1.0" encoding="UTF-8"?>
<Project NoOfControllers="1" >
<ModuleName>ddr3</ModuleName>
<TargetFPGA>xc6slx45t-fgg484/-3</TargetFPGA>
<Version>3.92</Version>
<Controller number="3" >
<MemoryDevice>DDR3_SDRAM/Components/MT41J64M16XX-187E</MemoryDevice>
<TimePeriod>2500</TimePeriod>
<EnableVoltageRange>0</EnableVoltageRange>
<DataMask>1</DataMask>
<CustomPart>FALSE</CustomPart>
<NewPartName></NewPartName>
<RowAddress>13</RowAddress>
<ColAddress>10</ColAddress>
<BankAddress>3</BankAddress>
<TimingParameters>
<Parameters twtr="7.5" trefi="7.8" twr="15" trtp="7.5" trfc="110" trp="13.13" tras="37.5" trcd="13.13" />
</TimingParameters>
<mrBurstLength name="Burst Length" >8(00)</mrBurstLength>
<mrCasLatency name="CAS Latency" >6</mrCasLatency>
<emrDllEnable name="DLL Enable" >Enable</emrDllEnable>
<emrOutputDriveStrength name="Output Driver Impedance Control" >RZQ/6</emrOutputDriveStrength>
<emrRTT name="RTT (nominal) - ODT" >RZQ/4</emrRTT>
<emrPosted name="Additive Latency (AL)" >0</emrPosted>
<emrOCD name="Write Leveling Enable" >Disabled</emrOCD>
<emrDQS name="TDQS enable" >Disabled</emrDQS>
<mr2PartialArraySelfRefresh name="Partial-Array Self Refresh" >Full Array</mr2PartialArraySelfRefresh>
<mr2CasWriteLatency name="CAS write latency" >5</mr2CasWriteLatency>
<mr2AutoSelfRefresh name="Auto Self Refresh" >Enabled</mr2AutoSelfRefresh>
<mr2SelfRefreshTempRange name="High Temparature Self Refresh Rate" >Normal</mr2SelfRefreshTempRange>
<PortInterface>NATIVE</PortInterface>
<Class>Class II</Class>
<DataClass>Class II</DataClass>
<InputPinTermination>UNCALIB_TERM</InputPinTermination>
<DataTermination>50 Ohms</DataTermination>
<CalibrationRowAddress></CalibrationRowAddress>
<CalibrationColumnAddress></CalibrationColumnAddress>
<CalibrationBankAddress></CalibrationBankAddress>
<SystemClock>Single-Ended</SystemClock>
<BypassCalibration>1</BypassCalibration>
<DebugSignals>Disable</DebugSignals>
<SystemClock>Single-Ended</SystemClock>
<Configuration>One 128-bit bi-directional port</Configuration>
<RzqPin>R7</RzqPin>
<ZioPin>W4</ZioPin>
<PortsSelected>Port0</PortsSelected>
<PortDirections>Bi-directional</PortDirections>
<UserMemoryAddressMap>ROW_BANK_COLUMN</UserMemoryAddressMap>
<ArbitrationAlgorithm>Round Robin</ArbitrationAlgorithm>
<TimeSlot0>0</TimeSlot0>
<TimeSlot1>0</TimeSlot1>
<TimeSlot2>0</TimeSlot2>
<TimeSlot3>0</TimeSlot3>
<TimeSlot4>0</TimeSlot4>
<TimeSlot5>0</TimeSlot5>
<TimeSlot6>0</TimeSlot6>
<TimeSlot7>0</TimeSlot7>
<TimeSlot8>0</TimeSlot8>
<TimeSlot9>0</TimeSlot9>
<TimeSlot10>0</TimeSlot10>
<TimeSlot11>0</TimeSlot11>
</Controller>
</Project>
/trunk/hw/vlog/xs6_ddr3/ddr3/user_design
trunk/hw/vlog/xs6_ddr3/ddr3/user_design Property changes : Added: svn:ignore ## -0,0 +1,5 ## +datasheet.txt +rtl +par +synth +sim Index: trunk/hw/vlog/xs6_ddr3/ddr3 =================================================================== --- trunk/hw/vlog/xs6_ddr3/ddr3 (nonexistent) +++ trunk/hw/vlog/xs6_ddr3/ddr3 (revision 64)
trunk/hw/vlog/xs6_ddr3/ddr3 Property changes : Added: svn:ignore ## -0,0 +1,2 ## +example_design +docs Index: trunk/hw/vlog/xs6_ddr3 =================================================================== --- trunk/hw/vlog/xs6_ddr3 (revision 63) +++ trunk/hw/vlog/xs6_ddr3 (revision 64)
trunk/hw/vlog/xs6_ddr3 Property changes : Modified: svn:ignore ## -6,3 +6,16 ## memc3_infrastructure.v mcb_soft_calibration_top.v mcb_raw_wrapper.v +ddr3.gise +ddr3.veo +mcb_ui_top.v +infrastructure.v +memc_wrapper.v +ddr3_readme.txt +ddr3_xmdf.tcl +ddr3.v +tmp +coregen.log +ddr3.xise +coregen_sp605.cgc +ddr3_flist.txt Index: trunk/hw/fpga/bin/xs6_constraints.ucf =================================================================== --- trunk/hw/fpga/bin/xs6_constraints.ucf (revision 63) +++ trunk/hw/fpga/bin/xs6_constraints.ucf (revision 64) @@ -59,12 +59,30 @@ TIMESPEC "TS_MRX_CLK" = PERIOD "MRX_CLK" 40.0 ns HIGH 50 %; # False paths between clocks -PIN "u_mcb_ddr3/memc3_infrastructure_inst/u_pll_adv.CLKOUT3" TNM = "DDR_CLK"; -PIN "u_clocks_resets/u_pll_adv.CLKOUT2" TNM = "SYS_CLK"; +PIN "u_ddr3/memc3_infrastructure_inst/u_pll_adv.CLKOUT3" TNM = "DDR_CLK"; +PIN "u_clocks_resets/u_pll_adv.CLKOUT2" TNM = "CLKOUT2"; +TIMESPEC "TS_false2" = FROM "DDR_CLK" TO "CLKOUT2" TIG; -TIMESPEC "TS_false1" = FROM "DDR_CLK" TO "SYS_CLK" TIG; +############################################################################ +# DDR2 requires the MCB to operate in Extended performance mode with higher Vccint +# specification to achieve maximum frequency. Therefore, the following CONFIG constraint +# follows the corresponding GUI option setting. However, DDR3 can operate at higher +# frequencies with any Vcciint value by operating MCB in extended mode. Please do not +# remove/edit the below constraint to avoid false errors. +############################################################################ +CONFIG MCB_PERFORMANCE= EXTENDED; + +################################################################################## +# Timing Ignore constraints for paths crossing the clock domain +################################################################################## +NET "u_ddr3/memc?_wrapper_inst/mcb_ui_top_inst/mcb_raw_wrapper_inst/selfrefresh_mcb_mode" TIG; +NET "u_ddr3/c?_pll_lock" TIG; +INST "u_ddr3/memc?_wrapper_inst/mcb_ui_top_inst/mcb_raw_wrapper_inst/gen_term_calib.mcb_soft_calibration_top_inst/mcb_soft_calibration_inst/DONE_SOFTANDHARD_CAL*" TIG; + + + ############################################################################ ## I/O TERMINATION ############################################################################ @@ -91,7 +109,7 @@ NET "ddr3_reset_n" IOSTANDARD = SSTL15_II; NET "ddr3_dm[*]" IOSTANDARD = SSTL15_II; NET "mcb3_rzq" IOSTANDARD = SSTL15_II; -NET "mcb3_zio" IOSTANDARD = SSTL15_II; +#NET "mcb3_zio" IOSTANDARD = SSTL15_II; NET "brd_clk_p" IOSTANDARD = LVDS_25; NET "brd_clk_n" IOSTANDARD = LVDS_25; NET "brd_rst" IOSTANDARD = LVCMOS15; @@ -181,7 +199,7 @@ # The following pins are available for used as RZQ or ZIO pins# NET "mcb3_rzq" LOC = "K7" ; -NET "mcb3_zio" LOC = "R7" ; +#NET "mcb3_zio" LOC = "R7" ; ############################################################################ # Ethernet MII MAC to PHY interface
/trunk/hw/fpga/bin/xs6_source_files.prj
119,11 → 119,12
verilog work ../../vlog/lib/xs6_sram_1024x128_byte_en.v
 
# Xilinx Spartan-6 DDR3 I/F
verilog work ../../vlog/xs6_ddr3/mcb_ddr3.v
verilog work ../../vlog/xs6_ddr3/ddr3.v
verilog work ../../vlog/xs6_ddr3/iodrp_controller.v
verilog work ../../vlog/xs6_ddr3/iodrp_mcb_controller.v
verilog work ../../vlog/xs6_ddr3/mcb_raw_wrapper.v
verilog work ../../vlog/xs6_ddr3/mcb_soft_calibration_top.v
verilog work ../../vlog/xs6_ddr3/mcb_soft_calibration.v
verilog work ../../vlog/xs6_ddr3/memc3_infrastructure.v
verilog work ../../vlog/xs6_ddr3/memc3_wrapper.v
verilog work ../../vlog/xs6_ddr3/mcb_ui_top.v
verilog work ../../vlog/xs6_ddr3/infrastructure.v
verilog work ../../vlog/xs6_ddr3/memc_wrapper.v
/trunk/hw/fpga/bin/Makefile
64,7 → 64,7
BOOT_LOADER_DEF =
endif
 
VERILOG_INCLUDE_PATH = ../../vlog/lib $(BOOT_LOADER_DIR)
VERILOG_INCLUDE_PATH = ../../vlog/lib ../../vlog/tb $(BOOT_LOADER_DIR)
 
# Name of top level verilog file (must be the same as its module name)
RTL_TOP = system

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