OpenCores
URL https://opencores.org/ocsvn/ao486/ao486/trunk

Subversion Repositories ao486

Compare Revisions

  • This comparison shows the changes necessary to convert path 
    /
    from Rev 2 to Rev 3
    ↔ Reverse comparison
  •

Rev 2 → Rev 3

/ao486/trunk/syn/soc/system.html
67,7 → 67,7
</table>
<table class="blueBar">
<tr>
<td class="l">2014.03.30.22:35:14</td>
<td class="l">2014.04.01.19:57:17</td>
<td class="r">Datasheet</td>
</tr>
</table>
5735,7 → 5735,7
<table class="blueBar">
<tr>
<td class="l">generation took 0.01 seconds</td>
<td class="r">rendering took 0.18 seconds</td>
<td class="r">rendering took 0.14 seconds</td>
</tr>
</table>
</body>
/ao486/trunk/syn/soc/soc.qws Cannot display: file marked as a binary type. svn:mime-type = application/octet-stream
/ao486/trunk/syn/soc/system.sopcinfo Cannot display: file marked as a binary type. svn:mime-type = application/xml
/ao486/trunk/syn/soc/firmware/exe/main.cpp
947,6 → 947,8
 
alt_irq_disable_all();
runtime_menu();
//release reset - start executing
IOWR(PIO_OUTPUT_BASE, 0, 0x00);
/ao486/trunk/syn/components/ao486/ao486.qsf
41,7 → 41,7
set_global_assignment -name TOP_LEVEL_ENTITY ao486
set_global_assignment -name ORIGINAL_QUARTUS_VERSION 13.0
set_global_assignment -name PROJECT_CREATION_TIME_DATE "22:37:57 JULY 09, 2013"
set_global_assignment -name LAST_QUARTUS_VERSION "13.0 SP1"
set_global_assignment -name LAST_QUARTUS_VERSION 13.1
set_global_assignment -name PROJECT_OUTPUT_DIRECTORY output_files
set_global_assignment -name MIN_CORE_JUNCTION_TEMP 0
set_global_assignment -name MAX_CORE_JUNCTION_TEMP 85
50,73 → 50,73
set_global_assignment -name PARTITION_NETLIST_TYPE SOURCE -section_id Top
set_global_assignment -name PARTITION_FITTER_PRESERVATION_LEVEL PLACEMENT_AND_ROUTING -section_id Top
set_global_assignment -name PARTITION_COLOR 16764057 -section_id Top
set_global_assignment -name SEARCH_PATH /home/alek/aktualne/ao486/rtl
set_global_assignment -name VERILOG_FILE ../../rtl/pipeline/write_string.v
set_global_assignment -name VERILOG_FILE ../../rtl/pipeline/write_stack.v
set_global_assignment -name VERILOG_FILE ../../rtl/pipeline/write_register.v
set_global_assignment -name VERILOG_FILE ../../rtl/pipeline/write_debug.v
set_global_assignment -name VERILOG_FILE ../../rtl/pipeline/write_commands.v
set_global_assignment -name VERILOG_FILE ../../rtl/pipeline/write.v
set_global_assignment -name VERILOG_FILE ../../rtl/pipeline/read_segment.v
set_global_assignment -name VERILOG_FILE ../../rtl/pipeline/read_mutex.v
set_global_assignment -name VERILOG_FILE ../../rtl/pipeline/read_effective_address.v
set_global_assignment -name VERILOG_FILE ../../rtl/pipeline/read_debug.v
set_global_assignment -name VERILOG_FILE ../../rtl/pipeline/read_commands.v
set_global_assignment -name VERILOG_FILE ../../rtl/pipeline/read.v
set_global_assignment -name VERILOG_FILE ../../rtl/pipeline/pipeline.v
set_global_assignment -name VERILOG_FILE ../../rtl/pipeline/microcode_commands.v
set_global_assignment -name VERILOG_FILE ../../rtl/pipeline/microcode.v
set_global_assignment -name VERILOG_FILE ../../rtl/pipeline/fetch.v
set_global_assignment -name VERILOG_FILE ../../rtl/pipeline/execute_shift.v
set_global_assignment -name VERILOG_FILE ../../rtl/pipeline/execute_offset.v
set_global_assignment -name VERILOG_FILE ../../rtl/pipeline/execute_multiply.v
set_global_assignment -name VERILOG_FILE ../../rtl/pipeline/execute_divide.v
set_global_assignment -name VERILOG_FILE ../../rtl/pipeline/execute_commands.v
set_global_assignment -name VERILOG_FILE ../../rtl/pipeline/execute.v
set_global_assignment -name VERILOG_FILE ../../rtl/pipeline/decode_regs.v
set_global_assignment -name VERILOG_FILE ../../rtl/pipeline/decode_ready.v
set_global_assignment -name VERILOG_FILE ../../rtl/pipeline/decode_prefix.v
set_global_assignment -name VERILOG_FILE ../../rtl/pipeline/decode_commands.v
set_global_assignment -name VERILOG_FILE ../../rtl/pipeline/decode.v
set_global_assignment -name VERILOG_FILE ../../rtl/pipeline/condition.v
set_global_assignment -name VERILOG_FILE ../../rtl/memory/tlb_regs.v
set_global_assignment -name VERILOG_FILE ../../rtl/memory/tlb_memtype.v
set_global_assignment -name VERILOG_FILE ../../rtl/memory/tlb.v
set_global_assignment -name VERILOG_FILE ../../rtl/memory/prefetch_fifo.v
set_global_assignment -name VERILOG_FILE ../../rtl/memory/prefetch_control.v
set_global_assignment -name VERILOG_FILE ../../rtl/memory/prefetch.v
set_global_assignment -name VERILOG_FILE ../../rtl/memory/memory_write.v
set_global_assignment -name VERILOG_FILE ../../rtl/memory/memory_read.v
set_global_assignment -name VERILOG_FILE ../../rtl/memory/memory.v
set_global_assignment -name VERILOG_FILE ../../rtl/memory/link_writeline.v
set_global_assignment -name VERILOG_FILE ../../rtl/memory/link_writeburst.v
set_global_assignment -name VERILOG_FILE ../../rtl/memory/link_readline.v
set_global_assignment -name VERILOG_FILE ../../rtl/memory/link_readcode.v
set_global_assignment -name VERILOG_FILE ../../rtl/memory/link_readburst.v
set_global_assignment -name VERILOG_FILE ../../rtl/memory/link_dcachewrite.v
set_global_assignment -name VERILOG_FILE ../../rtl/memory/link_dcacheread.v
set_global_assignment -name VERILOG_FILE ../../rtl/memory/icache_read.v
set_global_assignment -name VERILOG_FILE ../../rtl/memory/icache_matched.v
set_global_assignment -name VERILOG_FILE ../../rtl/memory/icache_control_ram.v
set_global_assignment -name VERILOG_FILE ../../rtl/memory/icache.v
set_global_assignment -name VERILOG_FILE ../../rtl/memory/dcache_write.v
set_global_assignment -name VERILOG_FILE ../../rtl/memory/dcache_to_icache_fifo.v
set_global_assignment -name VERILOG_FILE ../../rtl/memory/dcache_read.v
set_global_assignment -name VERILOG_FILE ../../rtl/memory/dcache_matched.v
set_global_assignment -name VERILOG_FILE ../../rtl/memory/dcache_control_ram.v
set_global_assignment -name VERILOG_FILE ../../rtl/memory/dcache.v
set_global_assignment -name VERILOG_FILE ../../rtl/memory/cache_data_ram.v
set_global_assignment -name VERILOG_FILE ../../rtl/memory/avalon_mem.v
set_global_assignment -name VERILOG_FILE ../../rtl/altera/altera_prefetch_fifo.v
set_global_assignment -name VERILOG_FILE ../../rtl/altera/altera_icache_control_ram.v
set_global_assignment -name VERILOG_FILE ../../rtl/altera/altera_dcache_to_icache_fifo.v
set_global_assignment -name VERILOG_FILE ../../rtl/altera/altera_dcache_control_ram.v
set_global_assignment -name VERILOG_FILE ../../rtl/altera/altera_cache_data_ram.v
set_global_assignment -name VERILOG_FILE ../../rtl/exception.v
set_global_assignment -name VERILOG_FILE ../../rtl/global_regs.v
set_global_assignment -name VERILOG_FILE ../../rtl/defines.v
set_global_assignment -name VERILOG_FILE ../../rtl/avalon_io.v
set_global_assignment -name VERILOG_FILE ../../rtl/ao486.v
set_global_assignment -name SEARCH_PATH ./../../../rtl/ao486
set_global_assignment -name VERILOG_FILE ../../../rtl/common/simple_single_rom.v
set_global_assignment -name VERILOG_FILE ../../../rtl/common/simple_bidir_ram.v
set_global_assignment -name VERILOG_FILE ../../../rtl/common/simple_rom.v
set_global_assignment -name VERILOG_FILE ../../../rtl/common/simple_ram.v
set_global_assignment -name VERILOG_FILE ../../../rtl/common/simple_mult.v
set_global_assignment -name VERILOG_FILE ../../../rtl/common/simple_fifo.v
set_global_assignment -name VERILOG_FILE ../../../rtl/ao486/pipeline/write_string.v
set_global_assignment -name VERILOG_FILE ../../../rtl/ao486/pipeline/write_stack.v
set_global_assignment -name VERILOG_FILE ../../../rtl/ao486/pipeline/write_register.v
set_global_assignment -name VERILOG_FILE ../../../rtl/ao486/pipeline/write_debug.v
set_global_assignment -name VERILOG_FILE ../../../rtl/ao486/pipeline/write_commands.v
set_global_assignment -name VERILOG_FILE ../../../rtl/ao486/pipeline/write.v
set_global_assignment -name VERILOG_FILE ../../../rtl/ao486/pipeline/read_segment.v
set_global_assignment -name VERILOG_FILE ../../../rtl/ao486/pipeline/read_mutex.v
set_global_assignment -name VERILOG_FILE ../../../rtl/ao486/pipeline/read_effective_address.v
set_global_assignment -name VERILOG_FILE ../../../rtl/ao486/pipeline/read_debug.v
set_global_assignment -name VERILOG_FILE ../../../rtl/ao486/pipeline/read_commands.v
set_global_assignment -name VERILOG_FILE ../../../rtl/ao486/pipeline/read.v
set_global_assignment -name VERILOG_FILE ../../../rtl/ao486/pipeline/pipeline.v
set_global_assignment -name VERILOG_FILE ../../../rtl/ao486/pipeline/microcode_commands.v
set_global_assignment -name VERILOG_FILE ../../../rtl/ao486/pipeline/microcode.v
set_global_assignment -name VERILOG_FILE ../../../rtl/ao486/pipeline/fetch.v
set_global_assignment -name VERILOG_FILE ../../../rtl/ao486/pipeline/execute_shift.v
set_global_assignment -name VERILOG_FILE ../../../rtl/ao486/pipeline/execute_offset.v
set_global_assignment -name VERILOG_FILE ../../../rtl/ao486/pipeline/execute_multiply.v
set_global_assignment -name VERILOG_FILE ../../../rtl/ao486/pipeline/execute_divide.v
set_global_assignment -name VERILOG_FILE ../../../rtl/ao486/pipeline/execute_commands.v
set_global_assignment -name VERILOG_FILE ../../../rtl/ao486/pipeline/execute.v
set_global_assignment -name VERILOG_FILE ../../../rtl/ao486/pipeline/decode_regs.v
set_global_assignment -name VERILOG_FILE ../../../rtl/ao486/pipeline/decode_ready.v
set_global_assignment -name VERILOG_FILE ../../../rtl/ao486/pipeline/decode_prefix.v
set_global_assignment -name VERILOG_FILE ../../../rtl/ao486/pipeline/decode_commands.v
set_global_assignment -name VERILOG_FILE ../../../rtl/ao486/pipeline/decode.v
set_global_assignment -name VERILOG_FILE ../../../rtl/ao486/pipeline/condition.v
set_global_assignment -name VERILOG_FILE ../../../rtl/ao486/memory/tlb_regs.v
set_global_assignment -name VERILOG_FILE ../../../rtl/ao486/memory/tlb_memtype.v
set_global_assignment -name VERILOG_FILE ../../../rtl/ao486/memory/tlb.v
set_global_assignment -name VERILOG_FILE ../../../rtl/ao486/memory/prefetch_fifo.v
set_global_assignment -name VERILOG_FILE ../../../rtl/ao486/memory/prefetch_control.v
set_global_assignment -name VERILOG_FILE ../../../rtl/ao486/memory/prefetch.v
set_global_assignment -name VERILOG_FILE ../../../rtl/ao486/memory/memory_write.v
set_global_assignment -name VERILOG_FILE ../../../rtl/ao486/memory/memory_read.v
set_global_assignment -name VERILOG_FILE ../../../rtl/ao486/memory/memory.v
set_global_assignment -name VERILOG_FILE ../../../rtl/ao486/memory/link_writeline.v
set_global_assignment -name VERILOG_FILE ../../../rtl/ao486/memory/link_writeburst.v
set_global_assignment -name VERILOG_FILE ../../../rtl/ao486/memory/link_readline.v
set_global_assignment -name VERILOG_FILE ../../../rtl/ao486/memory/link_readcode.v
set_global_assignment -name VERILOG_FILE ../../../rtl/ao486/memory/link_readburst.v
set_global_assignment -name VERILOG_FILE ../../../rtl/ao486/memory/link_dcachewrite.v
set_global_assignment -name VERILOG_FILE ../../../rtl/ao486/memory/link_dcacheread.v
set_global_assignment -name VERILOG_FILE ../../../rtl/ao486/memory/icache_read.v
set_global_assignment -name VERILOG_FILE ../../../rtl/ao486/memory/icache_matched.v
set_global_assignment -name VERILOG_FILE ../../../rtl/ao486/memory/icache_control_ram.v
set_global_assignment -name VERILOG_FILE ../../../rtl/ao486/memory/icache.v
set_global_assignment -name VERILOG_FILE ../../../rtl/ao486/memory/dcache_write.v
set_global_assignment -name VERILOG_FILE ../../../rtl/ao486/memory/dcache_to_icache_fifo.v
set_global_assignment -name VERILOG_FILE ../../../rtl/ao486/memory/dcache_read.v
set_global_assignment -name VERILOG_FILE ../../../rtl/ao486/memory/dcache_matched.v
set_global_assignment -name VERILOG_FILE ../../../rtl/ao486/memory/dcache_control_ram.v
set_global_assignment -name VERILOG_FILE ../../../rtl/ao486/memory/dcache.v
set_global_assignment -name VERILOG_FILE ../../../rtl/ao486/memory/cache_data_ram.v
set_global_assignment -name VERILOG_FILE ../../../rtl/ao486/memory/avalon_mem.v
set_global_assignment -name VERILOG_FILE ../../../rtl/ao486/exception.v
set_global_assignment -name VERILOG_FILE ../../../rtl/ao486/global_regs.v
set_global_assignment -name VERILOG_FILE ../../../rtl/ao486/avalon_io.v
set_global_assignment -name VERILOG_FILE ../../../rtl/ao486/ao486.v
set_global_assignment -name SDC_FILE ao486.sdc
set_global_assignment -name CYCLONEII_OPTIMIZATION_TECHNIQUE BALANCED
set_global_assignment -name SYNTH_TIMING_DRIVEN_SYNTHESIS ON
/ao486/trunk/syn/components/ao486/ao486.sdc
23,7 → 23,7
 
# Clock constraints
 
create_clock -name "clk" -period 20.000ns [get_ports {clk}]
create_clock -name "clk" -period 30.000ns [get_ports {clk}]
 
 
# Automatically constrain PLL and other generated clocks
/ao486/trunk/bios/bochs-2.6.2/bochs-2.6.2.diff
0,0 → 1,135
diff -ruN bochs-2.6.2/bios/rombios.c bochs-2.6.2-ao486/bios/rombios.c
--- bochs-2.6.2/bios/rombios.c 2013-04-21 22:09:49.000000000 +0200
+++ bochs-2.6.2-ao486/bios/rombios.c 2014-03-30 14:27:08.000000000 +0200
@@ -182,7 +182,7 @@
;; However, users can choose to make panics non-fatal and continue.
#if BX_VIRTUAL_PORTS
mov dx,#PANIC_PORT
- mov ax,#?1
+ mov ax,#0x21 //ao #?1
out dx,ax
#else
mov dx,#0x80
@@ -1537,8 +1537,12 @@
uart_tx_byte(BX_DEBUG_PORT, c);
#endif
#if BX_VIRTUAL_PORTS
- if (action & BIOS_PRINTF_DEBUG) outb(DEBUG_PORT, c);
- if (action & BIOS_PRINTF_INFO) outb(INFO_PORT, c);
+ if((action & BIOS_PRINTF_DEBUG) || (action & BIOS_PRINTF_INFO) || (action & BIOS_PRINTF_SCREEN)) {
+ while(inw(DEBUG_PORT+6) == 0) { ; }
+ }
+ if (action & BIOS_PRINTF_DEBUG) outb(DEBUG_PORT, c);
+ if (action & BIOS_PRINTF_INFO) outb(INFO_PORT, c);
+ if (action & BIOS_PRINTF_SCREEN) outb(INFO_PORT, c);
#endif
if (action & BIOS_PRINTF_SCREEN) {
if (c == '\n') wrch('\r');
@@ -1702,7 +1706,7 @@
if ((action & BIOS_PRINTF_DEBHALT) == BIOS_PRINTF_DEBHALT) {
#if BX_VIRTUAL_PORTS
- outb(PANIC_PORT2, 0x00);
+ outb(PANIC_PORT2, '&'); //ao 0x00
#endif
bios_printf (BIOS_PRINTF_SCREEN, "FATAL: ");
}
@@ -2509,7 +2513,9 @@
Bit16u base;
Bit16u timeout;
{
- Bit32u time=0,last=0;
+//AO modif
+ Bit16u time=0,last=0;
+//AO modif
Bit16u status;
Bit8u result;
status = inb(base + ATA_CB_STAT); // for the times you're supposed to throw one away
@@ -2530,17 +2536,27 @@
result = 0;
if (result) return 0;
- if (time>>16 != last) // mod 2048 each 16 ms
+//AO modif
+ if (time>>8 != last) // mod 2048 each 16 ms
+//AO modif
{
- last = time >>16;
- BX_DEBUG_ATA("await_ide: (TIMEOUT,BSY,!BSY,!BSY_DRQ,!BSY_!DRQ,!BSY_RDY) %d time= %ld timeout= %d\n",when_done,time>>11, timeout);
+//AO modif
+ last = time >>8;
+//AO modif
+//AO modif
+ BX_DEBUG_ATA("await_ide: (TIMEOUT,BSY,!BSY,!BSY_DRQ,!BSY_!DRQ,!BSY_RDY) %d time= %ld timeout= %d, status= %x\n",when_done,time>>3, timeout, status);
+//AO modif
}
if (status & ATA_CB_STAT_ERR)
{
- BX_DEBUG_ATA("await_ide: ERROR (TIMEOUT,BSY,!BSY,!BSY_DRQ,!BSY_!DRQ,!BSY_RDY) %d time= %ld timeout= %d\n",when_done,time>>11, timeout);
+//AO modif
+ BX_DEBUG_ATA("await_ide: ERROR (TIMEOUT,BSY,!BSY,!BSY_DRQ,!BSY_!DRQ,!BSY_RDY) %d time= %ld timeout= %d\n",when_done,time>>3, timeout);
+//AO modif
return -1;
}
- if ((timeout == 0) || ((time>>11) > timeout)) break;
+//AO modif
+ if ((timeout == 0) || ((time>>3) > timeout)) break;
+//AO modif
}
BX_INFO("IDE time out\n");
return -1;
@@ -3099,7 +3115,10 @@
current++;
write_word_DS(&EbdaData->ata.trsfsectors,current);
count--;
- if(ioflag == 0) await_ide(NOT_BSY, iobase1, IDE_TIMEOUT);
+//AO modification start
+//modif if(ioflag == 0) await_ide(NOT_BSY, iobase1, IDE_TIMEOUT);
+ await_ide(NOT_BSY, iobase1, IDE_TIMEOUT);
+//AO modification end
status = inb(iobase1 + ATA_CB_STAT);
if(ioflag == 0)
{
diff -ruN bochs-2.6.2/bios/rombios.h bochs-2.6.2-ao486/bios/rombios.h
--- bochs-2.6.2/bios/rombios.h 2012-11-11 09:11:17.000000000 +0100
+++ bochs-2.6.2-ao486/bios/rombios.h 2014-03-30 14:29:31.000000000 +0200
@@ -39,10 +39,10 @@
#define DEBUG_INT74 0
#define DEBUG_APM 0
-#define PANIC_PORT 0x400
-#define PANIC_PORT2 0x401
-#define INFO_PORT 0x402
-#define DEBUG_PORT 0x403
+#define PANIC_PORT 0x8888 //ao 0x400
+#define PANIC_PORT2 0x8888 //ao 0x401
+#define INFO_PORT 0x8888 //ao 0x402
+#define DEBUG_PORT 0x8888 //ao 0x403
#define BIOS_PRINTF_HALT 1
#define BIOS_PRINTF_SCREEN 2
@@ -95,19 +95,19 @@
#define BX_USE_EBDA 1
#define BX_SUPPORT_FLOPPY 1
#define BX_FLOPPY_ON_CNT 37 /* 2 seconds */
-#define BX_PCIBIOS 1
-#define BX_APM 1
-#define BX_PNPBIOS 1
+#define BX_PCIBIOS 0 //ao
+#define BX_APM 0 //ao
+#define BX_PNPBIOS 0 //ao
/* define it if the (emulated) hardware supports SMM mode */
#define BX_USE_SMM
#define BX_USE_ATADRV 1
-#define BX_ELTORITO_BOOT 1
+#define BX_ELTORITO_BOOT 0 //ao
#define BX_MAX_ATA_INTERFACES 4
#define BX_MAX_ATA_DEVICES (BX_MAX_ATA_INTERFACES*2)
-#define BX_VIRTUAL_PORTS 1 /* normal output to Bochs ports */
+#define BX_VIRTUAL_PORTS 0 //ao /* normal output to Bochs ports */
#define BX_DEBUG_SERIAL 0 /* output to COM1 */
/* model byte 0xFC = AT */
/ao486/trunk/bios/vgabios-0.7a/vgabios-0.7a.diff
0,0 → 1,23
diff -ruN vgabios-0.7a/Makefile vgabios-0.7a-ao486/Makefile
--- vgabios-0.7a/Makefile 2011-07-19 18:59:50.000000000 +0200
+++ vgabios-0.7a-ao486/Makefile 2014-03-30 14:39:25.000000000 +0200
@@ -31,7 +31,8 @@
VBE_FILES := vbe.h vbe.c vbetables.h
# build flags
-vgabios.bin : VGAFLAGS := -DVBE -DPCIBIOS
+vgabios.bin : VGAFLAGS :=
+#-DVBE -DPCIBIOS
vgabios.debug.bin : VGAFLAGS := -DVBE -DPCIBIOS -DDEBUG
vgabios-cirrus.bin : VGAFLAGS := -DCIRRUS -DPCIBIOS
vgabios-cirrus.debug.bin : VGAFLAGS := -DCIRRUS -DPCIBIOS -DCIRRUS_DEBUG
@@ -43,7 +44,8 @@
vgabios-cirrus.debug.bin : DISTNAME := VGABIOS-lgpl-latest.cirrus.debug.bin
# dependencies
-vgabios.bin : $(VGA_FILES) $(VBE_FILES) biossums
+vgabios.bin : $(VGA_FILES) biossums
+#$(VGA_FILES) $(VBE_FILES) biossums
vgabios.debug.bin : $(VGA_FILES) $(VBE_FILES) biossums
vgabios-cirrus.bin : $(VGA_FILES) clext.c biossums
vgabios-cirrus.debug.bin : $(VGA_FILES) clext.c biossums
/ao486/trunk/README.md
0,0 → 1,184
### Description
 
The ao486 is an x86 compatible Verilog core implementing all features of a 486 SX.
The core was modeled and tested based on the Bochs software x86 implementation.
Together with the 486 core, the ao486 project also contains a SoC capable of
booting the Linux kernel version 3.13 and Microsoft Windows 95.
 
### Features
 
The ao486 processor model has the following features:
- pipeline architecture with 4 main stages: decode, read, execute and write,
- all 486 instructions are implemented, together with CPUID,
- 16 kB instruction cache,
- 16 kB write-back data cache,
- TLB for 32 entries,
- Altera Avalon interfaces for memory and io access.
 
The ao486 SoC consists of the following components:
- ao486 processor,
- IDE hard drive that redirects to a HDL SD card driver,
- floppy controller that also redirects to the SD card driver,
- 8259 PIC,
- 8237 DMA,
- Sound Blaster 2.0 with DSP and OPL2 (FM synthesis not fully working).
Sound output redirected to a WM8731 audio codec,
- 8254 PIT,
- 8042 keyboard and mouse controller,
- RTC
- standard VGA.
 
All components are modeled as Altera Qsys components. Altera Qsys connects all
parts together, and supplies the SDRAM controller.
 
The ao486 project is currently only running on the Terasic DE2-115 board.
 
### Resource usage
 
The project is synthesised for the Altera Cyclone IV E EP4CE115F29C7 device.
Resource utilization is as follows:
 
| Unit | Logic cells | M9K memory blocks |
|--------------------|-------------|-------------------|
| ao486 processor | 36517 | 47 |
| floppy | 1514 | 2 |
| hdd | 2071 | 17 |
| nios2 | 1056 | 3 |
| onchip for nios2 | 0 | 32 |
| pc_dma | 848 | 0 |
| pic | 388 | 0 |
| pit | 667 | 0 |
| ps2 | 742 | 2 |
| rtc | 783 | 1 |
| sound | 37131 | 29 |
| vga | 2534 | 260 |
 
The fitter raport after compiling all components of the ao486 project is as
follows:
 
```
Fitter Status : Successful - Sun Mar 30 21:00:13 2014
Quartus II 64-Bit Version : 13.1.0 Build 162 10/23/2013 SJ Web Edition
Revision Name : soc
Top-level Entity Name : soc
Family : Cyclone IV E
Device : EP4CE115F29C7
Timing Models : Final
Total logic elements : 91,256 / 114,480 ( 80 % )
Total combinational functions : 86,811 / 114,480 ( 76 % )
Dedicated logic registers : 26,746 / 114,480 ( 23 % )
Total registers : 26865
Total pins : 108 / 529 ( 20 % )
Total virtual pins : 0
Total memory bits : 2,993,408 / 3,981,312 ( 75 % )
Embedded Multiplier 9-bit elements : 44 / 532 ( 8 % )
Total PLLs : 1 / 4 ( 25 % )
```
 
The maximum frequency is 39 MHz. The project uses a 30 MHz clock.
 
### Running software
 
The ao486 successfuly runs the following software:
- Microsoft MS-DOS version 6.22,
- Microsoft Windows for Workgroups 3.11,
- Microsoft Windows 95,
- Linux 3.13.1.
 
### BIOS
 
The ao486 project uses the BIOS from the Bochs project
(http://bochs.sourceforge.net, version 2.6.2). Some minor changes
were required to support the hard drive.
 
The VGA BIOS is from the VGABIOS project (http://www.nongnu.org/vgabios,
version 0.7a). No changes were required. The VGA model does not have VBE
extensions, so the extensions were disabled.
 
### NIOS2 controller
 
The ao486 SoC uses a Altera NIOS2 processor for managing all components and
displaying the contents of the On Screen Display.
 
The OSD allows the user to insert and remove floppy disks.
 
### License
 
All files in the following directories:
- rtl,
- ao486_tool,
- sim
 
are licensed under the BSD license:
 
All files in the following directories:
- bochs486,
- bochsDevs
 
are taken from the Bochs Project and are licensed under the LGPL license.
 
The binary file sd/fd_1_44m/fdboot.img is taken from the FreeDOS project.
 
The binary file sd/bios/bochs_legacy is a compiled BIOS from the Bochs project.
 
The binary file sd/vgabios/vgabios-lgpl is a compiled VGA BIOS from the vgabios
project.
 
### Compiling
To compile the SoC, which contains the NIOS II microcontroller, Altera Quartus II software is required.
The Verilog components of the SoC, in particular the ao486 processor, should be possible to compile
in any Verilog compiler. Currently synthesis project files are prepared only for Altera Quartus II.
 
NOTE: In the current version some synthesis project files -- especially the paths in those files, could be
broken.
 
#### ao486 processor
To compile the ao486 processor load the project file from syn/components/ao486/ao486.qpf.
 
#### SoC
To compile the ao486 SoC load the project file from syn/soc/soc.qpf.
 
#### BIOS
To compile the BIOS do the following:
- extract the bochs-2.6.2 source archive,
- apply the patch from the directory bios/bochs-2.6.2 by running in the extracted directory:
patch -p1 < (path to patch file)
- run ./configure in bochs
- run make in bochs
- cd bios
- make
- the binary file BIOS-bochs-legacy works with ao486 SoC.
 
#### VGABIOS
To compile the VGABIOS do the following:
- extract the vgabios-0.7a source archive,
- apply the patch form the directory bios/vgabios-0.7a by running in the extracted directory:
patch -p1 < (path to patch file)
- run make in vgabios,
- the binary file VGABIOS-lgpl-latest.bin works with ao486 SoC.
 
### Running the SoC on Terasic DE2-115
 
- compile the soc Altera Quartus II project in syn/soc/soc.qpf
- compile the firmware for the NIOS II by:
- opening the Nios II Software Build Tools for Eclipse,
- creating a workspace in the directory syn/soc/firmware,
- importing the two projects 'exe' and 'exe_bsp',
- genrating BSP on the 'exe_bsp' project,
- compiling the 'exe' project.
- compile the BIOS and copy the binary to the directory sd/bios
- compile the VGABIOS and copy the binary to the directory sd/vgabios
- compile the ao486_tool by running 'ant jar' in the directory ao486_tool
- edit the files in the directory sd/hdd. They contain the position of the virtual hard disk located on
the SD card. The start entry must be a multiplicity of 512. The values are in bytes from the begining
of the SD card,
- run 'java -cp ./dist/ao486_tool.jar ao486.SDGenerator' in the directory ao486_tool,
- copy the file ao486_tool/sd.dat to the first sectors of the SD card by using 'dd if=sd.dat of=/dev/sdXXX'.
- program the FPGA using the SOF file,
- load and run the firmware of the NIOS II controller,
- select the BIOS file on the On Screen Display by using KEY0 for down, KEY1 for up and KEY2 for select,
- select the VGABIOS file on the OSD,
- select the hard drive on the OSD,
- select the floppy on the OSD. Use the KEYs to select the floppy image. Use KEY3 to cancel.
- after selecting the floppy or pressing cancel, ao486 boots,
- to activate the OSD press KEY2.

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.