OpenCores
URL https://opencores.org/ocsvn/ao486/ao486/trunk

Subversion Repositories ao486

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    from Rev 6 to Rev 7
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Rev 6 → Rev 7

/ao486/trunk/rtl/ao486/ao486_hw.tcl
1,18 → 1,18
# TCL File Generated by Component Editor 13.1
# Sun Mar 30 12:22:06 CEST 2014
# TCL File Generated by Component Editor 14.0
# Mon Aug 18 22:50:23 CEST 2014
# DO NOT MODIFY
 
 
#
# ao486 "ao486" v1.0
# 2014.03.30.12:22:06
# 2014.08.18.22:50:23
#
#
 
#
# request TCL package from ACDS 13.1
# request TCL package from ACDS 14.0
#
package require -exact qsys 13.1
package require -exact qsys 14.0
 
 
#
28,9 → 28,9
set_module_property DISPLAY_NAME ao486
set_module_property INSTANTIATE_IN_SYSTEM_MODULE true
set_module_property EDITABLE true
set_module_property ANALYZE_HDL AUTO
set_module_property REPORT_TO_TALKBACK false
set_module_property ALLOW_GREYBOX_GENERATION false
set_module_property REPORT_HIERARCHY false
 
 
#
39,6 → 39,7
add_fileset QUARTUS_SYNTH QUARTUS_SYNTH "" ""
set_fileset_property QUARTUS_SYNTH TOP_LEVEL ao486
set_fileset_property QUARTUS_SYNTH ENABLE_RELATIVE_INCLUDE_PATHS false
set_fileset_property QUARTUS_SYNTH ENABLE_FILE_OVERWRITE_MODE false
add_fileset_file ao486.v VERILOG PATH ao486.v TOP_LEVEL_FILE
add_fileset_file avalon_io.v VERILOG PATH avalon_io.v
add_fileset_file defines.v VERILOG PATH defines.v
158,6 → 159,7
set_interface_property avalon_memory holdTime 0
set_interface_property avalon_memory linewrapBursts false
set_interface_property avalon_memory maximumPendingReadTransactions 0
set_interface_property avalon_memory maximumPendingWriteTransactions 0
set_interface_property avalon_memory readLatency 0
set_interface_property avalon_memory readWaitTime 1
set_interface_property avalon_memory setupTime 0
185,7 → 187,7
#
add_interface interrupt conduit end
set_interface_property interrupt associatedClock clock
set_interface_property interrupt associatedReset reset_sink
set_interface_property interrupt associatedReset ""
set_interface_property interrupt ENABLED true
set_interface_property interrupt EXPORT_OF ""
set_interface_property interrupt PORT_NAME_MAP ""
192,9 → 194,9
set_interface_property interrupt CMSIS_SVD_VARIABLES ""
set_interface_property interrupt SVD_ADDRESS_GROUP ""
 
add_interface_port interrupt interrupt_do export Input 1
add_interface_port interrupt interrupt_vector export Input 8
add_interface_port interrupt interrupt_done export Output 1
add_interface_port interrupt interrupt_do interrupt_do Input 1
add_interface_port interrupt interrupt_vector interrupt_vector Input 8
add_interface_port interrupt interrupt_done interrupt_done Output 1
 
 
#
212,6 → 214,7
set_interface_property avalon_io holdTime 0
set_interface_property avalon_io linewrapBursts false
set_interface_property avalon_io maximumPendingReadTransactions 0
set_interface_property avalon_io maximumPendingWriteTransactions 0
set_interface_property avalon_io readLatency 0
set_interface_property avalon_io readWaitTime 1
set_interface_property avalon_io setupTime 0
232,18 → 235,3
add_interface_port avalon_io avalon_io_writedata writedata Output 32
add_interface_port avalon_io avalon_io_waitrequest waitrequest Input 1
 
 
#
# connection point reset_only_ao486
#
add_interface reset_only_ao486 reset end
set_interface_property reset_only_ao486 associatedClock clock
set_interface_property reset_only_ao486 synchronousEdges DEASSERT
set_interface_property reset_only_ao486 ENABLED true
set_interface_property reset_only_ao486 EXPORT_OF ""
set_interface_property reset_only_ao486 PORT_NAME_MAP ""
set_interface_property reset_only_ao486 CMSIS_SVD_VARIABLES ""
set_interface_property reset_only_ao486 SVD_ADDRESS_GROUP ""
 
add_interface_port reset_only_ao486 rst_internal_n reset_n Input 1
 
/ao486/trunk/rtl/ao486/ao486.v
30,8 → 30,6
input clk,
input rst_n,
input rst_internal_n,
//--------------------------------------------------------------------------
input interrupt_do,
input [7:0] interrupt_vector,
154,7 → 152,7
 
exception exception_inst(
.clk (clk),
.rst_n (rst_internal_n),
.rst_n (rst_n),
//exception indicators
.dec_gp_fault (dec_gp_fault), //input
342,7 → 340,7
 
global_regs global_regs_inst(
.clk (clk),
.rst_n (rst_internal_n),
.rst_n (rst_n),
//input
.glob_param_1_set (glob_param_1_set), //input
450,7 → 448,6
memory memory_inst(
.clk (clk),
.rst_n (rst_n),
.rst_internal_n (rst_internal_n),
//REQ:
.read_do (read_do), //input
564,7 → 561,7
 
pipeline pipeline_inst(
.clk (clk),
.rst_n (rst_internal_n),
.rst_n (rst_n),
//to memory
.pr_reset (pr_reset), //output
/ao486/trunk/rtl/ao486/memory/memory.v
28,9 → 28,7
 
module memory(
input clk,
input rst_n,
input rst_internal_n,
//REQ:
input read_do,
173,7 → 171,7
 
link_writeburst link_writeburst_inst(
.clk (clk),
.rst_n (rst_internal_n),
.rst_n (rst_n),
// writeburst REQ
.req_writeburst_do (req_writeburst_do), //input
210,7 → 208,7
 
link_writeline link_writeline_inst(
.clk (clk),
.rst_n (rst_internal_n),
.rst_n (rst_n),
// writeline REQ
.req_writeline_do (req_writeline_do), //input
245,7 → 243,7
 
link_readburst link_readburst_inst(
.clk (clk),
.rst_n (rst_internal_n),
.rst_n (rst_n),
// readburst REQ
.req_readburst_do (req_readburst_do), //input
281,7 → 279,7
 
link_readline link_readline_inst(
.clk (clk),
.rst_n (rst_internal_n),
.rst_n (rst_n),
// readline REQ
.req_readline_do (req_readline_do), //input
316,7 → 314,7
 
link_readcode link_readcode_inst(
.clk (clk),
.rst_n (rst_internal_n),
.rst_n (rst_n),
// readcode REQ
.req_readcode_do (req_readcode_do), //input
355,7 → 353,7
 
link_dcacheread link_dcacheread_inst(
.clk (clk),
.rst_n (rst_internal_n),
.rst_n (rst_n),
// dcacheread REQ
.req_dcacheread_do (req_dcacheread_do), //input
396,7 → 394,7
 
link_dcachewrite link_dcachewrite_inst(
.clk (clk),
.rst_n (rst_internal_n),
.rst_n (rst_n),
// dcachewrite REQ
.req_dcachewrite_do (req_dcachewrite_do), //input
578,7 → 576,7
dcache dcache_inst(
// global
.clk (clk),
.rst_n (rst_internal_n),
.rst_n (rst_n),
//RESP:
.dcacheread_do (resp_dcacheread_do), //input
659,7 → 657,7
 
dcache_to_icache_fifo dcache_to_icache_fifo_inst(
.clk (clk),
.rst_n (rst_internal_n),
.rst_n (rst_n),
//RESP:
.dcachetoicache_write_do (dcachetoicache_write_do), //input
678,7 → 676,7
 
icache icache_inst(
.clk (clk),
.rst_n (rst_internal_n),
.rst_n (rst_n),
//RESP:
.pr_reset (pr_reset), //input
727,7 → 725,7
memory_read memory_read_inst(
// global
.clk (clk),
.rst_n (rst_internal_n),
.rst_n (rst_n),
// read step
.rd_reset (rd_reset), //input
768,7 → 766,7
 
memory_write memory_write_inst(
.clk (clk),
.rst_n (rst_internal_n),
.rst_n (rst_n),
// write step
.wr_reset (wr_reset), //input
808,7 → 806,7
 
prefetch prefetch_inst(
.clk (clk),
.rst_n (rst_internal_n),
.rst_n (rst_n),
.pr_reset (pr_reset), //input
836,7 → 834,7
 
prefetch_fifo prefetch_fifo_inst(
.clk (clk),
.rst_n (rst_internal_n),
.rst_n (rst_n),
.pr_reset (pr_reset), //input
867,7 → 865,7
 
prefetch_control prefetch_control_inst(
.clk (clk),
.rst_n (rst_internal_n),
.rst_n (rst_n),
.pr_reset (pr_reset), //input //same as reset to icache
906,7 → 904,7
 
tlb tlb_inst(
.clk (clk),
.rst_n (rst_internal_n),
.rst_n (rst_n),
 
.pr_reset (pr_reset), //input
.rd_reset (rd_reset), //input
/ao486/trunk/rtl/soc/driver_sd/driver_sd_hw.tcl
1,18 → 1,18
# TCL File Generated by Component Editor 13.1
# Thu Jan 16 22:27:48 CET 2014
# TCL File Generated by Component Editor 14.0
# Mon Aug 18 20:36:09 CEST 2014
# DO NOT MODIFY
 
 
#
# driver_sd "driver_sd" v1.0
# 2014.01.16.22:27:48
# driver_sd "driver_sd" v2.0
# 2014.08.18.20:36:09
#
#
 
#
# request TCL package from ACDS 13.1
# request TCL package from ACDS 14.0
#
package require -exact qsys 13.1
package require -exact qsys 14.0
 
 
#
20,7 → 20,7
#
set_module_property DESCRIPTION ""
set_module_property NAME driver_sd
set_module_property VERSION 1.0
set_module_property VERSION 2.0
set_module_property INTERNAL false
set_module_property OPAQUE_ADDRESS_MAP true
set_module_property GROUP ao486
28,9 → 28,9
set_module_property DISPLAY_NAME driver_sd
set_module_property INSTANTIATE_IN_SYSTEM_MODULE true
set_module_property EDITABLE true
set_module_property ANALYZE_HDL AUTO
set_module_property REPORT_TO_TALKBACK false
set_module_property ALLOW_GREYBOX_GENERATION false
set_module_property REPORT_HIERARCHY false
 
 
#
39,6 → 39,14
add_fileset QUARTUS_SYNTH QUARTUS_SYNTH "" ""
set_fileset_property QUARTUS_SYNTH TOP_LEVEL driver_sd
set_fileset_property QUARTUS_SYNTH ENABLE_RELATIVE_INCLUDE_PATHS false
set_fileset_property QUARTUS_SYNTH ENABLE_FILE_OVERWRITE_MODE false
add_fileset_file avalon_master.v VERILOG PATH avalon_master.v
add_fileset_file avalon_slave.v VERILOG PATH avalon_slave.v
add_fileset_file card_init.v VERILOG PATH card_init.v
add_fileset_file card_read.v VERILOG PATH card_read.v
add_fileset_file card_write.v VERILOG PATH card_write.v
add_fileset_file cmd.v VERILOG PATH cmd.v
add_fileset_file dat.v VERILOG PATH dat.v
add_fileset_file driver_sd.v VERILOG PATH driver_sd.v TOP_LEVEL_FILE
 
 
80,6 → 88,7
set_interface_property avalon_slave_0 holdTime 0
set_interface_property avalon_slave_0 linewrapBursts false
set_interface_property avalon_slave_0 maximumPendingReadTransactions 0
set_interface_property avalon_slave_0 maximumPendingWriteTransactions 0
set_interface_property avalon_slave_0 readLatency 0
set_interface_property avalon_slave_0 readWaitTime 1
set_interface_property avalon_slave_0 setupTime 0
96,7 → 105,6
add_interface_port avalon_slave_0 avs_readdata readdata Output 32
add_interface_port avalon_slave_0 avs_write write Input 1
add_interface_port avalon_slave_0 avs_writedata writedata Input 32
add_interface_port avalon_slave_0 avs_waitrequest waitrequest Output 1
set_interface_assignment avalon_slave_0 embeddedsw.configuration.isFlash 0
set_interface_assignment avalon_slave_0 embeddedsw.configuration.isMemoryDevice 0
set_interface_assignment avalon_slave_0 embeddedsw.configuration.isNonVolatileStorage 0
104,21 → 112,6
 
 
#
# connection point reset_sink
#
add_interface reset_sink reset end
set_interface_property reset_sink associatedClock clock
set_interface_property reset_sink synchronousEdges DEASSERT
set_interface_property reset_sink ENABLED true
set_interface_property reset_sink EXPORT_OF ""
set_interface_property reset_sink PORT_NAME_MAP ""
set_interface_property reset_sink CMSIS_SVD_VARIABLES ""
set_interface_property reset_sink SVD_ADDRESS_GROUP ""
 
add_interface_port reset_sink rst_n reset_n Input 1
 
 
#
# connection point avalon_master_0
#
add_interface avalon_master_0 avalon start
133,6 → 126,7
set_interface_property avalon_master_0 holdTime 0
set_interface_property avalon_master_0 linewrapBursts false
set_interface_property avalon_master_0 maximumPendingReadTransactions 0
set_interface_property avalon_master_0 maximumPendingWriteTransactions 0
set_interface_property avalon_master_0 readLatency 0
set_interface_property avalon_master_0 readWaitTime 1
set_interface_property avalon_master_0 setupTime 0
154,18 → 148,61
 
 
#
# connection point export_sd
# connection point reset_sink
#
add_interface export_sd conduit end
set_interface_property export_sd associatedClock clock
set_interface_property export_sd associatedReset reset_sink
set_interface_property export_sd ENABLED true
set_interface_property export_sd EXPORT_OF ""
set_interface_property export_sd PORT_NAME_MAP ""
set_interface_property export_sd CMSIS_SVD_VARIABLES ""
set_interface_property export_sd SVD_ADDRESS_GROUP ""
add_interface reset_sink reset end
set_interface_property reset_sink associatedClock clock
set_interface_property reset_sink synchronousEdges DEASSERT
set_interface_property reset_sink ENABLED true
set_interface_property reset_sink EXPORT_OF ""
set_interface_property reset_sink PORT_NAME_MAP ""
set_interface_property reset_sink CMSIS_SVD_VARIABLES ""
set_interface_property reset_sink SVD_ADDRESS_GROUP ""
 
add_interface_port export_sd sd_clk export Output 1
add_interface_port export_sd sd_dat export Bidir 4
add_interface_port export_sd sd_cmd export Bidir 1
add_interface_port reset_sink rst_n reset_n Input 1
 
 
#
# connection point conduit_cmd
#
add_interface conduit_cmd conduit end
set_interface_property conduit_cmd associatedClock clock
set_interface_property conduit_cmd associatedReset reset_sink
set_interface_property conduit_cmd ENABLED true
set_interface_property conduit_cmd EXPORT_OF ""
set_interface_property conduit_cmd PORT_NAME_MAP ""
set_interface_property conduit_cmd CMSIS_SVD_VARIABLES ""
set_interface_property conduit_cmd SVD_ADDRESS_GROUP ""
 
add_interface_port conduit_cmd sd_cmd export Bidir 1
 
 
#
# connection point conduit_dat
#
add_interface conduit_dat conduit end
set_interface_property conduit_dat associatedClock clock
set_interface_property conduit_dat associatedReset reset_sink
set_interface_property conduit_dat ENABLED true
set_interface_property conduit_dat EXPORT_OF ""
set_interface_property conduit_dat PORT_NAME_MAP ""
set_interface_property conduit_dat CMSIS_SVD_VARIABLES ""
set_interface_property conduit_dat SVD_ADDRESS_GROUP ""
 
add_interface_port conduit_dat sd_dat export Bidir 4
 
 
#
# connection point conduit_clk
#
add_interface conduit_clk conduit end
set_interface_property conduit_clk associatedClock clock
set_interface_property conduit_clk associatedReset reset_sink
set_interface_property conduit_clk ENABLED true
set_interface_property conduit_clk EXPORT_OF ""
set_interface_property conduit_clk PORT_NAME_MAP ""
set_interface_property conduit_clk CMSIS_SVD_VARIABLES ""
set_interface_property conduit_clk SVD_ADDRESS_GROUP ""
 
add_interface_port conduit_clk sd_clk export Output 1
 
/ao486/trunk/rtl/soc/driver_sd/driver_sd.v
1,933 → 1,373
/*
* Copyright (c) 2014, Aleksander Osman
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
*
* * Redistributions of source code must retain the above copyright notice, this
* list of conditions and the following disclaimer.
*
* * Redistributions in binary form must reproduce the above copyright notice,
* this list of conditions and the following disclaimer in the documentation
* and/or other materials provided with the distribution.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
* This file is subject to the terms and conditions of the BSD License. See
* the file "LICENSE" in the main directory of this archive for more details.
*
* Copyright (C) 2014 Aleksander Osman
*/
 
module driver_sd(
input clk,
input rst_n,
input clk,
input rst_n,
//
input [1:0] avs_address,
output avs_waitrequest,
input avs_read,
output [31:0] avs_readdata,
input avs_write,
input [31:0] avs_writedata,
output reg [31:0] avm_address,
//
output [31:0] avm_address,
input avm_waitrequest,
output reg avm_read,
output avm_read,
input [31:0] avm_readdata,
input avm_readdatavalid,
output reg avm_write,
output reg [31:0] avm_writedata,
output avm_write,
output [31:0] avm_writedata,
output reg sd_clk,
inout sd_cmd,
inout [3:0] sd_dat
//
output reg sd_clk,
inout sd_cmd,
inout [3:0] sd_dat
);
 
//------------------------------------------------------------------------------
 
//------------------------------------------------------------------------------ Avalon master
 
reg data_read;
reg data_write;
reg [31:0] data_part_contents;
reg wait_for_readdatavalid;
 
always @(posedge clk or negedge rst_n) begin
if(rst_n == 1'b0) begin
avm_address <= 32'd0;
avm_read <= 1'b0;
avm_write <= 1'b0;
avm_writedata <= 32'b0;
data_read <= 1'b0;
data_write <= 1'b0;
data_part_contents <= 32'd0;
wait_for_readdatavalid <= 1'b0;
end
else if(data_state == S_DATA_READ_READY_PART && data_read == 1'b0) begin
if(avm_write && avm_waitrequest == 1'b0) begin
avm_write <= 1'b0;
data_read <= 1'b1;
end
else begin
avm_address <= avalon_address_base + { 23'b0, part_counter, 2'b0 };
avm_write <= 1'b1;
avm_writedata <= { data_part[7:0], data_part[15:8], data_part[23:16], data_part[31:24] };
end
end
else if(data_state == S_DATA_WRITE_READY_PART && data_write == 1'b0) begin
if(avm_read && avm_waitrequest == 1'b0) begin
avm_read <= 1'b0;
end
else if(wait_for_readdatavalid && avm_readdatavalid) begin
avm_read <= 1'b0;
wait_for_readdatavalid <= 1'b0;
data_part_contents <= { avm_readdata[7:0], avm_readdata[15:8], avm_readdata[23:16], avm_readdata[31:24] };
data_write <= 1'b1;
end
else begin
avm_address <= avalon_address_base + { 23'b0, part_counter, 2'b0 };
avm_read <= 1'b1;
wait_for_readdatavalid <= 1'b1;
end
end
else if(data_state != S_DATA_READ_READY_PART && data_state != S_DATA_WRITE_READY_PART) begin
data_read <= 1'b0;
data_write <= 1'b0;
end
if(rst_n == 1'b0) sd_clk <= 1'b0;
else if(write_stop_sd_clk || read_stop_sd_clk) sd_clk <= 1'b0;
else sd_clk <= ~(sd_clk);
end
 
//------------------------------------------------------------------------------ Avalon slave
//------------------------------------------------------------------------------
 
//read mutex
wire current_dat0;
 
assign avs_readdata = (avs_address == 2'd0)? {29'd0, status[2:0]} : { 29'd0, mutex };
wire wr_data_done;
wire wr_data_last_in_sector;
wire wr_error;
wire wr_finished_sector;
 
wire rd_data_done;
wire rd_data_last_in_sector;
wire [31:0] rd_data;
wire rd_error;
 
dat dat_inst(
.clk (clk),
.rst_n (rst_n),
reg [2:0] mutex;
always @(posedge clk or negedge rst_n) begin
if(rst_n == 1'b0) mutex <= 3'd0;
else if(mutex == 3'd0 && avs_address == 2'd1 && avs_read && ~(avs_waitrequest)) mutex <= 3'd1;
else if(mutex == 3'd0 && avs_address == 2'd2 && avs_read && ~(avs_waitrequest)) mutex <= 2'd2;
else if(mutex == 3'd0 && avs_address == 2'd3 && avs_read && ~(avs_waitrequest)) mutex <= 3'd3;
else if(mutex < 3'd4 && (status == STATUS_READ || status == STATUS_WRITE)) mutex <= 3'd4;
else if(status == STATUS_IDLE && status_last != STATUS_IDLE) mutex <= 3'd0;
end
//
.sd_clk_is_one (sd_clk), //input
//
.wr_async_data_ready (wr_async_data_ready), //input
.wr_async_data (wr_async_data), //input [31:0]
.wr_data_done (wr_data_done), //output
.wr_data_last_in_sector (wr_data_last_in_sector), //output
.wr_error (wr_error), //output
.wr_finished_sector (wr_finished_sector), //output
//
.rd_async_start (rd_async_start), //input
.rd_async_abort (rd_async_abort), //input
.rd_data_done (rd_data_done), //output
.rd_data_last_in_sector (rd_data_last_in_sector), //output
.rd_data (rd_data), //output [31:0]
.rd_error (rd_error), //output
//
.current_dat0 (current_dat0), //output
//
.sd_dat (sd_dat) //inout [3:0]
);
 
assign avs_waitrequest = control_state == S_CTRL_PRE_IDLE;
//------------------------------------------------------------------------------
 
// write only
reg [31:0] sd_address;
reg [31:0] sd_block_count;
reg [1:0] control;
reg [31:0] avalon_address_base;
wire reply_ready;
wire [135:0] reply_contents;
wire reply_error;
 
localparam [1:0] CONTROL_IDLE = 2'd0;
localparam [1:0] CONTROL_REINIT = 2'd1;
localparam [1:0] CONTROL_READ = 2'd2;
localparam [1:0] CONTROL_WRITE = 2'd3;
wire cmd_ready = (operation_write)? write_cmd_ready : (operation_read)? read_cmd_ready : (operation_init)? init_cmd_ready : 1'b0;
wire [5:0] cmd_index = (operation_write)? write_cmd_index : (operation_read)? read_cmd_index : (operation_init)? init_cmd_index : 6'b0;
wire [31:0] cmd_arg = (operation_write)? write_cmd_arg : (operation_read)? read_cmd_arg : (operation_init)? init_cmd_arg : 32'b0;
wire [7:0] cmd_resp_length = (operation_write)? write_cmd_resp_length : (operation_read)? read_cmd_resp_length : (operation_init)? init_cmd_resp_length : 8'b0;
wire cmd_resp_has_crc7 = (operation_write)? write_cmd_resp_has_crc7 : (operation_read)? read_cmd_resp_has_crc7 : (operation_init)? init_cmd_resp_has_crc7 : 1'b0;
 
always @(posedge clk or negedge rst_n) begin
if(rst_n == 1'b0) begin
avalon_address_base <= 32'd0;
sd_address <= 32'd0;
sd_block_count <= 32'd0;
control <= 2'd0;
end
else begin
if(control_state == S_CTRL_PRE_IDLE) begin
sd_block_count <= sd_block_count - 32'd1;
sd_address <= sd_address + 32'd1;
avalon_address_base <= avalon_address_base + 32'd512;
if(sd_block_count == 32'd1) control <= CONTROL_IDLE;
end
else if(avs_write) begin
if(avs_address == 2'd0) avalon_address_base <= avs_writedata;
else if(avs_address == 2'd1) sd_address <= avs_writedata;
else if(avs_address == 2'd2) sd_block_count <= avs_writedata;
else if(avs_address == 2'd3) control <= avs_writedata[1:0];
end
end
end
cmd cmd_inst(
.clk (clk),
.rst_n (rst_n),
//
.sd_clk_is_one (sd_clk), //input
//
.cmd_ready (cmd_ready), //input
.cmd_index (cmd_index), //input [5:0]
.cmd_arg (cmd_arg), //input [31:0]
.cmd_resp_length (cmd_resp_length), //input [7:0]
.cmd_resp_has_crc7 (cmd_resp_has_crc7), //input
//
.reply_ready (reply_ready), //output
.reply_contents (reply_contents), //output [135:0]
.reply_error (reply_error), //output
//
.sd_cmd (sd_cmd) //inout
);
 
//------------------------------------------------------------------------------ Control state machine
//------------------------------------------------------------------------------
 
reg [3:0] control_state;
reg [15:0] error_count;
reg [2:0] status;
reg [37:0] cmd_send_contents;
wire [31:0] read_data;
wire read_done;
 
reg start_cmd;
reg start_read;
reg start_write;
wire write_done;
 
reg [2:0] status_last;
always @(posedge clk or negedge rst_n) begin
if(rst_n == 1'b0) status_last <= STATUS_INIT;
else status_last <= status;
end
avalon_master avalon_master_inst(
.clk (clk),
.rst_n (rst_n),
//
.avm_address (avm_address), //output [31:0]
.avm_waitrequest (avm_waitrequest), //input
.avm_read (avm_read), //output
.avm_readdata (avm_readdata), //input [31:0]
.avm_readdatavalid (avm_readdatavalid), //input
.avm_write (avm_write), //output
.avm_writedata (avm_writedata), //output [31:0]
//
.avalon_address_base (avalon_address_base), //input [31:0]
//
.read_start (read_start), //input
.read_next (read_next), //input
.read_data (read_data), //output [31:0]
.read_done (read_done), //output
//
.write_start (write_start), //input
.write_next (write_next), //input
.write_data (write_data), //input [31:0]
.write_done (write_done) //output
);
 
`define CRC7_REVERSE crc7[0],crc7[1],crc7[2],crc7[3],crc7[4],crc7[5],crc7[6]
//------------------------------------------------------------------------------
 
localparam [3:0] S_CTRL_INIT = 4'd0;
localparam [3:0] S_CTRL_CMD0 = 4'd1;
localparam [3:0] S_CTRL_CMD8 = 4'd2;
localparam [3:0] S_CTRL_CMD55 = 4'd3;
localparam [3:0] S_CTRL_ACMD41 = 4'd4;
localparam [3:0] S_CTRL_CMD2 = 4'd5;
localparam [3:0] S_CTRL_CMD3 = 4'd6;
localparam [3:0] S_CTRL_CMD7 = 4'd7;
localparam [3:0] S_CTRL_PRE_IDLE = 4'd8;
localparam [3:0] S_CTRL_IDLE = 4'd9;
localparam [3:0] S_CTRL_CMD17_READ = 4'd10;
localparam [3:0] S_CTRL_CMD24_WRITE = 4'd11;
wire operation_write;
wire operation_read;
wire operation_init;
 
localparam [2:0] STATUS_INIT = 3'd0;
localparam [2:0] STATUS_INIT_ERROR = 3'd1;
localparam [2:0] STATUS_IDLE = 3'd2;
localparam [2:0] STATUS_READ = 3'd3;
localparam [2:0] STATUS_WRITE = 3'd4;
localparam [2:0] STATUS_ERROR = 3'd5;
always @(posedge clk or negedge rst_n) begin
if(rst_n == 1'b0) begin
control_state <= S_CTRL_INIT;
status <= STATUS_INIT;
cmd_send_contents <= 38'd0;
start_cmd <= 1'b0;
start_read <= 1'b0;
start_write <= 1'b0;
error_count <= 16'd0;
end
else if(control_state == S_CTRL_INIT && error_count == 16'd65535) begin
status <= STATUS_INIT_ERROR;
if(control == CONTROL_REINIT) begin
error_count <= 16'd0;
control_state <= S_CTRL_INIT;
end
end
else if(control_state == S_CTRL_INIT) begin
status <= STATUS_INIT;
if(cmd_state == S_CMD_IDLE && start_cmd == 1'b0) begin
start_cmd <= 1'b1;
//CMD0, no arguments
cmd_send_contents <= { 6'd0, 32'd0 };
control_state <= S_CTRL_CMD0;
end
end
else if(control_state == S_CTRL_CMD0) begin
if(cmd_state == S_CMD_REPLY_ERROR) begin
error_count <= error_count + 16'd1;
control_state <= S_CTRL_INIT;
end
else if(cmd_state == S_CMD_IDLE && start_cmd == 1'b0) begin
start_cmd <= 1'b1;
//CMD8, supply voltage, check pattern
cmd_send_contents <= { 6'd8, 20'd0, 4'b0001, 8'b10101010 };
control_state <= S_CTRL_CMD8;
end
else start_cmd <= 1'b0;
end
else if(control_state == S_CTRL_CMD8) begin
if(start_cmd == 1'b1) begin
start_cmd <= 1'b0;
end
else if(cmd_state == S_CMD_REPLY_ERROR ||
(cmd_state == S_CMD_IDLE && cmd_reply != { 1'b0, 1'b0, 6'd8, 20'd0, 4'b0001, 8'b10101010, `CRC7_REVERSE, 1'b1 })
) begin
error_count <= error_count + 16'd1;
control_state <= S_CTRL_INIT;
end
else if(cmd_state == S_CMD_IDLE) begin
start_cmd <= 1'b1;
//CMD55, RCA
cmd_send_contents <= { 6'd55, 16'd0, 16'd0};
control_state <= S_CTRL_CMD55;
end
end
else if(control_state == S_CTRL_CMD55) begin
if(start_cmd == 1'b1) begin
start_cmd <= 1'b0;
end
else if(cmd_state == S_CMD_REPLY_ERROR ||
(cmd_state == S_CMD_IDLE &&
(cmd_reply[47:40] != { 1'b0, 1'b0, 6'd55 } || cmd_reply[39:27] != 13'b0 || cmd_reply[24:21] != 4'b0 ||
cmd_reply[13] != 1'b1 || cmd_reply[11] != 1'b0 || cmd_reply[7:0] != { `CRC7_REVERSE, 1'b1 }
)
)
) begin
error_count <= error_count + 16'd1;
control_state <= S_CTRL_INIT;
end
else if(cmd_state == S_CMD_IDLE && start_cmd == 1'b0) begin
start_cmd <= 1'b1;
//ACMD41,
cmd_send_contents <= { 6'd41, //command index
1'b0, //reserved bit
1'b1, //host capacity support HCS(OCR[30])
6'b0, //reserved bits
24'b0001_0000_0000_0000_0000_0000 //VDD voltage window OCR[23:0]
};
control_state <= S_CTRL_ACMD41;
end
end
else if(control_state == S_CTRL_ACMD41) begin
if(start_cmd == 1'b1) begin
start_cmd <= 1'b0;
end
else if(cmd_state == S_CMD_REPLY_ERROR ||
(cmd_state == S_CMD_IDLE && (cmd_reply[47:40] != { 1'b0, 1'b0, 6'b111111 } ||
cmd_reply[39:38] != 2'b11 || cmd_reply[7:0] != {7'b1111111, 1'b1 })
)
) begin
if(error_count == 16'd65535) begin
control_state <= S_CTRL_INIT;
end
else begin
error_count <= error_count + 16'd1;
start_cmd <= 1'b1;
//CMD55, RCA
cmd_send_contents <= { 6'd55, 16'd0, 16'd0};
control_state <= S_CTRL_CMD55;
end
end
else if(cmd_state == S_CMD_IDLE && start_cmd == 1'b0) begin
start_cmd <= 1'b1;
//CMD2, no arguments
cmd_send_contents <= { 6'd2, 32'd0 };
control_state <= S_CTRL_CMD2;
end
end
else if(control_state == S_CTRL_CMD2) begin
if(start_cmd == 1'b1) begin
start_cmd <= 1'b0;
end
else if(cmd_state == S_CMD_REPLY_ERROR ||
(cmd_state == S_CMD_IDLE && cmd_reply[0] != 1'b1)
) begin
error_count <= error_count + 16'd1;
control_state <= S_CTRL_INIT;
end
else if(cmd_state == S_CMD_IDLE && start_cmd == 1'b0) begin
start_cmd <= 1'b1;
//CMD3, no arguments
cmd_send_contents <= { 6'd3, 32'd0 };
control_state <= S_CTRL_CMD3;
end
end
else if(control_state == S_CTRL_CMD3) begin
if(start_cmd == 1'b1) begin
start_cmd <= 1'b0;
end
else if(cmd_state == S_CMD_REPLY_ERROR ||
(cmd_state == S_CMD_IDLE &&
(cmd_reply[47:40] != { 1'b0, 1'b0, 6'd3 } ||
/*23:8= 23,22,19,12:0 from card status*/
cmd_reply[23:21] != 3'b0 || cmd_reply[13] != 1'b0 || cmd_reply[11] != 1'b0 ||
cmd_reply[7:0] != { `CRC7_REVERSE, 1'b1 }
)
)
) begin
error_count <= error_count + 16'd1;
control_state <= S_CTRL_INIT;
end
else if(cmd_state == S_CMD_IDLE && start_cmd == 1'b0) begin
start_cmd <= 1'b1;
//CMD7, no arguments
cmd_send_contents <= { 6'd7, //command index
cmd_reply[39:24], //RCA
16'd0 //stuff bits
};
control_state <= S_CTRL_CMD7;
end
end
else if(control_state == S_CTRL_CMD7) begin
if(start_cmd == 1'b1) begin
start_cmd <= 1'b0;
end
else if(cmd_state == S_CMD_REPLY_ERROR ||
(cmd_state == S_CMD_IDLE &&
(cmd_reply[47:40] != { 1'b0, 1'b0, 6'd7 } || cmd_reply[39:27] != 13'b0 || cmd_reply[24:21] != 4'b0 ||
cmd_reply[13] != 1'b0 || cmd_reply[11] != 1'b0 || cmd_reply[7:0] != { `CRC7_REVERSE, 1'b1 }
)
)
) begin
error_count <= error_count + 16'd1;
control_state <= S_CTRL_INIT;
end
else if(cmd_state == S_CMD_IDLE && start_cmd == 1'b0) begin
start_cmd <= 1'b0;
error_count <= 16'd0;
control_state <= S_CTRL_IDLE;
end
end
else if(control_state == S_CTRL_PRE_IDLE) begin
control_state <= S_CTRL_IDLE;
end
else if(control_state == S_CTRL_IDLE && error_count != 16'd0) begin
status <= STATUS_ERROR;
if(control == CONTROL_IDLE) begin
control_state <= S_CTRL_IDLE;
error_count <= 16'd0;
end
else if(control == CONTROL_REINIT) begin
control_state <= S_CTRL_INIT;
error_count <= 16'd0;
end
end
else if(control_state == S_CTRL_IDLE) begin
if(control == CONTROL_READ && sd_block_count != 32'd0) begin
status <= STATUS_READ;
start_cmd <= 1'b1;
start_read <= 1'b1;
//CMD17, sector address
cmd_send_contents <= { 6'd17, //command index
sd_address[31:0] //sector address
};
control_state <= S_CTRL_CMD17_READ;
end
else if(control == CONTROL_WRITE && sd_block_count != 32'd0) begin
status <= STATUS_WRITE;
start_cmd <= 1'b1;
start_write <= 1'b1;
//CMD24, sector address
cmd_send_contents <= { 6'd24, //command index
sd_address[31:0] //sector address
};
control_state <= S_CTRL_CMD24_WRITE;
end
else begin
status <= STATUS_IDLE;
end
end
else if(control_state == S_CTRL_CMD17_READ) begin
if(start_cmd == 1'b1) begin
start_cmd <= 1'b0;
end
else if(cmd_state == S_CMD_REPLY_ERROR ||
(cmd_state == S_CMD_IDLE &&
(cmd_reply[47:40] != { 1'b0, 1'b0, 6'd17 } || cmd_reply[39:27] != 13'b0 || cmd_reply[24:21] != 4'b0 ||
cmd_reply[13] != 1'b0 || cmd_reply[11] != 1'b0 || cmd_reply[7:0] != { `CRC7_REVERSE, 1'b1 }
)
)
) begin
error_count <= error_count + 16'd1;
control_state <= S_CTRL_IDLE;
end
else if(cmd_state == S_CMD_IDLE && start_cmd == 1'b0 && start_read == 1'b1) begin
start_read <= 1'b0;
end
else if(cmd_state == S_CMD_IDLE && start_cmd == 1'b0 && start_read == 1'b0 && data_state == S_DATA_READ_ERROR) begin
error_count <= error_count + 16'd1;
control_state <= S_CTRL_IDLE;
end
else if(cmd_state == S_CMD_IDLE && start_cmd == 1'b0 && start_read == 1'b0 && data_state == S_DATA_IDLE) begin
error_count <= 16'd0;
control_state <= S_CTRL_PRE_IDLE;
end
end
else if(control_state == S_CTRL_CMD24_WRITE) begin
if(start_cmd == 1'b1) begin
start_cmd <= 1'b0;
end
else if(cmd_state == S_CMD_REPLY_ERROR ||
(cmd_state == S_CMD_IDLE &&
(cmd_reply[47:40] != { 1'b0, 1'b0, 6'd24 } || cmd_reply[39:27] != 13'b0 || cmd_reply[24:21] != 4'b0 ||
cmd_reply[13] != 1'b0 || cmd_reply[11] != 1'b0 || cmd_reply[7:0] != { `CRC7_REVERSE, 1'b1 }
)
)
) begin
error_count <= error_count + 16'd1;
control_state <= S_CTRL_IDLE;
end
else if(cmd_state == S_CMD_IDLE && start_cmd == 1'b0 && start_write == 1'b1) begin
start_write <= 1'b0;
end
else if(cmd_state == S_CMD_IDLE && start_cmd == 1'b0 && start_write == 1'b0 && data_state == S_DATA_WRITE_ERROR) begin
error_count <= error_count + 16'd1;
control_state <= S_CTRL_IDLE;
end
else if(cmd_state == S_CMD_IDLE && start_cmd == 1'b0 && start_write == 1'b0 && data_state == S_DATA_IDLE) begin
error_count <= 16'd0;
control_state <= S_CTRL_PRE_IDLE;
end
end
end
wire operation_sector_last;
 
//------------------------------------------------------------------------------ SD interface
wire [31:0] sd_address;
wire [31:0] avalon_address_base;
 
reg sd_cmd_reg = 1'b1;
reg sd_dat_reg = 1'b1;
wire operation_sector_update = (operation_write && write_operation_sector_update) || (operation_read && read_operation_sector_update);
wire operation_finished_ok = (operation_write && write_operation_finished_ok) || (operation_read && read_operation_finished_ok) || (operation_init && init_operation_finished_ok);
wire operation_finished_with_error = (operation_write && write_operation_finished_with_error) || (operation_read && read_operation_finished_with_error) || (operation_init && init_operation_finished_with_error);
 
assign sd_cmd = (sd_cmd_enable == 1'b1) ? sd_cmd_reg : 1'bZ;
assign sd_dat[0] = (sd_data_enable == 1'b1) ? sd_dat_reg : 1'bZ;
avalon_slave avalon_slave_inst(
.clk (clk),
.rst_n (rst_n),
//
.avs_address (avs_address), //input [1:0]
.avs_read (avs_read), //input
.avs_readdata (avs_readdata), //output [31:0]
.avs_write (avs_write), //input
.avs_writedata (avs_writedata), //input [31:0]
//
.operation_init (operation_init), //output
.operation_read (operation_read), //output
.operation_write (operation_write), //output
.operation_sector_update (operation_sector_update), //input
.operation_sector_last (operation_sector_last), //output
 
assign sd_dat[3:1] = 3'bZ;
.operation_finished_ok (operation_finished_ok), //input
.operation_finished_with_error (operation_finished_with_error), //input
//
.sd_address (sd_address), //output [31:0]
.avalon_address_base (avalon_address_base) //output [31:0]
);
 
//CID register not interpreted: CRC7 not checked, always accepted
//------------------------------------------------------------------------------
 
//---------------------------------------------------- SD data
wire init_operation_finished_ok;
wire init_operation_finished_with_error;
 
reg sd_data_enable;
reg [3:0] data_state;
reg [23:0] data_counter;
reg [6:0] part_counter;
reg [15:0] crc16;
reg [31:0] data_part;
wire init_cmd_ready;
wire [5:0] init_cmd_index;
wire [31:0] init_cmd_arg;
wire [7:0] init_cmd_resp_length;
wire init_cmd_resp_has_crc7;
 
reg clk_data_ena;
reg clk_master_ena;
card_init card_init_inst(
.clk (clk),
.rst_n (rst_n),
//
.operation_init (operation_init), //input
.operation_finished_ok (init_operation_finished_ok), //output
.operation_finished_with_error (init_operation_finished_with_error), //output
//
.cmd_ready (init_cmd_ready), //output
.cmd_index (init_cmd_index), //output [5:0]
.cmd_arg (init_cmd_arg), //output [31:0]
.cmd_resp_length (init_cmd_resp_length), //output [7:0]
.cmd_resp_has_crc7 (init_cmd_resp_has_crc7), //output
 
.reply_ready (reply_ready), //input
.reply_contents (reply_contents), //input [135:0]
.reply_error (reply_error), //input
//
.current_dat0 (current_dat0) //input
);
 
localparam [3:0] S_DATA_IDLE = 4'd0;
localparam [3:0] S_DATA_READ_START_BIT = 4'd1;
localparam [3:0] S_DATA_READ_CONTENTS = 4'd2;
localparam [3:0] S_DATA_READ_READY_PART = 4'd3;
localparam [3:0] S_DATA_READ_READY_PART_CONTINUE = 4'd4;
localparam [3:0] S_DATA_READ_CRC16_END_BIT = 4'd5;
localparam [3:0] S_DATA_READ_ERROR = 4'd6;
localparam [3:0] S_DATA_WRITE_START_BIT = 4'd7;
localparam [3:0] S_DATA_WRITE_READY_PART = 4'd8;
localparam [3:0] S_DATA_WRITE_CONTENTS = 4'd9;
localparam [3:0] S_DATA_WRITE_CRC16_END_BIT = 4'd10;
localparam [3:0] S_DATA_WRITE_CRC_STATUS_START = 4'd11;
localparam [3:0] S_DATA_WRITE_CRC_STATUS_CONTENTS_END_BIT = 4'd12;
localparam [3:0] S_DATA_WRITE_BUSY_START = 4'd13;
localparam [3:0] S_DATA_WRITE_BUSY_WAIT = 4'd14;
localparam [3:0] S_DATA_WRITE_ERROR = 4'd15;
//------------------------------------------------------------------------------
 
always @(posedge clk or negedge rst_n) begin
if(rst_n == 1'b0) begin
sd_data_enable <= 1'b0;
data_state <= S_DATA_IDLE;
data_counter <= 24'd0;
part_counter <= 7'd0;
crc16 <= 16'd0;
data_part <= 32'd0;
clk_data_ena <= 1'b0;
clk_master_ena <= 1'b1;
sd_dat_reg <= 1'b1;
end
else if(data_state == S_DATA_IDLE) begin
//do not wait for read command and reply
if(start_read == 1'b1) begin
data_state <= S_DATA_READ_START_BIT;
end
//wait for write command and reply
else if(start_write == 1'b1 && start_cmd == 1'b0 && cmd_state == S_CMD_IDLE) begin
data_state <= S_DATA_WRITE_START_BIT;
end
end
else if(clk_counter == 2'd0) begin
//wait for response and data simultaneously (data read)
if(data_state == S_DATA_READ_START_BIT) begin
clk_data_ena <= 1'b1;
if(sd_dat[0] == 1'b0) begin
crc16 <= { sd_dat[0] ^ crc16[0], crc16[15:12], sd_dat[0] ^ crc16[11] ^ crc16[0], crc16[10:5],
sd_dat[0] ^ crc16[4] ^ crc16[0], crc16[3:1] };
data_state <= S_DATA_READ_CONTENTS;
data_counter <= 24'd0;
end
else if(data_counter == 24'd65535) begin
data_state <= S_DATA_READ_ERROR;
data_counter <= 24'd0;
end
else data_counter <= data_counter + 24'd1;
end
else if(data_state == S_DATA_READ_CONTENTS) begin
crc16 <= { sd_dat[0] ^ crc16[0], crc16[15:12], sd_dat[0] ^ crc16[11] ^ crc16[0],
crc16[10:5], sd_dat[0] ^ crc16[4] ^ crc16[0], crc16[3:1] };
data_part <= { data_part[30:0], sd_dat[0] };
if(data_counter == 24'd30) begin
clk_master_ena <= 1'b0;
data_counter <= data_counter + 24'd1;
end
else if(data_counter == 24'd31) begin
data_state <= S_DATA_READ_READY_PART;
data_counter <= 24'd0;
end
else data_counter <= data_counter + 24'd1;
end
else if(data_state == S_DATA_READ_READY_PART) begin
if(data_read == 1'b1) begin
clk_master_ena <= 1'b1;
data_state <= S_DATA_READ_READY_PART_CONTINUE;
end
end
else if(data_state == S_DATA_READ_READY_PART_CONTINUE) begin
if(part_counter == 7'd127) begin
data_state <= S_DATA_READ_CRC16_END_BIT;
part_counter <= 7'd0;
end
else begin
data_state <= S_DATA_READ_CONTENTS;
part_counter <= part_counter + 7'd1;
end
end
else if(data_state == S_DATA_READ_CRC16_END_BIT) begin
data_part <= { sd_dat[0], data_part[31:1] };
if(data_counter == 24'd16) begin
if(data_part[31:16] != crc16[15:0] || sd_dat[0] != 1'b1) begin
data_state <= S_DATA_READ_ERROR;
data_counter <= 24'd0;
end
else begin
clk_data_ena <= 1'b0;
data_state <= S_DATA_IDLE;
data_counter <= 24'd0;
crc16 <= 16'd0;
end
end
else data_counter <= data_counter + 24'd1;
end
else if(data_state == S_DATA_READ_ERROR) begin
clk_data_ena <= 1'b0;
data_state <= S_DATA_IDLE;
data_counter <= 24'd0;
crc16 <= 16'd0;
end
//send data on data line, wait for crc status, wait while busy on data line (data write)
else if(data_state == S_DATA_WRITE_START_BIT) begin
sd_dat_reg <= 1'b0;
crc16 <= { 1'b0 ^ crc16[0], crc16[15:12], 1'b0 ^ crc16[11] ^ crc16[0], crc16[10:5],
1'b0 ^ crc16[4] ^ crc16[0], crc16[3:1] };
sd_data_enable <= 1'b1;
clk_data_ena <= 1'b1;
data_counter <= 24'd0;
data_state <= S_DATA_WRITE_READY_PART;
end
else if(data_state == S_DATA_WRITE_READY_PART) begin
if(data_write == 1'b1) begin
clk_data_ena <= 1'b1;
data_state <= S_DATA_WRITE_CONTENTS;
data_part <= data_part_contents;
end
else begin
clk_data_ena <= 1'b0;
end
end
else if(data_state == S_DATA_WRITE_CONTENTS) begin
sd_dat_reg <= data_part[31];
crc16 <= { data_part[31] ^ crc16[0], crc16[15:12], data_part[31] ^ crc16[11] ^ crc16[0], crc16[10:5],
data_part[31] ^ crc16[4] ^ crc16[0], crc16[3:1] };
data_part <= { data_part[30:0], 1'b0 };
if(data_counter == 24'd31) begin
data_counter <= 24'd0;
if(part_counter == 7'd127) begin
part_counter <= 7'd0;
data_state <= S_DATA_WRITE_CRC16_END_BIT;
end
else begin
clk_data_ena <= 1'b0;
part_counter <= part_counter + 7'd1;
data_state <= S_DATA_WRITE_READY_PART;
end
end
else data_counter <= data_counter + 24'd1;
end
else if(data_state == S_DATA_WRITE_CRC16_END_BIT) begin
sd_dat_reg <= crc16[0];
if(data_counter == 24'd16) begin
data_counter <= 24'd0;
crc16 <= 16'd0;
data_state <= S_DATA_WRITE_CRC_STATUS_START;
end
else begin
crc16 <= { 1'b1, crc16[15:1] };
data_counter <= data_counter + 24'd1;
end
end
else if(data_state == S_DATA_WRITE_CRC_STATUS_START) begin
sd_data_enable <= 1'b0;
if(sd_dat[0] == 1'b0) begin
data_state <= S_DATA_WRITE_CRC_STATUS_CONTENTS_END_BIT;
data_counter <= 24'b0;
end
else if(data_counter == 24'd65535) begin
data_state <= S_DATA_WRITE_ERROR;
data_counter <= 24'b0;
end
else data_counter <= data_counter + 24'd1;
end
else if(data_state == S_DATA_WRITE_CRC_STATUS_CONTENTS_END_BIT) begin
data_part <= { data_part[30:0], sd_dat[0] };
if(data_counter == 24'd3) begin
data_state <= S_DATA_WRITE_BUSY_START;
data_counter <= 24'b0;
end
else data_counter <= data_counter + 24'd1;
end
else if(data_state == S_DATA_WRITE_BUSY_START) begin
if(sd_dat[0] == 1'b0) begin
data_state <= S_DATA_WRITE_BUSY_WAIT;
data_counter <= 24'b0;
end
else if(data_counter == 24'd65535) begin
data_state <= S_DATA_WRITE_ERROR;
data_counter <= 24'b0;
end
else data_counter <= data_counter + 24'd1;
end
else if(data_state == S_DATA_WRITE_BUSY_WAIT) begin
if(sd_dat[0] == 1'b1 && data_part[3:0] != 4'b0101) begin
data_state <= S_DATA_WRITE_ERROR;
data_counter <= 24'd0;
end
else if(sd_dat[0] == 1'b1) begin
clk_data_ena <= 1'b0;
data_state <= S_DATA_IDLE;
data_counter <= 24'd0;
end
else if(data_counter == 24'hFFFFFF) begin
data_state <= S_DATA_WRITE_ERROR;
data_counter <= 24'd0;
end
else data_counter <= data_counter + 24'd1;
end
else if(data_state == S_DATA_WRITE_ERROR) begin
clk_data_ena <= 1'b0;
data_state <= S_DATA_IDLE;
data_counter <= 24'd0;
end
end
end
wire read_operation_sector_update;
wire read_operation_finished_ok;
wire read_operation_finished_with_error;
 
//------------------------------------------------------------------------------ SD command
wire rd_async_start;
wire rd_async_abort;
 
reg sd_cmd_enable;
reg [37:0] cmd_send;
reg [47:0] cmd_reply;
reg [3:0] cmd_state;
reg [7:0] cmd_counter;
reg [6:0] crc7;
reg clk_cmd_ena;
wire read_stop_sd_clk;
 
localparam [3:0] S_CMD_IDLE = 4'd0;
localparam [3:0] S_CMD_SEND_START_ONES = 4'd1;
localparam [3:0] S_CMD_SEND_START_BIT = 4'd2;
localparam [3:0] S_CMD_SEND_START_HOST = 4'd3;
localparam [3:0] S_CMD_SEND_CONTENTS = 4'd4;
localparam [3:0] S_CMD_SEND_CRC7 = 4'd5;
localparam [3:0] S_CMD_SEND_END_BIT = 4'd6;
localparam [3:0] S_CMD_SEND_END_ONES = 4'd7;
localparam [3:0] S_CMD_REPLY_START_BIT = 4'd8;
localparam [3:0] S_CMD_REPLY_CONTENTS = 4'd9;
localparam [3:0] S_CMD_REPLY_CRC7_END_BIT = 4'd10;
localparam [3:0] S_CMD_REPLY_FINISH_ONES = 4'd11;
localparam [3:0] S_CMD_REPLY_ERROR = 4'd12;
wire read_cmd_ready;
wire [5:0] read_cmd_index;
wire [31:0] read_cmd_arg;
wire [7:0] read_cmd_resp_length;
wire read_cmd_resp_has_crc7;
 
always @(posedge clk or negedge rst_n) begin
if(rst_n == 1'b0) begin
sd_cmd_enable <= 1'b0;
cmd_send <= 38'd0;
cmd_reply <= 48'd0;
cmd_state <= S_CMD_IDLE;
cmd_counter <= 8'd0;
crc7 <= 7'd0;
clk_cmd_ena <= 1'b0;
sd_cmd_reg <= 1'b1;
end
else if(cmd_state == S_CMD_IDLE) begin
if(start_cmd == 1'b1) begin
cmd_state <= S_CMD_SEND_START_ONES;
end
end
else if(clk_counter == 2'd0 && clk_master_ena == 1'b1) begin
//send command
if(cmd_state == S_CMD_SEND_START_ONES) begin
sd_cmd_enable <= 1'b1;
sd_cmd_reg <= 1'b1;
clk_cmd_ena <= 1'b1;
crc7 <= 7'd0;
if(cmd_counter == 8'd7) begin
cmd_state <= S_CMD_SEND_START_BIT;
cmd_counter <= 8'd0;
end
else cmd_counter <= cmd_counter + 8'd1;
end
else if(cmd_state == S_CMD_SEND_START_BIT) begin
sd_cmd_reg <= 1'b0;
crc7 <= { 1'b0 ^ crc7[0], crc7[6:5], 1'b0 ^ crc7[4] ^ crc7[0], crc7[3:1] };
cmd_state <= S_CMD_SEND_START_HOST;
end
else if(cmd_state == S_CMD_SEND_START_HOST) begin
sd_cmd_reg <= 1'b1;
crc7 <= { 1'b1 ^ crc7[0], crc7[6:5], 1'b1 ^ crc7[4] ^ crc7[0], crc7[3:1] };
cmd_send <= cmd_send_contents;
cmd_state <= S_CMD_SEND_CONTENTS;
end
else if(cmd_state == S_CMD_SEND_CONTENTS) begin
sd_cmd_reg <= cmd_send[37];
crc7 <= { cmd_send[37] ^ crc7[0], crc7[6:5], cmd_send[37] ^ crc7[4] ^ crc7[0], crc7[3:1] };
cmd_send <= { cmd_send[36:0], 1'b0 };
if(cmd_counter == 8'd37) begin
cmd_state <= S_CMD_SEND_CRC7;
cmd_counter <= 8'd0;
end
else cmd_counter <= cmd_counter + 8'd1;
end
else if(cmd_state == S_CMD_SEND_CRC7) begin
sd_cmd_reg <= crc7[0];
crc7 <= { 1'b0, crc7[6:1] };
if(cmd_counter == 8'd6) begin
cmd_state <= S_CMD_SEND_END_BIT;
cmd_counter <= 8'd0;
end
else cmd_counter <= cmd_counter + 8'd1;
end
else if(cmd_state == S_CMD_SEND_END_BIT) begin
sd_cmd_reg <= 1'b1;
// if CMD0: send ones
if(control_state == S_CTRL_CMD0) begin
cmd_state <= S_CMD_SEND_END_ONES;
end
else begin
crc7 <= 7'd0;
cmd_state <= S_CMD_REPLY_START_BIT;
end
end
else if(cmd_state == S_CMD_SEND_END_ONES) begin
sd_cmd_enable <= 1'b0;
sd_cmd_reg <= 1'b1;
if(cmd_counter == 8'd7) begin
clk_cmd_ena <= 1'b0;
cmd_state <= S_CMD_IDLE;
cmd_counter <= 8'd0;
end
else cmd_counter <= cmd_counter + 8'd1;
end
//wait for response: 48-bits with CRC7
//wait for response: 48-bits without CRC7
//wait for response: 136-bits (CMD2/R2)
//wait for response and busy on data line simultaneously: (CMD7/R1b)
else if(cmd_state == S_CMD_REPLY_START_BIT) begin
sd_cmd_enable <= 1'b0;
if(sd_cmd == 1'b0) begin
crc7 <= { sd_cmd ^ crc7[0], crc7[6:5], sd_cmd ^ crc7[4] ^ crc7[0], crc7[3:1] };
cmd_reply <= { cmd_reply[46:0], sd_cmd };
cmd_state <= S_CMD_REPLY_CONTENTS;
cmd_counter <= 8'd0;
end
else if(cmd_counter == 8'd255) begin
crc7 <= 7'd0;
cmd_state <= S_CMD_REPLY_ERROR;
cmd_counter <= 8'd0;
end
else cmd_counter <= cmd_counter + 8'd1;
end
else if(cmd_state == S_CMD_REPLY_CONTENTS) begin
crc7 <= { sd_cmd ^ crc7[0], crc7[6:5], sd_cmd ^ crc7[4] ^ crc7[0], crc7[3:1] };
cmd_reply <= { cmd_reply[46:0], sd_cmd };
if( (control_state != S_CTRL_CMD2 && cmd_counter == 8'd38) ||
(control_state == S_CTRL_CMD2 && cmd_counter == 8'd126)
) begin
cmd_state <= S_CMD_REPLY_CRC7_END_BIT;
cmd_counter <= 8'd0;
end
else cmd_counter <= cmd_counter + 8'd1;
end
else if(cmd_state == S_CMD_REPLY_CRC7_END_BIT) begin
cmd_reply <= { cmd_reply[46:0], sd_cmd };
if(cmd_counter == 8'd7) begin
cmd_state <= S_CMD_REPLY_FINISH_ONES;
cmd_counter <= 8'd0;
end
else cmd_counter <= cmd_counter + 8'd1;
end
//at least 2 clock cycles required for data write
else if(cmd_state == S_CMD_REPLY_FINISH_ONES) begin
//check is sd_dat[0] busy for CMD7
if(cmd_counter >= 8'd7 && (control_state != S_CTRL_CMD7 || sd_dat[0] == 1'b1)) begin
clk_cmd_ena <= 1'b0;
cmd_state <= S_CMD_IDLE;
cmd_counter <= 8'd0;
end
else if(cmd_counter == 8'd255) begin
cmd_state <= S_CMD_REPLY_ERROR;
cmd_counter <= 8'd0;
end
else cmd_counter <= cmd_counter + 8'd1;
end
else if(cmd_state == S_CMD_REPLY_ERROR) begin
clk_cmd_ena <= 1'b0;
cmd_state <= S_CMD_IDLE;
cmd_counter <= 8'd0;
end
end
end
wire write_start;
wire write_next;
wire [31:0] write_data;
 
//------------------------------------------------------------------------------ SD clock
card_read card_read_inst(
.clk (clk),
.rst_n (rst_n),
//
.operation_read (operation_read), //input
.operation_sector_last (operation_sector_last), //input
.operation_sector_update (read_operation_sector_update), //output
.operation_finished_ok (read_operation_finished_ok), //output
.operation_finished_with_error (read_operation_finished_with_error), //output
//
.cmd_ready (read_cmd_ready), //output
.cmd_index (read_cmd_index), //output [5:0]
.cmd_arg (read_cmd_arg), //output [31:0]
.cmd_resp_length (read_cmd_resp_length), //output [7:0]
.cmd_resp_has_crc7 (read_cmd_resp_has_crc7), //output
.reply_ready (reply_ready), //input
.reply_contents (reply_contents), //input [135:0]
.reply_error (reply_error), //input
//
.write_start (write_start), //output
.write_next (write_next), //output
.write_data (write_data), //output [31:0]
.write_done (write_done), //input
//
.rd_async_start (rd_async_start), //output
.rd_async_abort (rd_async_abort), //output
.rd_data_done (rd_data_done), //input
.rd_data_last_in_sector (rd_data_last_in_sector), //input
.rd_data (rd_data), //input [31:0]
.rd_error (rd_error), //input
//
.sd_address (sd_address), //input [31:0]
//
.current_dat0 (current_dat0), //input
//
.stop_sd_clk (read_stop_sd_clk) //output
);
 
reg [1:0] clk_counter;
//------------------------------------------------------------------------------
 
always @(posedge clk or negedge rst_n) begin
if(rst_n == 1'b0) begin
sd_clk <= 1'b0;
clk_counter <= 2'd0;
end
else if(clk_counter == 2'd0) begin
if(clk_master_ena == 1'b1 && (clk_cmd_ena == 1'b1 || clk_data_ena == 1'b1)) begin
clk_counter <= clk_counter + 2'd1;
end
end
else if(clk_counter == 2'd1) begin
sd_clk <= 1'b1;
clk_counter <= clk_counter + 2'd1;
end
else if(clk_counter == 2'd2) begin
clk_counter <= clk_counter + 2'd1;
end
else if(clk_counter == 2'd3) begin
sd_clk <= 1'b0;
clk_counter <= clk_counter + 2'd1;
end
end
wire write_operation_sector_update;
wire write_operation_finished_ok;
wire write_operation_finished_with_error;
 
wire read_start;
wire read_next;
 
wire write_stop_sd_clk;
 
wire write_cmd_ready;
wire [5:0] write_cmd_index;
wire [31:0] write_cmd_arg;
wire [7:0] write_cmd_resp_length;
wire write_cmd_resp_has_crc7;
 
wire wr_async_data_ready;
wire [31:0] wr_async_data;
 
card_write card_write_inst(
.clk (clk),
.rst_n (rst_n),
//
.operation_write (operation_write), //input
.operation_sector_last (operation_sector_last), //input
.operation_sector_update (write_operation_sector_update), //output
.operation_finished_ok (write_operation_finished_ok), //output
.operation_finished_with_error (write_operation_finished_with_error), //output
//
.cmd_ready (write_cmd_ready), //output
.cmd_index (write_cmd_index), //output [5:0]
.cmd_arg (write_cmd_arg), //output [31:0]
.cmd_resp_length (write_cmd_resp_length), //output [7:0]
.cmd_resp_has_crc7 (write_cmd_resp_has_crc7), //output
.reply_ready (reply_ready), //input
.reply_contents (reply_contents), //input [135:0]
.reply_error (reply_error), //input
//
.read_start (read_start), //output
.read_next (read_next), //output
.read_data (read_data), //input [31:0]
.read_done (read_done), //input
//
.wr_async_data_ready (wr_async_data_ready), //output
.wr_async_data (wr_async_data), //output [31:0]
.wr_data_done (wr_data_done), //input
.wr_data_last_in_sector (wr_data_last_in_sector), //input
.wr_error (wr_error), //input
.wr_finished_sector (wr_finished_sector), //input
//
.sd_address (sd_address), //input [31:0]
//
.current_dat0 (current_dat0), //input
//
.stop_sd_clk (write_stop_sd_clk) //output
);
 
//------------------------------------------------------------------------------
 
endmodule
 
/ao486/trunk/rtl/soc/ps2/ps2.v
158,7 → 158,7
 
reg disable_mouse;
always @(posedge clk or negedge rst_n) begin
if(rst_n == 1'b0) disable_mouse <= 1'b1;
if(rst_n == 1'b0) disable_mouse <= 1'b0;
else if(cmd_write_command_byte) disable_mouse <= io_writedata[5];
else if(cmd_disable_mouse) disable_mouse <= 1'b1;
else if(cmd_enable_mouse) disable_mouse <= 1'b0;
167,7 → 167,7
 
reg disable_mouse_visible;
always @(posedge clk or negedge rst_n) begin
if(rst_n == 1'b0) disable_mouse_visible <= 1'b1;
if(rst_n == 1'b0) disable_mouse_visible <= 1'b0;
else if(cmd_write_command_byte) disable_mouse_visible <= io_writedata[5];
else if(cmd_disable_mouse) disable_mouse_visible <= 1'b1;
else if(cmd_enable_mouse) disable_mouse_visible <= 1'b0;
/ao486/trunk/rtl/soc/soc.v
140,9 → 140,9
.export_sound_dat (AUD_DACDAT),
.export_sound_lr (AUD_DACLRCK),
.export_sd_clk (SD_CLK),
.export_sd_dat (SD_DAT),
.export_sd_cmd (SD_CMD),
.sd_clk_export (SD_CLK),
.sd_dat_export (SD_DAT),
.sd_cmd_export (SD_CMD),
.export_ps2_out_port_a20_enable (ps2_a20_enable),
.export_ps2_out_port_reset_n (ps2_reset_n),
/ao486/trunk/rtl/soc/pic/pic_hw.tcl
1,18 → 1,18
# TCL File Generated by Component Editor 13.1
# Fri Jan 17 22:12:28 CET 2014
# TCL File Generated by Component Editor 14.0
# Mon Aug 18 22:49:43 CEST 2014
# DO NOT MODIFY
 
 
#
# pic "pic" v1.0
# 2014.01.17.22:12:28
# 2014.08.18.22:49:43
#
#
 
#
# request TCL package from ACDS 13.1
# request TCL package from ACDS 14.0
#
package require -exact qsys 13.1
package require -exact qsys 14.0
 
 
#
28,9 → 28,9
set_module_property DISPLAY_NAME pic
set_module_property INSTANTIATE_IN_SYSTEM_MODULE true
set_module_property EDITABLE true
set_module_property ANALYZE_HDL AUTO
set_module_property REPORT_TO_TALKBACK false
set_module_property ALLOW_GREYBOX_GENERATION false
set_module_property REPORT_HIERARCHY false
 
 
#
39,6 → 39,7
add_fileset QUARTUS_SYNTH QUARTUS_SYNTH "" ""
set_fileset_property QUARTUS_SYNTH TOP_LEVEL pic
set_fileset_property QUARTUS_SYNTH ENABLE_RELATIVE_INCLUDE_PATHS false
set_fileset_property QUARTUS_SYNTH ENABLE_FILE_OVERWRITE_MODE false
add_fileset_file pic.v VERILOG PATH pic.v TOP_LEVEL_FILE
 
 
80,6 → 81,7
set_interface_property master holdTime 0
set_interface_property master linewrapBursts false
set_interface_property master maximumPendingReadTransactions 0
set_interface_property master maximumPendingWriteTransactions 0
set_interface_property master readLatency 0
set_interface_property master readWaitTime 1
set_interface_property master setupTime 0
116,6 → 118,7
set_interface_property slave holdTime 0
set_interface_property slave linewrapBursts false
set_interface_property slave maximumPendingReadTransactions 0
set_interface_property slave maximumPendingWriteTransactions 0
set_interface_property slave readLatency 0
set_interface_property slave readWaitTime 1
set_interface_property slave setupTime 0
158,7 → 161,7
#
add_interface conduit_interrupt conduit end
set_interface_property conduit_interrupt associatedClock clock
set_interface_property conduit_interrupt associatedReset reset_sink
set_interface_property conduit_interrupt associatedReset ""
set_interface_property conduit_interrupt ENABLED true
set_interface_property conduit_interrupt EXPORT_OF ""
set_interface_property conduit_interrupt PORT_NAME_MAP ""
165,9 → 168,9
set_interface_property conduit_interrupt CMSIS_SVD_VARIABLES ""
set_interface_property conduit_interrupt SVD_ADDRESS_GROUP ""
 
add_interface_port conduit_interrupt interrupt_do export Output 1
add_interface_port conduit_interrupt interrupt_vector export Output 8
add_interface_port conduit_interrupt interrupt_done export Input 1
add_interface_port conduit_interrupt interrupt_vector interrupt_vector Output 8
add_interface_port conduit_interrupt interrupt_done interrupt_done Input 1
add_interface_port conduit_interrupt interrupt_do interrupt_do Output 1
 
 
#
/ao486/trunk/syn/soc/.qsys_edit/preferences.xml Cannot display: file marked as a binary type. svn:mime-type = application/xml
/ao486/trunk/syn/soc/.qsys_edit/system.xml Cannot display: file marked as a binary type. svn:mime-type = application/xml
/ao486/trunk/syn/soc/.qsys_edit/filters.xml Cannot display: file marked as a binary type. svn:mime-type = application/xml
/ao486/trunk/syn/soc/.qsys_edit/layout.xml Cannot display: file marked as a binary type. svn:mime-type = application/xml
/ao486/trunk/syn/soc/system.qsys Cannot display: file marked as a binary type. svn:mime-type = application/xml
/ao486/trunk/syn/soc/components.ipx Cannot display: file marked as a binary type. svn:mime-type = application/xml
/ao486/trunk/syn/soc/soc.qws Cannot display: file marked as a binary type. svn:mime-type = application/octet-stream
/ao486/trunk/syn/soc/system.sopcinfo Cannot display: file marked as a binary type. svn:mime-type = application/xml
/ao486/trunk/syn/soc/firmware/exe/main.cpp
949,7 → 949,7
runtime_menu();
//release reset - start executing
//reset cycle - start executing
IOWR(PIO_OUTPUT_BASE, 0, 0x00);
while(true) {
/ao486/trunk/syn/soc/firmware/exe_bsp/summary.html
22,10 → 22,10
<td width="20%" bgcolor="#77BBFF">BSP Version:</td><td>default</td>
</tr>
<tr mode="wrap">
<td width="20%" bgcolor="#77BBFF">BSP Generated On:</td><td>Mar 30, 2014 5:20:07 PM</td>
<td width="20%" bgcolor="#77BBFF">BSP Generated On:</td><td>Aug 19, 2014 8:37:51 PM</td>
</tr>
<tr mode="wrap">
<td width="20%" bgcolor="#77BBFF">BSP Generated Timestamp:</td><td>1396192807247</td>
<td width="20%" bgcolor="#77BBFF">BSP Generated Timestamp:</td><td>1408473471717</td>
</tr>
<tr mode="wrap">
<td width="20%" bgcolor="#77BBFF">BSP Generated Location:</td><td>/home/alek/aktualne/github/ao486/syn/soc/firmware/exe_bsp</td>
189,7 → 189,7
<td width="20%">Description:</td><td>Build a custom version of newlib with the specified space-separated compiler flags.</td>
</tr>
<tr mode="wrap">
<td width="20%">Restrictions:</td><td>The custom newlib build will be placed in the &amp;lt;bsp root&gt;/newlib directory, and will be used only for applications that utilize this BSP.</td>
<td width="20%">Restrictions:</td><td>The custom newlib build will be placed in the &lt;bsp root&gt;/newlib directory, and will be used only for applications that utilize this BSP.</td>
</tr>
</table>
<br>
429,7 → 429,7
<td width="20%">Destination:</td><td>public_mk_define</td>
</tr>
<tr mode="wrap">
<td width="20%">Description:</td><td>Turns on HAL runtime stack checking feature. Enabling this setting causes additional code to be placed into each subroutine call to generate an exception if a stack collision occurs with the heap or statically allocated data. If true, adds -DALT_STACK_CHECK and -fstack-check to ALT_CPPFLAGS in public.mk.</td>
<td width="20%">Description:</td><td>Turns on HAL runtime stack checking feature. Enabling this setting causes additional code to be placed into each subroutine call to generate an exception if a stack collision occurs with the heap or statically allocated data. If true, adds -DALT_STACK_CHECK and -fstack-limit-register=et to ALT_CPPFLAGS in public.mk.</td>
</tr>
<tr mode="wrap">
<td width="20%">Restrictions:</td><td>none</td>
/ao486/trunk/syn/soc/firmware/exe_bsp/settings.bsp Cannot display: file marked as a binary type. svn:mime-type = application/xml
/ao486/trunk/syn/soc/firmware/exe_bsp/HAL/src/crt0.S
457,6 → 457,13
#endif /* ALT_SIM_OPTIMIZE */
 
/*
* Turn off the use of r1 (the assembler temporary register)
* so that call instructions can be safely relaxed across a
* 256MB boundary if needed
*/
.set at
 
/*
* The alt_load() facility is normally used when there is no bootloader.
* It copies some sections into RAM so it acts like a mini-bootloader.
*/
/ao486/trunk/syn/soc/firmware/exe_bsp/HAL/src/alt_load.c
37,15 → 37,15
* Linker defined symbols.
*/
 
extern void __flash_rwdata_start;
extern void __ram_rwdata_start;
extern void __ram_rwdata_end;
extern void __flash_rodata_start;
extern void __ram_rodata_start;
extern void __ram_rodata_end;
extern void __flash_exceptions_start;
extern void __ram_exceptions_start;
extern void __ram_exceptions_end;
extern alt_u32 __flash_rwdata_start;
extern alt_u32 __ram_rwdata_start;
extern alt_u32 __ram_rwdata_end;
extern alt_u32 __flash_rodata_start;
extern alt_u32 __ram_rodata_start;
extern alt_u32 __ram_rodata_end;
extern alt_u32 __flash_exceptions_start;
extern alt_u32 __ram_exceptions_start;
extern alt_u32 __ram_exceptions_end;
 
/*
* alt_load() is called when the code is executing from flash. In this case
60,8 → 60,8
*/
 
alt_load_section (&__flash_rwdata_start,
&__ram_rwdata_start,
&__ram_rwdata_end);
&__ram_rwdata_start,
&__ram_rwdata_end);
 
/*
* Copy the exception handler.
/ao486/trunk/syn/soc/firmware/exe_bsp/public.mk
78,12 → 78,12
 
# This following VERSION comment indicates the version of the tool used to
# generate this makefile. A makefile variable is provided for VERSION as well.
# ACDS_VERSION: 13.1
ACDS_VERSION := 13.1
# ACDS_VERSION: 14.0
ACDS_VERSION := 14.0
 
# This following BUILD_NUMBER comment indicates the build number of the tool
# used to generate this makefile.
# BUILD_NUMBER: 162
# BUILD_NUMBER: 200
 
# Qsys--generated SOPCINFO file. Required for resolving node instance ID's with
# design component names.
149,7 → 149,7
# setting altera_avalon_jtag_uart_driver.enable_small_driver is false
 
# Build a custom version of newlib with the specified space-separated compiler
# flags. The custom newlib build will be placed in the &lt;bsp root>/newlib
# flags. The custom newlib build will be placed in the <bsp root>/newlib
# directory, and will be used only for applications that utilize this BSP.
# setting hal.custom_newlib_flags is none
 
158,25 → 158,25
# multiple inheritance and exceptions are not supported. If false, adds
# -DALT_NO_C_PLUS_PLUS to ALT_CPPFLAGS in public.mk, and reduces code
# footprint. none
# setting hal.enable_c_plus_plus is 0
# setting hal.enable_c_plus_plus is false
ALT_CPPFLAGS += -DALT_NO_C_PLUS_PLUS
 
# When your application exits, close file descriptors, call C++ destructors,
# etc. Code footprint can be reduced by disabling clean exit. If disabled, adds
# -DALT_NO_CLEAN_EXIT to ALT_CPPFLAGS -D'exit(a)=_exit(a)' in public.mk. none
# setting hal.enable_clean_exit is 0
# setting hal.enable_clean_exit is false
ALT_CPPFLAGS += -DALT_NO_CLEAN_EXIT -D'exit(a)=_exit(a)'
 
# Add exit() support. This option increases code footprint if your "main()"
# routine does "return" or call "exit()". If false, adds -DALT_NO_EXIT to
# ALT_CPPFLAGS in public.mk, and reduces footprint none
# setting hal.enable_exit is 0
# setting hal.enable_exit is false
ALT_CPPFLAGS += -DALT_NO_EXIT
 
# Causes code to be compiled with gprof profiling enabled and the application
# ELF to be linked with the GPROF library. If true, adds -DALT_PROVIDE_GMON to
# ALT_CPPFLAGS and -pg to ALT_CFLAGS in public.mk. none
# setting hal.enable_gprof is 0
# setting hal.enable_gprof is false
 
# Enables lightweight device driver API. This reduces code and data footprint
# by removing the HAL layer that maps device names (e.g. /dev/uart0) to file
186,7 → 186,7
# devices. If true, adds -DALT_USE_DIRECT_DRIVERS to ALT_CPPFLAGS in public.mk.
# The Altera Host and read-only ZIP file systems can't be used if
# hal.enable_lightweight_device_driver_api is true.
# setting hal.enable_lightweight_device_driver_api is 1
# setting hal.enable_lightweight_device_driver_api is true
ALT_CPPFLAGS += -DALT_USE_DIRECT_DRIVERS
 
# Adds code to emulate multiply and divide instructions in case they are
194,7 → 194,7
# the compiler won't use multiply and divide instructions that aren't present
# in the CPU. If false, adds -DALT_NO_INSTRUCTION_EMULATION to ALT_CPPFLAGS in
# public.mk. none
# setting hal.enable_mul_div_emulation is 0
# setting hal.enable_mul_div_emulation is false
ALT_CPPFLAGS += -DALT_NO_INSTRUCTION_EMULATION
 
# Certain drivers are compiled with reduced functionality to reduce code
206,15 → 206,15
# access routines) to fail. You can define a symbol provided by each driver to
# prevent it from being removed. If true, adds -DALT_USE_SMALL_DRIVERS to
# ALT_CPPFLAGS in public.mk. none
# setting hal.enable_reduced_device_drivers is 1
# setting hal.enable_reduced_device_drivers is true
ALT_CPPFLAGS += -DALT_USE_SMALL_DRIVERS
 
# Turns on HAL runtime stack checking feature. Enabling this setting causes
# additional code to be placed into each subroutine call to generate an
# exception if a stack collision occurs with the heap or statically allocated
# data. If true, adds -DALT_STACK_CHECK and -fstack-check to ALT_CPPFLAGS in
# public.mk. none
# setting hal.enable_runtime_stack_checking is 0
# data. If true, adds -DALT_STACK_CHECK and -fstack-limit-register=et to
# ALT_CPPFLAGS in public.mk. none
# setting hal.enable_runtime_stack_checking is false
 
# The BSP is compiled with optimizations to speedup HDL simulation such as
# initializing the cache, clearing the .bss section, and skipping long delay
221,7 → 221,7
# loops. If true, adds -DALT_SIM_OPTIMIZE to ALT_CPPFLAGS in public.mk. When
# this setting is true, the BSP shouldn't be used to build applications that
# are expected to run real hardware.
# setting hal.enable_sim_optimize is 0
# setting hal.enable_sim_optimize is false
 
# Causes the small newlib (C library) to be used. This reduces code and data
# footprint at the expense of reduced functionality. Several newlib features
228,7 → 228,7
# are removed such as floating-point support in printf(), stdin input routines,
# and buffered I/O. The small C library is not compatible with Micrium
# MicroC/OS-II. If true, adds -msmallc to ALT_LDFLAGS in public.mk. none
# setting hal.enable_small_c_library is 1
# setting hal.enable_small_c_library is true
ALT_LDFLAGS += -msmallc
ALT_CPPFLAGS += -DSMALL_C_LIB
 
241,36 → 241,36
# application .elf file (and BSP it is linked against) corresponds to the
# hardware design on the target. If false, adds --accept-bad-sysid to
# SOPC_SYSID_FLAG in public.mk. none
# setting hal.enable_sopc_sysid_check is 0
# setting hal.enable_sopc_sysid_check is false
SOPC_SYSID_FLAG += --accept-bad-sysid
 
# Enable BSP generation to query if SOPC system is big endian. If true ignores
# export of 'ALT_CFLAGS += -meb' to public.mk if big endian system. none
# setting hal.make.ignore_system_derived.big_endian is 0
# setting hal.make.ignore_system_derived.big_endian is false
 
# Enable BSP generation to query if SOPC system has a debug core present. If
# true ignores export of 'CPU_HAS_DEBUG_CORE = 1' to public.mk if a debug core
# is found in the system. If true ignores export of 'CPU_HAS_DEBUG_CORE = 0' if
# no debug core is found in the system. none
# setting hal.make.ignore_system_derived.debug_core_present is 0
# setting hal.make.ignore_system_derived.debug_core_present is false
 
# Enable BSP generation to query if SOPC system has FPU present. If true
# ignores export of 'ALT_CFLAGS += -mhard-float' to public.mk if FPU is found
# in the system. If true ignores export of 'ALT_CFLAGS += -mhard-soft' if FPU
# is not found in the system. none
# setting hal.make.ignore_system_derived.fpu_present is 0
# setting hal.make.ignore_system_derived.fpu_present is false
 
# Enable BSP generation to query if SOPC system has hardware divide present. If
# true ignores export of 'ALT_CFLAGS += -mno-hw-div' to public.mk if no
# division is found in system. If true ignores export of 'ALT_CFLAGS +=
# -mhw-div' if division is found in the system. none
# setting hal.make.ignore_system_derived.hardware_divide_present is 0
# setting hal.make.ignore_system_derived.hardware_divide_present is false
 
# Enable BSP generation to query if SOPC system floating point custom
# instruction with a divider is present. If true ignores export of 'ALT_CFLAGS
# += -mcustom-fpu-cfg=60-2' and 'ALT_LDFLAGS += -mcustom-fpu-cfg=60-2' to
# public.mk if the custom instruction is found in the system. none
# setting hal.make.ignore_system_derived.hardware_fp_cust_inst_divider_present is 0
# setting hal.make.ignore_system_derived.hardware_fp_cust_inst_divider_present is false
 
# Enable BSP generation to query if SOPC system floating point custom
# instruction without a divider is present. If true ignores export of
277,38 → 277,38
# 'ALT_CFLAGS += -mcustom-fpu-cfg=60-1' and 'ALT_LDFLAGS +=
# -mcustom-fpu-cfg=60-1' to public.mk if the custom instruction is found in the
# system. none
# setting hal.make.ignore_system_derived.hardware_fp_cust_inst_no_divider_present is 0
# setting hal.make.ignore_system_derived.hardware_fp_cust_inst_no_divider_present is false
 
# Enable BSP generation to query if SOPC system has multiplier present. If true
# ignores export of 'ALT_CFLAGS += -mno-hw-mul' to public.mk if no multiplier
# is found in the system. If true ignores export of 'ALT_CFLAGS += -mhw-mul' if
# multiplier is found in the system. none
# setting hal.make.ignore_system_derived.hardware_multiplier_present is 0
# setting hal.make.ignore_system_derived.hardware_multiplier_present is false
 
# Enable BSP generation to query if SOPC system has hardware mulx present. If
# true ignores export of 'ALT_CFLAGS += -mno-hw-mulx' to public.mk if no mulx
# is found in the system. If true ignores export of 'ALT_CFLAGS += -mhw-mulx'
# if mulx is found in the system. none
# setting hal.make.ignore_system_derived.hardware_mulx_present is 0
# setting hal.make.ignore_system_derived.hardware_mulx_present is false
 
# Enable BSP generation to query if SOPC system has simulation enabled. If true
# ignores export of 'ELF_PATCH_FLAG += --simulation_enabled' to public.mk. none
# setting hal.make.ignore_system_derived.sopc_simulation_enabled is 0
# setting hal.make.ignore_system_derived.sopc_simulation_enabled is false
 
# Enable BSP generation to query SOPC system for system ID base address. If
# true ignores export of 'SOPC_SYSID_FLAG += --sidp=<address>' and
# 'ELF_PATCH_FLAG += --sidp=<address>' to public.mk. none
# setting hal.make.ignore_system_derived.sopc_system_base_address is 0
# setting hal.make.ignore_system_derived.sopc_system_base_address is false
 
# Enable BSP generation to query SOPC system for system ID. If true ignores
# export of 'SOPC_SYSID_FLAG += --id=<sysid>' and 'ELF_PATCH_FLAG +=
# --id=<sysid>' to public.mk. none
# setting hal.make.ignore_system_derived.sopc_system_id is 0
# setting hal.make.ignore_system_derived.sopc_system_id is false
 
# Enable BSP generation to query SOPC system for system timestamp. If true
# ignores export of 'SOPC_SYSID_FLAG += --timestamp=<timestamp>' and
# 'ELF_PATCH_FLAG += --timestamp=<timestamp>' to public.mk. none
# setting hal.make.ignore_system_derived.sopc_system_timestamp is 0
# setting hal.make.ignore_system_derived.sopc_system_timestamp is false
 
# Slave descriptor of STDERR character-mode device. This setting is used by the
# ALT_STDERR family of defines in system.h. none
/ao486/trunk/syn/soc/firmware/exe_bsp/mem_init.mk
109,6 → 109,7
 
mem_start_address = $($(target_stem)_START)
mem_end_address = $($(target_stem)_END)
mem_span = $($(target_stem)_SPAN)
mem_width = $($(target_stem)_WIDTH)
mem_endianness = $($(target_stem)_ENDIANNESS)
mem_create_lanes = $($(target_stem)_CREATE_LANES)
144,12 → 145,12
 
# This following VERSION comment indicates the version of the tool used to
# generate this makefile. A makefile variable is provided for VERSION as well.
# ACDS_VERSION: 13.1
ACDS_VERSION := 13.1
# ACDS_VERSION: 14.0
ACDS_VERSION := 14.0
 
# This following BUILD_NUMBER comment indicates the build number of the tool
# used to generate this makefile.
# BUILD_NUMBER: 162
# BUILD_NUMBER: 200
 
# Optimize for simulation
SIM_OPTIMIZE ?= 0
173,6 → 174,7
HDL_SIM_INSTALL_FILES += $(HDL_SIM_INSTALL_DIR)/$(MEM_0).sym
$(MEM_0)_START := 0x00010000
$(MEM_0)_END := 0x00017fff
$(MEM_0)_SPAN := 0x00008000
$(MEM_0)_HIERARCHICAL_PATH := onchip_for_nios2
$(MEM_0)_WIDTH := 32
$(MEM_0)_ENDIANNESS := --little-endian-mem
190,6 → 192,7
HDL_SIM_INSTALL_FILES += $(HDL_SIM_INSTALL_DIR)/$(MEM_1).sym
$(MEM_1)_START := 0x08000000
$(MEM_1)_END := 0x0fffffff
$(MEM_1)_SPAN := 0x08000000
$(MEM_1)_HIERARCHICAL_PATH := sdram
$(MEM_1)_WIDTH := 32
$(MEM_1)_ENDIANNESS := --little-endian-mem
/ao486/trunk/syn/soc/firmware/exe_bsp/Makefile
67,9 → 67,7
# Stash all BSP object files here
OBJ_DIR := ./obj
 
NEWLIB_DIR = $(BSP_ROOT_DIR)/newlib
 
 
#------------------------------------------------------------------------------
# MANAGED CONTENT
#
95,12 → 93,12
 
# This following VERSION comment indicates the version of the tool used to
# generate this makefile. A makefile variable is provided for VERSION as well.
# ACDS_VERSION: 13.1
ACDS_VERSION := 13.1
# ACDS_VERSION: 14.0
ACDS_VERSION := 14.0
 
# This following BUILD_NUMBER comment indicates the build number of the tool
# used to generate this makefile.
# BUILD_NUMBER: 162
# BUILD_NUMBER: 200
 
SETTINGS_FILE := settings.bsp
SOPC_FILE := ../../system.sopcinfo
733,12 → 731,8
NEWLIB_FLAGS += $(BSP_CFLAGS)
endif
 
ifneq ($(NEWLIB_FLAGS),)
ALT_LIBRARY_DIRS += $(NEWLIB_DIR)/nios2-elf/lib
endif
 
ifneq ($(NEWLIB_DIR),)
$(NEWLIB_DIR):
ifneq ($(NEWLIB_FLAGS),)
@$(ECHO) Creating $(NEWLIB_DIR)...
nios2-newlib-gen --no-multilib $(NEWLIB_DIR)-build-tmp $(NEWLIB_DIR) --custom "$(NEWLIB_FLAGS)"
@$(ECHO) Removing $(NEWLIB_DIR)-build-tmp...
/ao486/trunk/syn/soc/firmware/exe_bsp/drivers/src/altera_avalon_jtag_uart_write.c
184,7 → 184,7
;
#endif /* __ucosii__ */
 
if (out == sp->tx_out)
if (sp->host_inactive)
break;
}
}
/ao486/trunk/syn/soc/soc.qsf
41,7 → 41,7
set_global_assignment -name TOP_LEVEL_ENTITY soc
set_global_assignment -name ORIGINAL_QUARTUS_VERSION "13.0 SP1"
set_global_assignment -name PROJECT_CREATION_TIME_DATE "10:43:53 OCTOBER 31, 2013"
set_global_assignment -name LAST_QUARTUS_VERSION 13.1
set_global_assignment -name LAST_QUARTUS_VERSION 14.0
set_global_assignment -name PROJECT_OUTPUT_DIRECTORY output_files
set_global_assignment -name MIN_CORE_JUNCTION_TEMP 0
set_global_assignment -name MAX_CORE_JUNCTION_TEMP 85
327,7 → 327,7
set_global_assignment -name POWER_PRESET_COOLING_SOLUTION "23 MM HEAT SINK WITH 200 LFPM AIRFLOW"
set_global_assignment -name POWER_BOARD_THERMAL_MODEL "NONE (CONSERVATIVE)"
set_global_assignment -name ENABLE_SIGNALTAP OFF
set_global_assignment -name USE_SIGNALTAP_FILE output_files/stp_win95_ao486.stp
set_global_assignment -name QIP_FILE firmware/exe/mem_init/meminit.qip
set_global_assignment -name VERILOG_FILE ../../rtl/common/simple_single_rom.v
set_global_assignment -name VERILOG_FILE ../../rtl/common/simple_bidir_ram.v
set_global_assignment -name VERILOG_FILE ../../rtl/common/simple_rom.v
338,21 → 338,5
set_global_assignment -name VERILOG_FILE ../../rtl/soc/soc.v
set_global_assignment -name QIP_FILE altera/pll.qip
set_global_assignment -name SDC_FILE soc.sdc
set_global_assignment -name SIGNALTAP_FILE output_files/pc_bus.stp
set_global_assignment -name SIGNALTAP_FILE output_files/stp_ao486_io.stp
set_global_assignment -name SIGNALTAP_FILE output_files/stp_interrupt.stp
set_global_assignment -name SIGNALTAP_FILE output_files/stp_floppy.stp
set_global_assignment -name SIGNALTAP_FILE output_files/stp_dma.stp
set_global_assignment -name SIGNALTAP_FILE output_files/stp_vga.stp
set_global_assignment -name SIGNALTAP_FILE output_files/stp_ram_irq.stp
set_global_assignment -name SIGNALTAP_FILE output_files/stp_vga_color.stp
set_global_assignment -name SIGNALTAP_FILE output_files/stp_hdd.stp
set_global_assignment -name SIGNALTAP_FILE output_files/stp_ps2.stp
set_global_assignment -name SIGNALTAP_FILE output_files/stp_regs.stp
set_global_assignment -name SIGNALTAP_FILE output_files/stp_win311_start.stp
set_global_assignment -name SIGNALTAP_FILE output_files/stp_win311_start_eip.stp
set_global_assignment -name SIGNALTAP_FILE output_files/stp_win311_tlb.stp
set_global_assignment -name SIGNALTAP_FILE output_files/stp_rtc_pit.stp
set_global_assignment -name CDF_FILE Chain1.cdf
set_global_assignment -name SIGNALTAP_FILE output_files/stp_win95_ao486.stp
set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top
/ao486/trunk/README.md
5,6 → 5,10
Together with the 486 core, the ao486 project also contains a SoC capable of
booting the Linux kernel version 3.13 and Microsoft Windows 95.
 
### Current status
- 31 March 2014 - initial version 1.0.
- 19 August 2014 - driver_sd update, ps2 fix.
 
### Features
 
The ao486 processor model has the following features:

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