OpenCores
URL https://opencores.org/ocsvn/apb2spi/apb2spi/trunk

Subversion Repositories apb2spi

Compare Revisions

  • This comparison shows the changes necessary to convert path 
    /apb2spi
    from Rev 6 to Rev 7
    ↔ Reverse comparison
  •

Rev 6 → Rev 7

/trunk/tb/makefile
0,0 → 1,93
//////////////////////////////////////////////////////////////////////
//// ////
//// APB- SPI 0.1 IP Core VIP ////
//// ////
//// This file is part of the APB- SPI 0.1 IP Core project ////
//// http://www.opencores.org/cores/APB- SPI 0.1 VIP for IP Core ////
//// ////
//// Description ////
//// ----------- ////
//// Makefile has targets which are enabled in such a manner that ////
//// it works only for MS-Windows with VLOG, verilog compiler ////
//// and VSIM, simulator compile and simulate the code. Along with////
//// these two tools, a provision to create WORK directory using ////
//// VLIB tool is also there. The compiled code is kept under this////
//// directory ////
//// ////
//// So, to compile the code, set the following variables in ////
//// shell(using Cygwin), to make the makefile work. ////
//// Incase of compilation of code for a second time, unless there////
//// is a change in the code, the library doesn't get overwritten.////
//// To avoid this, a target called "CLEAN" is invoked each and ////
//// every time VLOG is invoked along with creating of VLIG again ////
//// ////
//// 1. vlog ////
//// 2. vlib ////
//// 3. vsim ////
//// 4. QVH_HOME (where UVM's HOME directory is there ////
//// 5. BUILD_HOME (Under which the trunk directory is kept) ////
//// ////
//// ////
//// To Do: ////
//// ------
//// 1. Addition of more targets to ensure coverage is also done. ////
//// 2. Incase of different tests, moving the log files to the ////
//// corresponding directories where they get stored along with////
//// coverage databases if coverage is also done. ////
//// ////
//// Author(s): ////
//// - Srikumar Kadagambadi, email@opencores.org ////
//// ////
//////////////////////////////////////////////////////////////////////
//// ////
//// Copyright (C) 2009 Authors and OPENCORES.ORG ////
//// ////
//// This source file may be used and distributed without ////
//// restriction provided that this copyright statement is not ////
//// removed from the file and that any derivative work contains ////
//// the original copyright notice and the associated disclaimer. ////
//// ////
//// This source file is free software; you can redistribute it ////
//// and/or modify it under the terms of the GNU Lesser General ////
//// Public License as published by the Free Software Foundation; ////
//// either version 2.1 of the License, or (at your option) any ////
//// later version. ////
//// ////
//// This source is distributed in the hope that it will be ////
//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
//// PURPOSE. See the GNU Lesser General Public License for more ////
//// details. ////
//// ////
//// You should have received a copy of the GNU Lesser General ////
//// Public License along with this source; if not, download it ////
//// from http://www.opencores.org/lgpl.shtml ////
//// ////
//////////////////////////////////////////////////////////////////////
BUILD_NAME =
BUILD_NAME = D:/prj_svn_apb_to_spi/apb2spi/trunk
QVH_HOME = D:/mentor/questasim64_10.2c/uvm-1.1d/win64
RTL_DIR = ${BUILD_NAME}/rtl
RTL_INC = +incdir+${RTL_DIR}
APB_INC = +incdir+${BUILD_NAME}/tb/env/apb_agent
SPI_INC = +incdir+${BUILD_NAME}/tb/env/spi_agent
ENV_INC = +incdir+${BUILD_NAME}/tb/env
ENV_SRC_INC = +incdir+${BUILD_NAME}/tb/env/src
TESTS_INC = +incdir+${BUILD_NAME}/tb/tests
 
WORK : clean
${vlib} work
 
RTL : WORK
${vlog} -sv ${RTL_INC} ${RTL_DIR}/APB_SLAVE.v ${RTL_DIR}/APB_SPI_Top.v
 
TB : RTL
${vlog} -sv ${RTL_INC} ${APB_INC} ${SPI_INC} ${ENV_INC} ${ENV_SRC_INC} ${TESTS_INC} tb_top.sv
 
SIM : TB
${vsim} ${RTL_INC} ${APB_INC} ${SPI_INC} ${ENV_INC} ${ENV_SRC_INC} ${TESTS_INC} tb_top -sv_lib ${QVH_HOME}/uvm_dpi -c -do "run -all; q" -l vsim.log
 
clean:
rm -rf work vlib.log vlog.log vsim.log questa.log qverilog.log

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.