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URL https://opencores.org/ocsvn/apb_slave/apb_slave/trunk

Subversion Repositories apb_slave

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/apb_slave/trunk/run/run.bat
0,0 → 1,6
 
echo off
 
..\..\..\robust.exe ../src/base/apb_slave.v -od out -I ../src/gen -list list.txt -listpath -header
 
echo Completed RobustVerilog APB slave run - results in run/out/
/apb_slave/trunk/run/run.sh
0,0 → 1,5
#!/bin/bash
 
../../../robust ../src/base/apb_slave.v -od out -I ../src/gen -list list.txt -listpath -header
 
echo Completed RobustVerilog APB slave run - results in run/out/
/apb_slave/trunk/src/gen/prgen_rand.v
0,0 → 1,87
/////////////////////////////////////////////////////////////////////
//// ////
//// Author: Eyal Hochberg ////
//// eyal@provartec.com ////
//// ////
//// Downloaded from: http://www.opencores.org ////
/////////////////////////////////////////////////////////////////////
//// ////
//// Copyright (C) 2010 Provartec LTD ////
//// www.provartec.com ////
//// info@provartec.com ////
//// ////
//// This source file may be used and distributed without ////
//// restriction provided that this copyright statement is not ////
//// removed from the file and that any derivative work contains ////
//// the original copyright notice and the associated disclaimer.////
//// ////
//// This source file is free software; you can redistribute it ////
//// and/or modify it under the terms of the GNU Lesser General ////
//// Public License as published by the Free Software Foundation.////
//// ////
//// This source is distributed in the hope that it will be ////
//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
//// PURPOSE. See the GNU Lesser General Public License for more////
//// details. http://www.gnu.org/licenses/lgpl.html ////
//// ////
/////////////////////////////////////////////////////////////////////
 
function integer rand_chance;
input [31:0] chance_true;
 
begin
if (chance_true > 100)
begin
$display("RAND_CHANCE-E-: fatal error, rand_chance called with percent chance larger than 100.\tTime: %0d ns", $time);
$finish;
end
rand_chance = (rand(1,100) <= chance_true);
end
endfunction // rand_chance
 
 
function integer rand;
input [31:0] min;
input [31:0] max;
 
integer range;
begin
if (min > max)
begin
$display("RAND-E-: fatal error, rand was called with min larger than max.\tTime: %0d ns", $time);
$finish;
end
 
range = (max - min) + 1;
if (range == 0) range = -1;
rand = min + ($random % range);
end
endfunction // rand
 
 
function integer align;
input [31:0] num;
input [31:0] align_size;
integer align;
begin
align = num - (num % align_size);
end
endfunction
 
 
function integer rand_align;
input [31:0] min;
input [31:0] max;
input [31:0] align;
 
integer rand_align;
begin
rand_align = rand(min, max);
if (rand_align > align)
rand_align = align(rand_align, align);
end
endfunction
 
/apb_slave/trunk/src/base/def_apb_slave_static.txt
0,0 → 1,57
<##//////////////////////////////////////////////////////////////////
//// ////
//// Author: Eyal Hochberg ////
//// eyal@provartec.com ////
//// ////
//// Downloaded from: http://www.opencores.org ////
/////////////////////////////////////////////////////////////////////
//// ////
//// Copyright (C) 2010 Provartec LTD ////
//// www.provartec.com ////
//// info@provartec.com ////
//// ////
//// This source file may be used and distributed without ////
//// restriction provided that this copyright statement is not ////
//// removed from the file and that any derivative work contains ////
//// the original copyright notice and the associated disclaimer.////
//// ////
//// This source file is free software; you can redistribute it ////
//// and/or modify it under the terms of the GNU Lesser General ////
//// Public License as published by the Free Software Foundation.////
//// ////
//// This source is distributed in the hope that it will be ////
//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
//// PURPOSE. See the GNU Lesser General Public License for more////
//// details. http://www.gnu.org/licenses/lgpl.html ////
//// ////
//////////////////////////////////////////////////////////////////##>
 
VERIFY (ADDR_BITS<=24) else Memory size should not be too big to prevent maloc fail
 
SWAP DATA_BITS 32 ##APB is always 32 bits data
GROUP STUB_APB is {
psel 1 output
penable 1 output
pwrite 1 output
paddr ADDR_BITS output
pwdata DATA_BITS output
prdata DATA_BITS input
IFDEF APB3
pslverr 1 input
pready 1 input
ENDIF APB3
}
 
GROUP STUB_MEM is {
WR 1 output
RD 1 output
ADDR_WR ADDR_BITS output
ADDR_RD ADDR_BITS output
DIN DATA_BITS output
BSEL DATA_BITS/8 output
DOUT DATA_BITS input
}
/apb_slave/trunk/src/base/apb_slave.v
0,0 → 1,181
/////////////////////////////////////////////////////////////////////
//// ////
//// Author: Eyal Hochberg ////
//// eyal@provartec.com ////
//// ////
//// Downloaded from: http://www.opencores.org ////
/////////////////////////////////////////////////////////////////////
//// ////
//// Copyright (C) 2010 Provartec LTD ////
//// www.provartec.com ////
//// info@provartec.com ////
//// ////
//// This source file may be used and distributed without ////
//// restriction provided that this copyright statement is not ////
//// removed from the file and that any derivative work contains ////
//// the original copyright notice and the associated disclaimer.////
//// ////
//// This source file is free software; you can redistribute it ////
//// and/or modify it under the terms of the GNU Lesser General ////
//// Public License as published by the Free Software Foundation.////
//// ////
//// This source is distributed in the hope that it will be ////
//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
//// PURPOSE. See the GNU Lesser General Public License for more////
//// details. http://www.gnu.org/licenses/lgpl.html ////
//// ////
/////////////////////////////////////////////////////////////////////
 
//////////////////////////////////////
//
// General:
// The APB slave can use APB or APB3 protocol (APB3 is with pslverr and pready)
// APB3 is set by DEFINE in def_apb_slave.txt
// All following tasks regard APB3 only.
//
//
// Tasks:
//
// set_random_delay(input min_delay, input max_delay)
// Description: Set random wait states on pready
// Parameters: min_delay - minimum delay
// max_delay = maximum delay
//
// set_fixed_delay(input delay)
// Description: Set fixed wait states on pready
// Parameters: delay - fixed delay on pready
//
// set_slverr(input address)
// Description: Set address to return slave error (pslverr)
// Parameters: address - address will return pslverr
//
//
//////////////////////////////////////
 
OUTFILE PREFIX.v
 
INCLUDE def_apb_slave.txt
module PREFIX(PORTS);
 
`include "prgen_rand.v"
 
parameter SLAVE_NUM = 0;
input clk;
input reset;
revport GROUP_STUB_APB;
 
 
wire GROUP_STUB_MEM;
 
IFDEF APB3
reg busy_rand_enable = 0; //enable random busy
integer busy_min = 0; //min busy cycles
integer busy_max = 5; //max busy cycles
integer busy_delay = 1; //fixed delay for pready
reg err_enable = 0;
reg [ADDR_BITS-1:0] err_addr = {ADDR_BITS{1'b1}}; //error address
 
wire pslverr = err_enable && (paddr == err_addr);
reg pready = 1'b1;
always @(negedge clk)
begin
#FFD;
if (psel)
begin
if (busy_rand_enable)
begin
busy_delay = rand(busy_min, busy_max);
end
if (busy_delay > 0)
begin
pready = 1'b0;
repeat (busy_delay)
begin
@(posedge clk); #FFD;
end
pready = 1'b1;
@(posedge clk); #FFD;
end
end
end
 
 
task set_random_delay;
input [31:0] delay_min;
input [31:0] delay_max;
begin
busy_rand_enable = 1;
busy_min = delay_min;
busy_max = delay_max;
end
endtask
 
task set_fixed_delay;
input [31:0] delay;
begin
busy_rand_enable = 0;
busy_delay = delay;
end
endtask
 
task set_slverr;
input [31:0] addr;
begin
err_enable = 1;
err_addr = addr;
end
endtask
 
 
ELSE APB3
wire pready = 1'b1;
wire pslverr = 1'b0;
ENDIF APB3
 
 
assign WR = psel & penable & pwrite;
assign RD = psel & (~penable) & (~pwrite);
assign ADDR_WR = paddr;
assign ADDR_RD = paddr;
assign DIN = pwdata;
assign BSEL = 4'b1111;
assign prdata = pready ? DOUT : {DATA_BITS{1'bx}};
 
CREATE apb_slave_mem.v
PREFIX_mem PREFIX_mem(
.clk(clk),
.reset(reset),
.GROUP_STUB_MEM(GROUP_STUB_MEM),
STOMP ,
);
 
 
IFDEF TRACE
CREATE apb_slave_trace.v
PREFIX_trace #(SLAVE_NUM)
PREFIX_trace(
.clk(clk),
.reset(reset),
.GROUP_STUB_MEM(GROUP_STUB_MEM),
STOMP ,
);
ENDIF TRACE
endmodule
 
 
/apb_slave/trunk/src/base/def_apb_slave.txt
0,0 → 1,41
<##//////////////////////////////////////////////////////////////////
//// ////
//// Author: Eyal Hochberg ////
//// eyal@provartec.com ////
//// ////
//// Downloaded from: http://www.opencores.org ////
/////////////////////////////////////////////////////////////////////
//// ////
//// Copyright (C) 2010 Provartec LTD ////
//// www.provartec.com ////
//// info@provartec.com ////
//// ////
//// This source file may be used and distributed without ////
//// restriction provided that this copyright statement is not ////
//// removed from the file and that any derivative work contains ////
//// the original copyright notice and the associated disclaimer.////
//// ////
//// This source file is free software; you can redistribute it ////
//// and/or modify it under the terms of the GNU Lesser General ////
//// Public License as published by the Free Software Foundation.////
//// ////
//// This source is distributed in the hope that it will be ////
//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
//// PURPOSE. See the GNU Lesser General Public License for more////
//// details. http://www.gnu.org/licenses/lgpl.html ////
//// ////
//////////////////////////////////////////////////////////////////##>
 
INCLUDE def_apb_slave_static.txt
 
SWAP.GLOBAL #FFD #1 ##Flip-Flop simulation delay
 
SWAP PREFIX apb_slave ##prefix for all module and file names
SWAP ADDR_BITS 16 ##AXI address bits
 
DEFINE APB3 ##Support APB3 protocol (pready and pslverr)
##DEFINE TRACE ##print memory trace to file
 
/apb_slave/trunk/src/base/apb_slave_mem.v
0,0 → 1,64
/////////////////////////////////////////////////////////////////////
//// ////
//// Author: Eyal Hochberg ////
//// eyal@provartec.com ////
//// ////
//// Downloaded from: http://www.opencores.org ////
/////////////////////////////////////////////////////////////////////
//// ////
//// Copyright (C) 2010 Provartec LTD ////
//// www.provartec.com ////
//// info@provartec.com ////
//// ////
//// This source file may be used and distributed without ////
//// restriction provided that this copyright statement is not ////
//// removed from the file and that any derivative work contains ////
//// the original copyright notice and the associated disclaimer.////
//// ////
//// This source file is free software; you can redistribute it ////
//// and/or modify it under the terms of the GNU Lesser General ////
//// Public License as published by the Free Software Foundation.////
//// ////
//// This source is distributed in the hope that it will be ////
//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
//// PURPOSE. See the GNU Lesser General Public License for more////
//// details. http://www.gnu.org/licenses/lgpl.html ////
//// ////
/////////////////////////////////////////////////////////////////////
 
OUTFILE PREFIX_mem.v
 
INCLUDE def_apb_slave.txt
 
ITER BX EXPR(DATA_BITS/8)
module PREFIX_mem (PORTS);
 
parameter MEM_WORDS = EXPR((2^ADDR_BITS)/(DATA_BITS/8));
parameter ADDR_LSB = LOG2(EXPR(DATA_BITS/8));
input clk;
input reset;
revport GROUP_STUB_MEM;
reg [DATA_BITS-1:0] Mem [MEM_WORDS-1:0];
reg [DATA_BITS-1:0] DOUT;
wire [DATA_BITS-1:0] BitSEL;
wire [ADDR_BITS-1:ADDR_LSB] ADDR_WR_word = ADDR_WR[ADDR_BITS-1:ADDR_LSB];
wire [ADDR_BITS-1:ADDR_LSB] ADDR_RD_word = ADDR_RD[ADDR_BITS-1:ADDR_LSB];
 
assign BitSEL = {CONCAT({8{BSEL[BX]}} ,)};
always @(posedge clk)
if (WR)
Mem[ADDR_WR_word] <= #FFD (Mem[ADDR_WR_word] & ~BitSEL) | (DIN & BitSEL);
always @(posedge clk or posedge reset)
if (reset)
DOUT <= #FFD {DATA_BITS{1'b0}};
else if (RD)
DOUT <= #FFD Mem[ADDR_RD_word];
 
endmodule
/apb_slave/trunk/src/base/apb_slave_trace.v
0,0 → 1,81
/////////////////////////////////////////////////////////////////////
//// ////
//// Author: Eyal Hochberg ////
//// eyal@provartec.com ////
//// ////
//// Downloaded from: http://www.opencores.org ////
/////////////////////////////////////////////////////////////////////
//// ////
//// Copyright (C) 2010 Provartec LTD ////
//// www.provartec.com ////
//// info@provartec.com ////
//// ////
//// This source file may be used and distributed without ////
//// restriction provided that this copyright statement is not ////
//// removed from the file and that any derivative work contains ////
//// the original copyright notice and the associated disclaimer.////
//// ////
//// This source file is free software; you can redistribute it ////
//// and/or modify it under the terms of the GNU Lesser General ////
//// Public License as published by the Free Software Foundation.////
//// ////
//// This source is distributed in the hope that it will be ////
//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
//// PURPOSE. See the GNU Lesser General Public License for more////
//// details. http://www.gnu.org/licenses/lgpl.html ////
//// ////
/////////////////////////////////////////////////////////////////////
 
OUTFILE PREFIX_trace.v
 
INCLUDE def_apb_slave.txt
module PREFIX_trace(PORTS);
parameter SLAVE_NUM = 0;
parameter FILE_NAME = "PREFIX.trc";
input clk;
input reset;
 
input GROUP_STUB_MEM;
 
reg RD_d;
reg [ADDR_BITS-1:0] ADDR_RD_d;
 
wire [31:0] ADDR_WR_disp = ADDR_WR;
wire [31:0] ADDR_RD_disp = ADDR_RD_d;
integer file_ptr;
initial
file_ptr = $fopen(FILE_NAME, "w");
 
always @(posedge clk or posedge reset)
if (reset)
begin
ADDR_RD_d <= #FFD 'd0;
RD_d <= #FFD 'd0;
end
else
begin
ADDR_RD_d <= #FFD ADDR_RD;
RD_d <= #FFD RD;
end
always @(posedge clk)
if (WR)
$fwrite(file_ptr, "%16d: %0s WR: Addr: 0x%8h, Data: 0x%8h, Bsel: 0x%2h\n", $time, FILE_NAME, ADDR_WR_disp, DIN, BSEL);
always @(posedge clk)
if (RD_d)
$fwrite(file_ptr, "%16d: %0s RD: Addr: 0x%8h, Data: 0x%8h\n", $time, FILE_NAME, ADDR_RD_disp, DOUT);
 
endmodule
 
/apb_slave/trunk/README.txt
0,0 → 1,23
 
------------------------------ Remark ----------------------------------------
This code is a generic code written in RobustVerilog. In order to convert it to Verilog a RobustVerilog parser is required.
It is possible to download a free RobustVerilog parser from www.provartec.com/edatools.
 
We will be very happy to receive any kind of feedback regarding our tools and cores.
We will also be willing to support any company intending to integrate our cores into their project.
For any questions / remarks / suggestions / bugs please contact info@provartec.com.
------------------------------------------------------------------------------
 
RobustVerilog generic APB slave stub
 
Supports APB and APB3 (pready and pslverr) bus protocols. Supports slave error, random wait states and fixed wait states.
 
In order to create the Verilog design use the run.sh script in the run directory (notice that the run scripts calls the robust binary (RobustVerilog parser)).
 
The RobustVerilog top source file is apb_slave.v, it calls the top definition file named def_apb_slave.txt.
 
Changing the stub parameters should be made only in def_apb_master.txt in the src/base directory (changing address bits adding trace etc.).
 
Once the Verilog files have been generated instruction on how to use the stub are at the top of apb_slave.v (tasks and parameters).
 
 

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