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URL https://opencores.org/ocsvn/apbi2c/apbi2c/trunk

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    /apbi2c
    from Rev 18 to Rev 19
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Rev 18 → Rev 19

/trunk/rtl/module_i2c.v
130,61 → 130,61
 
// TX PARAMETERS USED TO STATE MACHINE
 
localparam [5:0] TX_IDLE = 6'd0, //IDLE
localparam [5:0] RX_TX_IDLE = 6'd0, //IDLE
 
TX_START = 6'd1,//START BIT
RX_TX_START = 6'd1,//START BIT
 
TX_CONTROLIN_1 = 6'd2, //START BYTE
TX_CONTROLIN_2 = 6'd3,
TX_CONTROLIN_3 = 6'd4,
TX_CONTROLIN_4 = 6'd5,
TX_CONTROLIN_5 = 6'd6,
TX_CONTROLIN_6 = 6'd7,
TX_CONTROLIN_7 = 6'd8,
TX_CONTROLIN_8 = 6'd9, //END FIRST BYTE
RX_TX_CONTROLIN_1 = 6'd2, //START BYTE
RX_TX_CONTROLIN_2 = 6'd3,
RX_TX_CONTROLIN_3 = 6'd4,
RX_TX_CONTROLIN_4 = 6'd5,
RX_TX_CONTROLIN_5 = 6'd6,
RX_TX_CONTROLIN_6 = 6'd7,
RX_TX_CONTROLIN_7 = 6'd8,
RX_TX_CONTROLIN_8 = 6'd9, //END FIRST BYTE
 
TX_RESPONSE_CIN =6'd10, //RESPONSE
RX_TX_RESPONSE_CIN =6'd10, //RESPONSE
 
TX_ADRESS_1 = 6'd11,//START BYTE
TX_ADRESS_2 = 6'd12,
TX_ADRESS_3 = 6'd13,
TX_ADRESS_4 = 6'd14,
TX_ADRESS_5 = 6'd15,
TX_ADRESS_6 = 6'd16,
TX_ADRESS_7 = 6'd17,
TX_ADRESS_8 = 6'd18,//END FIRST BYTE
RX_TX_ADRESS_1 = 6'd11,//START BYTE
RX_TX_ADRESS_2 = 6'd12,
RX_TX_ADRESS_3 = 6'd13,
RX_TX_ADRESS_4 = 6'd14,
RX_TX_ADRESS_5 = 6'd15,
RX_TX_ADRESS_6 = 6'd16,
RX_TX_ADRESS_7 = 6'd17,
RX_TX_ADRESS_8 = 6'd18,//END FIRST BYTE
 
TX_RESPONSE_ADRESS =6'd19, //RESPONSE
RX_TX_RESPONSE_ADRESS =6'd19, //RESPONSE
 
TX_DATA0_1 = 6'd20,//START BYTE
TX_DATA0_2 = 6'd21,
TX_DATA0_3 = 6'd22,
TX_DATA0_4 = 6'd23,
TX_DATA0_5 = 6'd24,
TX_DATA0_6 = 6'd25,
TX_DATA0_7 = 6'd26,
TX_DATA0_8 = 6'd27,//END FIRST BYTE
RX_TX_DATA0_1 = 6'd20,//START BYTE
RX_TX_DATA0_2 = 6'd21,
RX_TX_DATA0_3 = 6'd22,
RX_TX_DATA0_4 = 6'd23,
RX_TX_DATA0_5 = 6'd24,
RX_TX_DATA0_6 = 6'd25,
RX_TX_DATA0_7 = 6'd26,
RX_TX_DATA0_8 = 6'd27,//END FIRST BYTE
 
TX_RESPONSE_DATA0_1 = 6'd28, //RESPONSE
RX_TX_RESPONSE_DATA0_1 = 6'd28, //RESPONSE
TX_DATA1_1 = 6'd29,//START BYTE
TX_DATA1_2 = 6'd30,
TX_DATA1_3 = 6'd31,
TX_DATA1_4 = 6'd32,
TX_DATA1_5 = 6'd33,
TX_DATA1_6 = 6'd34,
TX_DATA1_7 = 6'd35,
TX_DATA1_8 = 6'd36,//END FIRST BYTE
RX_TX_DATA1_1 = 6'd29,//START BYTE
RX_TX_DATA1_2 = 6'd30,
RX_TX_DATA1_3 = 6'd31,
RX_TX_DATA1_4 = 6'd32,
RX_TX_DATA1_5 = 6'd33,
RX_TX_DATA1_6 = 6'd34,
RX_TX_DATA1_7 = 6'd35,
RX_TX_DATA1_8 = 6'd36,//END FIRST BYTE
 
TX_RESPONSE_DATA1_1 = 6'd37,//RESPONSE
RX_TX_RESPONSE_DATA1_1 = 6'd37,//RESPONSE
 
TX_DELAY_BYTES = 6'd38,//USED ONLY IN ACK TO DELAY BETWEEN
TX_NACK = 6'd39,//USED ONLY IN ACK TO DELAY BETWEEN BYTES
TX_STOP = 6'd40;//USED TO SEND STOP BIT
RX_TX_DELAY_BYTES = 6'd38,//USED ONLY IN ACK TO DELAY BETWEEN
RX_TX_NACK = 6'd39,//USED ONLY IN ACK TO DELAY BETWEEN BYTES
RX_TX_STOP = 6'd40;//USED TO SEND STOP BIT
 
//STATE CONTROL
reg [5:0] state_tx;
reg [5:0] next_state_tx;
reg [5:0] state_tx_rx;
reg [5:0] next_state_tx_rx;
 
//ASSIGN REGISTERS TO BIDIRETIONAL PORTS
assign SDA = (DATA_CONFIG_REG[0] == 1'b1 & DATA_CONFIG_REG[1] == 1'b0)?SDA_OUT:1'b0;
199,475 → 199,475
 
//THE FUN START HERE :-)
//COMBINATIONAL UPDATE STATE BE CAREFUL WITH WHAT YOU MAKE HERE
next_state_tx = state_tx;
next_state_tx_rx = state_tx_rx;
 
case(state_tx)//STATE_TX IS MORE SECURE CHANGE ONLY IF YOU KNOW WHAT ARE YOU DOING
TX_IDLE:
case(state_tx_rx)//state_tx_rx IS MORE SECURE CHANGE ONLY IF YOU KNOW WHAT ARE YOU DOING
RX_TX_IDLE:
begin
//OBEYING SPEC
if(DATA_CONFIG_REG[0] == 1'b0 && (fifo_tx_f_full == 1'b1 || fifo_tx_f_empty == 1'b0) && DATA_CONFIG_REG[1] == 1'b0)
begin
next_state_tx = TX_IDLE;
next_state_tx_rx = RX_TX_IDLE;
end
else if(DATA_CONFIG_REG[0] == 1'b1 && (fifo_tx_f_full == 1'b1 || fifo_tx_f_empty == 1'b0) && DATA_CONFIG_REG[1] == 1'b1)
begin
next_state_tx = TX_IDLE;
next_state_tx_rx = RX_TX_IDLE;
end
else if(DATA_CONFIG_REG[0] == 1'b1 && (fifo_tx_f_full == 1'b1 || fifo_tx_f_empty == 1'b0) && DATA_CONFIG_REG[1] == 1'b0)
begin
next_state_tx = TX_START;
next_state_tx_rx = RX_TX_START;
end
 
 
end
TX_START://THIS IS USED TOO ALL STATE MACHINES THE COUNTER_SEND_DATA
RX_TX_START://THIS IS USED TOO ALL STATE MACHINES THE COUNTER_SEND_DATA
begin
if(count_send_data != DATA_CONFIG_REG[13:2])
begin
next_state_tx = TX_START;
next_state_tx_rx = RX_TX_START;
end
else
begin
next_state_tx = TX_CONTROLIN_1;
next_state_tx_rx = RX_TX_CONTROLIN_1;
end
end
TX_CONTROLIN_1:
RX_TX_CONTROLIN_1:
begin
if(count_send_data != DATA_CONFIG_REG[13:2])
begin
next_state_tx = TX_CONTROLIN_1;
next_state_tx_rx = RX_TX_CONTROLIN_1;
end
else
begin
next_state_tx = TX_CONTROLIN_2;
next_state_tx_rx = RX_TX_CONTROLIN_2;
end
 
end
TX_CONTROLIN_2:
RX_TX_CONTROLIN_2:
begin
 
if(count_send_data != DATA_CONFIG_REG[13:2])
begin
next_state_tx =TX_CONTROLIN_2;
next_state_tx_rx = RX_TX_CONTROLIN_2;
end
else
begin
next_state_tx = TX_CONTROLIN_3;
next_state_tx_rx = RX_TX_CONTROLIN_3;
end
 
end
TX_CONTROLIN_3:
RX_TX_CONTROLIN_3:
begin
 
if(count_send_data != DATA_CONFIG_REG[13:2])
begin
next_state_tx = TX_CONTROLIN_3;
next_state_tx_rx = RX_TX_CONTROLIN_3;
end
else
begin
next_state_tx = TX_CONTROLIN_4;
next_state_tx_rx = RX_TX_CONTROLIN_4;
end
end
TX_CONTROLIN_4:
RX_TX_CONTROLIN_4:
begin
 
if(count_send_data != DATA_CONFIG_REG[13:2])
begin
next_state_tx = TX_CONTROLIN_4;
next_state_tx_rx = RX_TX_CONTROLIN_4;
end
else
begin
next_state_tx = TX_CONTROLIN_5;
next_state_tx_rx = RX_TX_CONTROLIN_5;
end
end
TX_CONTROLIN_5:
RX_TX_CONTROLIN_5:
begin
 
if(count_send_data != DATA_CONFIG_REG[13:2])
begin
next_state_tx = TX_CONTROLIN_5;
next_state_tx_rx = RX_TX_CONTROLIN_5;
end
else
begin
next_state_tx = TX_CONTROLIN_6;
next_state_tx_rx = RX_TX_CONTROLIN_6;
end
end
TX_CONTROLIN_6:
RX_TX_CONTROLIN_6:
begin
 
if(count_send_data != DATA_CONFIG_REG[13:2])
begin
next_state_tx = TX_CONTROLIN_6;
next_state_tx_rx = RX_TX_CONTROLIN_6;
end
else
begin
next_state_tx = TX_CONTROLIN_7;
next_state_tx_rx = RX_TX_CONTROLIN_7;
end
end
TX_CONTROLIN_7:
RX_TX_CONTROLIN_7:
begin
 
if(count_send_data != DATA_CONFIG_REG[13:2])
begin
next_state_tx = TX_CONTROLIN_7;
next_state_tx_rx = RX_TX_CONTROLIN_7;
end
else
begin
next_state_tx = TX_CONTROLIN_8;
next_state_tx_rx = RX_TX_CONTROLIN_8;
end
end
TX_CONTROLIN_8:
RX_TX_CONTROLIN_8:
begin
 
if(count_send_data != DATA_CONFIG_REG[13:2])
begin
next_state_tx = TX_CONTROLIN_8;
next_state_tx_rx = RX_TX_CONTROLIN_8;
end
else
begin
next_state_tx = TX_RESPONSE_CIN;
next_state_tx_rx = RX_TX_RESPONSE_CIN;
end
end
TX_RESPONSE_CIN:
RX_TX_RESPONSE_CIN:
begin
 
if(count_send_data != DATA_CONFIG_REG[13:2])
begin
next_state_tx = TX_RESPONSE_CIN;
next_state_tx_rx = RX_TX_RESPONSE_CIN;
end
else if(RESPONSE == 1'b0)//ACK
begin
next_state_tx = TX_DELAY_BYTES;
next_state_tx_rx = RX_TX_DELAY_BYTES;
end
else if(RESPONSE == 1'b1)//NACK
begin
next_state_tx = TX_NACK;
next_state_tx_rx = RX_TX_NACK;
end
end
 
//NOW SENDING ADDRESS
TX_ADRESS_1:
RX_TX_ADRESS_1:
begin
if(count_send_data != DATA_CONFIG_REG[13:2])
begin
next_state_tx = TX_ADRESS_1;
next_state_tx_rx = RX_TX_ADRESS_1;
end
else
begin
next_state_tx = TX_ADRESS_2;
next_state_tx_rx = RX_TX_ADRESS_2;
end
end
TX_ADRESS_2:
RX_TX_ADRESS_2:
begin
if(count_send_data != DATA_CONFIG_REG[13:2])
begin
next_state_tx = TX_ADRESS_2;
next_state_tx_rx = RX_TX_ADRESS_2;
end
else
begin
next_state_tx = TX_ADRESS_3;
next_state_tx_rx = RX_TX_ADRESS_3;
end
end
TX_ADRESS_3:
RX_TX_ADRESS_3:
begin
if(count_send_data != DATA_CONFIG_REG[13:2])
begin
next_state_tx = TX_ADRESS_3;
next_state_tx_rx = RX_TX_ADRESS_3;
end
else
begin
next_state_tx = TX_ADRESS_4;
next_state_tx_rx = RX_TX_ADRESS_4;
end
end
TX_ADRESS_4:
RX_TX_ADRESS_4:
begin
if(count_send_data != DATA_CONFIG_REG[13:2])
begin
next_state_tx = TX_ADRESS_4;
next_state_tx_rx = RX_TX_ADRESS_4;
end
else
begin
next_state_tx = TX_ADRESS_5;
next_state_tx_rx = RX_TX_ADRESS_5;
end
end
TX_ADRESS_5:
RX_TX_ADRESS_5:
begin
if(count_send_data != DATA_CONFIG_REG[13:2])
begin
next_state_tx = TX_ADRESS_5;
next_state_tx_rx = RX_TX_ADRESS_5;
end
else
begin
next_state_tx = TX_ADRESS_6;
next_state_tx_rx = RX_TX_ADRESS_6;
end
end
TX_ADRESS_6:
RX_TX_ADRESS_6:
begin
if(count_send_data != DATA_CONFIG_REG[13:2])
begin
next_state_tx = TX_ADRESS_6;
next_state_tx_rx = RX_TX_ADRESS_6;
end
else
begin
next_state_tx = TX_ADRESS_7;
next_state_tx_rx = RX_TX_ADRESS_7;
end
end
TX_ADRESS_7:
RX_TX_ADRESS_7:
begin
if(count_send_data != DATA_CONFIG_REG[13:2])
begin
next_state_tx = TX_ADRESS_7;
next_state_tx_rx = RX_TX_ADRESS_7;
end
else
begin
next_state_tx = TX_ADRESS_8;
next_state_tx_rx = RX_TX_ADRESS_8;
end
end
TX_ADRESS_8:
RX_TX_ADRESS_8:
begin
if(count_send_data != DATA_CONFIG_REG[13:2])
begin
next_state_tx = TX_ADRESS_8;
next_state_tx_rx = RX_TX_ADRESS_8;
end
else
begin
next_state_tx = TX_RESPONSE_ADRESS;
next_state_tx_rx = RX_TX_RESPONSE_ADRESS;
end
end
TX_RESPONSE_ADRESS:
RX_TX_RESPONSE_ADRESS:
begin
if(count_send_data != DATA_CONFIG_REG[13:2])
begin
next_state_tx = TX_RESPONSE_ADRESS;
next_state_tx_rx = RX_TX_RESPONSE_ADRESS;
end
else if(RESPONSE == 1'b0)//ACK
begin
next_state_tx = TX_DELAY_BYTES;
next_state_tx_rx = RX_TX_DELAY_BYTES;
end
else if(RESPONSE == 1'b1)//NACK --> RESTART CONDITION AND BACK TO START BYTE AGAIN
begin
next_state_tx = TX_NACK;
next_state_tx_rx = RX_TX_NACK;
end
end
//data in
TX_DATA0_1:
RX_TX_DATA0_1:
begin
if(count_send_data != DATA_CONFIG_REG[13:2])
begin
next_state_tx = TX_DATA0_1;
next_state_tx_rx = RX_TX_DATA0_1;
end
else
begin
next_state_tx = TX_DATA0_2;
next_state_tx_rx = RX_TX_DATA0_2;
end
end
TX_DATA0_2:
RX_TX_DATA0_2:
begin
if(count_send_data != DATA_CONFIG_REG[13:2])
begin
next_state_tx = TX_DATA0_2;
next_state_tx_rx = RX_TX_DATA0_2;
end
else
begin
next_state_tx = TX_DATA0_3;
next_state_tx_rx = RX_TX_DATA0_3;
end
end
TX_DATA0_3:
RX_TX_DATA0_3:
begin
if(count_send_data != DATA_CONFIG_REG[13:2])
begin
next_state_tx = TX_DATA0_3;
next_state_tx_rx = RX_TX_DATA0_3;
end
else
begin
next_state_tx = TX_DATA0_4;
next_state_tx_rx = RX_TX_DATA0_4;
end
end
TX_DATA0_4:
RX_TX_DATA0_4:
begin
if(count_send_data != DATA_CONFIG_REG[13:2])
begin
next_state_tx = TX_DATA0_4;
next_state_tx_rx = RX_TX_DATA0_4;
end
else
begin
next_state_tx = TX_DATA0_5;
next_state_tx_rx = RX_TX_DATA0_5;
end
end
TX_DATA0_5:
RX_TX_DATA0_5:
begin
if(count_send_data != DATA_CONFIG_REG[13:2])
begin
next_state_tx = TX_DATA0_5;
next_state_tx_rx = RX_TX_DATA0_5;
end
else
begin
next_state_tx = TX_DATA0_6;
next_state_tx_rx = RX_TX_DATA0_6;
end
end
TX_DATA0_6:
RX_TX_DATA0_6:
begin
if(count_send_data != DATA_CONFIG_REG[13:2])
begin
next_state_tx = TX_DATA0_6;
next_state_tx_rx = RX_TX_DATA0_6;
end
else
begin
next_state_tx = TX_DATA0_7;
next_state_tx_rx = RX_TX_DATA0_7;
end
end
TX_DATA0_7:
RX_TX_DATA0_7:
begin
if(count_send_data != DATA_CONFIG_REG[13:2])
begin
next_state_tx = TX_DATA0_7;
next_state_tx_rx = RX_TX_DATA0_7;
end
else
begin
next_state_tx = TX_DATA0_8;
next_state_tx_rx = RX_TX_DATA0_8;
end
end
TX_DATA0_8:
RX_TX_DATA0_8:
begin
if(count_send_data != DATA_CONFIG_REG[13:2])
begin
next_state_tx = TX_DATA0_8;
next_state_tx_rx = RX_TX_DATA0_8;
end
else
begin
next_state_tx = TX_RESPONSE_DATA0_1;
next_state_tx_rx = RX_TX_RESPONSE_DATA0_1;
end
end
TX_RESPONSE_DATA0_1:
RX_TX_RESPONSE_DATA0_1:
begin
if(count_send_data != DATA_CONFIG_REG[13:2])
begin
next_state_tx = TX_RESPONSE_DATA0_1;
next_state_tx_rx = RX_TX_RESPONSE_DATA0_1;
end
else if(RESPONSE == 1'b0)//ACK
begin
next_state_tx = TX_DELAY_BYTES;
next_state_tx_rx = RX_TX_DELAY_BYTES;
end
else if(RESPONSE == 1'b1)//NACK
begin
next_state_tx = TX_NACK;
next_state_tx_rx = RX_TX_NACK;
end
end
 
//second byte
TX_DATA1_1:
RX_TX_DATA1_1:
begin
if(count_send_data != DATA_CONFIG_REG[13:2])
begin
next_state_tx = TX_DATA1_1;
next_state_tx_rx = RX_TX_DATA1_1;
end
else
begin
next_state_tx = TX_DATA1_2;
next_state_tx_rx = RX_TX_DATA1_2;
end
end
TX_DATA1_2:
RX_TX_DATA1_2:
begin
if(count_send_data != DATA_CONFIG_REG[13:2])
begin
next_state_tx = TX_DATA1_2;
next_state_tx_rx = RX_TX_DATA1_2;
end
else
begin
next_state_tx = TX_DATA1_3;
next_state_tx_rx = RX_TX_DATA1_3;
end
end
TX_DATA1_3:
RX_TX_DATA1_3:
begin
if(count_send_data != DATA_CONFIG_REG[13:2])
begin
next_state_tx = TX_DATA1_3;
next_state_tx_rx = RX_TX_DATA1_3;
end
else
begin
next_state_tx = TX_DATA1_4;
next_state_tx_rx = RX_TX_DATA1_4;
end
end
TX_DATA1_4:
RX_TX_DATA1_4:
begin
if(count_send_data != DATA_CONFIG_REG[13:2])
begin
next_state_tx = TX_DATA1_4;
next_state_tx_rx = RX_TX_DATA1_4;
end
else
begin
next_state_tx = TX_DATA1_5;
next_state_tx_rx = RX_TX_DATA1_5;
end
end
TX_DATA1_5:
RX_TX_DATA1_5:
begin
if(count_send_data != DATA_CONFIG_REG[13:2])
begin
next_state_tx = TX_DATA1_5;
next_state_tx_rx = RX_TX_DATA1_5;
end
else
begin
next_state_tx = TX_DATA1_6;
next_state_tx_rx = RX_TX_DATA1_6;
end
end
TX_DATA1_6:
RX_TX_DATA1_6:
begin
if(count_send_data != DATA_CONFIG_REG[13:2])
begin
next_state_tx = TX_DATA1_6;
next_state_tx_rx = RX_TX_DATA1_6;
end
else
begin
next_state_tx = TX_DATA1_7;
next_state_tx_rx = RX_TX_DATA1_7;
end
end
TX_DATA1_7:
RX_TX_DATA1_7:
begin
if(count_send_data != DATA_CONFIG_REG[13:2])
begin
next_state_tx = TX_DATA1_7;
next_state_tx_rx = RX_TX_DATA1_7;
end
else
begin
next_state_tx = TX_DATA1_8;
next_state_tx_rx = RX_TX_DATA1_8;
end
end
TX_DATA1_8:
RX_TX_DATA1_8:
begin
if(count_send_data != DATA_CONFIG_REG[13:2])
begin
next_state_tx = TX_DATA1_8;
next_state_tx_rx = RX_TX_DATA1_8;
end
else
begin
next_state_tx = TX_RESPONSE_DATA1_1;
next_state_tx_rx = RX_TX_RESPONSE_DATA1_1;
end
end
TX_RESPONSE_DATA1_1:
RX_TX_RESPONSE_DATA1_1:
begin
if(count_send_data != DATA_CONFIG_REG[13:2])
begin
next_state_tx = TX_RESPONSE_DATA1_1;
next_state_tx_rx = RX_TX_RESPONSE_DATA1_1;
end
else if(RESPONSE == 1'b0)//ACK
begin
next_state_tx = TX_DELAY_BYTES;
next_state_tx_rx = RX_TX_DELAY_BYTES;
end
else if(RESPONSE == 1'b1)//NACK
begin
next_state_tx = TX_NACK;
next_state_tx_rx = RX_TX_NACK;
end
end
TX_DELAY_BYTES://THIS FORM WORKS
RX_TX_DELAY_BYTES://THIS FORM WORKS
begin
 
if(count_send_data != DATA_CONFIG_REG[13:2])
begin
next_state_tx = TX_DELAY_BYTES;
next_state_tx_rx = RX_TX_DELAY_BYTES;
end
else
begin
674,69 → 674,72
 
if(count_tx == 2'd0)
begin
next_state_tx = TX_ADRESS_1;
next_state_tx_rx = RX_TX_ADRESS_1;
end
else if(count_tx == 2'd1)
begin
next_state_tx = TX_DATA0_1;
next_state_tx_rx = RX_TX_DATA0_1;
end
else if(count_tx == 2'd2)
begin
next_state_tx = TX_DATA1_1;
next_state_tx_rx = RX_TX_DATA1_1;
end
else if(count_tx == 2'd3)
begin
next_state_tx = TX_STOP;
next_state_tx_rx = RX_TX_STOP;
end
end
 
end
TX_NACK://NOT TESTED YET !!!!
RX_TX_NACK://NOT TESTED YET !!!!
begin
if(count_send_data != DATA_CONFIG_REG[13:2]*2'd2)
begin
next_state_tx = TX_NACK;
next_state_tx_rx = RX_TX_NACK;
end
else
begin
if(count_tx == 2'd0)
begin
next_state_tx = TX_CONTROLIN_1;
next_state_tx_rx = RX_TX_CONTROLIN_1;
end
else if(count_tx == 2'd1)
begin
next_state_tx = TX_ADRESS_1;
next_state_tx_rx = RX_TX_ADRESS_1;
end
else if(count_tx == 2'd2)
begin
next_state_tx = TX_DATA0_1;
next_state_tx_rx = RX_TX_DATA0_1;
end
else if(count_tx == 2'd3)
begin
next_state_tx = TX_DATA1_1;
next_state_tx_rx = RX_TX_DATA1_1;
end
end
end
TX_STOP://THIS WORK
RX_TX_STOP://THIS WORK
begin
if(count_send_data != DATA_CONFIG_REG[13:2])
begin
next_state_tx = TX_STOP;
next_state_tx_rx = RX_TX_STOP;
end
else
begin
next_state_tx = TX_IDLE;
next_state_tx_rx = RX_TX_IDLE;
end
end
default:
begin
next_state_tx = TX_IDLE;
next_state_tx_rx = RX_TX_IDLE;
end
endcase
 
 
end
 
 
 
//SEQUENTIAL TX
always@(posedge PCLK)
begin
746,7 → 749,7
begin
//SIGNALS MUST BE RESETED
count_send_data <= 12'd0;
state_tx <= TX_IDLE;
state_tx_rx <= RX_TX_IDLE;
SDA_OUT<= 1'b1;
fifo_tx_rd_en <= 1'b0;
count_tx <= 2'd0;
757,10 → 760,10
begin
// SEQUENTIAL FUN START
state_tx <= next_state_tx;
state_tx_rx <= next_state_tx_rx;
 
case(state_tx)
TX_IDLE:
case(state_tx_rx)
RX_TX_IDLE:
begin
 
fifo_tx_rd_en <= 1'b0;
785,7 → 788,7
end
 
end
TX_START:
RX_TX_START:
begin
 
if(count_send_data < DATA_CONFIG_REG[13:2])
805,7 → 808,7
end
 
end
TX_CONTROLIN_1:
RX_TX_CONTROLIN_1:
begin
 
839,7 → 842,7
end
TX_CONTROLIN_2:
RX_TX_CONTROLIN_2:
begin
 
870,7 → 873,7
end
 
TX_CONTROLIN_3:
RX_TX_CONTROLIN_3:
begin
 
902,7 → 905,7
 
end
TX_CONTROLIN_4:
RX_TX_CONTROLIN_4:
begin
 
933,7 → 936,7
end
 
TX_CONTROLIN_5:
RX_TX_CONTROLIN_5:
begin
 
965,7 → 968,7
end
 
 
TX_CONTROLIN_6:
RX_TX_CONTROLIN_6:
begin
 
if(count_send_data < DATA_CONFIG_REG[13:2])
995,7 → 998,7
end
 
TX_CONTROLIN_7:
RX_TX_CONTROLIN_7:
begin
 
if(count_send_data < DATA_CONFIG_REG[13:2])
1024,7 → 1027,7
 
end
TX_CONTROLIN_8:
RX_TX_CONTROLIN_8:
begin
 
if(count_send_data < DATA_CONFIG_REG[13:2])
1053,7 → 1056,7
 
end
TX_RESPONSE_CIN:
RX_TX_RESPONSE_CIN:
begin
 
if(count_send_data < DATA_CONFIG_REG[13:2])
1083,7 → 1086,7
 
 
end
TX_ADRESS_1:
RX_TX_ADRESS_1:
begin
 
if(count_send_data < DATA_CONFIG_REG[13:2])
1111,7 → 1114,7
end
end
TX_ADRESS_2:
RX_TX_ADRESS_2:
begin
 
if(count_send_data < DATA_CONFIG_REG[13:2])
1139,7 → 1142,7
end
 
end
TX_ADRESS_3:
RX_TX_ADRESS_3:
begin
 
if(count_send_data < DATA_CONFIG_REG[13:2])
1167,7 → 1170,7
end
 
end
TX_ADRESS_4:
RX_TX_ADRESS_4:
begin
 
if(count_send_data < DATA_CONFIG_REG[13:2])
1194,7 → 1197,7
SDA_OUT<=fifo_tx_data_out[12:12];
end
end
TX_ADRESS_5:
RX_TX_ADRESS_5:
begin
 
if(count_send_data < DATA_CONFIG_REG[13:2])
1223,7 → 1226,7
 
end
TX_ADRESS_6:
RX_TX_ADRESS_6:
begin
 
if(count_send_data < DATA_CONFIG_REG[13:2])
1251,7 → 1254,7
end
end
TX_ADRESS_7:
RX_TX_ADRESS_7:
begin
 
if(count_send_data < DATA_CONFIG_REG[13:2])
1280,7 → 1283,7
 
end
TX_ADRESS_8:
RX_TX_ADRESS_8:
begin
 
if(count_send_data < DATA_CONFIG_REG[13:2])
1308,7 → 1311,7
end
end
TX_RESPONSE_ADRESS:
RX_TX_RESPONSE_ADRESS:
begin
if(count_send_data < DATA_CONFIG_REG[13:2])
begin
1336,7 → 1339,7
end
 
end
TX_DATA0_1:
RX_TX_DATA0_1:
begin
 
if(count_send_data < DATA_CONFIG_REG[13:2])
1365,7 → 1368,7
 
end
TX_DATA0_2:
RX_TX_DATA0_2:
begin
 
if(count_send_data < DATA_CONFIG_REG[13:2])
1394,7 → 1397,7
 
end
TX_DATA0_3:
RX_TX_DATA0_3:
begin
 
if(count_send_data < DATA_CONFIG_REG[13:2])
1422,7 → 1425,7
end
end
TX_DATA0_4:
RX_TX_DATA0_4:
begin
 
if(count_send_data < DATA_CONFIG_REG[13:2])
1450,7 → 1453,7
end
end
TX_DATA0_5:
RX_TX_DATA0_5:
begin
 
if(count_send_data < DATA_CONFIG_REG[13:2])
1478,7 → 1481,7
end
 
end
TX_DATA0_6:
RX_TX_DATA0_6:
begin
 
if(count_send_data < DATA_CONFIG_REG[13:2])
1506,7 → 1509,7
end
end
TX_DATA0_7:
RX_TX_DATA0_7:
begin
 
if(count_send_data < DATA_CONFIG_REG[13:2])
1534,7 → 1537,7
end
end
TX_DATA0_8:
RX_TX_DATA0_8:
begin
 
if(count_send_data < DATA_CONFIG_REG[13:2])
1563,7 → 1566,7
end
end
TX_RESPONSE_DATA0_1:
RX_TX_RESPONSE_DATA0_1:
begin
 
if(count_send_data < DATA_CONFIG_REG[13:2])
1592,7 → 1595,7
end
 
end
TX_DATA1_1:
RX_TX_DATA1_1:
begin
 
if(count_send_data < DATA_CONFIG_REG[13:2])
1622,7 → 1625,7
 
end
TX_DATA1_2:
RX_TX_DATA1_2:
begin
 
if(count_send_data < DATA_CONFIG_REG[13:2])
1650,7 → 1653,7
end
 
end
TX_DATA1_3:
RX_TX_DATA1_3:
begin
 
if(count_send_data < DATA_CONFIG_REG[13:2])
1679,7 → 1682,7
end
end
TX_DATA1_4:
RX_TX_DATA1_4:
begin
 
if(count_send_data < DATA_CONFIG_REG[13:2])
1708,7 → 1711,7
end
end
TX_DATA1_5:
RX_TX_DATA1_5:
begin
 
if(count_send_data < DATA_CONFIG_REG[13:2])
1737,7 → 1740,7
end
end
TX_DATA1_6:
RX_TX_DATA1_6:
begin
 
if(count_send_data < DATA_CONFIG_REG[13:2])
1766,7 → 1769,7
end
end
TX_DATA1_7:
RX_TX_DATA1_7:
begin
 
if(count_send_data < DATA_CONFIG_REG[13:2])
1796,7 → 1799,7
 
end
TX_DATA1_8:
RX_TX_DATA1_8:
begin
 
if(count_send_data < DATA_CONFIG_REG[13:2])
1825,7 → 1828,7
end
end
TX_RESPONSE_DATA1_1:
RX_TX_RESPONSE_DATA1_1:
begin
//fifo_tx_rd_en <= 1'b1;
 
1856,7 → 1859,7
end
 
end
TX_DELAY_BYTES:
RX_TX_DELAY_BYTES:
begin
fifo_tx_rd_en <= 1'b0;
1898,7 → 1901,7
 
end
//THIS BLOCK MUST BE CHECKED WITH CARE
TX_NACK:// MORE A RESTART
RX_TX_NACK:// MORE A RESTART
begin
fifo_tx_rd_en <= 1'b0;
1961,7 → 1964,7
end
end
TX_STOP:
RX_TX_STOP:
begin
 
BR_CLK_O <= 1'b1;
1996,789 → 1999,5
 
end
 
endmodule
 
// RX PARAMETERS USED TO STATE MACHINE
 
localparam [5:0] RX_IDLE = 6'd0, //IDLE
 
RX_START = 6'd1,//START BIT
 
RX_CONTROLIN_1 = 6'd2, //START BYTE
RX_CONTROLIN_2 = 6'd3,
RX_CONTROLIN_3 = 6'd4,
RX_CONTROLIN_4 = 6'd5,
RX_CONTROLIN_5 = 6'd6,
RX_CONTROLIN_6 = 6'd7,
RX_CONTROLIN_7 = 6'd8,
RX_CONTROLIN_8 = 6'd9, //END FIRST BYTE
 
RX_RESPONSE_CIN =6'd10, //RESPONSE
 
RX_ADRESS_1 = 6'd11,//START BYTE
RX_ADRESS_2 = 6'd12,
RX_ADRESS_3 = 6'd13,
RX_ADRESS_4 = 6'd14,
RX_ADRESS_5 = 6'd15,
RX_ADRESS_6 = 6'd16,
RX_ADRESS_7 = 6'd17,
RX_ADRESS_8 = 6'd18,//END FIRST BYTE
 
RX_RESPONSE_ADRESS =6'd19, //RESPONSE
 
RX_DATA0_1 = 6'd20,//START BYTE
RX_DATA0_2 = 6'd21,
RX_DATA0_3 = 6'd22,
RX_DATA0_4 = 6'd23,
RX_DATA0_5 = 6'd24,
RX_DATA0_6 = 6'd25,
RX_DATA0_7 = 6'd26,
RX_DATA0_8 = 6'd27,//END FIRST BYTE
 
RX_RESPONSE_DATA0_1 = 6'd28, //RESPONSE
RX_DATA1_1 = 6'd29,//START BYTE
RX_DATA1_2 = 6'd30,
RX_DATA1_3 = 6'd31,
RX_DATA1_4 = 6'd32,
RX_DATA1_5 = 6'd33,
RX_DATA1_6 = 6'd34,
RX_DATA1_7 = 6'd35,
RX_DATA1_8 = 6'd36,//END FIRST BYTE
 
RX_RESPONSE_DATA1_1 = 6'd37,//RESPONSE
 
RX_DELAY_BYTES = 6'd38,//USED ONLY IN ACK TO DELAY BETWEEN
RX_NACK = 6'd39,//USED ONLY IN ACK TO DELAY BETWEEN BYTES
RX_STOP = 6'd40;//USED TO SEND STOP BIT
 
//STATE CONTROL
reg [5:0] state_rx;
reg [5:0] next_state_rx;
 
reg [11:0] count_receive_data;
 
reg [1:0] count_rx;
 
//COMBINATIONAL BLOCK RX
 
always@(*)
begin
 
 
next_state_rx = state_rx;
 
case(state_rx)//STATE_RX IS MORE SECURE CHANGE ONLY IF YOU KNOW WHAT ARE YOU DOING
RX_IDLE:
begin
//OBEYING SPEC
if(DATA_CONFIG_REG[1] == 1'b0 && DATA_CONFIG_REG[0] == 1'b0)
begin
next_state_rx = RX_IDLE;
end
else if(DATA_CONFIG_REG[1] == 1'b1 && DATA_CONFIG_REG[0] == 1'b1)
begin
next_state_rx = RX_IDLE;
end
else if(DATA_CONFIG_REG[1] == 1'b1 && DATA_CONFIG_REG[0] == 1'b0 && SDA == 1'b0 && SCL == 1'b1)
begin
next_state_rx = RX_START;
end
end
RX_START:
begin
 
if(SDA == 1'b0 && SCL == 1'b1)
begin
if(count_receive_data != DATA_CONFIG_REG[13:2])
begin
next_state_rx = RX_START;
end
else
begin
next_state_rx = RX_CONTROLIN_1;
end
end
else
begin
next_state_rx = RX_IDLE;
end
end
RX_CONTROLIN_1:
begin
if(count_receive_data != DATA_CONFIG_REG[13:2])
begin
next_state_rx = RX_CONTROLIN_1;
end
else
begin
next_state_rx = RX_CONTROLIN_2;
end
end
RX_CONTROLIN_2:
begin
if(count_receive_data != DATA_CONFIG_REG[13:2])
begin
next_state_rx = RX_CONTROLIN_2;
end
else
begin
next_state_rx = RX_CONTROLIN_3;
end
end
RX_CONTROLIN_3:
begin
if(count_receive_data != DATA_CONFIG_REG[13:2])
begin
next_state_rx = RX_CONTROLIN_3;
end
else
begin
next_state_rx = RX_CONTROLIN_4;
end
end
RX_CONTROLIN_4:
begin
if(count_receive_data != DATA_CONFIG_REG[13:2])
begin
next_state_rx = RX_CONTROLIN_4;
end
else
begin
next_state_rx = RX_CONTROLIN_5;
end
end
RX_CONTROLIN_5:
begin
if(count_receive_data != DATA_CONFIG_REG[13:2])
begin
next_state_rx = RX_CONTROLIN_5;
end
else
begin
next_state_rx = RX_CONTROLIN_6;
end
end
RX_CONTROLIN_6:
begin
if(count_receive_data != DATA_CONFIG_REG[13:2])
begin
next_state_rx = RX_CONTROLIN_6;
end
else
begin
next_state_rx = RX_CONTROLIN_7;
end
end
RX_CONTROLIN_7:
begin
if(count_receive_data != DATA_CONFIG_REG[13:2])
begin
next_state_rx = RX_CONTROLIN_7;
end
else
begin
next_state_rx = RX_CONTROLIN_8;
end
end
RX_CONTROLIN_8:
begin
if(count_receive_data != DATA_CONFIG_REG[13:2])
begin
next_state_rx = RX_CONTROLIN_8;
end
else
begin
next_state_rx = RX_RESPONSE_CIN;
end
end
RX_RESPONSE_CIN:
begin
if(count_receive_data != DATA_CONFIG_REG[13:2])
begin
next_state_rx = RX_CONTROLIN_8;
end
else
begin
next_state_rx = RX_RESPONSE_CIN;
end
end
 
RX_ADRESS_1:
begin
if(count_receive_data != DATA_CONFIG_REG[13:2])
begin
next_state_rx = RX_ADRESS_1;
end
else
begin
next_state_rx = RX_ADRESS_2;
end
end
RX_ADRESS_2:
begin
if(count_receive_data != DATA_CONFIG_REG[13:2])
begin
next_state_rx = RX_ADRESS_2;
end
else
begin
next_state_rx = RX_ADRESS_3;
end
end
RX_ADRESS_3:
begin
if(count_receive_data != DATA_CONFIG_REG[13:2])
begin
next_state_rx = RX_ADRESS_3;
end
else
begin
next_state_rx = RX_ADRESS_4;
end
end
RX_ADRESS_4:
begin
if(count_receive_data != DATA_CONFIG_REG[13:2])
begin
next_state_rx = RX_ADRESS_4;
end
else
begin
next_state_rx = RX_ADRESS_5;
end
end
RX_ADRESS_5:
begin
if(count_receive_data != DATA_CONFIG_REG[13:2])
begin
next_state_rx = RX_ADRESS_5;
end
else
begin
next_state_rx = RX_ADRESS_6;
end
end
RX_ADRESS_6:
begin
if(count_receive_data != DATA_CONFIG_REG[13:2])
begin
next_state_rx = RX_ADRESS_6;
end
else
begin
next_state_rx = RX_ADRESS_7;
end
end
RX_ADRESS_7:
begin
 
if(count_receive_data != DATA_CONFIG_REG[13:2])
begin
next_state_rx = RX_ADRESS_7;
end
else
begin
next_state_rx = RX_ADRESS_8;
end
 
end
RX_ADRESS_8:
begin
if(count_receive_data != DATA_CONFIG_REG[13:2])
begin
next_state_rx = RX_ADRESS_8;
end
else
begin
next_state_rx = RX_RESPONSE_ADRESS;
end
end
RX_RESPONSE_ADRESS:
begin
if(count_receive_data != DATA_CONFIG_REG[13:2])
begin
next_state_rx = RX_RESPONSE_ADRESS;
end
else
begin
next_state_rx = RX_DATA0_1;
end
end
 
RX_DATA0_1:
begin
if(count_receive_data != DATA_CONFIG_REG[13:2])
begin
next_state_rx = RX_DATA0_1;
end
else
begin
next_state_rx = RX_DATA0_2;
end
end
RX_DATA0_2:
begin
if(count_receive_data != DATA_CONFIG_REG[13:2])
begin
next_state_rx = RX_DATA0_2;
end
else
begin
next_state_rx = RX_DATA0_3;
end
end
RX_DATA0_3:
begin
if(count_receive_data != DATA_CONFIG_REG[13:2])
begin
next_state_rx = RX_DATA0_3;
end
else
begin
next_state_rx = RX_DATA0_4;
end
end
RX_DATA0_4:
begin
if(count_receive_data != DATA_CONFIG_REG[13:2])
begin
next_state_rx = RX_DATA0_4;
end
else
begin
next_state_rx = RX_DATA0_5;
end
end
RX_DATA0_5:
begin
if(count_receive_data != DATA_CONFIG_REG[13:2])
begin
next_state_rx = RX_DATA0_5;
end
else
begin
next_state_rx = RX_DATA0_6;
end
end
RX_DATA0_6:
begin
if(count_receive_data != DATA_CONFIG_REG[13:2])
begin
next_state_rx = RX_DATA0_6;
end
else
begin
next_state_rx = RX_DATA0_7;
end
end
RX_DATA0_7:
begin
if(count_receive_data != DATA_CONFIG_REG[13:2])
begin
next_state_rx = RX_DATA0_7;
end
else
begin
next_state_rx = RX_DATA0_8;
end
end
RX_DATA0_8:
begin
if(count_receive_data != DATA_CONFIG_REG[13:2])
begin
next_state_rx = RX_DATA0_8;
end
else
begin
next_state_rx = RX_RESPONSE_DATA0_1;
end
end
RX_RESPONSE_DATA0_1:
begin
if(count_receive_data != DATA_CONFIG_REG[13:2])
begin
next_state_rx = RX_RESPONSE_DATA0_1;
end
else
begin
next_state_rx = RX_DATA1_1;
end
end
RX_DATA1_1:
begin
if(count_receive_data != DATA_CONFIG_REG[13:2])
begin
next_state_rx = RX_DATA1_1;
end
else
begin
next_state_rx = RX_DATA1_2;
end
end
RX_DATA1_2:
begin
if(count_receive_data != DATA_CONFIG_REG[13:2])
begin
next_state_rx = RX_DATA1_1;
end
else
begin
next_state_rx = RX_DATA1_3;
end
end
RX_DATA1_3:
begin
if(count_receive_data != DATA_CONFIG_REG[13:2])
begin
next_state_rx = RX_DATA1_3;
end
else
begin
next_state_rx = RX_DATA1_4;
end
end
RX_DATA1_4:
begin
if(count_receive_data != DATA_CONFIG_REG[13:2])
begin
next_state_rx = RX_DATA1_4;
end
else
begin
next_state_rx = RX_DATA1_5;
end
end
RX_DATA1_5:
begin
if(count_receive_data != DATA_CONFIG_REG[13:2])
begin
next_state_rx = RX_DATA1_5;
end
else
begin
next_state_rx = RX_DATA1_6;
end
end
RX_DATA1_6:
begin
if(count_receive_data != DATA_CONFIG_REG[13:2])
begin
next_state_rx = RX_DATA1_6;
end
else
begin
next_state_rx = RX_DATA1_7;
end
end
RX_DATA1_7:
begin
if(count_receive_data != DATA_CONFIG_REG[13:2])
begin
next_state_rx = RX_DATA1_7;
end
else
begin
next_state_rx = RX_DATA1_8;
end
end
RX_DATA1_8:
begin
if(count_receive_data != DATA_CONFIG_REG[13:2])
begin
next_state_rx = RX_DATA1_8;
end
else
begin
next_state_rx = RX_RESPONSE_DATA1_1;
end
end
RX_RESPONSE_DATA1_1:
begin
if(count_receive_data != DATA_CONFIG_REG[13:2])
begin
next_state_rx = RX_RESPONSE_DATA1_1;
end
else
begin
next_state_rx = RX_DELAY_BYTES;
end
end
RX_DELAY_BYTES:
begin
if(count_receive_data != DATA_CONFIG_REG[13:2])
begin
next_state_rx = RX_DELAY_BYTES;
end
else
begin
 
if(count_rx == 2'd0)
begin
next_state_rx = RX_ADRESS_1;
end
else if(count_rx == 2'd1)
begin
next_state_rx = RX_DATA0_1;
end
else if(count_rx == 2'd2)
begin
next_state_rx = RX_DATA1_1;
end
else if(count_rx == 2'd3)
begin
next_state_rx = RX_STOP;
end
end
end
RX_NACK:
begin
 
if(count_receive_data != DATA_CONFIG_REG[13:2]*2'd2)
begin
next_state_rx = RX_NACK;
end
else
begin
if(count_rx == 2'd0)
begin
next_state_rx = RX_CONTROLIN_1;
end
else if(count_rx == 2'd1)
begin
next_state_rx = RX_ADRESS_1;
end
else if(count_rx == 2'd2)
begin
next_state_rx = RX_DATA0_1;
end
else if(count_rx == 2'd3)
begin
next_state_rx = RX_DATA1_1;
end
end
 
 
end
RX_STOP:
begin
 
if(count_receive_data != DATA_CONFIG_REG[13:2])
begin
next_state_rx = RX_STOP;
end
else
begin
next_state_rx = RX_IDLE;
end
 
end
default:
begin
next_state_rx = RX_IDLE;
end
endcase
end
 
 
//SEQUENTIAL BLOCK RX
 
always@(posedge PCLK)
begin
 
if(!PRESETn)
begin
//SIGNALS MUST BE RESETED
count_receive_data <= 12'd0;
state_rx <= RX_IDLE;
fifo_rx_wr_en <= 1'b0;
count_rx <= 2'd0;
end
else
begin
 
state_rx <= next_state_rx;
 
case(state_rx)//STATE_RX IS MORE SECURE CHANGE ONLY IF YOU KNOW WHAT ARE YOU DOING
RX_IDLE:
begin
if(SDA == 1'b0 && SCL == 1'b1)
begin
count_receive_data <= count_receive_data +12'd1;
end
else
begin
count_receive_data <= 12'd0;
end
end
RX_START:
begin
if(SDA == 1'b0 && SCL == 1'b0 && count_receive_data < DATA_CONFIG_REG[13:2] )
begin
count_receive_data <= count_receive_data +12'd1;
end
else
begin
count_receive_data <= 12'd0;
end
end
RX_CONTROLIN_1:
begin
end
RX_CONTROLIN_2:
begin
 
end
RX_CONTROLIN_3:
begin
 
end
RX_CONTROLIN_4:
begin
 
end
RX_CONTROLIN_5:
begin
 
end
RX_CONTROLIN_6:
begin
 
end
RX_CONTROLIN_7:
begin
 
end
RX_CONTROLIN_8:
begin
 
end
RX_RESPONSE_CIN:
begin
 
end
RX_ADRESS_1:
begin
end
RX_ADRESS_2:
begin
end
RX_ADRESS_3:
begin
end
RX_ADRESS_4:
begin
end
RX_ADRESS_5:
begin
end
RX_ADRESS_6:
begin
end
RX_ADRESS_7:
begin
end
RX_ADRESS_8:
begin
end
RX_RESPONSE_ADRESS:
begin
 
end
RX_DATA0_1:
begin
 
end
RX_DATA0_2:
begin
 
end
RX_DATA0_3:
begin
 
end
RX_DATA0_4:
begin
 
end
RX_DATA0_5:
begin
 
end
RX_DATA0_6:
begin
 
end
RX_DATA0_7:
begin
 
end
RX_DATA0_8:
begin
 
end
RX_RESPONSE_DATA0_1:
begin
end
 
RX_DATA1_1:
begin
 
end
RX_DATA1_2:
begin
 
end
RX_DATA1_3:
begin
 
end
RX_DATA1_4:
begin
 
end
RX_DATA1_5:
begin
 
end
RX_DATA1_6:
begin
 
end
RX_DATA1_7:
begin
 
end
RX_DATA1_8:
begin
 
end
RX_RESPONSE_DATA1_1:
begin
end
RX_DELAY_BYTES:
begin
 
end
RX_NACK:
begin
 
 
end
RX_STOP:
begin
 
 
end
default:
begin
count_receive_data <= 12'd4095;
fifo_rx_wr_en <= 1'b0;
count_rx <= 2'd3;
end
endcase
end
end
 
endmodule

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